Semiconductor structure, memory and method of making the same

Abstract

The application relates to a semiconductor structure, a memory and a manufacturing method thereof, the semiconductor structure comprising: a substrate; an inverter arranged on the substrate, the inverter comprising: a pull-down transistor comprising a first semiconductor layer extending along a first direction, the first direction being parallel to a top surface of the substrate, the first semiconductor layer comprising a first channel region; a pull-up transistor comprising a second semiconductor layer extending along the first direction, the second semiconductor layer being arranged above the first semiconductor layer along a second direction perpendicular to the top surface of the substrate, the second semiconductor layer comprising a second channel region; a common gate arranged on the substrate along the second direction, the common gate covering the first channel region and the second channel region; and a conductive plug arranged on one side of the common gate along the first direction, one end of the first semiconductor layer and one end of the second semiconductor layer being connected through the conductive plug, so that the integration density of devices in the semiconductor structure is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a semiconductor structure, a memory, and a method for fabricating the same. Background Technology

[0002] According to Moore's Law, the performance of an integrated circuit doubles for every doubling of the number of semiconductor devices. To improve the performance of integrated circuits, the feature size of semiconductor devices needs to be continuously reduced to increase integration density. However, there is a limit to the reduction of the feature size of semiconductor devices, and after a certain point, the impact of reducing the feature size on increasing the integration density of semiconductor devices becomes negligible.

[0003] In order to maintain the effectiveness of Moore's Law, integrated circuits began to evolve from planar structures to three-dimensional structures. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure, memory, and its fabrication method to address the problem that the integration density of semiconductor devices in existing technologies is difficult to further improve.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a semiconductor structure comprising:

[0006] Substrate;

[0007] An inverter, disposed on the substrate, the inverter comprising:

[0008] A pull-down transistor includes a first semiconductor layer extending along a first direction parallel to the top surface of the substrate, the first semiconductor layer including a first channel region;

[0009] A pull-up transistor includes a second semiconductor layer extending along the first direction and along a second direction perpendicular to the top surface of the substrate. The second semiconductor layer is disposed above the first semiconductor layer at a distance, and the second semiconductor layer includes a second channel region.

[0010] A common gate is disposed on the substrate along the second direction, and the common gate covers the first channel region and the second channel region;

[0011] A conductive plug is disposed on one side of the common gate along the first direction. The conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer. One end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug.

[0012] In one embodiment, along the first direction, the source and drain of the pull-down transistor are disposed opposite to each other in the first semiconductor layer on both sides of the first channel region;

[0013] The source and drain of the pull-up transistor are disposed opposite to each other in the second semiconductor layer on both sides of the second channel region.

[0014] The source of the pull-down transistor and the source of the pull-up transistor are located on the same side, and the drain of the pull-down transistor and the drain of the pull-up transistor are located on the same side.

[0015] In one embodiment, the conductive plug is disposed on the first semiconductor layer, and the drain of the pull-down transistor and the drain of the pull-up transistor are connected through the conductive plug.

[0016] In one embodiment, along the first direction, the two ends of the second semiconductor layer are recessed relative to the first semiconductor layer.

[0017] In one embodiment, the pull-down transistor is a dual-gate transistor and / or the pull-up transistor is a dual-gate transistor.

[0018] In one embodiment, the pull-down transistor is a dual-gate transistor, and the first semiconductor layer includes a bottom first semiconductor layer and a top first semiconductor layer spaced apart along the second direction.

[0019] In one embodiment, the conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer.

[0020] In a second aspect, the present invention provides a memory, including a substrate and at least one static random access memory cell disposed on the substrate, each of the static random access memory cells including a first inverter and a second inverter, the first inverter, the second inverter and the inverter in the semiconductor structure of any one of claims 1-7 having the same structure, the input terminal of the first inverter and the output terminal of the second inverter being connected, and the output terminal of the first inverter and the input terminal of the second inverter being connected.

[0021] Each of the static random access memory units further includes:

[0022] A first transmission transistor is disposed above the first inverter, and the first transmission transistor is connected to the input terminal or the output terminal of the first inverter.

[0023] The second transmission transistor is disposed above the second inverter, and the second transmission transistor is connected to the output terminal or the input terminal of the second inverter.

[0024] In one embodiment, the first inverter includes a first pull-down transistor, a first pull-up transistor, a first conductive plug, and a first common gate. The first pull-down transistor and the first pull-up transistor share the first common gate, and the drains of the first pull-down transistor and the first pull-up transistor are connected through the first conductive plug.

[0025] The second inverter includes a second pull-down transistor, a second pull-up transistor, a second conductive plug, and a second common gate. The second pull-down transistor and the second pull-up transistor share the second common gate. The drains of the second pull-down transistor and the second pull-up transistor are connected through the second conductive plug. The second common gate is connected to the first conductive plug, and the second conductive plug is connected to the first common gate.

[0026] In one embodiment, the memory further includes:

[0027] At the power supply terminal, the source of the first pull-up transistor, the source of the second pull-up transistor, and the power supply terminal are connected.

[0028] The ground terminal is connected to the source of the first pull-down transistor, the source of the second pull-down transistor, and the ground terminal.

[0029] In one embodiment, the first transmission transistor includes a drain, a channel region, and a source arranged sequentially in a direction away from the first inverter. The first transmission transistor also includes a gate, the gate of the first transmission transistor surrounding and covering the peripheral surface of the channel region of the first transmission transistor. The drain of the first transmission transistor is connected to the first inverter.

[0030] The second transmission transistor includes a drain, a channel region, and a source arranged sequentially in a direction away from the second inverter. The second transmission transistor also includes a gate, the gate of the second transmission transistor surrounding and covering the peripheral surface of the channel region of the second transmission transistor. The drain of the second transmission transistor is connected to the second inverter.

[0031] In one embodiment, the memory further includes:

[0032] The first bit line is connected to the source of the first transmission transistor;

[0033] The first word line and the first bit line extend perpendicularly to each other, and the first word line is connected to the gate of the first transmission transistor.

[0034] The second bit line is connected to the source of the second transmission transistor;

[0035] The second word line and the second bit line extend perpendicularly to each other, and the second word line is connected to the gate of the second transmission transistor.

[0036] Thirdly, the present invention provides a method for manufacturing a memory, comprising the following steps:

[0037] A composite substrate is provided, the composite substrate comprising a substrate substrate, at least one first semiconductor material layer and at least one second semiconductor material layer stacked thereon, adjacent first semiconductor material layers and / or second semiconductor material layers being spaced apart, and the first semiconductor material layer and the second semiconductor material layer having opposite conductivity types;

[0038] The composite substrate is etched to form a plurality of fins, the fins extending along a first direction and the fins being spaced apart along a third direction. The first direction and the third direction are parallel to the top surface of the substrate. The first semiconductor material layer retained in the fins forms a first semiconductor layer, and the second semiconductor material layer retained in the fins forms a second semiconductor layer. Along the direction away from the substrate, the lengths of at least one first semiconductor layer and at least one second semiconductor layer in the fins decrease sequentially in the first direction.

[0039] A common gate is formed, which extends on the substrate along a second direction perpendicular to the top surface of the substrate. The common gate covers the surface of the first semiconductor layer and the surface of the second semiconductor layer located in the middle region of the fin portion, forming a common-gate pull-down transistor and a pull-up transistor.

[0040] A conductive plug is formed along the first direction. The conductive plug is disposed on one side of the fin portion. The conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer. One end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug. The pull-down transistor and the pull-up transistor are connected through the conductive plug to form an inverter.

[0041] In one embodiment, the following steps are included before forming the common gate:

[0042] A pseudo-gate is formed, which extends along the third direction and covers the middle region of the fins arranged along the third direction;

[0043] The fin exposed by the dummy gate is etched to remove part of the fin. A gap is formed between adjacent first semiconductor layers and / or second semiconductor layers along the second direction to expose the surfaces of the first semiconductor layer and the second semiconductor layer outside the intermediate region.

[0044] An interlayer dielectric layer is formed, which covers the first semiconductor layer and the second semiconductor layer outside the intermediate region and fills the gap between the first semiconductor layer and / or the second semiconductor layer.

[0045] In one embodiment, forming a common gate includes:

[0046] Remove the pseudo-gate to expose the fin-shaped portion of the intermediate region;

[0047] Etching removes a portion of the fin in the intermediate region, exposing the surfaces of the first semiconductor layer and the second semiconductor layer in the intermediate region;

[0048] A gate dielectric layer is formed, which covers the surfaces of the first semiconductor layer and the second semiconductor layer in the intermediate region;

[0049] The common gate is formed, which covers the gate dielectric layer and fills the region between the first semiconductor layer and / or the second semiconductor layer in the intermediate region.

[0050] In one embodiment, forming a conductive plug includes:

[0051] A contact hole is formed in the interlayer dielectric layer, the contact hole exposing a portion of the surface of the first semiconductor layer and the second semiconductor layer located on one side of the intermediate region;

[0052] The conductive plug is formed in the contact hole.

[0053] In one embodiment, the method of manufacturing the memory further includes the following steps:

[0054] A word line is formed, the word line extends along the first direction, and the word line is correspondingly positioned above the inverter;

[0055] A transmission transistor is formed, the transmission transistor is disposed above the inverter, the gate of the transmission transistor is connected to the word line, and the drain of the transmission transistor is connected to the common gate of the inverter or the conductive plug.

[0056] A bit line is formed, the bit line extending above the inverter along the second direction, and the bit line is connected to the source of the transmission transistor;

[0057] Along the third direction, two transmission transistors are connected to two adjacent inverters, the drain of one of the transmission transistors is connected to the common gate of one inverter, and the drain of the other transmission transistor is connected to the conductive plug of the other inverter.

[0058] In one embodiment, a composite substrate is provided, comprising:

[0059] A first substrate and a second substrate are provided, the first substrate and the second substrate comprising a first semiconductor material, wherein the first substrate comprises a first back substrate, a first buried oxide layer and a first top substrate disposed sequentially;

[0060] The second substrate is disposed on the first top substrate, and the second substrate and the first top substrate are joined together.

[0061] A third substrate is provided, and an epitaxial substrate layer is epitaxially formed on the third substrate, the epitaxial substrate layer comprising a second semiconductor material;

[0062] The epitaxial substrate layer is disposed on the second substrate, and the surfaces of the epitaxial substrate layer and the second substrate on the side away from the first substrate are bonded together;

[0063] The third substrate is removed by etching, and the first substrate, the second substrate, and the epitaxial substrate layer together form the composite substrate.

[0064] In one embodiment, an epitaxial substrate layer is epitaxially formed on the third substrate, including:

[0065] The third substrate is placed in the reaction chamber, and the gas sources of the first semiconductor material and the second semiconductor material are introduced into the reaction chamber. The epitaxial substrate layer is grown on the top surface of the third substrate. During the epitaxial growth of the epitaxial substrate layer, the content of the gas source of the first semiconductor material introduced into the reaction chamber is gradually reduced, and the content of the gas source of the second semiconductor material introduced into the reaction chamber is gradually increased.

[0066] During the etching process to remove the third substrate, a portion of the epitaxial substrate layer is etched away, leaving a portion of the top structure of the epitaxial substrate layer to form the composite substrate.

[0067] In one embodiment, an epitaxial substrate layer is epitaxially formed on the third substrate, including:

[0068] At least one second semiconductor epitaxial layer is formed on the top surface of the third substrate, and the concentration of the second semiconductor material in the at least one second semiconductor epitaxial layer increases along the direction away from the top surface of the third substrate;

[0069] The epitaxial substrate layer is formed epitaxially on the top surface of at least one second semiconductor epitaxial layer;

[0070] During the etching process to remove the third substrate, at least one layer of the second semiconductor epitaxial layer is etched away.

[0071] The present invention relates to a semiconductor structure, a memory, and a method for fabricating the same. By utilizing the dimension perpendicular to the top surface of the substrate, pull-down transistors and pull-up transistors are stacked on top of the substrate to form an inverter. This increases the integration density of transistors, reduces the footprint of the inverter, and increases the usable area of ​​the semiconductor structure. This is beneficial for increasing the integration density of devices in the semiconductor structure and for setting up more semiconductor devices. Attached Figure Description

[0072] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0073] Figure 1 This is a schematic diagram of the inverter provided in one embodiment.

[0074] Figure 2 for Figure 1 A cross-sectional view along line AA.

[0075] Figure 3 This is a schematic diagram of the structure of the first inverter and the second inverter provided in one embodiment.

[0076] Figure 4 This is a schematic diagram of the structure of an SRAM cell provided in one embodiment.

[0077] Figure 5 for Figure 4 A cross-sectional view along line BB.

[0078] Figure 6 This is a circuit diagram of an SRAM cell provided in one embodiment.

[0079] Figure 7 This is a flowchart of a method for manufacturing a memory according to one embodiment.

[0080] Figure 8This is a schematic diagram of the structure of the first substrate provided in one embodiment.

[0081] Figure 9 This is a schematic diagram of the structure of the second substrate provided in one embodiment.

[0082] Figure 10 This is a schematic diagram of the structure after the first substrate and the second substrate are joined together in one embodiment.

[0083] Figure 11 This is a schematic diagram of the structure after removing the second back substrate and the second buried oxide layer in one embodiment.

[0084] Figure 12 This is a schematic diagram of the structure after an epitaxial substrate layer is formed on a third substrate in one embodiment.

[0085] Figure 13 This is a schematic diagram of an epitaxial substrate layer formed on a third substrate in one embodiment.

[0086] Figure 14 This is a schematic diagram of an epitaxial substrate layer formed on a third substrate in one embodiment.

[0087] Figure 15 This is a schematic diagram of the structure after a fourth oxide layer is formed on an epitaxial substrate in one embodiment.

[0088] Figure 16 This is a schematic diagram of the structure after the epitaxial substrate layer and the second top substrate are bonded together in one embodiment.

[0089] Figure 17 This is a schematic diagram of the structure of a composite substrate provided in one embodiment.

[0090] Figure 18 This is a schematic diagram of the structure after etching away part of the composite substrate in one embodiment.

[0091] Figure 19 This is a schematic diagram of the stepped structure formed in one embodiment.

[0092] Figure 20 This is a schematic diagram of the structure after the fourth dielectric layer is formed in one embodiment.

[0093] Figure 21 This is a schematic diagram of the structure from one perspective after the fin-shaped part has been formed in one embodiment.

[0094] Figure 22 This is a schematic diagram of the structure from another perspective after the fin-shaped part has been formed in one embodiment.

[0095] Figure 23 This is a structural schematic diagram from another perspective after the fin-shaped portion has been formed in one embodiment.

[0096] Figure 24 This is a schematic diagram of the structure after the pseudo-gate material layer is formed in one embodiment.

[0097] Figure 25 This is a schematic diagram of the structure from one perspective after the pseudo-gate is formed in one embodiment.

[0098] Figure 26 This is a schematic diagram of the structure from another perspective after the pseudo-gate is formed in one embodiment.

[0099] Figure 27 This is a schematic diagram of the structure from another perspective after the pseudo-gate is formed in one embodiment.

[0100] Figure 28 for Figure 27 Cross-sectional view along line BB.

[0101] Figure 29 This is a schematic diagram of the structure after the first semiconductor layer and the second semiconductor layer are exposed outside the middle region of the fin portion in one embodiment.

[0102] Figure 30 This is a schematic diagram of the structure after the interlayer dielectric layer has been formed in one embodiment.

[0103] Figure 31 This is a schematic diagram of the structure from another perspective after the interlayer dielectric layer has been formed in one embodiment.

[0104] Figure 32 This is a schematic diagram of the structure after removing the dummy gate in one embodiment.

[0105] Figure 33 for Figure 32 Cross-sectional view along the CC line.

[0106] Figure 34 This is a schematic diagram of the structure after the first and second semiconductor layers in one embodiment expose the intermediate region.

[0107] Figure 35 for Figure 34 Cross-sectional view along the DD line.

[0108] Figure 36 This is a schematic diagram of the structure after a common gate is formed in one embodiment.

[0109] Figure 37 This is a schematic diagram of the structure after the conductive plug is formed in one embodiment.

[0110] Figure 38 This is a top view of one embodiment after the conductive plug has been formed.

[0111] Figure 39This is a schematic diagram of the structure after the dielectric layer is formed in one embodiment.

[0112] Figure 40 This is a schematic diagram of the structure after the wiring layer is formed in one embodiment.

[0113] Figure 41 This is a top view of one embodiment after the wiring layer has been formed.

[0114] Figure 42 This is a schematic diagram of the structure after the formation of the third conductive material layer in one embodiment.

[0115] Figure 43 This is a schematic diagram of the structure after the character lines are formed in one embodiment.

[0116] Figure 44 This is a top view after the bit lines have been formed in one embodiment.

[0117] Figure 45 This is a schematic diagram of the structure of a transmission transistor formed in one embodiment.

[0118] Explanation of reference numerals in the attached figures:

[0119] NOT, inverter; T1, pull-down transistor; S1, source of pull-down transistor; D1, drain of pull-down transistor; T2, pull-up transistor; S2, source of pull-up transistor; D2, drain of pull-up transistor; C1, first channel region; C2, second channel region;

[0120] NOT1, First inverter; T11, First pull-down transistor; S11, Source of the first pull-down transistor; D11, Drain of the first pull-down transistor; T12, First pull-up transistor; S12, Source of the first pull-up transistor; D12, Drain of the first pull-up transistor; NOT2, Second inverter; T21, Second pull-down transistor; S21, Source of the second pull-down transistor; D21, Drain of the second pull-down transistor; T22, Second pull-up transistor; S22, Source of the second pull-up transistor; D22, Drain of the second pull-up transistor; T3, Transfer transistor; S3, Source of the transfer transistor; D3, Drain of the transfer transistor; C3, Transfer transistor... Channel region of the body transistor; G3, gate of the transfer transistor; T31, first transfer transistor; S31, source of the first transfer transistor; D31, drain of the first transfer transistor; C31, channel region of the first transfer transistor; G31, gate of the first transfer transistor; T32, second transfer transistor; S32, source of the second transfer transistor; D32, drain of the second transfer transistor; C32, channel region of the second transfer transistor; G32, gate of the second transfer transistor; BL, bit line; BL1, first bit line; BL2, second bit line; WL, word line; WL1, first word line; WL2, second word line; VDD, power supply terminal; VSS, ground terminal;

[0121] 10. Substrate; 20. Common gate; 30. Conductive plug; 40. First semiconductor layer; 140. Bottom first semiconductor layer; 240. Top first semiconductor layer; 50. Second semiconductor layer; 120. First common gate; 220. Second common gate; 130. First conductive plug; 230. Second conductive plug; 70. Interconnect layer; 170. First interconnect; 270. Second interconnect; 300. Composite substrate; 310. Substrate; 320. First semiconductor material layer; 132. Bottom first semiconductor material layer; 232. Top first semiconductor material layer; 330. Second semiconductor material layer; 350. Fin; 171. First dielectric layer; 271. Second dielectric layer; 371. Third dielectric layer; 471. Fourth dielectric layer; 571. Fifth dielectric layer; 671. Sixth dielectric layer; 771. Seventh dielectric layer; 181. Interlayer dielectric Layer; 281, Dielectric layer; 410, Pseudo-gate material layer; 420, Pseudo-gate; 40, Third conductive material layer; 510, First trench; 520, Second trench; 161, First conductor; 261, Second conductor; 801, First oxide layer; 802, Second oxide layer; 803, Third oxide layer; 804, Fourth oxide layer; 810, First substrate; 811, First back substrate; 812, First buried oxide layer; 813, First top layer Substrate; 820, Second substrate; 821, Second back substrate; 822, Second buried oxide layer; 823, Second top substrate; 830, Third substrate; 831, Third back substrate; 832, Third buried oxide layer; 833, Third top substrate; 840, Germanium-silicon layer; 850, Epitaxial substrate layer; 860, Germanium epitaxial layer; 870, Second semiconductor epitaxial layer; 871, First and Second semiconductor epitaxial layers; 872, Second and Second semiconductor epitaxial layers;

[0122] IM, intermediate area; E1, first end; E2, second end; D1, first direction; D2, second direction; D3, third direction. Detailed Implementation

[0123] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0124] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0125] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0126] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0127] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0128] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0129] This disclosure provides an exemplary embodiment of a semiconductor structure, with reference to... Figure 1 , Figure 2 As shown, the semiconductor structure includes a substrate 10 and an inverter NOT disposed on the substrate 10. The inverter NOT, disposed on the substrate 10, includes a pull-down transistor T1, a pull-up transistor T2, a common gate 20, and a conductive plug 30. The pull-down transistor T1 includes a first semiconductor layer 40 extending along a first direction D1, parallel to the top surface of the substrate 10, and the first semiconductor layer 40 includes a first channel region C1. The pull-up transistor T2 includes a second semiconductor layer 50 extending along the first direction D1, and a second semiconductor layer 50, spaced above the first semiconductor layer 40 along a second direction D2 perpendicular to the top surface of the substrate 10, includes a second channel region C1. A common gate 20 is disposed on the substrate 10 along the second direction D2, and the common gate 20 covers the first channel region 31 and the second channel region C2; a conductive plug 30 is disposed on one side of the common gate 20 along the first direction D1, and the conductive plug 30 covers part of the surface of the first semiconductor layer 30 and part of the surface of the second semiconductor layer 50, and one end of the first semiconductor layer 40 and one end of the second semiconductor layer 50 are connected through the conductive plug 30.

[0130] It should be noted that, referring to Figure 3 As shown, one or more inverters 20 can be disposed on the substrate 10. When multiple inverters 20 are disposed on the substrate 10, the multiple inverters 20 can be arranged in an array on the substrate 10 along a preset direction. The preset direction can be a first direction D1, or a third direction D3 perpendicular to the first direction D1, or other directions parallel to the top surface of the substrate 10. In specific applications, the number of inverters 20 can be set according to requirements.

[0131] In this embodiment, the semiconductor structure utilizes the dimension perpendicular to the top surface of the substrate 10 to stack pull-down transistor T1 and pull-up transistor T2 above the substrate 10 to form an inverter NOT. This increases the integration density of the transistors, reduces the footprint of the inverter 20, and increases the usable area of ​​the semiconductor structure. This is beneficial for increasing the integration density of devices in the semiconductor structure and allowing for the placement of more semiconductor devices.

[0132] Reference Figure 1 , Figure 2 As shown, along the first direction D1, the source S1 and drain D1 of pull-down transistor T1 are disposed opposite each other in the first semiconductor layer 40 on both sides of the first channel region C1. The source S2 and drain D2 of pull-up transistor T2 are disposed opposite each other in the second semiconductor layer 50 on both sides of the second channel region C2. The source S1 of pull-down transistor T1 and the source S2 of pull-up transistor T2 are disposed on the same side, and the drain D1 of pull-down transistor T1 and the drain D2 of pull-up transistor T2 are disposed on the same side. The source S1 of pull-down transistor T1 and the source S2 of pull-up transistor T2 are connected by a conductive plug 30, or the drain D1 of pull-down transistor T1 and the drain D2 of pull-up transistor T2 are connected by a conductive plug 30.

[0133] In some embodiments, refer to Figure 1 , Figure 2 As shown, the conductive plug 30 is disposed on the first semiconductor layer 40, and the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 are connected through the conductive plug 30.

[0134] In some embodiments, refer to Figure 1 , Figure 2 As shown, along the first direction D1, the two ends of the second semiconductor layer 50 are recessed relative to the first semiconductor layer 40, and along the second direction D2, the two ends of the first semiconductor layer 40 and the second semiconductor layer 50 form steps. That is, the length of the second semiconductor layer 50 in the first direction D1 is less than the length of the first semiconductor layer 40 in the first direction D1, and the two ends of the first semiconductor layer 40 are equivalent to the second semiconductor layer 50 extending outward. In this way, the conductive plug 30 can be placed on the end of the first semiconductor layer 10. The conductive plug 30 covers part of the surface of the end of the first semiconductor layer 40 on the drain side of the inverter NOT and part of the surface of the end of the second semiconductor layer 50 on the drain side, thereby connecting the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 together, further reducing the footprint of the inverter NOT, and further freeing up the usable area of ​​the semiconductor structure.

[0135] Similarly, wires can be provided at the ends of the first semiconductor layer 40 and the second semiconductor layer 50 on the source side of the inverter NOT to connect the source S1 of the pull-down transistor T1 and the source S2 of the pull-up transistor T2 to other structures or devices. For example, the source S1 of the pull-down transistor T1 can be connected to the ground terminal VSS through one wire, and the source S2 of the pull-up transistor T2 can be connected to the power supply terminal VDD through another wire, which facilitates the wiring of the semiconductor structure.

[0136] In some embodiments, refer to Figure 1 , Figure 2 As shown, pull-down transistor T1 is a dual-gate transistor and / or pull-up transistor T2 is a dual-gate transistor.

[0137] In some embodiments, refer to Figure 1 , Figure 2 As shown, the pull-down transistor T1 is a dual-gate transistor, and the first semiconductor layer 40 includes a bottom first semiconductor layer 140 and a top first semiconductor layer 240 spaced apart along the second direction D2.

[0138] In some embodiments, refer to Figure 1 , Figure 2 As shown, the conductivity type of the first semiconductor layer 40 is opposite to that of the second semiconductor layer 50. For example, the first semiconductor layer 40 has an N-type conductivity type, and the pull-down transistor T1 is an NMOS transistor; the second semiconductor layer 50 has a P-type conductivity type, and the pull-up transistor T2 is a PMOS transistor. Alternatively, the first semiconductor layer 40 has a P-type conductivity type, and the pull-down transistor T1 is a PMOS transistor; the second semiconductor layer 50 has an N-type conductivity type, and the pull-up transistor T2 is an NMOS transistor.

[0139] For example, the material of the first semiconductor layer 40 may include silicon, the material of the second semiconductor layer 50 may include germanium, the pull-down transistor T1 is a dual-gate NMOS transistor, and the pull-up transistor T2 is a PMOS transistor. The hole mobility of the germanium channel is 1.2 times that of the electron mobility of the silicon channel. In this example, the pull-down transistor T1 adopts a dual-gate structure to match the drive current of the pull-down transistor T1 and the pull-up transistor T2.

[0140] According to an exemplary embodiment, this embodiment provides a memory, referring to... Figure 3 , Figure 4 , Figure 5 and combined Figure 44As shown, the memory includes a substrate 10 and at least one static random access memory (SRAM) cell disposed on the substrate 10. Each SRAM cell includes a first inverter NOT1 and a second inverter NOT2. The first inverter NOT1, the second inverter NOT2, and the inverter NOT in the semiconductor structure of the above embodiment have the same structure. (Refer to...) Figure 6 As shown, the input terminal of the first inverter NOT1 is connected to the output terminal of the second inverter NOT1, and the output terminal of the first inverter NOT1 is connected to the input terminal of the second inverter NOT2. (Refer to...) Figure 3 , Figure 4 , Figure 6 Each static random access memory cell further includes a first transfer transistor T31 and a second transfer transistor T32. The first transfer transistor T31 is disposed above the first inverter NOT1 and is connected to the input terminal or the output terminal of the first inverter NOT1. The second transfer transistor T32 is disposed above the second inverter NOT2 and is connected to the output terminal or the input terminal of the second inverter NOT2.

[0141] Reference Figure 3 , Figure 4 , Figure 5 As shown, the first inverter NOT1 includes a first pull-down transistor T11, a first pull-up transistor T12, a first conductive plug 130, and a first common gate 120. The first pull-down transistor T11 and the first pull-up transistor T12 share the first common gate 120, which serves as the input terminal of the first inverter NOT1. The drains D11 of the first pull-down transistor T11 and D12 of the first pull-up transistor T12 are connected through the first conductive plug 130, serving as the output terminal of the first inverter NOT1.

[0142] Reference Figure 3 , Figure 4 As shown, the second inverter NOT2 includes a second pull-down transistor T21, a second pull-up transistor T22, a second conductive plug 230, and a second common gate 220. The second pull-down transistor T21 and the second pull-up transistor T22 share the second common gate 220, which serves as the input terminal of the second inverter NOT2. The drains D21 of the second pull-down transistor T21 and D22 of the second pull-up transistor T22 are connected through the second conductive plug 230, serving as the output terminal of the second inverter NOT2. The second common gate 220 of the second inverter NOT2 is connected to the first conductive plug 130 of the first inverter NOT1, and the second conductive plug 230 of the second inverter NOT2 is connected to the first common gate 120 of the first inverter NOT1.

[0143] In some embodiments, refer to Figure 4 and combined Figure 44 As shown, the memory also includes an interconnect layer 70, which includes at least a first interconnect 170 and a second interconnect 270. The second common gate 220 of the second inverter NOT2 and the first conductive plug 130 of the first inverter NOT1 are connected through the first interconnect 170, and the second conductive plug 230 of the second inverter NOT2 and the first common gate 120 of the first inverter NOT1 are connected through the second interconnect 270.

[0144] Reference Figure 3 , Figure 4 , Figure 5 and combined Figure 44 As shown, the first transmission transistor T31 includes a drain D31, a channel region C31, and a source S31 arranged sequentially along a direction away from the first inverter NOT1. The first transmission transistor T31 also includes a gate G31, which surrounds and covers the peripheral surface of the channel region C31. The drain D31 of the first transmission transistor T31 is connected to the first inverter NOT1. In this embodiment, the first transmission transistor T31 is a vertical-around-the-loop transistor. The drain D31 of the first transmission transistor T31 is coupled to the input terminal (first common gate 120) or the output terminal (first conductive plug 130) of the first inverter NOT1 via the interconnect layer 70.

[0145] The second transmission transistor T32 includes a drain D32, a channel region C32, and a source S32 arranged sequentially along a direction away from the second inverter NOT2. The second transmission transistor T32 also includes a gate G32, which surrounds and covers the peripheral surface of the channel region C32. The drain D32 of the second transmission transistor T32 is connected to the second inverter NOT2. In this embodiment, the second transmission transistor T32 is a vertical-around-the-loop transistor. The drain D32 of the second transmission transistor T32 is coupled to either the output terminal (first conductive plug 130) or the input terminal (first common gate 120) of the first inverter NOT1 via interconnect layer 70.

[0146] In some embodiments, refer to Figure 4 , Figure 5 and combined Figure 44 As shown, the memory also includes a first bit line BL1, which extends above the first inverter NOT1 along the second direction D2. The first bit line BL1 is connected to the source S31 of the first transmission transistor T31.

[0147] Reference Figure 4and combined Figure 44 As shown, the memory also includes a first word line WL1, which is disposed above the first inverter NOT1. In this embodiment, the first word line WL1 extends above the first inverter NOT1 along the first direction D1. The extension directions of the first word line WL1 and the first bit line BL1 intersect perpendicularly above the first inverter NOT1. The first word line WL1 is connected to the gate G31 of the first transmission transistor T31.

[0148] Reference Figure 4 and combined Figure 44 As shown, the memory also includes a second bit line BL2, which extends above the second inverter NOT2 along the second direction D2, and the second bit line BL2 is connected to the source S32 of the second transmission transistor T32.

[0149] Reference Figure 4 and combined Figure 44 As shown, the memory also includes a second word line WL2, which is disposed above the second inverter NOT2. In this embodiment, the second word line WL2 extends above the second inverter NOT2 along the first direction D1. The extension directions of the second word line WL2 and the second bit line BL2 intersect perpendicularly above the second inverter NOT2. The second word line WL2 is connected to the gate G32 of the second transmission transistor T32.

[0150] Reference Figure 6 The memory also includes a power supply terminal VDD and a ground terminal VSS. The source S12 of the first pull-up transistor T12 and the source S22 of the second pull-up transistor T22 are connected to the power supply terminal VDD, respectively. The source S11 of the first pull-down transistor T11 and the source S21 of the second pull-down transistor T21 are connected to the ground terminal VSS.

[0151] In this embodiment, the memory integrates six transistors in the footprint of two transistors to form a 6T static random access memory (SRAM) cell by utilizing the dimension perpendicular to the top surface of the substrate. This greatly improves the transistor integration density and reduces the footprint of the SRAM cell, which is beneficial for the continuous improvement of the device integration density of the memory.

[0152] This disclosure provides a method for manufacturing a memory in exemplary embodiments, such as... Figure 7 As shown, Figure 7 A flowchart illustrating a method for manufacturing a memory according to an exemplary embodiment of the present disclosure is shown. Figures 8-44 This is a schematic diagram illustrating the various stages of the memory fabrication process. The following section combines... Figures 8-44 And refer to Figures 1-6 The method for manufacturing the memory in this embodiment will be described.

[0153] This embodiment does not limit the semiconductor structure. The following description will take Static Random Access Memory (SRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0154] like Figure 8 As shown, an exemplary embodiment of this disclosure provides a method for manufacturing a memory, comprising the following steps:

[0155] Step S110: Provide a composite substrate, the composite substrate including a substrate substrate, at least one first semiconductor material layer and at least one second semiconductor material layer stacked together, adjacent first semiconductor material layers and / or second semiconductor material layers are spaced apart, and the first semiconductor material layers and second semiconductor material layers have opposite conductivity types.

[0156] Step S120: Etch the composite substrate to form a plurality of fins. The fins extend along a first direction and are spaced apart along a third direction. The first direction and the third direction are parallel to the top surface of the substrate. A first semiconductor material layer retained in the fins forms a first semiconductor layer, and a second semiconductor material layer retained in the fins forms a second semiconductor layer. Along the direction away from the substrate, the lengths of at least one first semiconductor layer and at least one second semiconductor layer in the fins decrease sequentially in the first direction.

[0157] Step S130: Form a gate extending on the substrate along a second direction perpendicular to the top surface of the substrate. The gate covers the surface of the first semiconductor layer and the surface of the second semiconductor layer located in the middle region of the fin portion, forming a common-gate pull-down transistor and a pull-up transistor.

[0158] Step S140: Form a conductive plug. Along the first direction, the conductive plug is disposed on one side of the fin portion. The conductive plug covers a portion of the surface of the first semiconductor layer and a portion of the surface of the second semiconductor layer. One end of the first semiconductor layer and one end of the second semiconductor layer are connected through the conductive plug. The pull-down transistor and the pull-up transistor are connected through the conductive plug to form an inverter.

[0159] In step S110, the composite substrate is a stacked structure 300. The composite substrate 300 includes a substrate 310. The material of the substrate 310 may include silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other materials with semiconductor properties, such as group III / V compounds or group II / VI compounds.

[0160] Reference Figure 17As shown, the composite substrate 300 further includes at least one first semiconductor material layer 320, which is stacked on the substrate 310. The first semiconductor material layer 320 and the substrate 310 are spaced apart, and adjacent first semiconductor material layers 320 are also spaced apart. For example, the first semiconductor material layer 320 and the substrate 310 are separated by other film layers, and adjacent first semiconductor material layers 320 are separated by other film layers. These other film layers can be insulating film layers and / or conductive film layers. The material of the first semiconductor material layer 320 may include silicon, germanium, or silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other materials with semiconductor properties, such as group III / V compounds or group II / VI compounds. The first semiconductor material layer 320 has a first conductivity type; for example, the first semiconductor material layer 320 may be doped with conductive dopant ions having a first conductivity type.

[0161] The composite substrate 300 further includes at least one second semiconductor material layer 330, which is stacked on top of at least one first semiconductor material layer 320. The second semiconductor material layer 330 and the first semiconductor material layer 320 are spaced apart, and adjacent second semiconductor material layers 330 are also spaced apart. For example, the second semiconductor material layer 330 and the first semiconductor material layer 320 are separated by other film layers, and adjacent second semiconductor material layers 330 are separated by other film layers. These other film layers can be insulating film layers and / or conductive film layers. The material of the second semiconductor material layer 330 can include silicon, germanium, or silicon-germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, or other materials with semiconductor properties, such as group III / V compounds or group II / VI compounds. The second semiconductor material layer 330 has a second conductivity type; for example, the second semiconductor material layer 330 can be doped with conductive dopant ions having a second conductivity type. The first semiconductor material layer 320 and the second semiconductor material layer 330 have opposite conductivity types. For example, the conductivity type of the first semiconductor material layer 320 can be N-type or P-type, and the conductivity type of the second semiconductor material layer 330 can be P-type or N-type.

[0162] In this embodiment, the composite substrate 300 is described as including two first semiconductor material layers 320 and one second semiconductor material layer 330, with reference to... Figure 17 As shown, the composite substrate 300 includes a substrate 310, a first dielectric layer 171, a bottom first semiconductor material layer 132, a second dielectric layer 271, a top first semiconductor material layer 232, a third dielectric layer 371, and a second semiconductor material layer 330, which are stacked sequentially.

[0163] The bottom first semiconductor material layer 132 and the top first semiconductor material layer 232 are made of silicon and have an N-type conductivity. The second semiconductor material layer 330 is made of germanium and has a P-type conductivity. The materials of the first dielectric layer 171, the second dielectric layer 271, and the third dielectric layer 371 may include at least one of silicon oxide or silicon oxynitride.

[0164] In step S120, in this embodiment, the composite substrate is etched to form multiple fin-shaped portions, which can be implemented in the following ways:

[0165] First, such as Figure 18 As shown, refer to Figure 17 A photoresist mask (not shown) is formed on the top surface of the composite substrate 300. Along the first direction D1, the photoresist mask exposes portions of the surfaces at both ends of the composite substrate 300. Using the top surface of the second dielectric layer 271 as an etching stop layer, the composite substrate 300 is etched according to the photoresist mask. Then, as... Figure 19 As shown, refer to Figure 18 The photoresist mask is trimmed along the first direction D1 to remove part of the structure at both ends of the photoresist mask, thereby increasing the surface area at both ends of the composite substrate 300 exposed by the photoresist mask. The composite substrate 300 is etched according to the trimmed photoresist mask, using the top surface of the third dielectric layer 371 as the etching stop layer, to etch away part of the second semiconductor material layer 330.

[0166] Reference Figure 19 As shown, the etched composite substrate 300 has Figure 19 The stepped structure shown in the figure has the following characteristics along the first direction D1: the length of the bottom first semiconductor material layer 132 is greater than the length of the top first semiconductor material layer 232, the two ends of the bottom first semiconductor material layer 132 extend outward relative to the top first semiconductor material layer 232, the length of the top first semiconductor material layer 232 is greater than the length of the second semiconductor material layer 330, and the two ends of the top first semiconductor material layer 232 extend outward relative to the second semiconductor material layer 330.

[0167] Then, as Figure 20 As shown, refer to Figure 19A fourth dielectric layer 471 is formed, filling the portion of the composite substrate 300 that has been etched away. For example, any suitable deposition process can be used to deposit a dielectric material to form the fourth dielectric material layer (not shown in the figure). The fourth dielectric material layer covers the top surface of the second semiconductor material layer 330 and fills the portion of the composite substrate 300 that has been etched away. The top surface of the fourth dielectric material layer is higher than the top surface of the second semiconductor material layer 330. Then, chemical mechanical polishing (CMP) is used to polish the fourth dielectric material layer until the top surface of the second semiconductor material layer 330 is exposed. The polished fourth dielectric material layer forms the fourth dielectric layer 471, whose top surface is flush with the top surface of the second semiconductor material layer 300. This provides a process plane for subsequent processes.

[0168] The material of the fourth dielectric layer 471 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0169] Next, as Figure 21 , Figure 22 , Figure 23 As shown, refer to Figure 20 A first mask layer (not shown in the figure) is formed, exposing a portion of the top surface of the second semiconductor material layer 330 and the fourth dielectric layer 471. The fourth dielectric layer 471 and the composite substrate 330 are etched according to the first mask layer to form multiple first trenches 510. The first trenches 510 extend along a first direction D1 and penetrate the composite substrate 300. The multiple first trenches 510 are spaced apart along a third direction D3, wherein the first direction D1 and the third direction D3 are parallel to the top surface of the substrate 310 and perpendicular to it. The first trenches 510 extend into the first dielectric layer 171, exposing the first dielectric layer 171. It is understood that in other embodiments, the first trenches 510 may expose the top surface of the substrate 310.

[0170] Reference Figure 21 , Figure 22 , Figure 23As shown, the first trench 510 divides the composite substrate 300 above the substrate 310 into a plurality of spaced fins 350. The fins 350 extend along the first direction D1 and are spaced along the third direction D3. The bottom first semiconductor material layer 132 retained in each fin 350 forms the bottom first semiconductor layer 140, the top first semiconductor material layer 232 forms the top first semiconductor layer 240, and the second semiconductor material layer 330 forms the second semiconductor layer 50. Along the direction away from the substrate 310, the lengths of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 decrease sequentially in the first direction D1. Steps are formed at both ends of the fins 350, and the steps of the fins 350 are covered by the fourth dielectric layer 471.

[0171] It is understood that in some other embodiments, the composite substrate 300 may be etched first to form a first trench 510 in the composite substrate 300 above the substrate 310. The first trench 510 divides the composite substrate 300 above the substrate 310 into multiple independently arranged strip structures. The strip structures extend along a first direction D1 and are spaced apart along a third direction D3. Then, the two ends of the strip structures are etched to form steps at the two ends of the strip structures, so that the lengths of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 decrease sequentially in the first direction D1 along the direction away from the substrate 310.

[0172] In some embodiments, after step S120 and before step S130, the following steps are also performed:

[0173] Step S1201: Form a pseudo-gate that extends along a third direction and covers the middle region of the fins arranged along the third direction.

[0174] First, such as Figure 24 As shown, refer to Figure 23 The pseudo-gate material layer 410 can be deposited using any of the following deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or sputtering. The pseudo-gate material layer 410 fills the first trench 510 and covers the top surface of the second semiconductor layer 50 and the fourth dielectric layer 471.

[0175] Then, as Figure 25 , Figure 26 , Figure 27 , Figure 28 As shown, refer to Figure 24A second mask layer (not shown in the figure) is formed on the top surface of the dummy gate material layer 410. The second mask layer is located above the middle region IM of the fin portion 350. The dummy gate material layer 410 is etched according to the second mask layer, and all of the dummy gate material layer 410 exposed by the second mask layer is removed. The etched and retained dummy gate material layer 410 forms a dummy gate 420. The dummy gate 420 extends along the third direction D2 and covers the middle region IM of the fin portion 350. The ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 are all located outside the dummy gate 420. The material of the dummy gate 420 may include monocrystalline silicon or polycrystalline silicon. In this embodiment, the dummy gate material layer 410 can be etched using a dry process or a wet process.

[0176] Step S1202: Etch the fin portion exposed by the dummy gate, remove part of the fin portion, and form a gap between adjacent first semiconductor layers and / or second semiconductor layers along the second direction to expose the surfaces of the first semiconductor layer and the second semiconductor layer outside the middle region.

[0177] In this embodiment, as Figure 29 As shown, refer to Figure 25 , Figure 26 , Figure 27 The fin portion 350 can be etched using either a dry or wet process. The etching process has a high etching selectivity relative to the first semiconductor layer 40 (including the bottom first semiconductor layer 140 and the top first semiconductor layer 240) and the second semiconductor layer 50, so as to remove all the first dielectric layer 171, the second dielectric layer 271, the third dielectric layer 371, and the fourth dielectric layer 471 exposed by the dummy gate 420. In this way, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 in the fin portion 350 are exposed.

[0178] In this embodiment, the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 of the composite substrate 300 all include semiconductor materials doped with conductive ions. Therefore, in subsequent steps, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 can be directly used as the source or drain of the transistor. In this embodiment, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 are no longer doped.

[0179] In other embodiments, after etching the fin portion 350 exposed by the dummy gate 420 and forming a gap between adjacent first semiconductor layers 40 and / or second semiconductor layers 50, doping treatment can be performed on both ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 to form doped regions at both ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50, respectively. Subsequently, the doped regions at both ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 serve as the source or drain of the transistor.

[0180] Step S1203: Form an isolation layer that covers the exposed surface of the first semiconductor layer and the exposed surface of the second semiconductor layer 50.

[0181] In this embodiment, refer to Figure 29 An isolation layer (not shown in the figure) can be formed by depositing a barrier material using atomic layer deposition (ALD) process. The isolation layer covers the exposed surface of the substrate 310, the exposed surface of the bottom first semiconductor layer 140, the exposed surface of the top first semiconductor layer 240, and the exposed surface of the second semiconductor layer 50.

[0182] Specifically, the material of the isolation layer has a high etch selectivity relative to the first semiconductor layer 40 (bottom first semiconductor layer 140 and top first semiconductor layer 240), a high etch selectivity relative to the second semiconductor layer 50, and a high etch selectivity relative to the dielectric layers (first dielectric layer 171, second dielectric layer 271, third dielectric layer 371, and fourth dielectric layer 471). This is to prevent the etching process from damaging the first semiconductor layer 40 and the second semiconductor layer 50 during subsequent etching of the intermediate region IM.

[0183] In this embodiment, the materials of the first dielectric layer 171, the second dielectric layer 271, the third dielectric layer 371 and the fourth dielectric layer 471 include silicon oxide, the material of the first semiconductor layer 40 (the bottom first semiconductor layer 140 and the top first semiconductor layer 240) includes silicon, the material of the second semiconductor layer 50 includes germanium, and the material of the isolation layer may include at least one of silicon carbon nitride (SiCN) or silicon carbon oxynitride (SiOCN).

[0184] Step S1204: Form an interlayer dielectric layer, which covers the first semiconductor layer and the second semiconductor layer outside the intermediate region and fills the gap between the first semiconductor layer and / or the second semiconductor layer.

[0185] like Figure 30 , Figure 31 As shown, refer to Figure 29An interlayer dielectric layer 181 can be deposited using a fluidic chemical vapor deposition (FCVD) process. The interlayer dielectric layer 181 covers the surfaces of the bottom first semiconductor layer 140 and the top first semiconductor layer 240, as well as the surface of the second semiconductor layer 50, excluding the intermediate region IM. It also fills the gaps between the bottom first semiconductor layer 140 and the top first semiconductor layer 240, and between the top first semiconductor layer 240 and the second semiconductor layer 50. The interlayer dielectric layer 181 also fills the region between adjacent fin portions 350. After forming the interlayer dielectric layer 181, a chemical mechanical polishing process is used to polish the top surface of the interlayer dielectric layer 181 until the top surface of the dummy gate 420 is exposed, making the top surface of the interlayer dielectric layer 181 flush with the top surface of the dummy gate 420.

[0186] The material of the interlayer dielectric layer 181 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0187] In step S130, a common gate is formed, including the following steps:

[0188] Step S131: Remove the pseudo-gate to expose the fin-shaped portion of the middle region.

[0189] like Figure 32 , Figure 33 As shown, refer to Figure 31 The dummy gate 420 can be removed by etching using either a dry or wet process. For example, in this embodiment, an etchant can be used to dissolve and remove the dummy gate 420, exposing the middle region IM of the fin portion 350. The etchant has a high etching selectivity for the interlayer dielectric layer 181 and the composite substrate 300.

[0190] Step S132: Etch away part of the fin in the middle region to expose the surfaces of the first semiconductor layer and the second semiconductor layer 50 in the middle region.

[0191] like Figure 34 , Figure 35 As shown, refer to Figure 32 , Figure 33The intermediate region IM of the fin portion 350 can be etched using either a dry or wet process, removing the first dielectric layer 171, the second dielectric layer 271, and the third dielectric layer 371 of the intermediate region IM. The etching process has a high etching selectivity relative to the first semiconductor layer 40 (bottom first semiconductor layer 140, top first semiconductor layer 240) and the second semiconductor layer 50. At the same time, the first semiconductor layer 40 (bottom first semiconductor layer 140, top first semiconductor layer 240) and the second semiconductor layer 50 of the intermediate region IM of the fin portion 350 are covered by the interlayer dielectric layer 181, thereby avoiding process damage to the first semiconductor layer 40 (bottom first semiconductor layer 140, top first semiconductor layer 240) and the second semiconductor layer 50.

[0192] like Figure 34 , Figure 35 As shown, after the first dielectric layer 171, the second dielectric layer 271, and the third dielectric layer 371 of the intermediate region 350 are removed, the two ends of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 are supported by the interlayer dielectric layer 181. The bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 of the intermediate region IM are suspended, and the surfaces of the bottom first semiconductor layer 140, the top first semiconductor layer 240, and the second semiconductor layer 50 of the intermediate region IM are exposed in the process space.

[0193] Step S133: Form a first epitaxial layer on the exposed surface of the second semiconductor layer.

[0194] Reference Figure 34 , Figure 25 As shown, a semiconductor structure is placed in a reaction chamber, with the exposed surface of the second semiconductor layer 50 serving as a seed crystal. A gas source for forming a first epitaxial layer (not shown) is introduced into the reaction chamber, and the first epitaxial layer is formed using a chemical vapor deposition process. The material of the first epitaxial layer may include silicon, silicon carbide, gallium arsenide, or indium gallium ionide. In this embodiment, the first epitaxial layer is a silicon epitaxial layer, and the first epitaxial layer may be doped with conductive ions, specifically P-type or N-type dopant ions.

[0195] It is understandable that during the epitaxial process, a silicon epitaxial layer is also grown on the surface of the first semiconductor layer 40 (bottom first semiconductor layer 140 and top first semiconductor layer 140).

[0196] In this embodiment, before forming the gate dielectric layer (which will be described in detail in subsequent steps), a first epitaxial layer is formed on the surface of the second semiconductor layer 50 in the intermediate region IM to reduce the band gap at the contact interface between the second semiconductor layer 50 and the gate dielectric layer, thereby reducing the threshold voltage of the transistor formed by the second semiconductor layer 50 in subsequent steps.

[0197] Step S134: Form a gate dielectric layer, which covers the surfaces of the first semiconductor layer and the second semiconductor layer 50 in the middle region.

[0198] Reference Figure 34 , Figure 35 As shown, a gate dielectric layer (not shown in the figure) can be deposited using chemical vapor deposition or atomic layer deposition. The gate dielectric layer covers the surface of the bottom first semiconductor layer 140 of the middle region IM, the surface of the top first semiconductor layer 240 of the middle region IM, and the surface of the second semiconductor layer 50 of the middle region IM.

[0199] The material of the gate dielectric layer may include at least one of alumina (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); or, the material of the gate dielectric layer may include at least one of hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSiON).

[0200] Step S135: Form a gate, the gate covers the gate dielectric layer and fills the region between the first semiconductor layer and / or the second semiconductor layer in the intermediate region.

[0201] Reference Figure 34 , Figure 35 As shown, a gate material layer (not shown in the figure) can be deposited using any of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The gate material layer covers the gate dielectric layer, the gap between the bottom first semiconductor layer 140 and the substrate 310 of the intermediate region IM, the gap between the bottom first semiconductor layer 140 and the top first semiconductor layer 240 of the intermediate region IM, and the gap between the top first semiconductor layer 240 and the second semiconductor layer 50 of the intermediate region IM. The gate material layer extends along the third direction D3 and also fills the unfilled areas between the intermediate regions IM of adjacent fin portions 350.

[0202] like Figure 36 As shown, refer to Figure 2A third mask layer (not shown in the figure) is formed on the top surface of the gate material layer. The third mask layer defines the pattern of the common gate 20 to be formed. The gate material layer is etched according to the third mask layer to form a second trench 520. The second trench 520 divides the gate material layer into multiple independently arranged common gates 20. The multiple common gates 20 are arranged along a third direction D3. The common gates 20 are arranged along a second direction D2 perpendicular to the top surface of the substrate 310. Each common gate 20 covers the surface of the first semiconductor layer 40 (bottom first semiconductor layer 140 and top first semiconductor layer 240) and the second semiconductor layer 50 in the middle region IM of each fin portion 350.

[0203] The material of the common gate 20 includes a work function metal, which may include at least one of titanium, tantalum, tungsten, or alloys thereof.

[0204] Reference Figure 1 , Figure 2 , Figure 36 The bottom first semiconductor layer 140, the top first semiconductor layer 240, and the common gate 20 form a pull-down transistor T1. The pull-down transistor T1 is a dual-gate transistor. The bottom first semiconductor layer 140 and the top first semiconductor layer 240, disposed along the first direction D1 on one side of the common gate 20, together serve as the source S1 of the pull-down transistor T1. The bottom first semiconductor layer 140 and the top first semiconductor layer 240, disposed on the other side of the common gate 20, together serve as the drain D1 of the pull-down transistor T1. The second semiconductor layer 50 and the common gate 20 form a dual-gate transistor T1. A pull-up transistor T2 is formed using a gate 20. A second semiconductor layer 50 disposed along the first direction D1 on one side of the common gate 20 serves as the source S1 of the pull-up transistor T2. A second semiconductor layer 50 disposed on the other side of the common gate 20 serves as the drain D2 of the pull-up transistor T2. The pull-down transistor T1 and the pull-up transistor T2 share the common gate 20. The source S2 of the pull-up transistor T2 and the source S1 of the pull-down transistor T1 are disposed on the same side. The drain D1 of the pull-up transistor T2 and the drain D2 of the pull-down transistor T1 are disposed on the same side.

[0205] In this embodiment, the bottom first semiconductor layer 140 and the top first semiconductor layer 240 are made of silicon. The pull-down transistor T1 is an NMOS transistor, the second semiconductor layer 50 is made of germanium, and the pull-up transistor T2 is a PMOS transistor. The hole mobility of the germanium channel of the pull-up transistor T2 is 1.2 times that of the electron mobility of the silicon channel of the pull-down transistor T1. To match the drive currents of the pull-down transistor T1 and the pull-up transistor T2, this embodiment uses two first semiconductor layers 40 to form a dual-gate pull-down transistor T1. However, the electron mobility of the silicon channel of the dual-gate pull-down transistor T1 is higher than the hole mobility of the germanium channel of the pull-up transistor T2. To further balance the drive currents of the pull-down transistor T1 and the pull-up transistor T2, the shared gate 20 in this embodiment is made of titanium nitride, which is more favorable to the pull-up transistor T2, to improve the hole mobility of the germanium channel of the pull-up transistor T2, so that the drive currents of the pull-down transistor T1 and the pull-up transistor T2 are more matched.

[0206] Then, a fifth dielectric layer 571 is formed to fill the second trench 520 and cover the top surface of the second semiconductor layer 50 and the top surface of the interlayer dielectric layer 181. The material of the second fifth dielectric layer 571 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0207] It is understood that, in other embodiments, reference is made to... Figure 29 During the formation of the dummy gate 420 in step S1201, the dummy gate material layer 410 can be etched to form multiple independently arranged dummy gates 420. These multiple dummy gates 420 are spaced apart along the third direction D3, and each dummy gate 420 covers the middle region IM of each fin portion 350. Then, referring to... Figure 30 , Figure 31 An interlayer dielectric layer 181 is formed, covering both ends of the fin-shaped portion 350 and filling the unfilled area of ​​the first trench 510. (Refer to...) Figure 36 In the process of forming the common gate 20, after removing the dummy gate 420, the common gate 20 is formed in each region where the dummy gate 420 is removed. In this way, one step of etching the gate material layer to form the second trench 520 and one step of forming the fifth dielectric layer 571 can be saved. The self-alignment and isolation of the common gate 20 can be completed in one step by forming the interlayer dielectric layer 181, saving process steps and process costs.

[0208] In step S140, a conductive plug is formed, including the following steps:

[0209] Step S141: A contact hole is formed in the interlayer dielectric layer, exposing a portion of the surface of the first semiconductor layer and the second semiconductor layer located on one side of the intermediate region.

[0210] Reference Figure 37A fourth mask layer (not shown) is formed on the fifth dielectric layer 571, defining a pattern for the contact holes to be formed. The fifth dielectric layer 571, the interlayer dielectric layer 181, and the isolation layer are etched according to the fourth mask layer to form contact holes (not shown) penetrating the interlayer dielectric layer 181. The contact holes expose a portion of the bottom first semiconductor 140, a portion of the top first semiconductor layer 240, and a portion of the second semiconductor layer 50 at one end of the fin portion 350.

[0211] Step S142: Form a conductive plug in the contact hole.

[0212] In this embodiment, the conductive plug can be formed using the following implementation method:

[0213] Reference Figure 37 and combined Figure 1 , Figure 2 First, a first barrier layer (not shown in the figure) is deposited using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The first barrier layer covers the hole wall of the contact hole (including the bottom first semiconductor 140, the top first semiconductor layer 240, and the second semiconductor layer 50 exposed by the contact hole). The material of the first barrier layer may include titanium or titanium compounds or tantalum (Ta) or tantalum compounds.

[0214] Then, a conductive material is deposited using any of the above-described deposition processes to form a first conductive material layer. This first conductive material layer covers the first barrier layer and fills the unfilled areas of the contact holes. The first conductive material layer also covers the top surface of the fifth dielectric layer 571. The first conductive material layer on the top surface of the fifth dielectric layer 571 is removed using a chemical mechanical polishing process, and the first conductive material layer located in the contact holes forms a conductive plug 30. The material of the conductive plug 30 may include metallic tungsten (W) or a tungsten compound. In this embodiment, the conductive plug 30 is separated from other film layers by the first barrier layer to prevent the metal material in the conductive plug 30 from diffusing into other film layers, causing contamination of other film layers or conductive devices, and affecting the electrical performance of the semiconductor structure.

[0215] The bottom first semiconductor 140, the top first semiconductor layer 240, and the second semiconductor layer 50 are connected by conductive plugs 30. That is, the drain D1 of the common-gate pull-down transistor T1 and the drain D2 of the pull-up transistor T2 are connected by conductive plugs 30, or the source S1 of the common-gate pull-down transistor T1 and the source S2 of the pull-up transistor T2 are connected by conductive plugs 30. The common-gate pull-down transistor T1 and the pull-up transistor T2 constitute an inverter NOT.

[0216] The memory fabrication method of this embodiment utilizes a second direction perpendicular to the top surface of the substrate to stack pull-down transistors and pull-up transistors above the substrate to form an inverter. This increases the integration density of transistors, reduces the footprint of the inverter, and increases the usable area of ​​the semiconductor structure. This is beneficial for increasing the integration density of devices in the semiconductor structure and allowing for the placement of more semiconductor devices.

[0217] It is understood that, in some embodiments, the following steps are performed concurrently with the formation of the conductive plug:

[0218] Reference Figure 37 While forming contact holes in the interlayer dielectric layer 181, a portion of the fifth dielectric layer 571, a portion of the interlayer dielectric layer 181, and a portion of the isolation layer are etched away to form a first hole and a second hole penetrating the interlayer dielectric layer 181. Along the first direction D1, the first hole and the second hole are formed at the end furthest from the contact hole. The first hole exposes a portion of the surface of the bottom first semiconductor layer 140 and a portion of the surface of the top first semiconductor layer 240, and the second hole exposes a portion of the surface of the second semiconductor layer 50.

[0219] In this embodiment, the formed first barrier layer covers the walls of the first hole and the second hole. A first conductive material layer covers the first barrier layer and fills the unfilled areas of the first and second holes. After grinding to remove the first conductive material layer on the top surface of the fifth dielectric layer 571, the first conductive material layer remaining in the first hole forms the first conductive wire 161, and the first conductive material layer remaining in the second hole forms the second conductive wire 261.

[0220] Thus, the source S1 of the pull-down transistor T1 and the source S2 of the pull-up transistor T2 of the inverter NOT are connected. The drain D1 of the pull-down transistor T1 can be led out through the first wire 161 and connected to other devices or structures. The drain S2 of the pull-up transistor T2 can be led out through the second wire 261 and connected to other devices or structures. Alternatively, the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T2 of the inverter NOT are connected. The source S1 of the pull-down transistor T1 can be led out through the first wire 161 and connected to other devices or structures. The source S2 of the pull-up transistor T2 can be led out through the second wire 261 and connected to other devices or structures.

[0221] According to an exemplary embodiment, this embodiment is a description of the above embodiment. The fin portion 350 includes a first end E1 and a second end E2 disposed opposite to each other along a first direction D1. In this embodiment, during the process of forming contact holes, contact holes are alternately formed at the first end E1 and the second end E2 of the fin portion 350 arranged along a third direction D3. Thus, the conductive plug 30 of one of the two adjacent inverters NOT along the third direction D3 is disposed at the first end E1, and the conductive plug 30 of the other inverter NOT is disposed at the second end E2.

[0222] In this embodiment, the common gate 20 shared by the pull-down transistor T1 and the pull-up transistor T2 of the inverter NOT is connected as the input terminal of the inverter NOT; the drain D1 of the pull-down transistor T1 and the drain D2 of the pull-up transistor T1 are connected through the conductive plug 30 as the output terminal of the inverter NOT; the source S1 of the pull-down transistor T1 is connected to the first wire 161, and the source S2 of the pull-up transistor T2 is connected to the second wire 261. That is, the output terminals of the two inverter NOTs adjacent to each other along the third direction D2 are arranged opposite each other.

[0223] Reference Figure 37 , Figure 38 The inverter NOT with its output terminal set at the first terminal E1 is defined as the first inverter NOT1, and the inverter NOT with its output terminal set at the second terminal E2 is defined as the second inverter NOT2. In the semiconductor structure formed in the above embodiment, the first inverter NOT1 and the second inverter NOT2 are alternately arranged along the third direction D3. After forming the conductive plug 30 in step S140, this embodiment also performs the following steps:

[0224] Step S150: Form the wiring layer.

[0225] In this embodiment, a wiring layer is formed using the following implementation method:

[0226] First, such as Figure 39 As shown, refer to Figure 37A dielectric layer 281 is formed by depositing a dielectric material using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The dielectric layer 281 covers the top surface of the fifth dielectric layer 571. The material of the dielectric layer 281 may include an ultra-low dielectric constant (ULK) material or an extra-low dielectric constant (ELK) material. The dielectric constant of the ultra-low dielectric constant (ULK) material is less than 2.4, while the dielectric constant of the extra-low dielectric constant (ELK) material is less than 3.4. Alternatively, the material of the dielectric layer 281 may also be other oxides. For example, the material of the dielectric layer 281 may include fluorinated silicate glass, polyimide, fluorinated polyimide, siloxane, or porous silica.

[0227] Reference Figure 38 , Figure 39 The first inverter NOT1 and its adjacent second inverter NOT2 are grouped together, and a dielectric layer 281 is etched to form a first connection trench (not shown) and a second connection trench (not shown) in the dielectric layer 281 above each group of first inverter NOT1 and second inverter NOT2. The first connection trench exposes the top surface of the common gate 20 of the first inverter NOT1 and the top surface of the conductive plug 30 of the second inverter NOT2, and the second connection trench exposes the top surface of the common gate 20 of the second inverter NOT2 and the top surface of the conductive plug 30 of the first inverter NOT1.

[0228] Next, a second barrier layer (not shown in the figure) is deposited using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The second barrier layer covers the walls of the first and second connection trenches and the top surface of the dielectric layer 281. The material of the second barrier layer may include titanium or titanium compounds, tantalum or tantalum compounds.

[0229] Next, as Figure 40 , Figure 41 As shown, refer to Figure 39A second conductive material layer (not shown in the figure) is deposited using any of the above-described deposition processes. This second conductive material layer covers the second barrier layer and fills the unfilled areas of the first and second connection trenches. The second conductive material layer and the second barrier layer covering the top surface of the dielectric layer 281 are removed using a chemical mechanical polishing process. The second conductive material layer located in the first connection trench forms the first interconnect 171, and the second conductive material layer located in the second connection trench forms the second interconnect 172. The materials of the first interconnect 171 and the second interconnect 172 may include tungsten or copper. In this embodiment, the first interconnect 171 and the second interconnect 172 are separated from other material layers and devices by the second barrier layer, thereby preventing the materials of the first interconnect 171 and the second interconnect 172 from diffusing to other material layers or devices, causing contamination of other material layers or devices and affecting the electrical performance of the semiconductor structure, further improving the operating life of the semiconductor structure.

[0230] The semiconductor structure formed in this embodiment has two adjacent inverter input terminals and output terminals arranged opposite each other along a third direction. This allows the inverters to be arranged more compactly, which facilitates subsequent wiring connections between inverters or between inverters and other devices. Thus, after the wiring layer is formed, the input terminal of the first inverter and the output terminal of the second inverter in each group are connected through the first interconnect line, and the output terminal of the first inverter and the input terminal of the second inverter are connected. The layout of the interconnect lines in the wiring layer is more reasonable.

[0231] According to an exemplary embodiment, this embodiment is a description of the above embodiments, and this embodiment also includes the following steps:

[0232] Step S160: Form word lines, which extend along the first direction and are positioned above the inverter.

[0233] Step S170: Form a transmission transistor. The transmission transistor is positioned above the inverter. The gate of the transmission transistor is connected to the word line. The drain of the transmission transistor is connected to the common gate of the inverter or to a conductive plug.

[0234] Step S180: Form a bit line that extends above the inverter along the second direction and is connected to the source of the transfer transistor.

[0235] Steps S160, S170, and S180 are executed after step S150. In this embodiment, word lines, transmission transistors, and bit lines are formed using the following implementation method:

[0236] First, such as Figure 42 As shown, refer to Figure 40A sixth dielectric layer 671 is deposited using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The sixth dielectric layer 671 covers the top surface of the interconnect layer 70. The material of the sixth dielectric layer 671 may include at least one of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate phosphosilicate glass (BPSG), ultra-low dielectric (ULK) material, or extra-low dielectric (ELK) material.

[0237] Then, as Figure 42 As shown, a third conductive material layer 440 is deposited using any of the above deposition processes, and the third conductive material layer 440 covers the top surface of the sixth dielectric layer 671. The material of the third conductive material layer 440 includes a conductive metal; for example, the material of the third conductive material layer 440 may include at least one of titanium or its alloy, tantalum or its alloy, or tungsten or its alloy. In this embodiment, the material of the third conductive material layer 440 includes tungsten.

[0238] Next, as Figure 43 As shown, a portion of the third conductive material layer 440 is etched away to form multiple independently configured word lines WL. The multiple word lines WL extend above multiple inverters NOT along the first direction D1, and the multiple word lines WL are spaced apart along the third direction D3.

[0239] Next, as Figure 44 As shown, a seventh dielectric layer 771 is deposited to form a layer that covers the word lines WL and fills the area between adjacent word lines WL. The material of the seventh dielectric layer 771 is the same as that of the sixth dielectric layer 671, and will not be described again here.

[0240] Next, as Figure 44 As shown and combined Figure 3 , Figure 4 A fifth mask layer (not shown) is formed on the top surface of the seventh dielectric layer 771. The fifth mask layer defines the pattern of the bit line BL to be formed. The seventh dielectric layer 771, word line WL, sixth dielectric layer 671 and dielectric layer 181 are etched layer by layer according to the fifth mask layer until the top surface of the first interconnect 171 or the top surface of the second interconnect 172 of the interconnect layer 70 is exposed, forming a trench (not shown). Each trench extends along the second direction D2 and corresponds to a word line WL. Each trench exposes the top surface of the first interconnect 171 or the top surface of the second interconnect 172.

[0241] Next, a gate oxide layer (not shown in the figure) is deposited using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The gate oxide layer covers the trench wall. The material of the gate oxide layer may include at least one of the following: alumina (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); or, the material of the gate oxide layer may include at least one of the following: hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSiON).

[0242] Next, as Figure 44 As shown and combined Figure 3 , Figure 4 Metal oxide is deposited using atomic layer deposition (ALD) to cover the gate oxide layer and fill the unfilled areas in the channel trench. The metal oxide also covers the top surface of the seventh dielectric layer 771. The metal oxide covering the top surface of the seventh dielectric layer 771 is removed using chemical mechanical polishing (CMP) or etching to form the transmission transistor T3. The metal oxide covered by the word line WL forms the channel region of the transmission transistor T3. The portion of the metal oxide below the channel region forms the drain D3 of the transmission transistor T3, and the portion of the metal oxide above the channel region forms the source S3 of the transmission transistor T3. Simultaneously, the metal oxide in the seventh dielectric layer 771 forms the bit line BL.

[0243] The transmission transistor T3 formed in this embodiment is a vertical annular channel (CAA) transistor. The gate G3 of the transmission transistor T3 surrounds and covers the periphery of the channel region C3. The gate G3 is connected to the word line WL. The source S3 of the transmission transistor T3 is located above the channel region C3 and is connected to the bit line BL. The drain D3 of the transmission transistor T3 is located below the channel region C3 and is connected to the first interconnect 170 or the second interconnect 270. It is also connected to the common gate 20 of the inverter NOT or the conductive plug 30 of the inverter NOT through the first interconnect 170 or the second interconnect 270.

[0244] The metal oxide material can be indium gallium zinc oxide (IGZO). For example, the metal oxide material can include at least one of the following: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tungsten-doped indium oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc oxide (InSnOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), and indium gallium zinc oxide (InxGayZnzOa). Zinc indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), and indium gallium silicon oxide (InGaSiO).

[0245] like Figure 44 , Figure 45 As shown, and in combination Figure 3 , Figure 4 In this embodiment, the transmission transistor T3 is an IGZO NMOS transistor, and the channel material of the transmission transistor T3 is indium gallium zinc oxide, which can reduce the leakage current of the channel region C3 of the transmission transistor T3 and improve the control of the transmission transistor T3 over the channel region C3.

[0246] In this embodiment, the word line WL located above the first inverter NOT1 is defined as the first word line WL1, and the bit line BL located above the first inverter NOT1 is defined as the first bit line BL1. The first bit line BL1 is located above the first interconnect line 171. The source S31 of the first transmission transistor T31 is connected to the first bit line BL1, and the drain D31 of the first transmission transistor T31 is connected to the common gate 20 of the first inverter NOT1.

[0247] The word line WL located above the second inverter NOT2 is defined as the second word line WL2, and the bit line BL located in the direction of the second inverter NOT2 is defined as the second bit line BL2. The second bit line BL2 and the second word line WL2 intersect perpendicularly in their extension direction above the second inverter NOT2. The source S32 of the second transmission transistor T32 is connected to the second bit line BL2, and the drain D32 of the second transmission transistor T32 is connected to the common gate 20 of the second inverter NOT2.

[0248] Thus, the first inverter NOT1 and the first transmission transistor T31 above it, the second inverter NOT2 and the second transmission transistor T32 above it together constitute a 6T static random access memory cell. In this embodiment, a semiconductor structure is formed, integrating two inverters and two transmission transistors on the area of ​​two transistors to form a 6T static random access memory cell, saving the occupied area and improving the integration density.

[0249] According to an exemplary embodiment, this embodiment is a description of the above embodiment. In this embodiment, step S110 provides a composite substrate, including the following steps:

[0250] Step S111: Provide a first substrate and a second substrate, wherein the first substrate and the second substrate include a first semiconductor material, wherein the first substrate includes a first back substrate, a first buried oxide layer and a first top substrate disposed sequentially.

[0251] Step S112: The second substrate is placed on the first top substrate, and the second substrate and the first top substrate are joined together.

[0252] Step S113: Provide a third substrate and epitaxially form an epitaxial substrate layer on the third substrate, the epitaxial substrate layer including a second semiconductor material.

[0253] Step S114: An epitaxial substrate layer is disposed on the second substrate, and the surfaces of the epitaxial substrate layer and the second substrate on the side away from the first substrate are bonded together.

[0254] Step S115: Etch away the third substrate, and the first substrate, the second substrate and the epitaxial substrate layer together form a composite substrate.

[0255] In step S111, firstly, as Figure 8 , Figure 9 As shown, a first substrate 810 and a second substrate 820 are provided. In this embodiment, both the first substrate 810 and the second substrate 820 are SOI substrates. Figure 8 As shown, the first substrate 810 includes a first back substrate 811, a first buried oxide layer 812, and a first top substrate 813 sequentially disposed therefrom. Figure 9 As shown, the second substrate 820 includes a second back substrate 821, a second buried oxide layer 822 and a second top substrate 823 disposed sequentially.

[0256] In this embodiment, both the first substrate 810 and the second substrate 820 include a first semiconductor material. Both the first substrate 810 and the second substrate 820 are silicon substrates. The materials of the first back substrate 811, the first top substrate 813, the second back substrate 821, and the second back substrate 821 all include silicon.

[0257] In step S112, as Figure 8As shown, a first oxide layer 801 is formed on the top surface of the first top substrate 813 of the first substrate 810 using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. Figure 9 As shown, a second oxide layer 802 is formed on the top surface of the second top substrate 823 of the second substrate 820. The materials of the first oxide layer 801 and the second oxide layer 802 may include at least one of silicon oxide or silicon oxynitride.

[0258] like Figure 10 As shown, the second top substrate 823 of the second substrate 820 is disposed facing the first top substrate 813 of the first substrate 810, and the second substrate 820 is disposed on the first substrate 810. The first substrate 810 and the second substrate 820 are joined and connected in a face-to-back manner through the first oxide layer 801 and the second oxide layer 802. The first oxide layer 801 and the second oxide layer 802 together form the second dielectric layer 271.

[0259] The following description uses the composite substrate 300, which includes two first semiconductor material layers 320, to illustrate this embodiment:

[0260] Hydrogen ions or helium ions are implanted into the second back substrate 821 of the second substrate 820. Then, the first substrate 810 and the second substrate 820 are annealed at 400°C to 500°C to cause the second back substrate 821 to crack in the hydrogen ion or helium ion enrichment region. Then, the cracked second back substrate 821 is peeled off. In this embodiment, the annealing process can be performed in a furnace tube.

[0261] The second back substrate 821 is polished using a chemical mechanical polishing process to completely remove the second back substrate 821 and expose the top surface of the second buried oxide layer 822.

[0262] Reference Figure 11 The second buried oxide layer 822 of the second substrate 820 is removed by cleaning with a buffered oxide etching solution, exposing the second top substrate 823. In this embodiment, the buffered oxide etching solution can be a mixture of hydrogen peroxide and hydrofluoric acid.

[0263] Reference Figure 11 A third oxide layer 803 is formed on the top surface of the second top substrate 823 using any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering processes. The material of the third oxide layer 803 may include at least one of silicon oxide or silicon oxynitride.

[0264] It is understood that in other embodiments, the composite substrate 300 formed may include only one first semiconductor material layer 320. When forming the composite substrate 300, the second substrate 820 may be omitted, and the first substrate 810 and the subsequent epitaxial substrate layer 850 may be used to form the composite substrate 300. Alternatively, in other embodiments, the composite substrate 300 formed may include three or more first semiconductor material layers 320. The second back substrate 821 of the second substrate 820 may not be removed, and the second back substrate 821 may be retained as one of the first semiconductor material layers 320 in the composite substrate 300.

[0265] In step S113, as Figure 12 As shown, a third substrate 830 is provided, the material of the third substrate 830 including the first semiconductor material, wherein the third substrate 830 can be a single silicon substrate, or the third substrate 830 can also be an SOI substrate.

[0266] In this embodiment, the third substrate 830 is an SOI substrate, which includes a third back substrate 831, a third buried oxide layer 832, and a third top substrate 833 sequentially disposed therefrom. It is understood that in other embodiments, the third substrate 830 may be a single silicon wafer.

[0267] In some embodiments, forming an epitaxial substrate layer 850 on the surface of the third substrate 830 can be achieved using the following implementation:

[0268] Reference Figure 12 , Figure 13 The third substrate 830 is placed in the reaction chamber, and the gas source of the first semiconductor material and the gas source of the second semiconductor material are introduced into the reaction chamber. An epitaxial substrate layer 850 is epitaxially grown on the top surface of the third substrate 830. During the epitaxial growth of the epitaxial substrate layer 850, the content of the gas source of the first semiconductor material introduced into the reaction chamber is gradually reduced, and the content of the gas source of the second semiconductor material introduced into the reaction chamber is gradually increased.

[0269] During the etching process to remove the third substrate 850, a portion of the epitaxial substrate layer 850 is etched away, while the top portion of the structure of the epitaxial substrate layer 850 is retained to form the composite substrate 300.

[0270] In this embodiment, germanium is used as the second semiconductor material, and germanium epitaxial layer 850 is used as the epitaxial substrate layer for this embodiment.

[0271] A third substrate 830 is placed in a reaction chamber, and silicon source gas and germanium source gas are introduced into the reaction chamber. Using the top surface of the third substrate 830 as a seed layer, a germanium-silicon layer 840 is epitaxially grown on the top surface of the third substrate 830. The material of the germanium-silicon layer 840 includes germanium-silicon SixGey, where 0≤x≤1 and 0≤y≤1. During the formation of the germanium-silicon layer 840, the content of silicon source gas introduced into the reaction chamber is gradually decreased, while the content of germanium source gas introduced into the reaction chamber is increased. Thus, the germanium concentration in the formed germanium-silicon layer 840 gradually increases from the bottom surface to the top surface.

[0272] like Figure 13 As shown, in this embodiment, during the formation of the germanium-silicon layer 840, from the bottom surface to the top surface of the germanium-silicon layer 840, the concentration of Ge in the germanium-silicon layer 840 increases in increments of 0.1. For each 0.1 increase in Ge concentration, the thickness of the germanium-silicon layer 840 increases by 0.1 μm. The concentration of Ge in the germanium-silicon layer 840 increases from 0.1 to 1, and the total thickness of the germanium-silicon layer 840 is 1 μm. The germanium-silicon layer 840 formed in this embodiment includes Si atoms sequentially disposed from the bottom surface to the top surface. 0.9 Ge 0.1 Layer, Si 0.8 Ge 0.2 Layer, Si 0.7 Ge 0.3 Layer, Si 0.6 Ge 0.4 Layer, Si 0.5 Ge 0.5 Layer, Si 0.4 Ge 0.6 Layer, Si 0.7 Ge 0.3 Layer, Si 0.8 Ge 0.2 Layer, Si 0.9 Ge 0.1 Layer. That is, the top layer of the germanium-silicon layer 840 formed in this embodiment is a germanium crystal layer.

[0273] Next, germanium source gas is introduced into the reaction chamber. Using the top surface of the germanium-silicon layer 840 as a seed layer, a germanium epitaxial layer 860 is epitaxially grown on the top surface of the germanium-silicon layer 840. In this way, the germanium epitaxial layer 860 has fewer defects and higher germanium crystal purity. In this embodiment, the thickness of the germanium epitaxial layer 860 is 100 μm.

[0274] The epitaxial substrate layer 850 formed in this embodiment includes a germanium-silicon layer 840 and a germanium epitaxial layer 860. In this embodiment, during the etching process of removing the third substrate 850, the germanium-silicon layer 840 is etched away, and the high-purity germanium epitaxial layer 860 is used to form the second semiconductor material layer 330 of the composite substrate 300.

[0275] In other embodiments, an epitaxial substrate layer 850 is formed on the surface of the third substrate 830, which can be achieved using the following methods:

[0276] Step S1131: At least one second semiconductor epitaxial layer is formed on the top surface of the third substrate, and the concentration of the second semiconductor material in the at least one second semiconductor epitaxial layer increases along the direction away from the top surface of the third substrate.

[0277] In this embodiment, the second semiconductor epitaxial layer 870 is a germanium-silicon layer. This embodiment will be described with the formation of two second semiconductor epitaxial layers 870 as an example:

[0278] Reference Figure 12 , Figure 14 First, a first and a second semiconductor epitaxial layer 871 are epitaxially formed on the top surface of the third substrate 830. For example, the third substrate 830 is placed in a reaction chamber, the reaction temperature in the reaction chamber is adjusted to 350°C~450°C, silicon source gas and germanium source gas are introduced into the reaction chamber, and the first and a second semiconductor epitaxial layer 871 are epitaxially formed on the top surface of the third substrate 830. The material of the first and a second semiconductor epitaxial layer 871 includes Si. 0.4 Ge 0.6 The thickness of the first and second semiconductor epitaxial layers 871 is 1 μm.

[0279] Then, as Figure 14 As shown, a second semiconductor epitaxial layer 872 is epitaxially formed on the top surface of the first second semiconductor epitaxial layer 871, and the concentration of germanium in the second second semiconductor epitaxial layer 872 is greater than the concentration of germanium in the first second semiconductor epitaxial layer 871. For example, the reaction temperature in the reaction chamber can be adjusted to 550℃~650℃, and the second second semiconductor epitaxial layer 872 is epitaxially formed on the top surface of the first second semiconductor epitaxial layer 871. The material of the second second semiconductor epitaxial layer 872 includes Si. 0.3 Ge 0.7 The thickness of the second semiconductor epitaxial layer 872 is 1 μm.

[0280] Step S1132: An epitaxial substrate layer is formed on the top surface of at least one second semiconductor epitaxial layer.

[0281] Reference Figure 12 , Figure 14 An epitaxial substrate layer 850 is formed on the top surface of the second semiconductor epitaxial layer 872. Using the top surface of the second semiconductor epitaxial layer 872 as a seed layer, the epitaxial substrate layer 850 is epitaxially grown on the top surface of the second semiconductor epitaxial layer 872. This results in an epitaxial substrate layer 850 with fewer defects and higher germanium crystal purity. In this embodiment, the thickness of the epitaxial substrate layer 850 is 100 μm.

[0282] In this embodiment, after the epitaxial substrate layer 850 is formed, at least one second semiconductor epitaxial layer 870 is etched away during the etching process of removing the third substrate 830.

[0283] In step S114, as Figure 15 As shown, firstly, a fourth oxide layer 804 is formed on the top surface of the epitaxial substrate 850 using any one of the following deposition processes: chemical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), high-density plasma deposition (HDP), high aspect ratio process (HARP), and plasma-enhanced chemical vapor deposition (PECVD). The material of the fourth oxide layer 804 may include at least one of silicon oxide or silicon oxynitride. This results in a higher density of the fourth oxide layer 804, a tighter bond between the fourth oxide layer 804 and the epitaxial substrate 850, and a higher bonding strength. This allows the subsequent epitaxial substrate 850 to bond more firmly to the second top substrate 823, resulting in the composite substrate 300 with the highest stability and yield, and also avoids device degradation caused by heat treatment of the composite substrate 300.

[0284] Then, as Figure 16 As shown, the epitaxial substrate 850 is disposed on the second substrate 820 with the second top substrate 823 facing the second substrate 820. The epitaxial substrate 850 and the second top substrate 823 are joined together by the third oxide layer 803 and the fourth oxide layer 804.

[0285] Next, hydrogen ions or helium ions are implanted into the third back substrate 831 of the third substrate 830. Then, the third substrate 830 is annealed at 400°C to 500°C to cause the third back substrate 831 to crack in the hydrogen or helium ion enrichment region. Then, the cracked third back substrate 831 is peeled off. In this embodiment, the annealing process can be performed in a furnace tube.

[0286] The third back substrate 831 is polished using a chemical mechanical polishing process to completely remove the third back substrate 831 and expose the top surface of the third buried oxide layer 832.

[0287] The third buried oxide layer 832 of the third substrate 830 is removed by cleaning with a buffered oxide etching solution, exposing the third top substrate 833. In this embodiment, the buffered oxide etching solution can be a mixture of hydrogen peroxide and hydrofluoric acid.

[0288] Then, the third top substrate 833 of the third substrate 830 is removed. In this embodiment, the method of removing the third top substrate 833 is the same as the method of removing the third back substrate 831, and will not be described again here.

[0289] Next, a wet process is used to remove the germanium-silicon layer 840 or at least one second semiconductor epitaxial layer 870 until the epitaxial substrate layer 850 is exposed, such as... Figure 17 As shown, a composite substrate 300 is formed. Specifically, the first back substrate 811 of the first substrate 810 serves as the substrate base 310 of the composite substrate 300; the first buried oxide layer 812 serves as the first dielectric layer 171 of the composite substrate 300; the first top substrate 813 serves as the bottom first semiconductor material layer 132 of the composite substrate 300; the first oxide layer 801 and the second oxide layer 802 together form the second dielectric layer 271 of the composite substrate 300; the second top substrate 823 of the second substrate 820 serves as the top first semiconductor material layer 232 of the composite substrate 300; the third oxide layer 803 and the fourth oxide layer 804 together form the third dielectric layer 371 of the composite substrate 300; and the epitaxial substrate layer 850 serves as the second semiconductor material layer 330 of the composite substrate 300.

[0290] The composite substrate 300 formed in this embodiment has a substrate 310 and a first semiconductor material layer 320 made of silicon, and a second semiconductor material layer 330 made of germanium. It is understood that this embodiment is merely an example of the composite substrate 300 provided in step S110. In other embodiments, the composite substrate 300 can be fabricated using any other reasonable method, and the number and materials of the first semiconductor material layer 320 and the second semiconductor material layer 330 in the composite substrate 300 can be adjusted according to the actual application.

[0291] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0292] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An inverter, disposed on the substrate, the inverter comprising: A pull-down transistor includes a first semiconductor layer extending along a first direction parallel to the top surface of the substrate. The first semiconductor layer includes a bottom first semiconductor layer and a top first semiconductor layer spaced apart along a second direction. Both the bottom first semiconductor layer and the top first semiconductor layer include a first channel region. The materials of the bottom first semiconductor layer and the top first semiconductor layer include silicon. A pull-up transistor includes a second semiconductor layer extending along the first direction and along a second direction perpendicular to the top surface of the substrate. The second semiconductor layer is disposed above the first semiconductor layer at intervals, and the second semiconductor layer includes a second channel region. The second semiconductor layer is a germanium crystal layer. A common gate is disposed on the substrate along the second direction, and the common gate covers the first channel region of the bottom first semiconductor layer and the top first semiconductor layer and the second channel region of the second semiconductor layer; A conductive plug is disposed on one side of the common gate along the first direction. The conductive plug covers a portion of the surface of the bottom first semiconductor layer and the top first semiconductor layer and a portion of the surface of the second semiconductor layer. The ends of the bottom first semiconductor layer and the top first semiconductor layer are connected to the ends of the second semiconductor layer through the conductive plug.

2. The semiconductor structure according to claim 1, characterized in that, Along the first direction, the source and drain of the pull-down transistor are disposed opposite to each other in the first semiconductor layer on both sides of the first channel region; The source and drain of the pull-up transistor are disposed opposite to each other in the second semiconductor layer on both sides of the second channel region. The source of the pull-down transistor and the source of the pull-up transistor are located on the same side, and the drain of the pull-down transistor and the drain of the pull-up transistor are located on the same side.

3. The semiconductor structure according to claim 2, characterized in that, The conductive plug is disposed on the first semiconductor layer, and the drain of the pull-down transistor and the drain of the pull-up transistor are connected through the conductive plug.

4. The semiconductor structure according to claim 1, characterized in that, Along the first direction, the two ends of the second semiconductor layer are recessed relative to the first semiconductor layer.

5. The semiconductor structure according to any one of claims 1-4, characterized in that, The conductivity type of the first semiconductor layer is opposite to that of the second semiconductor layer.

6. A memory, characterized in that, The device includes a substrate and at least one static random access memory cell disposed on the substrate. Each static random access memory cell includes a first inverter and a second inverter. The first inverter, the second inverter, and the inverter in the semiconductor structure according to any one of claims 1-5 have the same structure. The input terminal of the first inverter and the output terminal of the second inverter are connected, and the output terminal of the first inverter and the input terminal of the second inverter are connected. Each of the static random access memory units further includes: A first transmission transistor is disposed above the first inverter, and the first transmission transistor is connected to the input terminal or the output terminal of the first inverter. The second transmission transistor is disposed above the second inverter, and the second transmission transistor is connected to the output terminal or the input terminal of the second inverter.

7. The memory according to claim 6, characterized in that, The first inverter includes a first pull-down transistor, a first pull-up transistor, a first conductive plug, and a first common gate. The first pull-down transistor and the first pull-up transistor share the first common gate, and the drain of the first pull-down transistor and the drain of the first pull-up transistor are connected through the first conductive plug. The second inverter includes a second pull-down transistor, a second pull-up transistor, a second conductive plug, and a second common gate. The second pull-down transistor and the second pull-up transistor share the second common gate. The drains of the second pull-down transistor and the second pull-up transistor are connected through the second conductive plug. The second common gate is connected to the first conductive plug, and the second conductive plug is connected to the first common gate.

8. The memory according to claim 7, characterized in that, The memory also includes: At the power supply terminal, the source of the first pull-up transistor, the source of the second pull-up transistor, and the power supply terminal are connected. The ground terminal is connected to the source of the first pull-down transistor, the source of the second pull-down transistor, and the ground terminal.

9. The memory according to claim 8, characterized in that, The first transmission transistor includes a drain, a channel region, and a source arranged sequentially in a direction away from the first inverter. The first transmission transistor also includes a gate, the gate of the first transmission transistor surrounding and covering the peripheral surface of the channel region of the first transmission transistor. The drain of the first transmission transistor is connected to the first inverter. The second transmission transistor includes a drain, a channel region, and a source arranged sequentially in a direction away from the second inverter. The second transmission transistor also includes a gate, the gate of the second transmission transistor surrounding and covering the peripheral surface of the channel region of the second transmission transistor. The drain of the second transmission transistor is connected to the second inverter.

10. The memory according to claim 9, characterized in that, The memory also includes: The first bit line is connected to the source of the first transmission transistor; The first word line and the first bit line extend perpendicularly to each other, and the first word line is connected to the gate of the first transmission transistor. The second bit line is connected to the source of the second transmission transistor; The second word line extends perpendicularly to the second bit line, and the second word line is connected to the gate of the second transmission transistor.

11. A method for manufacturing a memory, characterized in that, Includes the following steps: A composite substrate is provided, the composite substrate comprising a substrate substrate, at least one first semiconductor material layer and at least one second semiconductor material layer stacked thereon, adjacent first semiconductor material layers and / or second semiconductor material layers being spaced apart, the first semiconductor material layer and the second semiconductor material layer having opposite conductivity types; the material of the first semiconductor material layer includes silicon; the second semiconductor material layer is a germanium crystal layer; the first semiconductor material layer includes a bottom first semiconductor material layer and a top first semiconductor material layer spaced apart along a second direction; The composite substrate is etched to form a plurality of fins, the fins extending along a first direction and the fins being spaced apart along a third direction, the first direction and the third direction being parallel to the top surface of the substrate, the bottom first semiconductor material layer retained in the fins forming a bottom first semiconductor layer, the top first semiconductor material layer retained in the fins forming a top first semiconductor layer, and the second semiconductor material layer retained in the fins forming a second semiconductor layer; A common gate is formed, which extends on the substrate along a second direction perpendicular to the top surface of the substrate. The common gate covers the surface of the bottom first semiconductor layer, the surface of the top first semiconductor layer, and the surface of the second semiconductor layer located in the middle region of the fin portion, forming a common-gate pull-down transistor and a pull-up transistor. A conductive plug is formed along the first direction. The conductive plug is disposed on one side of the fin portion. The conductive plug covers a portion of the surface of the bottom first semiconductor layer and the top first semiconductor layer and a portion of the surface of the second semiconductor layer. The ends of the bottom first semiconductor layer and the top first semiconductor layer are connected to the ends of the second semiconductor layer through the conductive plug. The pull-down transistor and the pull-up transistor are connected through the conductive plug to form an inverter.

12. The method for manufacturing a memory according to claim 11, characterized in that, Before forming the common gate, the following steps are also included: A pseudo-gate is formed, which extends along the third direction and covers the middle region of the fins arranged along the third direction; The fin exposed by the dummy gate is etched to remove part of the fin. A gap is formed between adjacent first semiconductor layers and / or second semiconductor layers along the second direction to expose the surfaces of the first semiconductor layer and the second semiconductor layer outside the intermediate region. An interlayer dielectric layer is formed, which covers the first semiconductor layer and the second semiconductor layer outside the intermediate region and fills the gap between the first semiconductor layer and / or the second semiconductor layer.

13. The method for manufacturing a memory according to claim 12, characterized in that, Forming a common gate includes: Remove the pseudo-gate to expose the fin-shaped portion of the intermediate region; Etching removes a portion of the fin in the intermediate region, exposing the surfaces of the first semiconductor layer and the second semiconductor layer in the intermediate region; A gate dielectric layer is formed, which covers the surfaces of the first semiconductor layer and the second semiconductor layer in the intermediate region; The common gate is formed, which covers the gate dielectric layer and fills the region between the first semiconductor layer and / or the second semiconductor layer in the intermediate region.

14. The method for manufacturing a memory according to claim 13, characterized in that, Forming a conductive plug includes: A contact hole is formed in the interlayer dielectric layer, the contact hole exposing a portion of the surface of the first semiconductor layer and the second semiconductor layer located on one side of the intermediate region; The conductive plug is formed in the contact hole.

15. The method for manufacturing a memory according to claim 11, characterized in that, The method for manufacturing the memory also includes the following steps: A word line is formed, the word line extends along the first direction, and the word line is correspondingly positioned above the inverter; A transmission transistor is formed, the transmission transistor is disposed above the inverter, the gate of the transmission transistor is connected to the word line, and the drain of the transmission transistor is connected to the common gate of the inverter or the conductive plug. A bit line is formed, the bit line extending above the inverter along the second direction, and the bit line is connected to the source of the transmission transistor; Along the third direction, two transmission transistors are connected to two adjacent inverters, the drain of one of the transmission transistors is connected to the common gate of one inverter, and the drain of the other transmission transistor is connected to the conductive plug of the other inverter.

16. The method for manufacturing a memory according to claim 11, characterized in that, Provide a composite substrate, including: A first substrate and a second substrate are provided, the first substrate and the second substrate comprising a first semiconductor material, wherein the first substrate comprises a first back substrate, a first buried oxide layer and a first top substrate disposed sequentially; The second substrate is disposed on the first top substrate, and the second substrate and the first top substrate are joined together. A third substrate is provided, and an epitaxial substrate layer is epitaxially formed on the third substrate, the epitaxial substrate layer comprising a second semiconductor material; The epitaxial substrate layer is disposed on the second substrate, and the surfaces of the epitaxial substrate layer and the second substrate on the side away from the first substrate are bonded together; The third substrate is removed by etching, and the first substrate, the second substrate, and the epitaxial substrate layer together form the composite substrate.

17. The method for manufacturing a memory according to claim 16, characterized in that, An epitaxial substrate layer is formed on the third substrate, including: The third substrate is placed in the reaction chamber, and the gas sources of the first semiconductor material and the second semiconductor material are introduced into the reaction chamber. The epitaxial substrate layer is grown on the top surface of the third substrate. During the epitaxial growth of the epitaxial substrate layer, the content of the gas source of the first semiconductor material introduced into the reaction chamber is gradually reduced, and the content of the gas source of the second semiconductor material introduced into the reaction chamber is gradually increased. During the etching process to remove the third substrate, a portion of the epitaxial substrate layer is etched away, leaving a portion of the top structure of the epitaxial substrate layer to form the composite substrate.

18. The method for manufacturing a memory according to claim 16, characterized in that, An epitaxial substrate layer is formed on the third substrate, including: At least one second semiconductor epitaxial layer is formed on the top surface of the third substrate, and the concentration of the second semiconductor material in the at least one second semiconductor epitaxial layer increases along the direction away from the top surface of the third substrate; The epitaxial substrate layer is formed epitaxially on the top surface of at least one second semiconductor epitaxial layer; During the etching process to remove the third substrate, at least one layer of the second semiconductor epitaxial layer is etched away.

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