Dual-CDR receiving and transmitting integrated chip suitable for inter-satellite link

Abstract

The invention discloses a dual-CDR receiving and transmitting integrated chip suitable for an inter-satellite link, belongs to the field of inter-satellite link optical communication and integrated circuits, and aims to solve the problem that an existing optical module cannot be used for inter-satellite link optical communication. The chip is manufactured by a continuous mode receiving unit CMRX, a continuous mode transmitting unit CM TX and a digital control unit Digital on the same wafer substrate. The receiving end of the continuous mode receiving unit CM RX and the transmitting end of the continuous mode transmitting unit CM TX are both provided with equalizers, and the equalizers add high-frequency component optimization signals into attenuated electric signals transmitted from a superior to prevent the signals from being degraded during inter-satellite link transmission; the continuous mode receiving unit CM RX and the continuous mode transmitting unit CM TX are both internally provided with high-speed CDRs which are used for recovering degraded signals in the inter-satellite link transmission process; the digital control unit Digital adopts an anti-space radiation logic subunit design, configures the continuous mode receiving unit CM RX and the continuous mode transmitting unit CM TX, and optimizes the eye pattern transmission quality.

Description

Technical Field

[0001] The invention relates to a dual-CDR transceiver integrated chip suitable for an intersatellite link, and belongs to the field of intersatellite link optical communication and integrated circuits. Background Art

[0002] In satellite communication systems, satellites have two types of communication links. One is the space-to-earth link, and the other is the space-to-space link. On the space-to-space link, optical communication can achieve large-capacity data transmission, such as Figure 1 As shown in Figure 1, low earth orbit LEO satellites can transmit data to medium earth orbit MEO satellites, and medium earth orbit MEO satellites can also transmit data to each other. In the space-earth link, high-band radio waves are used to pass through the atmosphere to achieve large-capacity communication.

[0003] Intersatellite link refers to the link used for communication between satellites. It is also called interstellar link or crosslink. The communication methods of intersatellite link can also be divided into optical communication and radio communication. The choice of wireless link or optical link depends on many factors such as technology, funds, and payload weight. When the transmission rate is lower than 1Mbps, it is advantageous to use wireless link, and when the transmission rate is higher than 50Mbps, it is advantageous to use optical link.

[0004] There are three basic stages in intersatellite link optical communication:

[0005] ① Capture: At the beginning, satellite A uses a high-power laser generator TX to generate a wide light beam to scan the location area of ​​the receiver RX installed on satellite B. When satellite B receiver RX receives the signal, it enters the tracking phase and transmits the receiving signal to satellite A in that direction. After satellite A receives the signal returned by satellite B, the transmitter of satellite A also enters the tracking phase.

[0006] ② Tracking: At this time, the optical beam is reduced to normal width and the laser transmitter TX of satellite A changes to continuous operation mode. At this stage, to provide complete tracking, the pointing error control equipment must allow platform motion and relative motion between the two satellites.

[0007] ③Communication: Information exchange between two satellites.

[0008] In the all-optical network solution for intersatellite links, the optical module completes the reception of high-speed optical signals (RX) and quickly generates modulated current to drive the laser to transmit (TX) optical signals; it is common to separate the two functional chips and design them separately, and finally fix both of them on a PCB board at the same time, and connect peripheral devices with a metal layer to realize the transceiver function of optical signals. The TIA (transimpedance amplifier) ​​converts the received weak optical signal into an electrical signal and amplifies it. In the RX receiving chip, the limiting amplifier LA further amplifies the electrical signal to the limiting state. In the TX transmitting chip, the LDD laser driver generates a modulated current to drive the laser to emit or extinguish to transmit the optical signal. This design scheme of two independent functional chips makes the volume of the optical module relatively large.

[0009] In the harsh space environment, small size, light weight and low power consumption are the primary basic requirements for electronic devices, but existing optical modules cannot meet this requirement; secondly, existing optical modules are mostly used in short-distance scenarios, and the signal will not be degraded due to long-distance transmission, so the existing optical modules do not consider signal degradation well; thirdly, there are particle rays in space, and some high-energy particles will bombard the chip. The digital part of the chip is more susceptible to logical errors than the analog part, and the existing optical modules do not involve this aspect of design and are not suitable for intersatellite link optical communications. Summary of the invention

[0010] In view of the problem that the existing optical modules cannot be used for inter-satellite link optical communication, the present invention provides a dual CDR transceiver integrated chip suitable for inter-satellite links.

[0011] The dual CDR transceiver integrated chip suitable for intersatellite links of the present invention is manufactured by a continuous mode receiving unit CMRX, a continuous mode transmitting unit CM TX and a digital control unit Digital on the same wafer substrate;

[0012] The receiving end of the continuous mode receiving unit CM RX and the transmitting end of the continuous mode transmitting unit CM TX are both provided with an equalizer, which adds a high-frequency component to the attenuated electrical signal transmitted from the upper stage to optimize the signal, so as to prevent the signal from being degraded during the intersatellite link transmission;

[0013] The high-speed CDR built into both the continuous mode receiving unit CM RX and the continuous mode transmitting unit CM TX is used to recover the degraded signal during the inter-satellite link transmission;

[0014] The digital control unit Digital adopts a space radiation-resistant logic sub-unit design to configure the continuous mode receiving unit CMRX and the continuous mode transmitting unit CM TX to optimize the eye diagram transmission quality.

[0015] Preferably, the continuous mode receiving unit CM RX includes an equalizer EQ, a limiting amplifier LA, a peak detection module peak detector, a clock data recovery module CDR, a signal bypass module Bypass and a pre-emphasis output driver module Emphasis Driver;

[0016] The equalizer EQ adds the attenuated electrical signal output by the chip's upper-level TIA to the high-frequency component optimization signal, and then divides the optimized signal into two paths. One path is directly transmitted to the next module, the limiting amplifier LA, which gradually amplifies the small-amplitude electrical signal into a high- and low-level signal with a full swing. The other path is transmitted to the peak detection module peak detector, which synchronously detects the amplitude of the signal. Only when the amplitude meets the threshold requirement, the module outputs an instruction to start the output of the pre-emphasis output driver module Emphasis Driver, and at the same time transmits the judgment result to the host outside the chip;

[0017] When the signal is not degraded, the output signal of the limiting amplifier LA is directly output to the pre-emphasis output driver module Emphasis Driver through the signal bypass module Bypass. When the signal is degraded, the clock data recovery module CDR is turned on to obtain a clock consistent with the signal rate. The clock is used to recover a signal with better quality and then output to the pre-emphasis output driver module Emphasis Driver.

[0018] Preferably, the continuous mode transmitting unit CM TX includes an equalizer EQ, a clock data recovery module CDR, a signal bypass module Bypass, an eye crossing point adjustment module CPA, a laser driver LDD and a bias current control module Bias CurrentControl;

[0019] The electrical signal data stream of the host is received, and the attenuated electrical signal data stream is first added with a high-frequency component optimization signal through the equalizer EQ. When the signal is not degraded, the output optimization signal of the equalizer EQ is directly output to the next module, the eye crossing point adjustment module CPA, through the signal bypass module Bypass. When the signal is degraded, the clock data recovery module CDR is turned on to obtain a clock consistent with the signal rate, and the clock is used to recover a signal with better quality and then output to the eye crossing point adjustment module CPA; the eye crossing point adjustment module CPA optimizes the eye crossing point of the output signal of the clock data recovery module CDR or the signal bypass module Bypass, and the optimized signal drives the aerospace laser to emit and extinguish through the laser driver LDD to realize data transmission in the universe; the bias current control module Bias Current Control is used to provide bias current for the aerospace laser.

[0020] Preferably, the continuous mode transmitting unit CM TX further comprises a digital-to-analog converter ADC, which is used to convert quantifiable data into digital quantities and feed them back to the digital control unit Digital. The quantifiable data includes but is not limited to ambient temperature, monitoring current value, bias current value and modulation current value.

[0021] Preferably, the digital control unit Digital includes a control register digital core Register ControlDigital Core, a high-precision analog-to-digital converter ADC and a slave I 2 C Slave I2C;

[0022] The data fed back by the ADC is transmitted from the I 2 C Slave I2C data signal line SDA reads into external or chip internal register;

[0023] The register digital core Register Control Digital Core communicates with the satellite control unit through two signal lines SCL and SDA. The register digital core also realizes the configuration of the continuous mode transmitting unit CM TX and the continuous mode transmitting unit CM TX through the control port.

[0024] Preferably, the control ports configured for the continuous mode receiving unit CM RX in the digital control unit Digital include a continuous equalizer adjustment port EQ, a signal loss threshold setting port LOS_TH and an output swing adjustment port OP_SWING.

[0025] Preferably, the control ports of the continuous mode transmitting unit CM TX configured in the digital control unit Digital include a continuous equalizer adjustment port EQ, an eye diagram shaping port EYE_SHAPING, a TX signal detection port TX_SD, a modulation current control port IMOD, an automatic optical power control port APC, a bias current control port IBIAS and an eye diagram crossing point adjustment port CPA.

[0026] Beneficial effects of the present invention: The present invention proposes an overall framework structure of a dual CDR 10Gbps rate transceiver integrated chip suitable for intersatellite links. After solving the problems of the prior art, the continuous mode RX part, the continuous mode TX part, and the Digital part designed with anti-space radiation logic subunits are combined together to form a chip. High-speed CDRs are built into both the receiving and transmitting channels. When data is degraded during intersatellite transmission, the CDR module can be turned on to restore data with better quality. Conversely, non-degraded signals can also be directly transmitted through the Bypass path. The above design architecture makes this chip suitable for use in harsh space environments, and the integrated receiving and transmitting ends reduce the size of the optical module, which is beneficial to reducing the volume and mass of the satellite.

[0027] The digital part of the present invention adopts a space radiation resistant logic sub-unit design, which can ensure the correctness of the logic function even in the space full of high-energy particle rays.

[0028] The integrated chip of the present invention is small in size and light in weight, can cope with the complex, changeable and harsh space environment, and can transmit data information through light between satellites at a rate of 10Gbps. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the application scenario of this chip;

[0030] Figure 2 It is a specific structural schematic diagram of the dual CDR transceiver integrated chip suitable for intersatellite links described in the present invention. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0033] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0034] Specific implementation method 1: The following is combined Figure 1 and Figure 2 The present embodiment is described. The dual CDR transceiver chip suitable for intersatellite links described in the present embodiment integrates the continuous mode 10Gbps rate RX and the continuous mode 10Gbps rate TX on the same wafer within the chip framework, and then cooperates with the digital module to optimize the eye diagram transmission quality, thereby greatly reducing the bit error rate of the output signal; the dual CDR design restores the degraded signal after transmission through the PCB board or space into a signal with better quality, and the digital part inside the transceiver chip adopts a space radiation-resistant logic subunit design, coupled with aerospace-specific optoelectronic sensors, so that the chip can send and receive data between satellites at a rate of 10Gbps in harsh space environments, making the chip more suitable for space environments. The above is the key to the implementation of the invention.

[0035] See also Figure 1, the transceiver chip used in intersatellite links is a one-to-one optical communication between satellite A and satellite B. The continuous mode receiver is built into the transceiver chip, and its rate is 10Gbps. The chip is made of a continuous mode receiving unit CM RX, a continuous mode transmitting unit CM TX and a digital control unit Digital on the same wafer substrate;

[0036] The receiving end of the continuous mode receiving unit CM RX and the transmitting end of the continuous mode transmitting unit CM TX are both provided with an equalizer, which adds a high-frequency component to the attenuated electrical signal transmitted from the upper stage to optimize the signal, so as to prevent the signal from being degraded during the intersatellite link transmission;

[0037] The high-speed CDR built into both the continuous mode receiving unit CM RX and the continuous mode transmitting unit CM TX is used to recover the degraded signal during the inter-satellite link transmission;

[0038] The digital control unit Digital adopts a space radiation-resistant logic sub-unit design to configure the continuous mode receiving unit CMRX and the continuous mode transmitting unit CM TX to optimize the eye diagram transmission quality.

[0039] The continuous mode receiving unit CM RX includes an equalizer EQ, a limiting amplifier LA, a peak detection module peakdetector, a clock data recovery module CDR, a signal bypass module Bypass and a pre-emphasis output driver module EmphasisDriver;

[0040] The equalizer EQ adds the attenuated electrical signal output by the upper-level TIA of the chip to the high-frequency component optimization signal, and then divides the optimized signal into two paths. One path is directly transmitted to the next module, the limiting amplifier LA, which gradually amplifies the small-amplitude electrical signal into a high- and low-level signal with a full swing. The other path is transmitted to the peak detection module peak detector, which synchronously detects the amplitude of the signal. Only when the amplitude meets the threshold requirement, the module outputs an instruction to turn on the output of the pre-emphasis output driver module Emphasis Driver, and at the same time transmits the judgment result to the host outside the chip; the output stage Emphasis Driver with pre-emphasis function adds a certain amplitude of overshoot on the rising edge of the signal to cope with the attenuation of the signal on the PCB board.

[0041] When the signal is not degraded, the output signal of the limiting amplifier LA is directly output to the pre-emphasis output driver module Emphasis Driver through the signal bypass module Bypass. When the signal is degraded, the clock data recovery module CDR is turned on to obtain a clock consistent with the signal rate. The clock is used to recover a signal with better quality and then output to the pre-emphasis output driver module Emphasis Driver.

[0042] The continuous mode transmitting unit CM TX includes an equalizer EQ, a clock data recovery module CDR, a signal bypass module Bypass, an eye crossing point adjustment module CPA, a laser driver LDD and a bias current control module Bias CurrentControl;

[0043] The main channel can receive the electrical signal data stream of the host, and the rate of the data stream is 10Gbps. The attenuated electrical signal data stream is first added with a high-frequency component optimization signal through the equalizer EQ. When the signal is not degraded, the output optimization signal of the equalizer EQ is directly output to the next module, the eye crossing point adjustment module CPA, through the signal bypass module Bypass. When the signal is degraded, the clock data recovery module CDR is turned on to obtain a clock consistent with the signal rate, and the clock is used to recover a signal with better quality and then output to the eye crossing point adjustment module CPA; the eye crossing point adjustment module CPA optimizes the eye crossing point of the output signal of the clock data recovery module CDR or the signal bypass module Bypass. The optimized signal drives the aerospace laser to emit and extinguish through the laser driver LDD to realize data transmission in the universe; the bias current control module Bias Current Control is used to provide bias current for the aerospace laser.

[0044] Aerospace lasers transmit data in the universe by emitting light and extinguishing it, so an output current driver LDD is required inside the TX. The laser bias current IBIAS and modulation current IMOD need to adjust the current in real time according to the ambient temperature, laser luminous efficiency, and laser aging. Therefore, the Current Control module cooperates with the APC optical power control module to feedback the laser luminous power information collected by the monitoring photodiode MPD, and then configures a reasonable current value by writing the data in the digital part.

[0045] The continuous mode transmitting unit CM TX also includes a digital-to-analog converter ADC, which is used to convert quantifiable data into digital quantities and feed them back to the digital control unit Digital. The quantifiable data includes but is not limited to ambient temperature, monitoring current value, bias current value and modulation current value.

[0046] The digital control unit Digital adopts the design of space radiation-resistant logic subunits. There are particle rays in space, and some high-energy particles will bombard the chip. The digital part is more susceptible to logical errors than the analog part. Therefore, the logic unit of the digital part has been specially processed to cope with this situation, which improves the reliability of the digital part in space. Specifically, the digital control unit Digital includes a control register digital core Register Control DigitalCore, a high-precision analog-to-digital converter ADC and an I 2 C Slave I2C;

[0047] The data fed back by the ADC is transmitted from the I 2 C Slave I2C data signal line SDA reads the data into the external or internal register of the chip; users can also use the external master I 2 C writes digital values ​​to the register RegisterControl Digital core inside the chip to optimize the transmission performance of the transceiver chip. The digital part also adds digital diagnostics monitoring (DDM) function to monitor light level, chip temperature, power supply voltage and other data in real time.

[0048] The register digital core Register Control Digital Core communicates with the satellite control unit through two signal lines SCL and SDA. The register digital core also realizes the configuration of the continuous mode transmitting unit CM TX and the continuous mode transmitting unit CM TX through the control port.

[0049] The control ports of the continuous mode receiving unit CM RX configured in the digital control unit Digital include a continuous equalizer adjustment port EQ, a signal loss threshold setting port LOS_TH and an output swing adjustment port OP_SWING.

[0050] The control ports of the continuous mode transmitting unit CM TX configured in the digital control unit Digital include a continuous equalizer adjustment port EQ, an eye shaping port EYE_SHAPING, a TX signal detection port TX_SD, a modulation current control port IMOD, an automatic optical power control port APC, a bias current control port IBIAS and an eye crossing point adjustment port CPA.

[0051] See also Figure 2 The present invention provides an example, a dual CDR 10Gbps transceiver integrated chip suitable for an intersatellite link includes a continuous mode receiving unit CM RX, a continuous mode transmitting unit CM TX and a digital control unit Digital,

[0052] The continuous mode receiving unit CM RX includes an equalizer EQ, a limiting amplifier LA, a peak detection module peakdetector, a clock data recovery module CDR, a signal bypass module Bypass and a pre-emphasis output driver module EmphasisDriver;

[0053] The positive input pin RXINP of the CM RX part is connected to the equalizer EQ1 input terminal;

[0054] The inverting input pin RXINN of the CM RX part is connected to the equalizer EQ1 input terminal;

[0055] The two output ends of the equalizer EQ are simultaneously connected to the two input ends of the peak detector and the two input ends of the limiting amplifier LA;

[0056] The two output ends of the limiting amplifier LA are simultaneously connected to the two input ends of the signal bypass module Bypass and the two input ends of the clock data recovery module CDR;

[0057] The two input ends of the pre-emphasis output driver Emphasis Driver are simultaneously connected to the two output ends of the signal bypass Bypass and the two output ends of the clock data recovery CDR;

[0058] The two output ends of the pre-emphasis output driver module Emphasis Driver come from the chip pins RXOUTP and RXOUTN respectively;

[0059] The output end of the peak detector module is connected to the on / off control end of the pre-emphasis output driver module EmphasisDriver and the chip pin RX_LOS at the same time;

[0060] The continuous mode transmitting unit CM TX includes an equalizer EQ, a clock data recovery module CDR, a signal bypass module Bypass, an eye crossing point adjustment module CPA, a laser driver LDD, a digital-to-analog converter ADC and a bias current control module Bias Current Control;

[0061] The chip pins TXINP and TXINN are respectively connected to the two input terminals of the equalizer EQ of the CM TX part;

[0062] The two output ends of the equalizer EQ are simultaneously connected to the two input ends of the signal bypass module Bypass and the two input ends of the clock data recovery module CDR;

[0063] Two input ends of the eye crossing point adjustment module CPA are simultaneously connected to two output ends of the signal bypass module Bypass and two output ends of the clock data recovery module CDR;

[0064] Two output ends of the eye crossing point adjustment module CPA are connected to two input ends of the laser driver LDD;

[0065] The two output ends of the laser driver LDD are connected to the chip pins TXOUTP and TXOUTN;

[0066] The output end of the bias current control module Bias Current Control is connected to the chip pin IBIAS;

[0067] The input end of the automatic optical power control module APC is connected to the chip pin monitoring current MPD;

[0068] The output port TEMP of the temperature sensor Temp Sensor is connected to the input port of the digital-to-analog converter ADC; the converted digital code value is output to Digital;

[0069] The output port of the MPD monitoring current is connected to the input port of the digital-to-analog converter ADC; the converted digital code value is output to Digital;

[0070] The IBIAS bias current output port is connected to the input port of the digital-to-analog converter ADC; the converted digital code value is output to Digital;

[0071] The sampled output of the power supply voltage VCC is connected to the input port of the digital-to-analog converter ADC; the converted digital code value is output to Digital;

[0072] The digital control unit Digital includes a control register digital core Register Control Digital Core, a high-precision analog-to-digital converter ADC and a slave I 2 C Slave I2C;

[0073] From I 2 C Slave I 2 The input end of C is connected to the chip pin SCL;

[0074] From I 2 C Slave I 2 The input and output ports of C are connected to the chip pin SDA;

[0075] From I 2 C Slave I 2 The output port of C is directly connected to the input port of the control register digital core Register ControlDigital Core;

[0076] The control register digital core Register Control Digital Core outputs control signals to: jitter optimization EQ, signal loss threshold setting LOS_TH, and output swing adjustment OP_SWING respectively;

[0077] The control register digital core Register Control Digital Core outputs control signals to: jitter optimization EQ, TX signal detection TX_SD, automatic optical power control APC, eye diagram crossing point adjustment CPA, bias current IBIAS, modulation current IMOD, eye diagram shaping EYE_SHAPING respectively;

[0078] The DDM digital diagnosis module is embedded in the Register Control Digital Core, uses ADC to collect key information, and then transmits the information to the outside of the chip through the SDA pin.

[0079] The dual CDR 10Gbps transceiver chip suitable for intersatellite links proposed in the present invention can be used for optical communication transmission between two satellites in the interstellar space. The dual CDR structure in the chip is conducive to the transceiver chip working in the harsh environment of the universe. After receiving the degraded signal, it can still restore the data signal with good quality. The transmitter and the receiver are designed with an equalizer EQ to add high-frequency components to the signal to avoid degradation during signal transmission. The DDM function is enabled to monitor the working status inside the chip in real time. If overheating and overload occur, the chip will be automatically shut down. The most important thing is the digital part designed with anti-space radiation logic subunits, which can still ensure the correctness of the logic function even in space full of high-energy particle rays. In summary, the chip can cope with the complex, changeable and harsh space environment, and transmit data information between satellites through light at a rate of 10Gbps.

[0080] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that the features described in conjunction with a single embodiment may be used in other described embodiments.

Claims

1. A dual CDR transceiver integrated chip suitable for intersatellite links, characterized in that: The chip is manufactured by the continuous mode receiving unit CMRX, the continuous mode transmitting unit CM TX and the digital control unit Digital on the same wafer substrate; The receiving end of the continuous mode receiving unit CM RX and the transmitting end of the continuous mode transmitting unit CM TX are both provided with an equalizer, which adds a high-frequency component to the attenuated electrical signal transmitted from the upper stage to optimize the signal, so as to prevent the signal from being degraded during the intersatellite link transmission; The high-speed CDR built into both the continuous mode receiving unit CM RX and the continuous mode transmitting unit CM TX is used to recover the degraded signal during the inter-satellite link transmission; The digital control unit Digital adopts a space radiation-resistant logic sub-unit design to configure the continuous mode receiving unit CM RX and the continuous mode transmitting unit CM TX to optimize the eye diagram transmission quality.

2. The dual CDR transceiver integrated chip suitable for intersatellite links according to claim 1, characterized in that: The continuous mode receiving unit CM RX includes an equalizer EQ, a limiting amplifier LA, a peak detection module peak detector, a clock data recovery module CDR, a signal bypass module Bypass and a pre-emphasis output driver module Emphasis Driver; The equalizer EQ adds the attenuated electrical signal output by the chip's upper-level TIA to the high-frequency component optimization signal, and then divides the optimized signal into two paths. One path is directly transmitted to the next module, the limiting amplifier LA, which gradually amplifies the small-amplitude electrical signal into a high- and low-level signal with a full swing. The other path is transmitted to the peak detection module peak detector, which synchronously detects the amplitude of the signal. Only when the amplitude meets the threshold requirement, the module outputs an instruction to start the output of the pre-emphasis output driver module Emphasis Driver, and at the same time transmits the judgment result to the host outside the chip; When the signal is not degraded, the output signal of the limiting amplifier LA is directly output to the pre-emphasis output driver module Emphasis Driver through the signal bypass module Bypass. When the signal is degraded, the clock data recovery module CDR is turned on to obtain a clock consistent with the signal rate. The clock is used to recover a signal with better quality and then output to the pre-emphasis output driver module Emphasis Driver.

3. The dual CDR transceiver integrated chip suitable for intersatellite links according to claim 2, characterized in that: The continuous mode transmitting unit CM TX includes an equalizer EQ, a clock data recovery module CDR, a signal bypass module Bypass, an eye crossing point adjustment module CPA, a laser driver LDD and a bias current control module Bias Current Control; The electrical signal data stream of the receiving host is firstly added with a high-frequency component optimization signal through the equalizer EQ to the attenuated electrical signal data stream. When the signal is not degraded, the output optimization signal of the equalizer EQ is directly output to the next module, the eye crossing point adjustment module CPA, through the signal bypass module Bypass. When the signal is degraded, the clock data recovery module CDR is turned on to obtain a clock consistent with the signal rate, and the clock is used to recover a signal with better quality and then output to the eye crossing point adjustment module CPA; The eye crossing point adjustment module CPA optimizes the eye crossing point of the output signal of the clock data recovery module CDR or the signal bypass module Bypass. The optimized signal drives the aerospace laser to light up and extinguish through the laser driver LDD to realize data transmission in the universe. The Bias Current Control module is used to provide bias current for aerospace lasers.

4. The dual CDR transceiver integrated chip suitable for intersatellite links according to claim 3, characterized in that: The continuous mode transmitting unit CM TX also includes a digital-to-analog converter ADC, which is used to convert quantifiable data into digital quantities and feed them back to the digital control unit Digital. The quantifiable data includes but is not limited to ambient temperature, monitoring current value, bias current value and modulation current value.

5. The dual CDR transceiver integrated chip suitable for intersatellite links according to claim 4, characterized in that: The digital control unit Digital includes a control register digital core Register Control Digital Core, a high-precision analog-to-digital converter ADC and a slave I 2 C Slave I2C; The data fed back by the ADC is transmitted from the I 2 C Slave I2C data signal line SDA reads into external or chip internal register; The register digital core Register Control Digital Core communicates with the satellite control unit through two signal lines SCL and SDA. The register digital core also realizes the configuration of the continuous mode transmitting unit CM TX and the continuous mode transmitting unit CM TX through the control port.

6. The dual CDR transceiver integrated chip suitable for intersatellite links according to claim 5, characterized in that: The control ports of the continuous mode receiving unit CM RX configured in the digital control unit Digital include a continuous equalizer adjustment port EQ, a signal loss threshold setting port LOS_TH and an output swing adjustment port OP_SWING.

7. The dual CDR transceiver integrated chip suitable for intersatellite links according to claim 5, characterized in that: The control ports of the continuous mode transmitting unit CM TX configured in the digital control unit Digital include a continuous equalizer adjustment port EQ, an eye shaping port EYE_SHAPING, a TX signal detection port TX_SD, a modulation current control port IMOD, an automatic optical power control port APC, a bias current control port IBIAS and an eye crossing point adjustment port CPA.

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