Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel, and relates to the technical field of display, wherein the array substrate comprises a substrate, a plurality of sub-pixels, a first metal trace and a second metal trace; the plurality of sub-pixels are arranged on the surface of the substrate at intervals, and a non-display area is arranged between two adjacent sub-pixels; each sub-pixel comprises a main area and a secondary area; the main area comprises a first pixel electrode; and the secondary area comprises a second pixel electrode; the first metal trace is electrically connected with the first pixel electrode and the second pixel electrode, and is used for providing a first voltage signal for the first pixel electrode and the second pixel electrode; the second metal trace is electrically connected with the first pixel electrode or the second pixel electrode, and is used for providing a second voltage signal for the first pixel electrode or the second pixel electrode; and the first metal trace and the second metal trace are both located in the non-display area. The application solves the problem that the existing metal trace is arranged in the display area, thereby causing the high reflectivity of the display panel, and improves the display effect of the display panel.

Description

Array substrate and display panel Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] With the development of LCD technology and the increasing demands of users for the display effect of LCD panels, more and more users require display panels to provide a good visual experience even in strong light environments. Therefore, it is necessary to reduce the reflection of display panels in strong light environments in order to achieve higher contrast and brightness.

[0003] To improve display quality, existing display panels have changed from the traditional 4-domain design to an 8-domain design. In the traditional 4-domain design, each sub-pixel of the display panel is divided into a main / sub region, and each main and sub region contains two sub-pixel electrodes. Each sub-pixel electrode can be used to independently control the alignment direction of liquid crystal molecules. The 8-domain design, based on the 4-domain design, divides the pixel electrodes of the main and sub regions into four sub-pixel electrodes each, meaning each sub-pixel has eight domains.

[0004] By placing gate lines and multiple thin-film transistors (TFTs) between the main and sub-regions, and electrically connecting the TFTs to data lines located on one side of the main and sub-regions, the data lines provide a first operating voltage of the same value to the sub-pixel electrodes of both the main and sub-regions. Simultaneously, metal traces are placed within the main and sub-regions, and these metal traces are electrically connected to the sub-pixel electrodes of the sub-regions via TFTs, providing a second operating voltage to the sub-pixel electrodes. Therefore, different voltage values ​​can be achieved for the sub-pixel electrodes of the main and sub-regions, thereby enabling independent display control of the eight domains of each sub-pixel. This reduces brightness and contrast variations caused by viewing angle changes, improving the display effect.

[0005] However, since the main area and sub area are equipped with metal traces, and the materials of the metal traces are generally metals such as Al, Ti, Mo or Cu, which have high reflectivity, the reflectivity of the panel is also increased accordingly, affecting the display effect of the display panel. Summary of the Invention

[0006] The main objective of this invention is to provide an array substrate and display panel that aims to solve the problem of high reflectivity in existing display panels.

[0007] To achieve the above objectives, the present invention proposes an array substrate comprising a substrate, a plurality of sub-pixels, a first metal trace, and a second metal trace; the plurality of sub-pixels are arranged at intervals on the surface of the substrate, with a non-display area between two adjacent sub-pixels; each sub-pixel includes a main area and a secondary area, the main area including a first pixel electrode, and the secondary area including a second pixel electrode; the first metal trace is electrically connected to both the first pixel electrode and the second pixel electrode, and is used to provide a first voltage signal to the first pixel electrode and the second pixel electrode; the second metal trace is electrically connected to either the first pixel electrode or the second pixel electrode, and is used to provide a second voltage signal to either the first pixel electrode or the second pixel electrode; wherein, both the first metal trace and the second metal trace are located in the non-display area.

[0008] In one embodiment of the present invention, each of the non-display areas is provided with a first metal trace and a second metal trace, and the first metal trace and the second metal trace of each of the non-display areas are electrically connected to two adjacent sub-pixels respectively.

[0009] In one embodiment of the present invention, each of the non-display areas is provided with two first metal traces or two second metal traces, and the first metal traces and second metal traces electrically connected to each sub-pixel are respectively located in two adjacent non-display areas.

[0010] In one embodiment of the present invention, the main area and the secondary area are both spaced apart along a first direction, and the extension directions of the first metal trace and the second metal trace are parallel to the first direction.

[0011] In one embodiment of the present invention, the first metal trace and the second metal trace are respectively disposed close to the two sub-pixels adjacent to the non-display area.

[0012] In one embodiment of the present invention, the array substrate further includes a plurality of common electrodes. Each main region and each secondary region are provided with a common electrode. The common electrode of each main region and the first pixel electrode form a first storage capacitor. The common electrode of each secondary region and the second pixel electrode form a second storage capacitor. The first storage capacitor and the second storage capacitor are respectively used to stabilize the voltage of the first pixel electrode and the second pixel electrode.

[0013] In one embodiment of the present invention, the common electrode is a closed rectangular frame.

[0014] In one embodiment of the present invention, the common electrode includes a first segment, a second segment, and a third segment connected in sequence, the first segment, the second segment, and the third segment enclosing a rectangular frame with an opening.

[0015] In one embodiment of the present invention, the sub-pixel includes a first metal layer, a second metal layer, a color resist layer and an electrode layer sequentially stacked on the surface of the substrate;

[0016] The first metal layer is disposed on the surface of the substrate and includes the common electrode; the second metal layer includes the first metal trace and the second metal trace; and the electrode layer includes the first pixel electrode and the second pixel electrode.

[0017] In each of the non-display areas, a first via and a second via are formed on the side opposite to the substrate, penetrating the electrode layer and the color resist layer. The inner walls of the first via and the second via are plated with a conductive layer. The first metal trace is electrically connected to the first pixel electrode through the conductive layer, and the second metal trace is electrically connected to the second pixel electrode through the conductive layer.

[0018] The present invention also proposes a display panel, the display panel comprising a color filter substrate, a liquid crystal layer, and an array substrate as described above; the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

[0019] The array substrate proposed in this invention includes a substrate, multiple sub-pixels, a first metal trace, and a second metal trace. The multiple sub-pixels are arranged at intervals on the surface of the substrate along a direction parallel to the substrate, with the area between two adjacent sub-pixels being a non-display area. Each sub-pixel includes a main region and a secondary region. The main region includes a first pixel electrode, and the secondary region includes a second pixel electrode. The first and second pixel electrodes are respectively used to cooperate with a color filter electrode to form an electric field to adjust the arrangement of the liquid crystal molecule layer. The first metal trace is electrically connected to both the first and second pixel electrodes and provides a first voltage signal to both electrodes. The second metal trace is electrically connected to either the first or second pixel electrode and provides a second voltage signal to either electrode. Therefore, the voltage of the first pixel electrode in the main region can be different from the voltage of the second sub-pixel in the secondary region, thereby achieving independent display control of the main and secondary regions.

[0020] The first and second metal traces are both placed in the non-display area. Since the non-display area of ​​the display panel is equipped with a black matrix, that is, the first and second metal traces are placed in the positive projection area of ​​the black matrix onto the substrate, the black matrix can absorb light, thereby solving the problem of high reflectivity of the display panel caused by placing the existing metal traces in the display area and improving the display effect. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0022] Figure 1 is a schematic diagram of an embodiment of the array substrate provided by the present invention;

[0023] Figure 2 is a schematic diagram of another embodiment of the array substrate provided by the present invention;

[0024] Figure 3 is a schematic diagram of another embodiment of the array substrate provided by the present invention;

[0025] Figure 4 is a cross-sectional view of Figure 3 at point AA;

[0026] Figure 5 is a cross-sectional view of Figure 3 at point BB;

[0027] Figure 6 is a schematic diagram of another embodiment of the array substrate provided by the present invention.

[0028] Explanation of icon numbers:

[0029] 10. Substrate; 20. Subpixel; 21. Main area; 22. Secondary area; 23. Non-display area; 201. First pixel electrode; 202. Second pixel electrode; 210. First metal layer; 220. Second metal layer; 230. Insulating layer; 240. Color resist layer; 250. Electrode layer; 260. Conductive layer; 270. First via; 280. Second via; 30. First metal trace; 40. Second metal trace; 50. Common electrode; 60. Liquid crystal layer; 70. Transparent conductive film layer; 80. Glass substrate.

[0030] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0033] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0034] This invention proposes an array substrate.

[0035] Referring to Figures 1 to 6, in one embodiment of the present invention, the array substrate includes a substrate 10, a plurality of sub-pixels 20, a first metal trace 30, and a second metal trace 40; the plurality of sub-pixels 20 are spaced apart on the surface of the substrate 10, and a non-display area 23 is located between two adjacent sub-pixels 20; each sub-pixel 20 includes a main area 21 and a secondary area 22, the main area 21 includes a first pixel electrode 201, and the secondary area 22 includes a second pixel electrode 202; the first metal trace 30 is electrically connected to both the first pixel electrode 201 and the second pixel electrode 202, and is used to provide a first voltage signal to the first pixel electrode 201 and the second pixel electrode 202; the second metal trace 40 is electrically connected to either the first pixel electrode 201 or the second pixel electrode 202, and is used to provide a second voltage signal to either the first pixel electrode 201 or the second pixel electrode 202; wherein, both the first metal trace 30 and the second metal trace 40 are located in the non-display area 23.

[0036] In this embodiment, the substrate 10 can be a glass substrate 10 or other transparent substrate material, such as a plastic substrate. Glass has good transparency and mechanical strength, making it suitable for TFT-LCD display panels. Plastic substrates, on the other hand, are lightweight and flexible, making them suitable for flexible display panels.

[0037] Multiple sub-pixels 20 are arranged in an array on the surface of the substrate 10, parallel to the substrate 10. These sub-pixels 20 constitute the display area of ​​the display panel. The size of each sub-pixel 20 can be adjusted according to the resolution and pixel density of the display panel. The width of the non-display area 23 between two adjacent sub-pixels 20 can be adjusted according to actual needs, typically between 10 and 20 micrometers. A light-shielding layer (i.e., a black matrix) is also provided in the non-display area 23 of the display panel to prevent light from two adjacent sub-pixels 20 from interfering with each other, thereby improving the contrast of the display panel. At the same time, other auxiliary film layers, such as an insulating layer 230 and a protective layer, are also provided in the non-display area 23 to enhance the stability and reliability of the structure.

[0038] Each sub-pixel 20 is divided into a main region 21 and a secondary region 22, which respectively include a first pixel electrode 201 and a second pixel electrode 202. The first pixel electrode 201 and the second pixel electrode 202 are made of ITO (indium tin oxide), which has good conductivity and transparency. The main region 21 and the secondary region 22 can each be provided with multiple pixel electrodes. For example, in one embodiment, the main region 21 includes four first pixel electrodes 201, and the secondary region 22 includes four second pixel electrodes 202, meaning each sub-pixel 20 has eight domains. Each pixel electrode consists of multiple spaced electrode lines, and the extension directions of the electrode lines in the four pixel electrodes of the main region 21 and the secondary region 22 are set differently. For example, the electrode lines of the four first pixel electrodes 201 of the main region 21 can extend along the horizontal direction, the vertical direction, the left diagonal direction, and the right diagonal direction, respectively, and the electrode lines of the four second pixel electrodes 202 of the secondary region 22 can also extend along these four directions, but the directions can be different to achieve different electric field distributions. Each pixel electrode works in conjunction with the color filter electrode to adjust the arrangement of liquid crystal molecules. This configuration allows for independent adjustment of the display effect between the first pixel electrode 201 and the second pixel electrode 202.

[0039] A gate line and a thin-film transistor are disposed between the main region 21 and the secondary region 22. Specifically, each main region 21 and secondary region 22 is provided with a main region 21 thin-film transistor, a secondary region 22 thin-film transistor, and a third thin-film transistor. The source of the main region 21 thin-film transistor is electrically connected to the first metal trace 30, the drain of the main region 21 thin-film transistor is electrically connected to the first pixel electrode 201, and the gate of the main region 21 thin-film transistor is electrically connected to the gate line. Under the signal drive of the gate line, the main region 21 thin-film transistor is turned on and transmits the first voltage signal of the first metal trace 30 to the first pixel electrode 201, so that the first pixel electrode 201 has a first voltage. The source of the secondary region 22 thin-film transistor is electrically connected to the first metal trace 30, the drain of the secondary region 22 thin-film transistor is electrically connected to the second pixel electrode 202, and the gate of the secondary region 22 thin-film transistor is electrically connected to the gate line. Driven by the signal from the gate line, the thin-film transistor in the secondary region 22 is turned on, transmitting the first voltage signal from the first metal trace 30 to the second pixel electrode 202, so that the second pixel electrode 202 has a first voltage. The source of the third thin-film transistor is electrically connected to the second metal trace 40, the drain of the third thin-film transistor is electrically connected to the second pixel electrode 202, and the gate of the third thin-film transistor is electrically connected to the gate line. Driven by the signal from the gate line, the third thin-film transistor is turned on, transmitting the second voltage signal from the second metal trace 40 to the second pixel electrode 202, so that the second pixel electrode 202 has a second voltage. Therefore, the voltage value of the first pixel electrode 201 depends on the first voltage, and the voltage of the second pixel electrode 202 depends on the sum of the first voltage and the second voltage. Thus, by changing the magnitude of the second voltage, the rotation angle of the liquid crystal molecule corresponding to the first pixel electrode 201 relative to the liquid crystal molecule corresponding to the second pixel electrode 202 can be adjusted.

[0040] Therefore, the function of the first metal trace 30 (i.e., the data line) is to provide a first voltage signal to the first pixel electrode 201 and the second pixel electrode 202, ensuring the normal operation of each sub-pixel 20. The function of the second metal trace 40 (i.e., the share bar line) is to achieve different voltages between the main region 21 and the sub-region 22, thereby achieving different voltages for multiple pixel electrodes in the main region 21 and the sub-region 22, and thus controlling the different arrangements of liquid crystal molecules. In this way, independent display control of the eight domains of each sub-pixel 20 can be achieved, reducing brightness and contrast changes caused by viewing angle variations and improving the display effect.

[0041] The first metal trace 30 and the second metal trace 40 can be made of metals such as aluminum (Al), titanium (Ti), molybdenum (Mo), or copper (Cu), possessing good conductivity and mechanical strength. The width and thickness of the traces can be adjusted according to actual needs, typically between 2-5 micrometers. The first metal trace 30 and the second metal trace 40 are disposed on the same layer to improve processing efficiency and reduce processing costs. The first metal trace 30 and the second metal trace 40 are connected to the first pixel electrode 201 and the second pixel electrode 202 through vias. The material of the vias can be the same as that of the metal traces to ensure good conductivity and reliability. An insulating layer 230 can be disposed between the first metal trace 30 and the second metal trace 40 to prevent short circuits. The material of the insulating layer 230 can be silicon dioxide (SiO2), silicon nitride (SiN), etc.

[0042] The first metal trace 30 and the second metal trace 40 are both located in the non-display area 23. Since the non-display area 23 of the display panel has a light-shielding layer that absorbs light and has low reflectivity to external light, placing the first metal trace 30 and the second metal trace 40 within the orthogonal projection area of ​​the black matrix onto the substrate 10 solves the problem of high reflectivity of the display panel caused by placing metal traces in the display area, thus improving the display effect. It also avoids the metal traces in the display area blocking the light emitted by the backlight source transmitted through the display area, thereby increasing the aperture ratio of the display panel.

[0043] Referring to Figure 3, in one embodiment of the present invention, each non-display area 23 is provided with a first metal trace 30 and a second metal trace 40, and the first metal trace 30 and the second metal trace 40 of each non-display area 23 are electrically connected to two adjacent sub-pixels 20 respectively.

[0044] In this embodiment, since the first metal trace 30 and the second metal trace 40 are both disposed within the same metal layer, and the main region 21 thin-film transistor, the secondary region 22 thin-film transistor, and the third thin-film transistor are all disposed between the main region 21 and the secondary region 22, both the first metal trace 30 and the second metal trace 40 need to extend electrical connection lines between the main region 21 and the secondary region 22. Therefore, the first metal trace 30 and the second metal trace 40 of each non-display area 23 are electrically connected to two adjacent sub-pixels 20, which avoids the crossing of the first metal trace 30 and the second metal trace 40 and thus avoids the problem of short circuit. In addition, since the first metal trace 30 and the second metal trace 40 of each non-display area 23 are connected to different sub-pixels 20, it is also convenient to place the first metal trace 30 and the second metal trace 40 close to the electrically connected sub-pixels 20, thereby increasing the number of first metal traces 30 and second metal traces 40 and further reducing the occurrence of short circuit.

[0045] As shown in Figures 1 and 2, in one embodiment of the present invention, each non-display area 23 is provided with two first metal traces 30 or two second metal traces 40, and the first metal traces 30 and the second metal traces 40 electrically connected to each sub-pixel 20 are respectively located in two adjacent non-display areas 23.

[0046] In this embodiment, each non-display area 23 is provided with two identical metal traces, as shown in Figures 1 and 2. The two first metal traces 30 in one non-display area 23 are electrically connected to the second pixel electrodes 202 of the two sub-pixels 20 on the left and right sides, respectively. The two second metal traces 40 in the adjacent non-display area 23 are electrically connected to the first pixel electrodes 201 and the second pixel electrodes 202 of the two sub-pixels 20 on the left and right sides, respectively. The metal traces of multiple non-display areas 23 are arranged sequentially according to the above arrangement of the two non-display areas 23.

[0047] Referring to Figures 1 to 3, in one embodiment of the present invention, the main region 21 and the secondary region 22 are both spaced apart along a first direction, and the extension directions of the first metal trace 30 and the second metal trace 40 are parallel to the first direction.

[0048] In this embodiment, the first direction is the vertical direction shown in Figure 1. The first metal trace 30 and the second metal trace 40 are both disposed within the non-display area 23 parallel to the first direction, and both are parallel to the first direction. This design facilitates the layout of the first metal trace 30 and the second metal trace 40 within the non-display area 23, simplifies wiring design, reduces wiring complexity, and minimizes signal interference between different metal traces. Furthermore, since the thin-film transistors and gate lines are disposed between the main area 21 and the secondary area 22, the first metal trace 30 and the second metal trace 40 are parallel to the first direction and disposed on one side of the sub-pixel 20 to facilitate the connection of the first metal trace 30 and the second metal trace 40 with each thin-film transistor.

[0049] Referring to Figures 1 to 3, in one embodiment of the present invention, the first metal trace 30 and the second metal trace 40 are respectively disposed close to the two sub-pixels 20 adjacent to the non-display area 23.

[0050] In this embodiment, the width of the non-display area 23 is generally around 15µm, and the width of the first metal trace 30 and the second metal trace 40 is generally 2-5µm. The first metal trace 30 and the second metal trace 40 are positioned close to the two sub-pixels 20 adjacent to the non-display area 23, meaning the spacing between the two metal traces within the non-display area 23 is set as large as possible. This facilitates the deposition of two metal traces within the same non-display area 23 and avoids short circuits between the two metal traces. Simultaneously, it reduces signal interference between the two metal traces, especially in high-resolution and high-refresh-rate applications, better maintaining signal integrity and stability. Furthermore, positioning the first metal trace 30 and the second metal trace 40 close to the two sub-pixels 20 adjacent to the non-display area 23 reduces the spacing between the metal traces and the sub-pixels 20, thereby reducing the signal transmission path length, lowering signal attenuation and noise interference, and improving signal transmission efficiency and stability.

[0051] Referring to Figures 1 to 3, in one embodiment of the present invention, the array substrate further includes a plurality of common electrodes 50. Each main region 21 and each secondary region 22 is provided with a common electrode 50. The common electrode 50 of each main region 21 and the first pixel electrode 201 form a first storage capacitor. The common electrode 50 of each secondary region 22 and the second pixel electrode 202 form a second storage capacitor. The first storage capacitor and the second storage capacitor are respectively used to stabilize the voltage of the first pixel electrode 201 and the second pixel electrode 202.

[0052] In this embodiment, in practical applications, the voltage on the first pixel electrode 201 and the second pixel electrode 202 may fluctuate due to factors such as voltage signal transmission delay and noise interference of the first metal trace 30 and the second metal trace 40. Furthermore, during display, the pixel electrodes are not constantly electrically conductive; instead, multiple pixel electrodes are frequently switched on and off according to the display requirements. The common electrode 50 disposed in the main area 21 and the secondary area 22 forms a first storage capacitor and a second storage capacitor with the first pixel electrode 201 and the second pixel electrode 202, respectively. The main function of the first storage capacitor and the second storage capacitor is to maintain the voltage stability of the first pixel electrode 201 and the second pixel electrode 202.

[0053] Specifically, when the first metal trace 30 provides a first voltage signal to the first pixel electrode 201 and the second pixel electrode 202, the first voltage signal is simultaneously stored in the corresponding first and second storage capacitors. Even if the first metal trace 30 stops providing the first voltage signal, the charge in the first and second storage capacitors will continue to maintain the voltage on the first pixel electrode 201 and the second pixel electrode 202, thereby keeping the deflection state of the corresponding liquid crystal molecules unchanged, thus improving the image display quality of the display panel. Especially in high-resolution and high-refresh-rate applications, this optimized layout can better maintain display integrity and stability.

[0054] Furthermore, the common electrode 50 is electrically connected to the color filter electrode so that their voltages are the same, so that no electric field is formed between the common electrode 50 and the color filter electrode, thereby avoiding affecting the angle of the liquid crystal molecules between the common electrode 50 and the color filter electrode.

[0055] Referring to Figure 1, in one embodiment of the present invention, the common electrode 50 is a closed rectangular frame, and the orthographic projections of the common electrode 50 of the main region 21 and the secondary region 22 onto the surface of the substrate 10 are located at the outer edges of the first pixel electrode 201 and the second pixel electrode 202, respectively.

[0056] In this embodiment, the common electrode 50 is designed as a closed rectangular frame. When both the main region 21 and the secondary region 22 are provided with multiple pixel electrodes, the common electrode 50 can form a first storage capacitor with each of the multiple pixel electrodes to keep the deflection state of the liquid crystal molecules between the different pixel electrodes and the color filter electrode unchanged. Meanwhile, since the common electrode 50 is made of metal, the common electrodes 50 of the main region 21 and the secondary region 22 are respectively located at the outer edges of the first pixel electrode 201 and the second pixel electrode 202 to reduce the impact of the common electrode 50 on the reflectivity of the central display area of ​​the main region 21 and the secondary region 22.

[0057] Referring to Figures 2 and 3, in one embodiment of the present invention, the common electrode 50 includes a first segment, a second segment, and a third segment connected in sequence. The first segment, the second segment, and the third segment enclose a rectangular frame with an opening. The orthographic projection of the common electrode 50 of the main region 21 and the secondary region 22 onto the surface of the substrate 10 is located on the outer periphery of the first pixel electrode 201 and the second pixel electrode 202, respectively.

[0058] In this embodiment, the common electrode 50 is designed as a rectangular frame with an opening to further reduce the area of ​​the common electrode 50, thereby further reducing the impact of the common electrode 50 on the reflectivity of the central display areas of the main area 21 and the secondary area 22. The opening of the rectangular common electrode 50 can face another main area 21 or secondary area 22 of the same sub-pixel 20, or it can face the non-display area 23 or another main area 21 or secondary area 22 away from the same sub-pixel 20. As shown in Figures 2 and 3, in one embodiment, the opening of the rectangular frame of the common electrode 50 of the main area 21 is designed to face the side away from the secondary area 22, and the opening of the rectangular frame of the common electrode 50 of the secondary area 22 is designed to face the side away from the main area 21. This design allows the common electrode 50 to be located as close as possible to the central area of ​​the same sub-pixel 20, so as to ensure the effect of the common electrode 50 in the central area on maintaining the deflection state of the liquid crystal molecules.

[0059] As shown in Figures 4 and 5, in one embodiment of the present invention, the sub-pixel 20 includes a first metal layer 210, a second metal layer 220, a color resist layer 240 and an electrode layer 250 sequentially stacked on the surface of the substrate 10.

[0060] The first metal layer 210 is disposed on the surface of the substrate 10. The first metal layer 210 includes a common electrode 50. The second metal layer 220 includes a first metal trace 30 and a second metal trace 40. The electrode layer 250 includes a first pixel electrode 201 and a second pixel electrode 202.

[0061] In each non-display area 23, a first via 270 and a second via 280 are formed on the side opposite to the substrate 10, penetrating the electrode layer 250 and the color resist layer 240. The first metal trace 30 and the second metal trace 40 are exposed in the first via 270 and the second via 280, respectively. The inner walls of the first via 270 and the second via 280 are plated with a conductive layer 260. The first metal trace 30 is electrically connected to the first pixel electrode 201 through the conductive layer 260, and the second metal trace 40 is electrically connected to the second pixel electrode 202 through the conductive layer 260.

[0062] In this embodiment, the array substrate has a multilayer structure. The first metal layer 210 is provided with a common electrode 50, gate lines, etc. The common electrode 50 and the gate lines can be made of the same metal to improve processing convenience. The second metal layer 220 includes first metal traces 30 and second metal traces 40 spaced apart. Since they are also on the same layer, the first metal traces 30 and second metal traces 40 can also be made of the same metal to improve processing convenience. The color resist layer 240 is used to realize color display and includes color resists for red, green, and blue. The first pixel electrode 201 and the second pixel electrode 202 are disposed on the electrode layer 250 to control the deflection of liquid crystal molecules.

[0063] Insulating layers 230 are provided between the first metal layer 210 and the second metal layer 220, between the second metal layer 220 and the color resist layer 240, between the color resist layer 240 and the electrode layer 250, and between each metal line in the first metal layer 210 and the second metal layer 220. The insulating layers 230 are used to isolate the electrical connections between the layers, prevent short circuits, and ensure stable signal transmission.

[0064] By setting a first via 270 and a second via 280 in the non-display area 23, and electroplating or depositing a conductive layer 260 within the first via 270 and the second via 280, electrical connection between the first metal trace 30 and the second metal trace 40 and the pixel electrode is achieved. The first via 270 and the second via 280 are inverted trapezoidal in shape. During the etching process, the inverted trapezoidal structure is easier to form, reducing the problem of uneven etching and improving the production yield. At the same time, the inverted trapezoidal via design can increase the contact area between the via wall and the conductive layer 260 and reduce the tilt angle of the conductive layer 260, thereby improving the reliability of the conductive layer 260 adhering to the via wall. The conductive layer 260 can be made of the same material as the first metal trace 30 and the second metal trace 40 to improve the reliability of the connection between the conductive layer 260 and the first metal trace 30 and the second metal trace 40.

[0065] The present invention also proposes a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate. The specific structure of the array substrate is as described in the above embodiments. Since the display panel adopts all the technical solutions of all the above-described array substrate embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0066] The liquid crystal layer 60 is sandwiched between the color filter substrate and the array substrate. The color filter substrate includes a glass substrate 80 and a transparent conductive thin film layer 70 disposed on the side of the glass substrate 80 facing the liquid crystal layer 60. The liquid crystal layer 60 is composed of liquid crystal molecules. Under the action of an electric field, the transparent conductive thin film side 70 and the electrode layer 250 control the deflection of the liquid crystal molecules, thereby regulating the light transmitted through the liquid crystal layer 60 to achieve image display. Because this application places the second metal trace 40 in the array substrate in the non-display area 23 and optimizes the shape of the common electrode 50, the reflectivity of the display panel is reduced, thereby improving the display effect of the display panel.

[0067] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. An array substrate, characterized in that, The array substrate includes: a substrate; a plurality of sub-pixels, the plurality of sub-pixels being arranged at intervals on the surface of the substrate, with a non-display area between two adjacent sub-pixels, each sub-pixel including a main area and a secondary area, the main area including a first pixel electrode, the secondary area including a second pixel electrode; a first metal trace, the first metal trace being electrically connected to both the first pixel electrode and the second pixel electrode, and used to transmit a first voltage signal to the first pixel electrode and the second pixel electrode, so that the first pixel electrode and the second pixel electrode respectively have a first voltage; and a second metal trace, the second metal trace being made of a metal material, the second metal trace being electrically connected to either the first pixel electrode or the second pixel electrode, and used to transmit a second voltage signal to either the first pixel electrode or the second pixel electrode, so that it has a second voltage; wherein, both the first metal trace and the second metal trace are located in the non-display area.

2. The array substrate as described in claim 1, characterized in that, Each of the non-display areas is provided with the first metal trace and the second metal trace, and the first metal trace and the second metal trace of each of the non-display areas are electrically connected to two adjacent sub-pixels respectively.

3. The array substrate as described in claim 1, characterized in that, Each of the non-display areas is provided with two first metal traces or two second metal traces, and the first metal traces and second metal traces electrically connected to each sub-pixel are respectively located in two adjacent non-display areas.

4. The array substrate as described in any one of claims 1 to 3, characterized in that, The main area and the secondary area are both spaced apart along a first direction, and the extension directions of the first metal trace and the second metal trace are parallel to the first direction.

5. The array substrate as described in any one of claims 1 to 3, characterized in that, The first metal trace and the second metal trace are respectively positioned close to the two sub-pixels adjacent to the non-display area.

6. The array substrate as described in any one of claims 1 to 3, characterized in that, The array substrate further includes multiple common electrodes. Each main region and each secondary region is provided with a common electrode. The common electrode of each main region and the first pixel electrode form a first storage capacitor. The common electrode of each secondary region and the second pixel electrode form a second storage capacitor. The first storage capacitor and the second storage capacitor are used to stabilize the voltage of the first pixel electrode and the second pixel electrode, respectively.

7. The array substrate as described in claim 6, characterized in that, The common electrode is in the shape of a closed rectangle.

8. The array substrate as described in claim 6, characterized in that, The common electrode includes a first segment, a second segment, and a third segment connected in sequence, which together form a rectangular frame with an opening.

9. The array substrate as described in claim 6, characterized in that, The sub-pixel includes a first metal layer, a second metal layer, a color resist layer, and an electrode layer sequentially stacked on the surface of the substrate. The first metal layer is disposed on the surface of the substrate and includes the common electrode. The second metal layer includes the first metal trace and the second metal trace. The electrode layer includes the first pixel electrode and the second pixel electrode. Each non-display area has a first via and a second via that penetrate the electrode layer and the color resist layer on the side opposite to the substrate. The inner walls of the first via and the second via are plated with a conductive layer. The first metal trace is electrically connected to the first pixel electrode through the conductive layer, and the second metal trace is electrically connected to the second pixel electrode through the conductive layer.

10. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate as described in any one of claims 1 to 9; the liquid crystal layer is sandwiched between the color filter substrate and the array substrate.

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