Sampling system of relay protection device

Abstract

The invention relates to the technical field of intelligent substations, and provides a relay protection device sampling system which comprises a mutual inductor, a master CPU module and a slave CPU module. The mutual inductor isolates and converts the secondary current of the power system into small signals which are respectively collected by the A / D conversion chips in the master CPU module and the slave CPU module; each of the master CPU module and the slave CPU module comprises an RC filter circuit; an operational amplifier follower circuit; an A / D conversion chip; the FPGA is provided with a voltage monitoring module; a synchronous sampling pulse module; an A / D conversion control module; a serial transceiver module; a tolerance comparison module; and a CPU. According to the method, the single fault tolerance of the sampling signal chain of the relay protection device can be effectively improved, and the probability of protection maloperation is reduced. When a single element of the sampling signal chain fails, the FPGA can timely sense the failure and notify the CPU to take an alarm locking measure so as to remind the equipment that the equipment needs to be maintained to prevent operation refusing.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent substations, and in particular to a sampling system for a relay protection device. Background Art

[0002] The relay protection device is responsible for quickly cutting off the fault in the power system, isolating the faulty equipment from the system to prevent damage to the faulty equipment, while reducing the scope of the fault and minimizing the harm caused by the fault. The reliability of the relay protection device directly affects the stable operation of the power system. It must not only operate reliably when a primary equipment fails, but also not malfunction when the primary equipment is not faulty.

[0003] Sampling is the cornerstone of relay protection. The sampling signal chain includes signal transmission (transformer), signal conditioning (filtering and following), analog-to-digital conversion (A / D), sampling control and algorithm logic (FPGA / CPU), etc. It is composed of many discrete components and a small number of large-scale integrated circuits. The current national standard requires that the relay protection device should operate continuously without fault for no less than 12 years. During this period, component failure is inevitable. If the possibility of component error is not fully considered and countermeasures are not taken during the design stage, the failure of a single component may cause protection refusal or malfunction.

[0004] To enhance the reliability of the sampling signal chain, the industry has adopted a dual-CPU module architecture in hardware in high-voltage relay protection devices. Each module has an independent sampling circuit, and the logic results of the dual CPUs are connected to the logic output to reduce the risk of false operation. At the same time, in order to prevent refusal to operate, the HMI (human-machine interface) is arranged to perform a dual-channel redundant data consistency comparison and alarm lockout after an abnormality.

[0005] However, the current design still cannot fully meet the requirements of fault safety. The sampling signal chains of the dual CPUs share the power supply and transformer, and there are two common cause failure points. Taking the failure of the current transformer (TA) as an example, the failure will cause the dual CPU sampling to be abnormal at the same time. The dual CPU architecture cannot identify this failure and may malfunction. The current design does not meet the provisions of GB / T14285-2006 "Technical Regulations for Relay Protection and Safety Automatic Devices" that "Except for the output relay, when any component in the device is damaged, the device should not malfunction and trip." In addition, there is a lack of information interaction between the two sets of sampling signal chains, and the judgment of inconsistent sampling between the two channels can only be achieved indirectly through the HMI, with poor real-time performance. Summary of the invention

[0006] The purpose of the present invention is to solve at least one technical problem in the background technology and provide a sampling system for a relay protection device.

[0007] To achieve the above object, the present invention provides a sampling system for a relay protection device, comprising: a current transformer, a master CPU module and a slave CPU module;

[0008] The current transformer isolates and transforms the secondary current of the power system into a small signal for collection by the A / D conversion chips in the main CPU module and the slave CPU module respectively;

[0009] The main CPU module and the slave CPU module both include:

[0010] RC filter circuit to filter out potential high-frequency signals to avoid frequency aliasing;

[0011] The operational amplifier follower circuit enhances the signal output by the RC filter circuit and improves the quality of the signal collected by the A / D conversion chip;

[0012] A / D conversion chip performs analog-to-digital conversion, and the conversion result is sent through the serial port, generating a CRC check code for each frame of data sent;

[0013] FPGA, which features:

[0014] The voltage monitoring module uses the A / D conversion control circuit in the FPGA to monitor the operating power supply of the operational amplifier follower circuit and the A / D conversion chip, and notifies the CPU when encountering abnormal conditions such as overvoltage or undervoltage of the power supply;

[0015] Synchronous sampling pulse module: the FPGA on the master CPU module sends second pulses to the slave CPU module through the synchronous sampling pulse module, thus realizing synchronous sampling between the master CPU module and the slave CPU module;

[0016] A / D conversion control module: FPGA controls the A / D conversion chip to perform A / D conversion and A / D sampling through the A / D conversion control module according to the acquisition density required by the protection function, and then reads the A / D conversion data through the serial port, and performs CRC check on each frame of data;

[0017] Serial transceiver module, the two FPGAs on the master CPU module and the slave CPU module respectively send their own sampling data to each other through the serial transceiver module, and receive the sampling point data sent by the other party at the same time;

[0018] Tolerance comparison module: two FPGAs on the master CPU module and the slave CPU module respectively synchronize the two groups of sampling data in the master CPU module and the slave CPU module in the buffer through the sequence number, and then perform tolerance comparison between the two groups of sampling data through the tolerance comparison module to determine whether the two groups of sampling data are consistent;

[0019] The CPU performs logical judgment and processing based on the output signal of the FPGA to prevent protection from refusing to operate or malfunctioning.

[0020] According to one aspect of the present invention, the current transformer has a single primary winding and a double secondary winding, which are used for data collection by two A / D conversion chips of a main CPU module and a slave CPU module.

[0021] According to one aspect of the present invention, the RC filter circuit is a second-order RC low-pass circuit with a -3dB cutoff frequency of 270 Hz.

[0022] According to one aspect of the present invention, the A / D conversion chip is a SAR structure, with ±10V input and a serial port output of conversion results. The A / D conversion chip has a hardware CRC for serial communication error detection.

[0023] According to one aspect of the present invention, the voltage monitoring module utilizes the A / D conversion control circuit in the FPGA to monitor the operational amplifier follower circuit and the A / D conversion chip working power supply, and notifies the CPU when the voltage deviates from the rated value by ±3%.

[0024] According to one aspect of the present invention, the FPGA on the main CPU module sends a second pulse to the synchronous sampling pulse module in the FPGA on the slave CPU module through the synchronous sampling pulse module. The synchronous sampling pulse module in the FPGA on the slave CPU module divides the pulse into equal parts as a sampling time sequence, thereby realizing synchronous sampling between the main CPU module and the slave CPU module.

[0025] According to one aspect of the present invention, the pulse accuracy of the synchronous sampling pulse modules in the master CPU module and the slave CPU module in sending and receiving synchronous pulses is ±2 μs.

[0026] According to one aspect of the present invention, the sampling frequency of the A / D conversion control module for A / D sampling is between 4 and 12 kHz.

[0027] According to one aspect of the present invention, the A / D conversion control module triggers A / D sampling according to a sampling time sequence, and if the A / D conversion performed by the A / D conversion chip is not completed within a preset time, the FPGA determines that the A / D conversion has timed out;

[0028] The FPGA performs a CRC check each time it reads the A / D conversion result through the serial port of the A / D conversion control module, and if it fails, the data is judged to be invalid;

[0029] A channel is reserved on each A / D conversion chip to collect the A / D reference voltage. The FPGA checks whether the value of the channel meets the expectations through the A / D conversion control module. If the error exceeds the standard, the FPGA determines that the A / D conversion is wrong.

[0030] According to one aspect of the present invention, when the U / I value of two sets of sampling data reaches above 5% of the rated value and the difference between the two sets of sampling data is greater than 2% of the rated value, the tolerance comparison module determines that the two sets of sampling data are inconsistent.

[0031] According to one solution of the present invention, the present invention adds a TA second secondary winding, signal chain power supply monitoring, and uses FPGA to realize the mutual transmission of sampling data between dual sampling signal chains and perform inconsistency judgment on the basis of the original dual CPU module architecture of the hardware of the high-voltage relay protection device, each module has an independent sampling circuit. The solution can identify the faults of each link in the sampling signal chain from the source, and also has a certain preventive effect on data bit flips and program logic anomalies caused by the single particle effect of FPGA devices. The design method of the present invention has the characteristics of clear and simple system structure and general and easy to promote. It can significantly improve the single fault tolerance of the sampling signal chain of the relay protection device and reduce the probability of protection misoperation. When a single component of the signal chain fails, the FPGA can sense it in time and notify the CPU to take alarm locking measures to remind the equipment that maintenance is required to prevent refusal to operate.

[0032] According to one solution of the present invention, the present invention adopts a design solution that the secondary dual winding output is respectively provided for acquisition by the master and slave CPU modules for the two main failure modes of TA. This solution, combined with the dual-path sampling consistency criterion, can effectively identify the two disconnection faults of TA. The design method of the present invention eliminates the common cause failure point in the sampling signal chain, enables the relay protection device to have the detection capability and fault tolerance of TA faults, realizes comprehensive monitoring of the device operation status, improves the reliability of the device, and reduces the risk of refusal and malfunction caused by hardware failure.

[0033] According to one solution of the present invention, the present invention fully considers the possibility of power failure, and uses the A / D in the FPGA chip to realize power monitoring. The method can reliably identify power anomalies caused by aging after long-term operation and prevent the chip from working under overvoltage or undervoltage. Monitoring of power aging helps to improve the regular maintenance / replacement of power automation equipment to precise operation and maintenance based on actual conditions, saving labor costs and expenses.

[0034] According to one solution of the present invention, the present invention fully considers the possibility of A / D chip failure, identifies potential A / D chip failures during operation through conversion timeout monitoring, reference voltage monitoring and serial communication CRC check functions, and ensures the safety of the sampling signal chain of the relay protection device against A / D chip failures. It can improve the precision operation and maintenance level of relay protection equipment and save labor costs and expenses.

[0035] According to one solution of the present invention, the present invention can partially protect against bit flips caused by single-particle effects and detect bit flips caused by atmospheric neutron radiation. Protection against single-particle effects can improve the precision operation and maintenance level of relay protection equipment and save labor costs and expenses.

[0036] According to one solution of the present invention, the present invention makes full use of the logic capability of FPGA to realize power supply voltage monitoring, A / D chip result validity judgment, dual-chain data intercommunication and tolerance verification. While reducing the complexity of system hardware, hardware costs are saved. The present invention has the characteristics of low cost and easy implementation. After promotion, it will help to improve the single fault tolerance of the sampling signal chain of the relay protection device and reduce the probability of protection misoperation, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A structural block diagram schematically showing a sampling system for a relay protection device according to an embodiment of the present invention;

[0038] Figure 2 The flowchart schematically shows a method for preventing errors in improving the single fault tolerance of a sampling system of a relay protection device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will now be discussed with reference to exemplary embodiments. It should be understood that the embodiments discussed are only to enable those skilled in the art to better understand and thus implement the present invention, rather than implying any limitation on the scope of the present invention.

[0040] As used herein, the term “including” and variations thereof are to be interpreted as open-ended terms meaning “including, but not limited to.” The term “based on” is to be interpreted as “based, at least in part, on.” The terms “one embodiment” and “an embodiment” are to be interpreted as “at least one embodiment.”

[0041] Figure 1 The structure block diagram of the sampling system of the relay protection device according to one embodiment of the present invention is schematically shown. Figure 1 As shown, in this embodiment, the sampling system of the relay protection device includes: a current transformer, a main CPU module and a slave CPU module;

[0042] The current transformer 13 isolates and transforms the secondary current of the power system into a small signal for collection by the A / D conversion chips in the main CPU module and the slave CPU module;

[0043] The main CPU module 1 and the slave CPU module 2 both include:

[0044] RC filter circuit 3, to filter out potential high-frequency signals to avoid frequency aliasing;

[0045] The operational amplifier follower circuit 4 enhances the signal output by the RC filter circuit, thereby improving the quality of the signal collected by the A / D conversion chip;

[0046] A / D conversion chip 5 performs analog-to-digital conversion, and the conversion result is sent through the serial port, generating a CRC check code for each frame of data sent;

[0047] FPGA6, which has:

[0048] Voltage monitoring module 7, using the A / D conversion control circuit in the FPGA to monitor the operational amplifier follower circuit and the A / D conversion chip working power supply, and notifying the CPU when encountering abnormal working conditions of power supply overvoltage or undervoltage;

[0049] Synchronous sampling pulse module 8, the FPGA on the master CPU module sends second pulses to the slave CPU module through the synchronous sampling pulse module, so as to realize synchronous sampling between the master CPU module and the slave CPU module;

[0050] A / D conversion control module 9, FPGA controls the A / D conversion chip to perform A / D conversion and A / D sampling through the A / D conversion control module according to the acquisition density required by the protection function, and then reads the A / D conversion data through the serial port, and performs CRC check on each frame of data;

[0051] Serial transceiver module 10, the two FPGAs on the master CPU module and the slave CPU module respectively send their own sampled data to each other through the serial transceiver module, and receive the sampled point data sent by the other party at the same time;

[0052] Tolerance comparison module 11, two FPGAs on the master CPU module and the slave CPU module respectively synchronize the two groups of sampled data in the master CPU module and the slave CPU module in the buffer, and then perform tolerance comparison between the two groups of sampled data through the tolerance comparison module to determine whether the two groups of sampled data are consistent;

[0053] CPU12 performs logic judgment and processing based on the output signal of FPGA to prevent protection from refusing to operate or malfunctioning.

[0054] Further, according to an embodiment of the present invention, the primary side of the current transformer is a single winding, the secondary side is a double winding, and two analog small signals are output, which are respectively connected to the filter circuits on the main CPU module and the slave CPU module for collection by the two A / D conversion chips of the main CPU module and the slave CPU module. The upper limit of the current transformer range is 40 times the rated current, and a silicon steel air-gap core is used. The insulation impedance of the primary and secondary sides is greater than 500MΩ. The double windings of the secondary side of the current transformer are connected in parallel with an external resistor to generate a voltage. At the rated current, the voltage error (ratio difference) is <0.5%, and the phase difference is <1°. At 20 times the rated current, 80% of the non-periodic components are superimposed, the decay time is 100ms, the output waveform has no obvious distortion, and the transmission error of the power frequency signal in each cycle is not more than 5%.

[0055] Further, according to an embodiment of the present invention, the RC filter circuit is a second-order RC low-pass circuit, and the -3dB cut-off frequency is 270 Hz. The RC filter circuit is responsible for filtering out potential high-frequency signals to avoid frequency aliasing.

[0056] Further, according to an embodiment of the present invention, the operational amplifier follower circuit is responsible for reducing the equivalent impedance of the signal source and improving the signal quality collected by the A / D chip. The operational amplifier follower circuit is also responsible for eliminating the DC interference voltage after the current transformer is disconnected from the RC filter circuit.

[0057] Further, according to an embodiment of the present invention, the A / D conversion chip is a SAR structure, with ±10V input and a serial port output of conversion results, and the A / D conversion chip has a hardware CRC for serial communication error detection.

[0058] Furthermore, according to one embodiment of the present invention, the voltage monitoring module utilizes the A / D conversion control circuit in the FPGA to periodically monitor the operating power supply of the operational amplifier follower circuit and the A / D conversion chip, and notifies the CPU locking device outlet when the voltage deviates from the rated value by ±3%, thereby preventing the chip from malfunctioning under conditions such as power supply overvoltage or undervoltage.

[0059] Further, according to one embodiment of the present invention, the FPGA on the main CPU module sends a second pulse to the synchronous sampling pulse module in the FPGA on the slave CPU module through the synchronous sampling pulse module. The synchronous sampling pulse module in the FPGA on the slave CPU module divides the pulse into equal parts as a sampling time sequence, thereby realizing synchronous sampling between the main CPU module and the slave CPU module.

[0060] In this embodiment, the pulse accuracy of the synchronous sampling pulse modules in the master CPU module and the slave CPU module in sending and receiving synchronous pulses is ±2 μs.

[0061] In this embodiment, the sampling frequency of the A / D conversion control module for A / D sampling is between 4 and 12 kHz.

[0062] Further, according to an embodiment of the present invention, the A / D conversion control module triggers A / D sampling according to the sampling time sequence, and if the A / D conversion performed by the A / D conversion chip is not completed within a preset time, the FPGA determines that the A / D conversion has timed out;

[0063] Every time the FPGA reads the A / D conversion result through the serial port of the A / D conversion control module, it performs a CRC check. If it fails, the data is considered invalid.

[0064] A channel is reserved on each A / D conversion chip to collect the A / D reference voltage. The FPGA checks whether the value of the channel meets the expectations through the A / D conversion control module. If the error exceeds the standard, the FPGA determines that the A / D conversion is wrong.

[0065] Further, according to an embodiment of the present invention, the FPGA implements the exchange of two sets of sampled data through high-speed serial communication, the data transmission and reception buffer is 32 bits wide and 64 levels deep, and the sampled data is packaged according to a private protocol, and the data packet length is between 64-1518Bytes. The FPGA implements consistency comparison of the two sets of sampled data. When the U / I value of the two sets of sampled data reaches more than 5% of the rated value, and the difference between the two sets of sampled data is greater than 2% of the rated value, the tolerance comparison module determines that the two sets of sampled data are inconsistent. When the FPGA tolerance comparison module detects that the two sets of sampled data are inconsistent, it means that there is a component failure in the signal chain of the main CPU module and the slave CPU module. The FPGA promptly notifies the CPU to take alarm locking measures to remind the equipment that maintenance is required to prevent refusal to operate.

[0066] It should be noted that the current transformer, as the source of the sampling signal chain of the relay protection device, is responsible for isolating and converting the secondary current into voltage for the CPU module to collect. The failure risk of the current transformer is mainly: the iron core is heavy, and its signal output pin is easy to fall off from the PCB welding hole due to vibration during transportation, resulting in poor contact between the secondary winding and the external resistor to generate high voltage, which in turn causes the protection to malfunction; the secondary winding has a thin wire diameter and many turns, which is easy to cause wire breakage due to poor control of the winding and welding process, and the signal disappears, resulting in malfunction of the protection. In the traditional sampling signal chain (i.e., the overall sampling structure of the main CPU module or the slave CPU module) design, there is only one winding on the secondary side of the current transformer. After the current transformer fails, the dual-channel sampling is affected at the same time, which is one of the common cause failure points of the sampling signal chain. In response to this problem, the present invention enlarges the volume of the current transformer by 30% and adds a second winding on its secondary side for the master and slave (master CPU module and slave CPU module) to collect separately. Under the above two faults, because the signals collected by the two channels are seriously unbalanced, the two-channel consistency judgment can reliably detect the fault, thereby ensuring the safety of the sampling signal chain of the relay protection device against current transformer faults.

[0067] The present invention utilizes the A / D conversion control module in the FPGA to periodically monitor the working power supply of the operational amplifier follower circuit and the A / D conversion chip, and notifies the CPU to lock protection when encountering abnormal working conditions such as power supply overvoltage and undervoltage, thereby realizing the safety of the sampling signal chain of the relay protection device against power supply failure.

[0068] Based on the A / D conversion timeout monitoring, the present invention further diagnoses whether the A / D works normally by monitoring the A / D reference voltage. Furthermore, when the FPGA reads the conversion result through the serial port, it can identify potential errors in the transmission process through CRC check. The above measures ensure the safety of the sampling signal chain of the relay protection device against A / D chip failure.

[0069] The present invention uses the high-speed communication function of FPGA to realize the mutual transmission of sampling data between dual CPU modules and perform inconsistency judgment of dual-channel collected data. When a single component of the signal chain fails, the FPGA can promptly sense and notify the CPU to take alarm locking measures, reminding the equipment that maintenance is required to prevent refusal to operate, thereby realizing the single fault tolerance of the sampling signal chain of the relay protection device, which can effectively reduce the probability of false protection operation.

[0070] According to the above scheme of the present invention, firstly, at the source of the sampling signal chain, the second winding of the secondary side is increased by enlarging the TA volume by about 30%, so as to improve the independence of the dual CPU module sampling. Then, the status of each power supply in the device is monitored to prevent the chip from malfunctioning under the working conditions of power supply overvoltage, undervoltage, etc. Further, a monitoring channel is reserved for each A / D conversion chip, and the A / D reference voltage (reference voltage) is monitored to diagnose whether the conversion is normal. Further, when the FPGA reads the A / D conversion data through the serial port, the CRC check is used to identify potential errors in the transmission process. Finally, the high-speed communication function of the FPGA is used to realize the mutual transmission of sampling data between the dual CPU modules, and perform the inconsistency judgment of the dual-channel acquisition data. The scheme of the present invention improves the single fault tolerance of the sampling signal chain of the relay protection device, and can effectively reduce the probability of protection misoperation; after a single component of the signal chain fails, the FPGA can timely perceive and notify the CPU to take locking measures to prevent misoperation, and remind the operating personnel that the equipment needs maintenance to prevent refusal to operate.

[0071] According to the above scheme of the present invention, on the basis of the original dual CPU module architecture of the high voltage level relay protection device hardware, each CPU module has an independent sampling circuit (sampling signal chain), the second secondary winding of TA and signal chain power supply monitoring are added, and FPGA is used to realize the mutual transmission of sampling data between the dual sampling signal chains, and the inconsistency judgment is performed. It has the characteristics of being simple, universal and easy to promote.

[0072] According to the above scheme of the present invention, the present invention adopts a design scheme in which the secondary dual winding output is respectively provided for collection by the master and slave CPU modules for the two main failure modes of the current transformer. This scheme, combined with the dual-path sampling consistency criterion, can effectively identify the two types of disconnection faults of the current transformer. The present invention eliminates the common cause failure point in the sampling signal chain, enables the relay protection device to have the detection capability and fault tolerance of the current transformer fault, realizes comprehensive monitoring of the device operation status, improves the reliability of the device, and reduces the risk of refusal and malfunction caused by hardware failure.

[0073] According to the scheme of the present invention, the present invention fully considers the possibility of power failure, and realizes power monitoring by using the A / D in the FPGA chip, which can reliably identify the power anomaly caused by aging after long-term operation, and prevent the chip from working under overvoltage or undervoltage. The monitoring of power aging helps to improve the regular maintenance / replacement of power automation equipment to precise operation and maintenance according to actual conditions, saving manpower costs and expenses. The present invention makes full use of the logic capability of FPGA, realizes power supply voltage monitoring, A / D conversion chip result validity judgment, dual-chain data intercommunication and tolerance verification. While reducing the complexity of system hardware, it saves hardware costs. The present invention has the characteristics of low cost and easy implementation. After promotion, it helps to improve the single fault tolerance of the sampling signal chain of the relay protection device, reduce the probability of protection misoperation, and has good application prospects. It can also improve the precise operation and maintenance level of power automation equipment, saving manpower costs and expenses.

[0074] Furthermore, in order to achieve the above-mentioned purpose, the present invention also provides a method for preventing errors by improving the single fault tolerance of the sampling system of the relay protection device, and its flow chart is as follows: Figure 2 As shown, specifically including:

[0075] a.FPGA triggers sampling and starts A / D conversion according to the sampling time sequence;

[0076] b. After a 4μs delay, the FPGA checks whether the IO pin where the A / D conversion is completed is reversed. If it is not reversed, it is judged as a conversion timeout and the current data is unavailable;

[0077] c. FPGA reads the result of A / D conversion through the serial port, sends the A / D code value of each channel in turn according to the data rules of the A / D conversion chip, and finally sends the CRC16 check code of the current message;

[0078] d.FPGA calculates the CRC checksum of the message and compares it with the CRC data sent by the serial port. If the two are consistent, the data is valid, otherwise the current data is unavailable.

[0079] e. For each A / D conversion chip, the A / D reference voltage is fixed at channel 0. The converted code value is fixed as a constant. The FPGA monitors whether the data collected by this reference voltage is correct. If the error exceeds ±1%, the current data is unavailable.

[0080] f. For the sampling point data that passes the aforementioned verification, the FPGA numbers the sampling data and stores it in the buffer;

[0081] g. FPGA sends the current sampling data together with the serial number to another FPGA in the sampling signal chain through the high-speed serial port;

[0082] h. FPGA receives the sampling data from another FPGA in the sampling signal chain through the high-speed serial port, and stores the data in the receiving buffer in the order;

[0083] i. FPGA knows whether the current round of data transmission and reception is normal based on the flag of the high-speed serial port module;

[0084] j.FPGA compares the tolerance of the dual-channel sampled data according to the sampling point sequence number;

[0085] k.FPGA determines whether the current data has passed the consistency check;

[0086] l. If there is no invalid data judgment conclusion in the previous links and the current data passes the consistency check, the data of this sampling chain is available.

[0087] The present invention introduces continuous monitoring of the power supply of the sampling signal chain, uses the on-chip A / D conversion control module of the FPGA to collect the working power supply of the operational amplifier follower circuit and the A / D conversion chip, and implements monitoring every 1ms. If the power supply voltage deviates from the rated value by ±3% for three consecutive times, the CPU is notified to lock the protection, thereby ensuring the safety of the sampling signal chain of the relay protection device against power failure.

[0088] The present invention continuously monitors the validity of A / D conversion data, firstly monitoring A / D conversion timeout, secondly reserving a monitoring channel in the A / D sampling circuit to diagnose whether the A / D works normally, and finally using the CRC check function of the A / D conversion chip serial port to prevent potential errors in the transmission process. The monitoring method can reliably identify potential A / D conversion chip failures during equipment operation and ensure the safety of the sampling signal chain of the relay protection device against A / D conversion chip failures.

[0089] After the local A / D sampling is completed, the present invention sends the current sampling data point to the FPGA of another sampling signal chain after numbering, and receives the sampling data of the FPGA of another sampling signal chain at the same time, and stores the data in the receiving buffer by numbering. According to the sampling point sequence number, the FPGA performs tolerance comparison on the data sampled by the two channels. According to the comparison result, it is determined whether the two groups of sampling data are consistent. If they are inconsistent, an alarm is locked.

[0090] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. Relay protection device sampling system, characterized in that: include: Mutual inductor, master CPU module and slave CPU module; The mutual inductor isolates and transforms the secondary current of the power system into small signals for collection by the A / D conversion chips in the main CPU module and the slave CPU module respectively; The main CPU module and the slave CPU module both include: RC filter circuit to filter out potential high-frequency signals to avoid frequency aliasing; The operational amplifier follower circuit enhances the signal output by the RC filter circuit and improves the quality of the signal collected by the A / D conversion chip; A / D conversion chip performs analog-to-digital conversion, and the conversion result is sent through the serial port, generating a CRC check code for each frame of data sent; FPGA, which features: The voltage monitoring module uses the A / D conversion control circuit in the FPGA to monitor the operating power supply of the operational amplifier follower circuit and the A / D conversion chip, and notifies the CPU when encountering abnormal conditions such as overvoltage or undervoltage of the power supply; Synchronous sampling pulse module: the FPGA on the master CPU module sends second pulses to the slave CPU module through the synchronous sampling pulse module, thus realizing synchronous sampling between the master CPU module and the slave CPU module; A / D conversion control module: FPGA controls the A / D conversion chip to perform A / D conversion and A / D sampling through the A / D conversion control module according to the acquisition density required by the protection function, and then reads the A / D conversion data through the serial port, and performs CRC check on each frame of data; Serial transceiver module, the two FPGAs on the master CPU module and the slave CPU module respectively send their own sampling data to each other through the serial transceiver module, and receive the sampling point data sent by the other party at the same time; Tolerance comparison module: two FPGAs on the master CPU module and the slave CPU module respectively synchronize the two groups of sampling data in the master CPU module and the slave CPU module in the buffer through the sequence number, and then perform tolerance comparison between the two groups of sampling data through the tolerance comparison module to determine whether the two groups of sampling data are consistent; The CPU performs logical judgment and processing based on the output signal of the FPGA to prevent protection from refusing to operate or malfunctioning.

2. The relay protection device sampling system according to claim 1, characterized in that: The current transformer has a single winding on the primary side and double windings on the secondary side, which are used for data collection by two A / D conversion chips of the main CPU module and the slave CPU module.

3. The relay protection device sampling system according to claim 1, characterized in that: The RC filter circuit is a second-order RC low-pass circuit, and the -3dB cut-off frequency is 270Hz.

4. The relay protection device sampling system according to claim 1, characterized in that: The A / D conversion chip is a SAR structure, with ±10V input and a serial port output of conversion results. The A / D conversion chip has a hardware CRC for serial communication error detection.

5. The relay protection device sampling system according to claim 1, characterized in that: The voltage monitoring module uses the A / D conversion control circuit in the FPGA to monitor the operational amplifier follower circuit and the A / D conversion chip working power supply, and notifies the CPU when the voltage deviates from the rated value by ±3%.

6. The relay protection device sampling system according to claim 1, characterized in that: The FPGA on the main CPU module sends a second pulse to the synchronous sampling pulse module in the FPGA on the slave CPU module through the synchronous sampling pulse module. The synchronous sampling pulse module in the FPGA on the slave CPU module divides the pulse into equal parts as a sampling time sequence, thereby realizing synchronous sampling between the main CPU module and the slave CPU module.

7. The relay protection device sampling system according to claim 1, characterized in that: The pulse accuracy of the synchronous sampling pulse modules in the master CPU module and the slave CPU module in sending and receiving synchronous pulses is ±2μs.

8. The relay protection device sampling system according to claim 1, characterized in that: The sampling frequency of the A / D conversion control module for A / D sampling is between 4 and 12 kHz.

9. The relay protection device sampling system according to claim 1, characterized in that: The A / D conversion control module triggers A / D sampling according to the sampling time sequence. If the A / D conversion performed by the A / D conversion chip is not completed within a preset time, the FPGA determines that the A / D conversion has timed out; The FPGA performs a CRC check each time it reads the A / D conversion result through the serial port of the A / D conversion control module, and if it fails, the data is judged to be invalid; A channel is reserved on each A / D conversion chip to collect the A / D reference voltage. The FPGA checks whether the value of the channel meets the expectations through the A / D conversion control module. If the error exceeds the standard, the FPGA determines that the A / D conversion is wrong.

10. The relay protection device sampling system according to any one of claims 1 to 9, characterized in that: When the U / I values ​​of the two sets of sampling data are above 5% of the rated value, and the difference between the two sets of sampling data is greater than 2% of the rated value, the tolerance comparison module determines that the two sets of sampling data are inconsistent.

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