Memory device and operating method thereof, memory system
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2023-11-02
- Publication Date
- 2026-06-16
Smart Images
Figure CN119943114B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology
[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) flash memory has become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.
[0003] During the use of memory devices, sudden power outages may occur. How to mitigate the negative impact of sudden power outages on memory devices has become an urgent problem to be solved. Summary of the Invention
[0004] In view of the above, this disclosure provides a memory device and its operation method, and a memory system, in order to solve at least one problem existing in the prior art.
[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:
[0006] In a first aspect, embodiments of this disclosure provide a memory device, the memory device including peripheral circuitry and a memory array coupled to the peripheral circuitry; the memory array includes conductive lines; the peripheral circuitry includes a discharge circuit coupled to the conductive lines, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit; wherein...
[0007] The first sub-discharge circuit is configured to discharge the operating voltage on the conductive line to a first voltage in response to a power-down signal;
[0008] The second sub-discharge circuit is configured to discharge the first voltage to the second voltage.
[0009] In one optional embodiment, the first sub-discharge circuit includes a current mirror circuit; the current mirror circuit includes a constant current source, a first transistor, a second transistor, and a first switch; the first terminal of the first transistor and the first terminal of the second transistor are both connected to ground voltage; the control terminal and the second terminal of the first transistor are both connected to the constant current source; the second terminal of the second transistor is coupled to the conductive line; the first terminal of the first switch is connected to the control terminal of the first transistor, and the second terminal of the first switch is connected to the control terminal of the second transistor.
[0010] In one optional embodiment, the first sub-discharge circuit further includes a third transistor; the second terminal of the third transistor is connected to the conductive line, and the first terminal of the third transistor is connected to the second terminal of the second transistor; the control terminal of the third transistor is connected to the ground voltage.
[0011] In one optional embodiment, the second sub-discharge circuit includes a fourth transistor and a second switch; the second terminal of the fourth transistor is connected to the conductive line, and the first terminal of the fourth transistor is connected to the ground voltage; the first terminal of the second switch is connected to the control terminal of the fourth transistor, and the second terminal of the second switch receives a first control voltage.
[0012] In one optional embodiment, the second sub-discharge circuit includes the third transistor, the fifth transistor, and the third switch; the first terminal of the fifth transistor is connected to the first terminal of the third transistor, and the second terminal of the fifth transistor is connected to the ground voltage; the first terminal of the third switch is connected to the control terminal of the fifth transistor, and the second terminal of the third switch receives a second control voltage.
[0013] In one optional embodiment, the second sub-discharge circuit includes the third transistor, the second transistor, and a capacitor; the first plate of the capacitor is connected to the second terminal of the first switch and the control terminal of the second transistor; the second plate of the capacitor is connected to the ground voltage.
[0014] In one alternative implementation, the conductive lines include source lines and / or bit lines.
[0015] In a second aspect, embodiments of this disclosure provide a memory system, including:
[0016] At least one memory device according to any of the above embodiments;
[0017] A memory controller, coupled to and configured to control the memory device.
[0018] Thirdly, embodiments of this disclosure provide an operation method for a memory device, characterized in that the memory device includes a memory array and a discharge circuit coupled to conductive lines in the memory array, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit; the operation method includes:
[0019] In response to a power failure signal, the operating voltage on the conductive line is discharged to a first voltage through the first sub-discharge circuit;
[0020] The first voltage is discharged to the second voltage through the second sub-discharge circuit.
[0021] In one optional embodiment, the first sub-discharge circuit includes a current mirror circuit and a third transistor; the current mirror circuit includes a first transistor, a second transistor, and a first switch; the first switch is located between the control terminal of the first transistor and the control terminal of the second transistor; discharging the operating voltage to the first voltage through the first sub-discharge circuit includes:
[0022] In response to the power failure signal, the first switch is closed, and the operating voltage is discharged to the first voltage through the third transistor and the current mirror circuit; the first voltage is higher than the ground voltage.
[0023] In one optional embodiment, the second sub-discharge circuit includes a fourth transistor and a second switch connected to the control terminal of the fourth transistor; the step of discharging the first voltage to the second voltage through the second sub-discharge circuit includes:
[0024] The first switch is turned off and the second switch is turned on to turn on the fourth transistor through the first control voltage, and the first voltage is discharged to the second voltage through the fourth transistor.
[0025] In one optional embodiment, the second sub-discharge circuit includes the third transistor, the fifth transistor, and a third switch connected to the control terminal of the fifth transistor; the step of discharging the first voltage to the second voltage through the second sub-discharge circuit includes:
[0026] The first switch is turned off and the third switch is turned on to turn on the fifth transistor through the second control voltage, and the first voltage is discharged to the second voltage through the third transistor and the fifth transistor.
[0027] In one optional embodiment, the second sub-discharge circuit includes the third transistor, the second transistor, and a capacitor; the first and second plates of the capacitor are respectively connected to the control terminal of the second transistor and the ground voltage; discharging the first voltage to the second voltage through the second sub-discharge circuit includes:
[0028] The first switch is turned off, and the first voltage is discharged to the second voltage through the third transistor and the second transistor.
[0029] In the technical solution provided in this disclosure, the memory device includes a discharge circuit coupled to a conductive line. When the memory device experiences a sudden power failure, a first sub-discharge circuit in the discharge circuit can discharge the operating voltage on the conductive line to a first voltage in response to a power failure signal, and a second sub-discharge circuit can discharge the first voltage to a second voltage. On one hand, the first sub-discharge circuit includes a current mirror circuit, which can control the discharge current, thereby reducing the instantaneous discharge rate of the high voltage and avoiding damage to other circuit components in the memory device due to the coupling effect caused by the excessively fast instantaneous discharge rate. On the other hand, when the voltage drops to a point where the normal operation of the current mirror circuit can no longer be maintained, the second sub-discharge circuit can continue to discharge using a faster discharge method or a discharge method similar to that of the first sub-discharge circuit, thereby discharging the higher operating voltage on the conductive line to a lower voltage, avoiding damage to the circuit components in the memory device caused by the higher operating voltage, and mitigating the negative impact of a sudden power failure on the memory device. Attached Figure Description
[0030] Figure 1 A schematic diagram of an exemplary system with a memory system provided in the embodiments of this disclosure;
[0031] Figure 2 A schematic diagram of an exemplary memory card with a memory system provided for embodiments of this disclosure;
[0032] Figure 3 A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this disclosure;
[0033] Figure 4 A schematic diagram of an exemplary memory device including peripheral circuitry provided for embodiments of this disclosure;
[0034] Figure 5 A schematic diagram of an exemplary memory device including a memory array and peripheral circuitry, provided for embodiments of this disclosure;
[0035] Figure 6 A circuit diagram of a discharge circuit provided as a specific example of this disclosure;
[0036] Figure 7 A voltage curve on a conductive line provided in an embodiment of this disclosure;
[0037] Figure 8 Circuit for another specific example of the discharge circuit provided in this disclosure Figure 1 ;
[0038] Figure 9 Circuit for another specific example of the discharge circuit provided in this disclosure Figure 2 ;
[0039] Figure 10 Voltage curve two on the conductive line provided in this embodiment of the disclosure;
[0040] Figure 11 The circuit of the discharge circuit provided as yet another specific example of this disclosure Figure 1 ;
[0041] Figure 12 The circuit of the discharge circuit provided as yet another specific example of this disclosure Figure 2 ;
[0042] Figure 13 This is a flowchart illustrating the operation method of a memory device provided in an embodiment of this disclosure. Detailed Implementation
[0043] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0045] In the accompanying drawings, the same reference numerals denote the same elements throughout.
[0046] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0048] The memory systems in the embodiments of this disclosure include, but are not limited to, memory systems including three-dimensional NAND type memory. For ease of understanding, the memory systems provided in this disclosure will be described using a memory system including three-dimensional NAND type memory as an example.
[0049] Figure 1 This is a schematic diagram of an exemplary system with a memory system provided for embodiments of this disclosure. In embodiments of this disclosure, system 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown, system 100 may include a host device 101 and a memory system 102. The memory system 102 may include one or more memory devices 103 and a memory controller 104. The host device 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host device 101 may be configured to send data to or receive data from the memory system 102.
[0050] In some embodiments, memory controller 104 is coupled to memory device 103 and host device 101 and is configured to control memory device 103. Memory controller 104 can manage data stored in memory device 103 and communicate with host device 101. In some embodiments, memory controller 104 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 104 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).
[0051] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.
[0052] In such Figure 2 In one example shown, the memory controller 104 and a single memory device 103 can be integrated into the memory card 201. The memory card 201 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a connection between the memory card 201 and a host device (e.g., Figure 1 The host device 101) is coupled to the memory card connector 202. In such a... Figure 3 In another example shown, the memory controller 104 and multiple memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include components for connecting the SSD 203 to host devices (e.g., Figure 1 The SSD connector 204 is coupled to the host device 101. In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.
[0053] Figure 4A circuit diagram of an exemplary memory device 300 including peripheral circuitry, provided for embodiments of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 103 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 305 are NAND memory cells, provided in the form of an array of memory strings 304, each memory string 304 extending vertically above a substrate (not shown). In some embodiments, each memory string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 305. Each memory cell 305 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.
[0054] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.
[0055] like Figure 4As shown, each memory string 304 may include a bottom-select transistor (BST) 307 at its source end and a top-select transistor (TST) 306 at its drain end. The bottom-select transistor 307 and the top-select transistor 306 may be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the sources of memory strings 304 within the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 303 share a common source (ACS). According to some embodiments, the top-select transistor 306 of each memory string 304 is coupled to a corresponding bit line (BL) 311, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper select transistor 306) or a deselection voltage (e.g., 0V) to the corresponding upper select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower select transistor 307) or a deselection voltage (e.g., 0V) to the corresponding lower select transistor 307 via one or more bottom select lines (BSL) 309.
[0056] like Figure 4 As shown, memory strings 304 can be organized into multiple memory blocks 303, each of which may have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and to unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory strings 304 can be coupled via word lines 312, which select which row of memory cells 305 is affected by a read or program operation.
[0057] In some embodiments, peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit line 311, word line 312, common-source line 310, lower select line 309, and upper select line 308, and for sensing voltage and / or current signals from each target memory cell 305 to operate the memory array 301. Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.
[0058] Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface 407, and a data bus 408. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.
[0059] Page buffer / sensor amplifier 401 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 301. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cells coupled to selected word lines. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit lines representing data bits stored in the memory cells and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory strings by applying a bit line voltage generated from voltage generator 404.
[0060] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 301 and select / deselect word lines of memory blocks. The row decoder / word line driver 408 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive lower select lines and upper select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.
[0061] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.
[0062] For the aforementioned memory devices, higher operating voltages may be required when performing programming, reading, or erasing operations. However, with the increasing integration of memory devices and the shrinking size of circuit components, the voltage withstand capability of these components decreases. When a sudden power failure occurs, the high operating voltage may damage the circuit components, leading to reduced performance after power is restored, or even failure to continue normal operation. Therefore, mitigating the negative impact of sudden power failures on memory devices has become a pressing issue. This disclosure proposes the following implementation methods.
[0063] This disclosure provides a memory device including peripheral circuitry and a memory array coupled to the peripheral circuitry; the memory array includes conductive lines, and the peripheral circuitry includes a discharge circuit coupled to the conductive lines, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit; wherein the first sub-discharge circuit is configured to discharge an operating voltage on the conductive lines to a first voltage in response to a power-down signal; and the second sub-discharge circuit is configured to discharge the first voltage to a second voltage.
[0064] In some specific examples, such as Figure 4 As shown, the conductive lines can be source lines 310, bit lines 311, word lines 312, or other conductive lines that need to withstand high operating voltages during the operation of the memory device. For example, when performing an erase operation on the memory array using the Gate Induced Drain Leakage (GIDL) erase mechanism, an erase voltage needs to be applied to both source lines 310 and bit lines 311 simultaneously, and the erase voltage can reach over 20V; when performing a read operation on the memory array, a high on-state voltage needs to be applied to the unselected word line 312; when performing a programming operation on the memory array, a high programming voltage needs to be applied to the selected word line 312. When the memory device experiences a sudden power loss, if these operating voltages cannot be discharged in time, they may damage the circuit components in the memory device.
[0065] In the embodiments of this disclosure, the discharge circuit coupled to the conductive lines in the memory array can, in response to a power-down signal, discharge the operating voltage on the conductive lines through a first sub-discharge circuit and a second sub-discharge circuit. This allows for timely discharge of the higher operating voltage to a lower second voltage in the event of a sudden power failure, preventing damage to the circuit components in the memory device from the higher operating voltage and mitigating the negative impact of a sudden power failure on the memory device. The memory device including the discharge circuit provided in this disclosure will now be described in detail with reference to specific examples.
[0066] Figure 6 A circuit diagram of a discharge circuit provided as a specific example of this disclosure, such as... Figure 6 As shown, the two ends of the discharge circuit 500 are coupled to the conductive line and the ground voltage VSS, respectively. The discharge circuit 500 includes a first sub-discharge circuit 501 and a second sub-discharge circuit 502.
[0067] The first sub-discharge circuit 501 includes a current mirror circuit, which includes a first transistor Q1, a second transistor Q2, a constant current source I, and a first switch S1. The first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are both connected to the ground voltage VSS. The control terminal and the second terminal of the first transistor Q1 are both connected to the constant current source I. The second terminal of the second transistor Q2 is coupled to a conductive line. The first terminal of the first switch S1 is connected to the control terminal of the first transistor Q1, and the second terminal of the first switch S1 is connected to the control terminal of the second transistor Q2.
[0068] The first sub-discharge circuit 501 also includes a third transistor Q3; the second terminal of the third transistor Q3 is connected to a conductive line, and the first terminal of the third transistor Q3 is connected to the second terminal of the second transistor Q2; the control terminal of the third transistor Q3 is connected to the ground voltage VSS.
[0069] The second sub-discharge circuit 502 includes a fourth transistor Q4 and a second switch S2; the second terminal of the fourth transistor Q4 is connected to a conductive line, and the first terminal of the fourth transistor Q4 is connected to the ground voltage VSS; the first terminal of the second switch S2 is connected to the control terminal of the fourth transistor Q4, and the second terminal of the second switch S2 receives a first control voltage.
[0070] In some specific examples, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all NMOS transistors.
[0071] In this embodiment, when the first switch S1 is closed and the second switch S2 is open, the voltage on the conductive line can be discharged through the first sub-discharge circuit 501, and the magnitude of the discharge current is determined by the magnitude of the current output by the constant current source I; when the first switch S1 is open and the second switch S2 is closed, the first control voltage can turn on the fourth transistor Q4, and the voltage on the conductive line can be discharged through the second sub-discharge circuit 502, and the magnitude of the discharge current is determined by the magnitude of the voltage on the conductive line and the on-resistance of the fourth transistor Q4.
[0072] In some embodiments, the peripheral circuit further includes control logic, which can be configured to: in response to a power failure signal, close the first switch S1 to allow the first sub-discharge circuit 501 to discharge the operating voltage on the conductive line to a first voltage; open the first switch S1 and close the second switch S2 to allow the second sub-discharge circuit 502 to discharge the voltage on the conductive line from the first voltage to a second voltage.
[0073] In some specific examples, the peripheral circuit may also include a power-down detection unit, which may be coupled to the power supply voltage VDD of the memory device and the control logic. When the power-down detection unit detects that the power supply voltage VDD is lower than a preset voltage for a certain period of time and the duration exceeds the preset duration, the power-down detection unit may determine that the memory device has suddenly lost power and may send a power-down signal to the control logic.
[0074] In a specific example, Figure 7 The voltage profile on the conductive lines of the memory device, including the discharge circuit 500, shows that during the operation execution phase prior to the first discharge phase T1, the voltage on the conductive lines gradually rises from the ground voltage VSS to the operating voltage. Here, the conductive lines can be source lines or bit lines, and the operating voltage can be the erase voltage, which can be 22.5V.
[0075] When a sudden power failure occurs, in the first discharge stage T1, the first sub-discharge circuit 501 can discharge the operating voltage to the first voltage. Since the operating voltage is high, the discharge current can be controlled by the current mirror circuit in the first sub-discharge circuit 501, thereby reducing the instantaneous discharge speed of the high voltage and avoiding damage to other circuit components in the memory device due to the coupling effect caused by the excessively fast instantaneous discharge speed.
[0076] The first sub-discharge circuit 501 can only discharge the erasure voltage to the first voltage. This is because the operating time of the constant current source I is limited after a sudden power failure. After the operating voltage is discharged to the first voltage, the power supply voltage connected to the constant current source I is already low and cannot continue to maintain the operation of the current mirror circuit. However, the first voltage is still higher than the ground voltage VSS, which may still damage the circuit components.
[0077] In some specific examples, the first voltage can range from 1V to 2V. In one specific example, the first voltage can be 1.65V.
[0078] In the second discharge stage T2, the second sub-discharge circuit 502 can continue to discharge the first voltage to the second voltage, which can be the ground voltage VSS, for example, 0V. Since the first voltage is already low relative to the erasure voltage, it can be discharged to the second voltage at a faster discharge rate through the fourth transistor Q4 in the second sub-discharge circuit 502.
[0079] In this embodiment of the disclosure, the first sub-discharge circuit 501 in the discharge circuit can discharge the operating voltage on the conductive line to a first voltage, and the second sub-discharge circuit 502 can continue to discharge the first voltage to a second voltage. In this way, when the memory device experiences a sudden power failure, the higher operating voltage on the conductive line can be discharged to the ground voltage VSS, avoiding damage to the circuit components in the memory device caused by the higher operating voltage and mitigating the negative impact of the sudden power failure on the memory device.
[0080] Figure 8 and Figure 9 A circuit diagram of a discharge circuit provided as another specific example of this disclosure, such as Figure 8 and Figure 9 As shown, the two ends of the discharge circuit 600 are coupled to the conductive line and the ground voltage VSS, respectively. The discharge circuit 600 includes a first sub-discharge circuit 601 and a second sub-discharge circuit 602.
[0081] The first sub-discharge circuit 601 includes a current mirror circuit and a third transistor Q3. The current mirror circuit includes a first transistor Q1, a second transistor Q2, a constant current source I, and a first switch S1. The first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are both connected to the ground voltage VSS. The control terminal and the second terminal of the first transistor Q1 are both connected to the constant current source I. The second terminal of the second transistor Q2 is coupled to a conductive line. The first terminal of the first switch S1 is connected to the control terminal of the first transistor Q1, and the second terminal of the first switch S1 is connected to the control terminal of the second transistor Q2. The second terminal of the third transistor Q3 is connected to a conductive line, and the first terminal of the third transistor Q3 is connected to the second terminal of the second transistor Q2. The control terminal of the third transistor Q3 is connected to the ground voltage VSS.
[0082] The second sub-discharge circuit 602 includes a third transistor Q3, a fifth transistor Q5, and a third switch S3; the first terminal of the fifth transistor Q5 is connected to the first terminal of the third transistor Q3, and the second terminal of the fifth transistor Q5 is connected to the ground voltage VSS; the first terminal of the third switch S3 is connected to the control terminal of the fifth transistor Q5, and the second terminal of the third switch S3 receives a second control voltage.
[0083] In some specific examples, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all NMOS transistors, and the fifth transistor Q5 is a PMOS transistor.
[0084] In this embodiment, when the first switch S1 is closed and the third switch S3 is open, the voltage on the conductive line can be discharged through the first sub-discharge circuit 601, and the magnitude of the discharge current is determined by the magnitude of the current output by the constant current source I; when the first switch S1 is open and the third switch S3 is closed, the second control voltage can turn on the fifth transistor Q5, and the voltage on the conductive line can be discharged through the second sub-discharge circuit 602, and the magnitude of the discharge current is jointly determined by the magnitude of the voltage on the conductive line, the on-resistance of the third transistor Q3, and the on-resistance of the fifth transistor Q5.
[0085] In this embodiment of the disclosure, the control logic can be configured to: in response to a power-down signal, close the first switch S1 to allow the first sub-discharge circuit 601 to discharge the operating voltage on the conductive line to a first voltage; open the first switch S1 and close the third switch S3 to allow the second sub-discharge circuit 602 to discharge the voltage on the conductive line from the first voltage to a second voltage.
[0086] In a specific example, Figure 10 The voltage profile on the conductive lines of the memory device including the discharge circuit 600 shows that during the operation execution phase prior to the first discharge phase T1, the voltage on the conductive lines gradually rises from the ground voltage VSS to the operating voltage. Here, the conductive lines can be source lines or bit lines, and the operating voltage can be the erase voltage, which can be 22.5V.
[0087] When a sudden power failure occurs, in the first discharge stage T1, the first sub-discharge circuit 601 can discharge the operating voltage to the first voltage. Since the operating voltage is high, the discharge current can be controlled by the current mirror circuit in the first sub-discharge circuit 601, thereby reducing the instantaneous discharge speed of the high voltage and avoiding damage to other circuit components in the memory device due to the coupling effect caused by the excessively fast instantaneous discharge speed.
[0088] After the first sub-discharge circuit 601 discharges the operating voltage to the first voltage, the power supply voltage connected to the constant current source I is too low to continue operating the current mirror circuit. In the second discharge stage T2, the second sub-discharge circuit 602 can continue to discharge the first voltage to the second voltage, which can be the ground voltage VSS, for example, 0V. Here, the second sub-discharge circuit 602 can maintain almost the same discharge rate as the first sub-discharge circuit 601.
[0089] In this embodiment of the present disclosure, during the second discharge stage T2, the fifth transistor Q5 is turned on by the second control voltage. Since the fifth transistor Q5 is a PMOS transistor, it only requires a small gate voltage to turn on, thereby further improving the reliability of the discharge circuit in the low-voltage discharge section. That is, when the voltage in the memory device has dropped to a low level, the fifth transistor Q5 can still be turned on, thereby allowing the first voltage to be further discharged to the second voltage.
[0090] Figure 11 and Figure 12 A circuit diagram of a discharge circuit provided as yet another specific example of this disclosure, such as Figure 11 and Figure 12 As shown, the two ends of the discharge circuit 700 are coupled to the conductive line and the ground voltage VSS, respectively. The discharge circuit 700 includes a first sub-discharge circuit 701 and a second sub-discharge circuit 702.
[0091] The first sub-discharge circuit 701 includes a current mirror circuit and a third transistor Q3. The current mirror circuit includes a first transistor Q1, a second transistor Q2, a constant current source I, and a first switch S1. The first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are both connected to the ground voltage VSS. The control terminal and the second terminal of the first transistor Q1 are both connected to the constant current source I. The second terminal of the second transistor Q2 is coupled to a conductive line. The first terminal of the first switch S1 is connected to the control terminal of the first transistor Q1, and the second terminal of the first switch S1 is connected to the control terminal of the second transistor Q2. The second terminal of the third transistor Q3 is connected to a conductive line, and the first terminal of the third transistor Q3 is connected to the second terminal of the second transistor Q2. The control terminal of the third transistor Q3 is connected to the ground voltage VSS.
[0092] The second sub-discharge circuit 702 includes a third transistor Q3, a second transistor Q2, and a capacitor C; the first plate of the capacitor C is connected to the second terminal of the first switch S1 and the control terminal of the second transistor Q2, and the second plate of the capacitor C is connected to the ground voltage VSS.
[0093] In some specific examples, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all NMOS transistors.
[0094] In some embodiments, the control logic can be configured to: close the first switch S1 in response to a power failure signal, so that the first sub-discharge circuit 701 discharges the operating voltage on the conductive line to a first voltage; and open the first switch S1, so that the second sub-discharge circuit 702 discharges the voltage on the conductive line from the first voltage to a second voltage.
[0095] In this embodiment of the present disclosure, when the first switch S1 is closed, the voltage on the conductive line can be discharged through the first sub-discharge circuit 701, and the magnitude of the discharge current is determined by the magnitude of the current output by the constant current source I. At the same time, the constant current source I can charge the capacitor C. When the first switch S1 is open, the voltage on the first plate of the capacitor C can maintain the gate voltage of the second transistor Q2, and the voltage on the conductive line can be discharged through the second sub-discharge circuit 702.
[0096] Return to reference Figure 10 For a memory device including discharge circuit 700, the voltage curve on the conductive line when a sudden power failure occurs during operation is similar to that of a memory device including discharge circuit 600. During the operation execution phase before the first discharge phase T1, the voltage on the conductive line gradually rises from the ground voltage VSS to the operating voltage.
[0097] When a sudden power failure occurs, in the first discharge stage T1, the first sub-discharge circuit 701 can discharge the operating voltage to the first voltage. Since the operating voltage is high, the discharge current can be controlled by the current mirror circuit in the first sub-discharge circuit 701, thereby reducing the instantaneous discharge speed of the high voltage and avoiding damage to other circuit components in the memory device due to the coupling effect caused by the excessively fast instantaneous discharge speed.
[0098] After the first sub-discharge circuit 701 discharges the operating voltage to the first voltage, the power supply voltage connected to the constant current source I is too low to continue operating the current mirror circuit. In the second discharge stage T2, the second sub-discharge circuit 702 can continue to discharge the first voltage to the second voltage, which can be the ground voltage VSS, for example, 0V. Here, the second sub-discharge circuit 702 can maintain almost the same discharge rate as the first sub-discharge circuit 701.
[0099] In this embodiment of the disclosure, when the voltage drops to a level that cannot sustain the operation of the current mirror circuit, the voltage on the first plate of capacitor C can continue to maintain the voltage on the control terminal of the second transistor Q2, thereby keeping the second transistor Q2 in the on state. The second sub-discharge circuit 702 can continue to discharge the voltage on the conductive line to the second voltage, thereby discharging the higher operating voltage on the conductive line to the ground voltage VSS when the memory device experiences a sudden power failure, avoiding damage to the circuit components in the memory device caused by the higher operating voltage, and mitigating the negative impact of the sudden power failure on the memory device.
[0100] In addition, in conjunction with reference Figure 6 , Figure 9 and Figure 12Compared to discharge circuits 500 and 600, discharge circuit 700 occupies a smaller circuit area, which is more conducive to the miniaturization of memory devices.
[0101] In some embodiments, the memory device may include one or more of the discharge circuits selected from discharge circuit 500, discharge circuit 600, and discharge circuit 700.
[0102] In some embodiments, the number of discharge circuits coupled to the same conductive line can be multiple, that is, the operating voltage on the same conductive line can be discharged by multiple discharge circuits to further mitigate the negative impact of sudden power failure on the memory device and improve the reliability of the memory device.
[0103] Based on a concept similar to the memory devices described above, this disclosure also provides a memory system comprising: at least one memory device as described in any of the foregoing embodiments; and a memory controller coupled to and configured to control the memory device. For the specific composition and functional implementation of the memory system, please refer to the preceding description. Figures 1 to 5 For the sake of brevity, the description will not be repeated here.
[0104] This disclosure also provides a method for operating a memory device. Figure 13 The flowchart illustrating the operation method of the memory device provided in this disclosure is as follows: Figure 13 As shown, the method of operating the memory device includes the following steps:
[0105] Step S10: In response to the power failure signal, the operating voltage on the conductive line is discharged to the first voltage through the first sub-discharge circuit;
[0106] Step S20: Discharge the first voltage to the second voltage through the second sub-discharge circuit.
[0107] In some embodiments, the memory device includes a memory array and a discharge circuit coupled to conductive lines in the memory array, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit.
[0108] In some embodiments, the conductive lines may be source lines, bit lines, or word lines. Before performing step S10, the method of operating the memory device further includes applying an operating voltage to the conductive lines, for example, applying an erase voltage to the source lines and bit lines, or applying an on-state voltage or a programming voltage to the word lines.
[0109] In some embodiments, refer to Figure 6 , Figure 8 and Figure 11The first sub-discharge circuit includes a current mirror circuit and a third transistor Q3. The current mirror circuit includes a first transistor Q1, a second transistor Q2, and a first switch S1 located between the control terminals of the first transistor Q1 and the second transistor Q2. The specific process of executing step S10 includes: in response to a power-down signal, closing the first switch S1, and discharging the operating voltage on the conductive line to a first voltage through the third transistor Q3 and the current mirror circuit. The first voltage is higher than the ground voltage VSS.
[0110] In a specific example, refer to Figure 6 The discharge circuit 500 coupled to the conductive line includes a first sub-discharge circuit 501 and a second sub-discharge circuit 502. The second sub-discharge circuit 502 includes a fourth transistor Q4 and a second switch S2 connected to the control terminal of the fourth transistor Q4. The specific process of executing step S20 includes: opening the first switch S1 and closing the second switch S2 to turn on the fourth transistor Q4 through a first control voltage, and discharging the first voltage to the second voltage through the fourth transistor Q4.
[0111] In another specific example, refer to Figure 8 and Figure 9 The discharge circuit 600 includes a first sub-discharge circuit 601 and a second sub-discharge circuit 602. The second sub-discharge circuit 602 includes a third transistor Q3, a fifth transistor Q5, and a third switch S3 connected to the control terminal of the fifth transistor Q5. The specific process of executing step S20 includes: opening the first switch S1 and closing the third switch S3 to turn on the fifth transistor Q5 through the second control voltage, and discharging the first voltage to the second voltage through the third transistor Q3 and the fifth transistor Q5.
[0112] In yet another specific example, refer to Figure 11 and Figure 12 The discharge circuit 700 coupled to the conductive line includes a first sub-discharge circuit 701 and a second sub-discharge circuit 702. The second sub-discharge circuit 702 includes a third transistor Q3, a second transistor Q2, and a capacitor C. The first and second plates of the capacitor C are respectively connected to the control terminal of the second transistor Q2 and the ground voltage VSS. The specific process of executing step S20 includes: opening the first switch S1, and discharging the first voltage to the second voltage through the third transistor Q3 and the second transistor Q2.
[0113] In this embodiment, after a sudden power failure in the memory device, the current mirror circuit in the first sub-discharge circuit can be used for discharge, and the magnitude of the discharge current can be controlled to reduce the instantaneous discharge rate of the high voltage, thus avoiding damage to other circuit components in the memory device due to the coupling effect caused by the excessively fast instantaneous discharge rate. When the voltage on the conductive line drops to the first voltage, the current mirror circuit in the first sub-discharge circuit can no longer operate. Discharge can then continue through a second sub-discharge circuit including the fourth transistor Q4, a second sub-discharge circuit including the third transistor Q3 and the fifth transistor Q5, or a second sub-discharge circuit including the third transistor Q3, the second transistor Q2, and the capacitor C, to discharge the first voltage to the second voltage, which can be the 0V ground voltage VSS. This discharges the higher operating voltage on the conductive line to a lower voltage, avoiding damage to the circuit components in the memory device caused by the higher operating voltage and mitigating the negative impact of the sudden power failure on the memory device.
[0114] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.
[0115] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.
[0116] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A memory device, characterized in that, The memory device includes peripheral circuitry and a memory array coupled to the peripheral circuitry; the memory array includes conductive lines; the peripheral circuitry includes a discharge circuit coupled to the conductive lines, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit; wherein... The first sub-discharge circuit is configured to discharge the operating voltage on the conductive line to a first voltage in response to a power-down signal; the first sub-discharge circuit includes a current mirror circuit; the current mirror circuit includes a constant current source, a first transistor, a second transistor, and a first switch; the first terminal of the first transistor and the first terminal of the second transistor are both connected to ground voltage; the control terminal and the second terminal of the first transistor are both connected to the constant current source; the second terminal of the second transistor is coupled to the conductive line; the first terminal of the first switch is connected to the control terminal of the first transistor, and the second terminal of the first switch is connected to the control terminal of the second transistor; The second sub-discharge circuit is configured to discharge the first voltage to the second voltage.
2. The memory device according to claim 1, characterized in that, The first sub-discharge circuit further includes a third transistor; the second terminal of the third transistor is connected to the conductive line, and the first terminal of the third transistor is connected to the second terminal of the second transistor; the control terminal of the third transistor is connected to the ground voltage.
3. The memory device according to claim 2, characterized in that, The second sub-discharge circuit includes a fourth transistor and a second switch; the second terminal of the fourth transistor is connected to the conductive line, and the first terminal of the fourth transistor is connected to the ground voltage; the first terminal of the second switch is connected to the control terminal of the fourth transistor, and the second terminal of the second switch receives a first control voltage.
4. The memory device according to claim 2, characterized in that, The second sub-discharge circuit includes the third transistor, the fifth transistor, and the third switch; the first terminal of the fifth transistor is connected to the first terminal of the third transistor, and the second terminal of the fifth transistor is connected to the ground voltage; the first terminal of the third switch is connected to the control terminal of the fifth transistor, and the second terminal of the third switch receives the second control voltage.
5. The memory device according to claim 2, characterized in that, The second sub-discharge circuit includes the third transistor, the second transistor, and a capacitor; the first plate of the capacitor is connected to the second terminal of the first switch and the control terminal of the second transistor; The second plate of the capacitor is connected to the ground voltage.
6. The memory device according to claim 1, characterized in that, The conductive lines include source lines and / or bit lines.
7. A memory system, characterized in that, include: At least one memory device as claimed in any one of claims 1 to 6; A memory controller, coupled to and configured to control the at least one memory device.
8. A method of operating a memory device, characterized in that, The memory device includes a memory array and a discharge circuit coupled to conductive lines in the memory array, the discharge circuit including a first sub-discharge circuit and a second sub-discharge circuit; the operation method includes: In response to a power-down signal, the operating voltage on the conductive line is discharged to a first voltage through the first sub-discharge circuit; the first sub-discharge circuit includes a current mirror circuit; the current mirror circuit includes a first transistor, a second transistor, and a first switch; the first switch is located between the control terminal of the first transistor and the control terminal of the second transistor; The first voltage is discharged to the second voltage through the second sub-discharge circuit.
9. The method of operating the memory device according to claim 8, characterized in that, The first sub-discharge circuit further includes a third transistor; the step of discharging the operating voltage to the first voltage through the first sub-discharge circuit includes: In response to the power failure signal, the first switch is closed, and the operating voltage is discharged to the first voltage through the third transistor and the current mirror circuit; the first voltage is higher than the ground voltage.
10. The method of operating the memory device according to claim 9, characterized in that, The second sub-discharge circuit includes a fourth transistor and a second switch connected to the control terminal of the fourth transistor; The step of discharging the first voltage to the second voltage through the second sub-discharge circuit includes: The first switch is turned off and the second switch is turned on to turn on the fourth transistor through the first control voltage, and the first voltage is discharged to the second voltage through the fourth transistor.
11. The method of operating the memory device according to claim 9, characterized in that, The second sub-discharge circuit includes the third transistor, the fifth transistor, and a third switch connected to the control terminal of the fifth transistor; The step of discharging the first voltage to the second voltage through the second sub-discharge circuit includes: The first switch is turned off and the third switch is turned on to turn on the fifth transistor through the second control voltage, and the first voltage is discharged to the second voltage through the third transistor and the fifth transistor.
12. The method of operating the memory device according to claim 9, characterized in that, The second sub-discharge circuit includes the third transistor, the second transistor, and a capacitor; the first plate and the second plate of the capacitor are respectively connected to the control terminal of the second transistor and the ground voltage; The step of discharging the first voltage to the second voltage through the second sub-discharge circuit includes: The first switch is turned off, and the first voltage is discharged to the second voltage through the third transistor and the second transistor.