Display panel and display device

Abstract

The application belongs to the technical field of display, and particularly relates to a display panel and a display device. The display panel comprises a substrate, a pixel unit, a scanning line and a pixel electrode. The scanning line is provided with a plurality of openings which are closed in the thickness direction of the scanning line, and the openings correspond to the sub-pixels one by one. The pixel electrode comprises an electrode body part, an electrode extension part and an electrode connection part. The electrode connection part is connected with the electrode body part through the electrode extension part, and the electrode connection part is connected with the source electrode through a through hole. The orthographic projection of the electrode connection part on the substrate is located in the orthographic projection of the opening on the substrate, and the orthographic projection of the electrode connection part on the substrate and the inner edge of the orthographic projection of the opening on the substrate both have a gap. The scheme can effectively improve the parasitic capacitance difference between the electrode connection part of the pixel electrode and the scanning line caused by different sub-pixels due to the process.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a display panel and a display device. Background Art

[0002] In the field of display technology, display panels and display devices are typically driven by thin-film transistors. With the advancement of display technology, a half-source (also known as dual-gate) drive method is often used to drive pixel arrays to reduce costs. This dual-gate drive method can halve the number of data lines compared to traditional drive methods, thereby reducing the number of source driver circuits, and thus the number of driver chips, thereby lowering costs.

[0003] However, the parasitic capacitance generated by each sub-pixel in the existing dual-gate drive display panel is different, resulting in differences between different sub-pixels, leading to poor display effects of the display panel. Summary of the Invention

[0004] The purpose of the present application is to solve the problem in the prior art that parasitic capacitances generated by different sub-pixels are different, resulting in differences between different sub-pixels and poor display effects of the display panel.

[0005] According to a first aspect of the present application, a display panel is provided, comprising a substrate and pixel units formed on the substrate, wherein a plurality of the pixel units are arranged in an array in row and column directions, each of the pixel units comprises a plurality of sub-pixels arranged in an array, each of the sub-pixels comprises a transistor, the transistor comprising a gate, a semiconductor layer, and a source and a drain provided at opposite ends of the semiconductor layer, the orthographic projection of the semiconductor layer on the substrate being located within the orthographic projection of the gate on the substrate; the display panel further comprises: a scan line extending in the row direction, the scan line being provided with a plurality of openings closed in the thickness direction thereof, and the openings corresponding one-to-one to the sub-pixels; a pixel electrode comprising an electrode body, an electrode extension, and an electrode connection portion, the electrode connection portion being connected to the electrode body via the electrode extension, and the electrode connection portion being connected to the source via a through-hole; wherein the orthographic projection of the electrode connection portion on the substrate is located within the orthographic projection of the opening on the substrate, and a gap is left between the orthographic projection of the electrode connection portion on the substrate and the inner edge of the orthographic projection of the opening on the substrate.

[0006] In an exemplary embodiment of the present application, the orthographic projection of the electrode connecting portion on the base substrate is located at the center of the orthographic projection of the opening on the base substrate.

[0007] In an exemplary embodiment of the present application, the scanning line includes a plurality of scanning units connected in sequence, and the scanning units correspond one-to-one to the sub-pixels. The scanning unit includes a main body, a first extension part, a second extension part and a third extension part, the first extension part and the second extension part are arranged parallel to each other, the main body connects one end of the first extension part and the second extension part, and the opposite two ends of the third extension part are respectively connected to the other end of the first extension part and the second extension part, and the main body, the first extension part, the second extension part and the third extension part are arranged to form a closed opening; the main body of a scanning unit is connected to the first extension part of the adjacent scanning unit; part of the main body is the gate of the transistor; the display panel also includes a data line extending in the column direction, and the data line is connected to the drain; wherein the orthographic projection of the third extension part on the substrate is located between the orthographic projection of the electrode connecting part on the substrate and the orthographic projection of the data line on the substrate.

[0008] In an exemplary embodiment of the present application, the display panel includes a first scan line and a second scan line arranged between two adjacent rows of pixel units, and the first scan line and the second scan line are arranged at intervals from each other; the display panel includes a first pixel unit and a second pixel unit arranged at intervals in the row direction, the first pixel unit includes a plurality of first sub-pixels arranged in sequence in the row direction, the first sub-pixels each include a first transistor, and the gate of the first transistor is connected to the first scan line; the second pixel unit includes a plurality of second sub-pixels arranged in sequence in the row direction, the second sub-pixels each include a second transistor, and the gate of the second transistor is connected to the second scan line; the direction in which the source in the first transistor points to the drain is the same as the direction in which the source in the second transistor points to the drain.

[0009] In an exemplary embodiment of the present application, the scanning direction is from the first scanning line to the second scanning line.

[0010] In an exemplary embodiment of the present application, the display panel further includes: a first pixel electrode, including a first electrode body portion, a first electrode connecting portion, and a first electrode extension portion for connecting the first electrode body portion and the first electrode connecting portion, the first electrode connecting portion being connected to the source of the first transistor through a first through-hole, the first electrode body portion including a first column trunk extending in the column direction and a first row trunk extending in the row direction, the first column trunk and the first row trunk intersecting and dividing the first electrode body portion into four first slit electrode portions, the first slit electrode portion having a plurality of electrode branches spaced apart, adjacent electrodes in the first slit electrode portion A slit is formed between the two electrode branches; the second pixel electrode includes a second electrode body, a second electrode connecting portion, and a second electrode extension portion for connecting the second electrode body and the second electrode connecting portion, the second electrode connecting portion is connected to the source of the second transistor through a second through hole, the second electrode body includes a second column trunk extending in the column direction and a second row trunk extending in the row direction, the second column trunk and the second row trunk intersect and divide the second electrode body into four second slit electrode portions, the second slit electrode portion has a plurality of electrode branches arranged at intervals, and the slit is formed between two adjacent electrode branches in the second slit electrode portion.

[0011] In an exemplary embodiment of the present application, the length of the second electrode extension portion in the column direction is greater than the length of the first electrode extension portion in the column direction; the first pixel electrode also includes a first electrode strip, the first electrode strip is arranged on a side of the first electrode body portion away from the first electrode extension portion, and extends in a direction away from the first electrode body portion, and the first electrode strip and the first electrode extension portion are located on the same column; the second pixel electrode also includes a second electrode strip, the second electrode strip is arranged on a side of the second electrode body portion away from the second electrode extension portion, and extends in a direction away from the second electrode body portion, and the second electrode strip and the second electrode extension portion are located on the same column; wherein the sum of the lengths of the first electrode strip and the first electrode extension portion in the column direction is equal to the sum of the lengths of the second electrode strip and the second electrode extension portion in the column direction.

[0012] In an exemplary embodiment of the present application, the display panel also includes a data line, the data line includes a data main line, a first data branch line and a second data branch line, the first data branch line and the second data branch line are both connected to the data main line, the first data branch line is used to connect to the drain of the Nth (N≥1) first sub-pixel in the first pixel unit, and the second data branch line is used to connect to the drain of the Nth (N≥1) second sub-pixel in the second pixel unit.

[0013] In an exemplary embodiment of the present application, the colors of the first sub-pixels in the same column are the same; the colors of the second sub-pixels in the same column are the same.

[0014] A second aspect of the present application provides a display device, comprising: a flexible circuit board; a chip-on-film connected to the flexible circuit board; and a display panel as described in any one of the above items, wherein the display panel is electrically connected to the flexible circuit board via the chip-on-film.

[0015] The display panel and display device of the present application have at least the following beneficial effects:

[0016] The display panel of the present application includes a base substrate and pixel units, scanning lines and pixel electrodes arranged on the base substrate. The scanning lines are extended in the row direction. The scanning lines are provided with multiple closed openings, and the openings correspond one-to-one to the sub-pixels. The electrode connection portion in the pixel electrode for connecting to the transistor source is provided in the opening, and there is a gap between the positive projection of the electrode connection portion on the base substrate and the inner edge of the positive projection of the opening on the base substrate. Therefore, in the process of preparing the pixel electrode, when the electrode connection portion of the pixel electrode is offset up, down, left, and right, the parasitic capacitance generated between the electrode connection portion of the pixel electrode and the scanning line is a constant value, which can effectively improve the parasitic capacitance difference between the electrode connection portion of the pixel electrode and the scanning line between different sub-pixels due to process reasons, and can also improve the quality difference between the same encoding pieces and encoding pieces of the display panel, thereby effectively improving the quality and product yield of the display panel.

[0017] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 A structural schematic diagram of the arrangement of the first pixel unit and the second pixel unit provided in Example 1, Example 2 or Example 3 of the present application is shown.

[0021] Figure 2A schematic structural diagram of the first sub-pixel and the second sub-pixel provided in Example 1 or Example 3 of the present application is shown.

[0022] Figure 3 A structural schematic diagram of the arrangement of the first scan line, the second scan line, the first common electrode and the second common electrode provided in the first, second or third embodiment of the present application is shown.

[0023] Figure 4 A schematic structural diagram of the first pixel electrode and the second pixel electrode provided in Example 1 or Example 3 of the present application is shown.

[0024] Figure 5 A schematic structural diagram is shown in which the source and drain provided in Example 1, Example 2 or Example 3 of the present application are respectively overlapped at opposite ends of the semiconductor layer.

[0025] Figure 6 A structural schematic diagram is shown in which the first pixel electrode provided in the second or third embodiment of the present application is provided with a first electrode strip and the second pixel electrode is provided with a second electrode strip.

[0026] Figure 7 A schematic structural diagram of the second pixel electrode provided in the second or third embodiment of the present application is shown.

[0027] Description of reference numerals:

[0028] 10. Display device; 100. Display panel; 110. Base substrate; 120. Pixel unit;

[0029] 120a, first pixel unit; 1210, first sub-pixel; 1211, first transistor; 12110, first gate; 12111, first semiconductor layer; 12112, first source; 12113, first drain; 1212, first common electrode;

[0030] 1213, first pixel electrode; 12130, first electrode connecting portion; 12131, first electrode main portion; 121310, first column trunk; 121311, first row trunk; 12132, first electrode extension portion; 12133, first electrode strip;

[0031] 120b, second pixel unit; 1220, second sub-pixel; 1221, second transistor; 12210, second gate; 12211, second semiconductor layer; 12212, second source; 12213, second drain; 1222, second common electrode;

[0032] 1223, second pixel electrode; 12230, second electrode connecting portion; 12231, second electrode main body; 122310, second column trunk; 122311, second row trunk; 12232, second electrode extension portion; 12233, second electrode strip;

[0033] 130a, first scanning line; 130b, second scanning line; 131, first opening; 132, second opening; 133, main body; 134, first extension; 135, second extension; 136, third extension;

[0034] 140, first through hole; 150, second through hole; 160, data line; 161, main data line; 162, first data branch line; 163, second data branch line; 200, flexible circuit board; 300, chip-on-film. DETAILED DESCRIPTION

[0035] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0036] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0037] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0038] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0039] Example 1

[0040] Figure 1 A structural schematic diagram of the arrangement of the first pixel unit and the second pixel unit provided in this application is shown. Figure 2 A schematic structural diagram of the first sub-pixel and the second sub-pixel provided in this application is shown. Figure 3 A schematic structural diagram of the arrangement of the first scan line, the second scan line, the first common electrode and the second common electrode provided by the present application is shown. Figure 4 A schematic structural diagram of the first pixel electrode and the second pixel electrode provided in this application is shown. Figure 5 A schematic diagram of the structure in which the source and drain provided by the present application are respectively overlapped at two opposite ends of the semiconductor layer is shown.

[0041] See also Figure 1 As shown, the first embodiment of the present application provides a display panel 100 , which may include a base substrate 110 and a plurality of pixel units 120 .

[0042] The base substrate 110 can be a glass substrate, but can also be a substrate made of other materials, such as PI material.

[0043] See also Figure 1 As shown, a plurality of pixel units 120 may be arrayed on the substrate 110 along the row direction X and the column direction Y. Each pixel unit 120 may include a plurality of sub-pixels arranged in an array, and the plurality of sub-pixels may be sequentially spaced in the row direction X and the column direction Y.

[0044] Each sub-pixel may include a transistor, which includes a gate, a semiconductor layer, and a source and a drain located at opposite ends of the semiconductor layer. A gate insulating layer is provided between the gate and the semiconductor layer to insulate the gate and the semiconductor layer from each other.

[0045] It should be noted that the orthographic projection of the semiconductor layer on the substrate 110 may be located within the orthographic projection of the gate on the substrate 110. The source and drain are respectively overlapped on the source and drain doped regions of the semiconductor layer; that is, the source and drain are respectively overlapped on opposite ends of the semiconductor layer.

[0046] In addition, the gate electrode and the scan line described below are arranged on the same layer, and the source electrode, the drain electrode and the data line 160 described below are arranged on the same layer.

[0047] In addition, in this application, "same-layer arrangement" refers to the use of the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0048] In some embodiments of the present application, the display panel 100 further includes scan lines. The scan lines extend in the row direction X, and a plurality of scan lines are sequentially spaced apart in the column direction Y. The scan lines can be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but are not limited thereto and can also be made of other materials with good electrical conductivity.

[0049] In some embodiments of the present application, each scanning line is provided with a plurality of closed openings extending through the scanning line in its thickness direction, and the openings correspond to sub-pixels one-to-one, that is, one sub-pixel corresponds to one opening.

[0050] In some embodiments of the present application, the display panel 100 further includes pixel electrodes. The pixel electrodes may be transparent electrodes, for example, they may be made of ITO (indium tin oxide) material to improve light transmittance, but are not limited thereto and may also be made of other transparent conductive materials.

[0051] In some embodiments of the present application, a pixel electrode may include an electrode body portion, an electrode extension portion, and an electrode connection portion. The electrode body portion is configured to receive electrical signals to control the deflection of liquid crystal molecules. The electrode connection portion is connected to the source of the transistor via a through-hole, such that the electrical signal is transmitted from the source to the electrode connection portion. The electrode connection portion is connected to the electrode body portion via the electrode extension portion. In other words, the electrical signal on the source is transmitted to the electrode body portion via the electrode connection portion and the electrode extension portion to control the deflection of the liquid crystal molecules.

[0052] In some embodiments of the present application, the orthographic projection of the electrode connection portion on the base substrate 110 is located within the orthographic projection of the closed opening of the scan line on the base substrate 110, and a gap is left between the orthographic projection of the electrode connection portion on the base substrate 110 and the inner edge of the orthographic projection of the opening on the base substrate 110. In this way, when an offset occurs during the preparation of the pixel electrode, when the electrode connection portion of the pixel electrode offsets up, down, left, or right, the parasitic capacitance generated between the electrode connection portion of the pixel electrode and the scan line is constant, which can effectively improve the parasitic capacitance difference between the electrode connection portion of the pixel electrode and the scan line between different sub-pixels due to process reasons, and can also improve the quality difference between the same encoding chips of the display panel 100, thereby effectively improving the quality and product yield of the display panel 100, and improving product efficiency and competitiveness.

[0053] In some embodiments of the present application, the orthographic projection of the electrode connection portion on the base substrate 110 is located at the center of the orthographic projection of the opening on the base substrate 110. In other words, the electrode connection portion is centered to ensure that the parasitic capacitance between the electrode connection portion and the scan line does not change due to process factors. This can effectively reduce the parasitic capacitance differences between different sub-pixels, thereby improving the quality and product yield of the display panel 100.

[0054] It is understandable that the opening may also be other types of closed holes, such as circular, diamond or triangular closed holes, and the electrode connecting portion is located at the center of the closed opening.

[0055] In some embodiments of the present application, each scan line includes a plurality of interconnected scan units, and there is a one-to-one correspondence between the scan units and the sub-pixels, that is, one sub-pixel corresponds to one scan unit (not shown in the figure).

[0056] In some embodiments of this application, see Figure 3 As shown, each scanning unit includes a main body 133, a first extension portion 134, a second extension portion 135, and a third extension portion 136. The first extension portion 134 and the second extension portion 135 are arranged parallel to each other and extend in the row direction X. The main body 133 is connected to one end of the first extension portion 134 and the second extension portion 135, and the opposite ends of the third extension portion 136 are respectively connected to the other ends of the first extension portion 134 and the second extension portion 135. The third extension portion 136 extends in the column direction Y. The main body 133, the first extension portion 134, the second extension portion 135, and the third extension portion 136 surround and form the aforementioned closed opening, which is a square hole.

[0057] It should be noted that the main body 133 of a scanning unit is connected to the first extension portion 134 of an adjacent scanning unit, so that the adjacent scanning units are connected.

[0058] In addition, at least a portion of the main body 133 may be a gate of a transistor, that is, the orthographic projection of the semiconductor layer on the base substrate 110 is located within the orthographic projection of the main body 133 on the base substrate 110 .

[0059] In some embodiments of the present application, the distance between the orthographic projection of the electrode connection portion on the substrate 110 and the orthographic projection of the main portion 133 on the substrate 110 is the same as the distance between the orthographic projection of the electrode connection portion on the substrate 110 and the orthographic projection of the third extension portion 136 on the substrate 110; and the distance between the orthographic projection of the electrode connection portion on the substrate 110 and the orthographic projection of the first extension portion 134 on the substrate 110 is the same as the distance between the orthographic projection of the electrode connection portion on the substrate 110 and the orthographic projection of the second extension portion 135 on the substrate 110. In this way, the orthographic projection of the electrode connection portion on the substrate 110 is located at the center of the opening, ensuring that the parasitic capacitance between each sub-pixel is the same, preventing parasitic capacitance from changing due to process factors, and improving the quality and product yield of the display panel 100.

[0060] In some embodiments of the present application, the display panel 100 may include data lines 160 extending in the column direction Y. A plurality of data lines 160 are arranged at intervals in the row direction X, and the data lines 160 are electrically connected to the drain of the transistor to transmit the data signal transmitted on the data line 160 to the drain, and then to the source through the semiconductor layer, and then to the pixel electrode to control the deflection angle of the liquid crystal molecules.

[0061] The data line 160 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but is not limited thereto and may also be made of other materials with good electrical conductivity.

[0062] In some embodiments of this application, see Figure 2 As shown, the orthographic projection of the third extension portion 136 of the scanning line on the base substrate 110 is located between the orthographic projection of the electrode connecting portion on the base substrate 110 and the orthographic projection of the data line 160 on the base substrate 110. The third extension portion 136 is arranged between the electrode connecting portion and the data line 160, and because the scanning signal transmitted on the third extension portion 136 is different from the data signal and the signal of the pixel electrode, the third extension portion 136 can shield the lateral parasitic capacitance formed between the data line 160 and the pixel electrode, thereby improving the panel crosstalk problem.

[0063] It can be understood that the electrode main body is connected to the electrode connecting part through the electrode extension part, and since the electrode connecting part is located in the closed opening, part of the electrode extension part will also be located in this closed opening. The third extension part 136 will also shield the parasitic capacitance generated between the electrode extension parts, further improving the panel crosstalk problem.

[0064] In addition, since the lateral parasitic capacitance between the data line 160 and the pixel electrode can be shielded, the distance between the data line 160 and the pixel electrode can be reduced, thereby effectively improving the pixel aperture ratio and the transmittance of the display panel 100.

[0065] The following describes in detail the display panel including two different pixel units:

[0066] In some embodiments of the present application, the display panel 100 includes a first pixel unit 120a and a second pixel unit 120b. The first pixel unit 120a and the second pixel unit 120b have the same structure and are arranged in the same row in a sequential order.

[0067] In some embodiments of the present application, the first pixel unit 120a and the second pixel unit 120b both include the same number of sub-pixels.

[0068] For example, see Figure 1 As shown, the first pixel unit 120a includes six first sub-pixels 1210, and the six first sub-pixels 1210 are arranged in sequence along the row direction X. The six first sub-pixels 1210 may include two red first sub-pixels, two green first sub-pixels, and two blue first sub-pixels. Correspondingly, the second pixel unit 120b may also include six second sub-pixels 1220, and the six second sub-pixels 1220 are arranged in sequence along the row direction X. The six second sub-pixels 1220 may include two red second sub-pixels, two green second sub-pixels, and two blue second sub-pixels.

[0069] The six first sub-pixels 1210 in the first pixel unit 120a can be arranged as a red first sub-pixel, a green first sub-pixel, a blue first sub-pixel, a red first sub-pixel, a green first sub-pixel, and a blue first sub-pixel. The six second sub-pixels 1220 in the second pixel unit 120b can be arranged in the same manner as the six first sub-pixels 1210 in the first pixel unit 120a to prevent color difference and maintain the display effect of the display panel 100. For example, the six second sub-pixels 1220 in the second pixel unit 120b can be arranged as a red second sub-pixel, a green second sub-pixel, a blue second sub-pixel, a red second sub-pixel, a green second sub-pixel, and a blue second sub-pixel.

[0070] It can be understood that the red first / second sub-pixel, the green first / second sub-pixel and the blue first / second sub-pixel correspond to sub-pixels emitting corresponding color light. For example, the red first / second sub-pixel emits red light, the green first / second sub-pixel emits green light, and the blue first / second sub-pixel emits blue light.

[0071] Among them, see Figures 2 to 5 As shown, each first sub-pixel 1210 includes a first transistor 1211. The first transistor 1211 includes a first gate electrode 12110, a first semiconductor layer 12111, and a first source electrode 12112 and a first drain electrode 12113 disposed on the same layer. A gate insulating layer (not shown) is disposed between the first gate electrode 12110 and the first semiconductor layer 12111 to insulate the first gate electrode 12110 from the first semiconductor layer 12111.

[0072] It should be noted that the orthographic projection of the first semiconductor layer 12111 on the base substrate 110 may be located within the orthographic projection of the first gate 12110 on the base substrate 110. The first source electrode 12112 and the first drain electrode 12113 are respectively overlapped on the source and drain doped regions of the first semiconductor layer 12111; that is, the first source electrode 12112 and the first drain electrode 12113 are respectively overlapped on opposite ends of the first semiconductor layer 12111.

[0073] Accordingly, see Figures 2 to 5 As shown, each second sub-pixel 1220 includes a second transistor 1221. The second transistor 1221 includes a second gate electrode 12210, a second semiconductor layer 12211, and a second source electrode 12212 and a second drain electrode 12213 disposed on the same layer. A gate insulating layer is provided between the second gate electrode 12210 and the second semiconductor layer 12211 to insulate the second gate electrode 12210 from the second semiconductor layer 12211.

[0074] It should be noted that the orthographic projection of the second semiconductor layer 12211 on the base substrate 110 can be located within the orthographic projection of the second gate 12210 on the base substrate 110. The second source 12212 and the second drain 12213 are respectively overlapped on the source and drain doped regions of the second semiconductor layer 12211; that is, the second source 12212 and the second drain 12213 are respectively overlapped on opposite ends of the second semiconductor layer 12211.

[0075] In addition, the first gate 12110, the second gate 12210, and the first scan line 130a and the second scan line 130b described below are arranged on the same layer, the first source 12112, the first drain 12113, the second source 12212, the second drain 12213, and the data line 160 described below are arranged on the same layer, and the first semiconductor layer 12111 and the second semiconductor layer 12211 are arranged on the same layer.

[0076] It is worth mentioning that see Figure 2 As shown, the channel curvature direction of the first transistor 1211 in the first sub-pixel 1210 is the same as the channel curvature direction of the second transistor 1221 in the second sub-pixel 1220. That is, the direction from the first source 12112 to the first drain 12113 is the same as the direction from the second source 12212 to the second drain 12213. This prevents differences in the parasitic capacitance Cgs generated between the first source 12112 and the first gate 12110 and between the second source 12212 and the second gate 12210 due to manufacturing process factors. This ensures consistent brightness between adjacent sub-pixels at the same grayscale, reduces the appearance of head shake lines, and improves the quality of the display panel 100.

[0077] For example, the direction from the first source electrode 12112 to the first drain electrode 12113 and the direction from the second source electrode 12212 to the second drain electrode 12213 are designed to be the same. When the first / second semiconductor layer shifts left or right due to manufacturing process reasons, the area covered by the first semiconductor layer 12111 in the first sub-pixel 1210 and the area covered by the first semiconductor layer 12111 in the second sub-pixel 1220 are the same. In other words, the parasitic capacitance Cgs generated between the first source electrode 12112 and the first gate electrode 12110 is the same as the parasitic capacitance Cgs generated between the second source electrode 12212 and the second gate electrode 12210. This ensures consistent pixel brightness at the same grayscale, reduces the appearance of head shake lines, and improves the quality of the display panel 100.

[0078] In some embodiments of this application, see Figure 1 and Figure 2 As shown, a first scan line 130a and a second scan line 130b are provided between two adjacent rows of pixel units 120, and are spaced apart in the column direction Y. That is, the first scan line 130a is located above the second scan line 130b. Furthermore, the first scan line 130a and the second scan line 130b are both extended in the row direction X.

[0079] It should be noted that the closed openings are formed on both the first scanning line 130 a and the second scanning line 130 b .

[0080] For example, seeFigure 2 and Figure 3 As shown, a first opening 131 is defined on the first scan line 130a, and a second opening 132 is defined on the second scan line 130b. The first opening 131 corresponds to the first sub-pixel 1210, and the second opening 132 corresponds to the second sub-pixel 1220. That is, the electrode connection portion of the pixel electrode in the first sub-pixel 1210 is located within the first opening 131, and the electrode connection portion of the pixel electrode in the second sub-pixel 1220 is located within the second opening 132. This ensures that the parasitic capacitance generated between the electrode connection portion of the pixel electrode and the scan line remains constant when the pixel electrode is shifted, such as vertically, horizontally, or horizontally, during the manufacturing process. This effectively reduces parasitic capacitance differences between the electrode connection portion of the pixel electrode and the scan line between different sub-pixels due to manufacturing process issues, and also reduces quality differences between the same encoding chips of the display panel 100. This effectively improves the quality and product yield of the display panel 100, enhancing product efficiency and competitiveness.

[0081] In addition, the first scan line 130a is connected to the first gate 12110 in the first sub-pixel 1210 to provide a scan signal to the first gate 12110; the second scan line 130b is connected to the second gate 12210 in the second sub-pixel 1220 to provide a scan signal to the second gate 12210.

[0082] That is, the scan signal on the first scan line 130a controls the first transistor 1211 in the first sub-pixel 1210 to turn on or off, and the scan signal on the second scan line 130b controls the second transistor 1221 in the second sub-pixel 1220 to turn on or off, and both control the sub-pixels in different pixel units 120 respectively.

[0083] The first scanning line 130a and the second scanning line 130b can be made of metal or alloy materials, such as molybdenum, aluminum and titanium, to ensure good electrical conductivity, but are not limited thereto and can also be made of other materials with good electrical conductivity.

[0084] In some embodiments of the present application, the scanning direction in the present application is from the first scanning line 130a to the second scanning line 130b, that is, the first transistor 1211 in the first sub-pixel 1210 is first turned on, and then the second transistor 1221 in the second sub-pixel 1220 is turned on.

[0085] In this way, when the first scan line 130a controls the first transistor 1211 in the first sub-pixel 1210 to turn on, the second sub-pixel 1220 is affected by the parasitic capacitance Cgs between the first source 12112 and the first gate 12110 in the first sub-pixel 1210 and generates a feedthrough voltage (Feedthrough △V). However, after scanning the first scan line 130a, the second scan line 130b is scanned again, so that the second sub-pixel 1220 is charged with its own preset signal. The final charging effect of the second sub-pixel 1220 will not be affected by the feedthrough voltage (Feedthrough △V) generated by the parasitic capacitance Cgs between the first source 12112 and the first gate 12110 in the first sub-pixel 1210, thereby reducing the difference in brightness between the first sub-pixel 1210 and the second sub-pixel 1220, further alleviating the shaking head problem of the display panel 100, and improving the display quality of the display panel 100.

[0086] For example, a first scan line 130a, a second scan line 130b, a third scan line, and a fourth scan line are sequentially provided from top to bottom. The first scan line 130a and the second scan line 130b are located between two adjacent rows of pixel units 120, and the third scan line and the fourth scan line are located between another two adjacent rows of pixel units 120. They are respectively connected to transistors in different sub-pixels. For example, the first scan line 130a is connected to the first sub-pixel 1210, the second scan line 130b is connected to the second sub-pixel 1220, the third scan line is connected to the third sub-pixel, and the fourth scan line is connected to the fourth sub-pixel. The first sub-pixel 1210 and the second sub-pixel 1220 are arranged in the same row and adjacent to each other, the first sub-pixel 1210 and the third sub-pixel are arranged in the same column and adjacent to each other, the third sub-pixel and the fourth sub-pixel are arranged in the same row and adjacent to each other, and the second sub-pixel 1220 and the fourth sub-pixel are arranged in the same column and adjacent to each other.

[0087] Scanning is performed in the direction of the first scan line 130a, the second scan line 130b, the third scan line, and the fourth scan line. When the second scan line 130b is turned on, the third subpixel is affected by the feedthrough voltage (ΔV) generated by the parasitic capacitance Cgs between the gate and source of the second subpixel 1220. However, when the third scan line is then turned on, the third subpixel is charged with its own preset signal. The final charging effect of the third subpixel is not affected by the feedthrough voltage (ΔV) generated by the parasitic capacitance Cgs between the gate and source of the second subpixel 1220. When the second scan line 130b or the third scan line is turned on, the fourth sub-pixel is affected by the feedthrough voltage (Feedthrough △V) generated by the parasitic capacitance Cgs between the source and gate in the second sub-pixel 1220 and the third sub-pixel, respectively. That is, the fourth sub-pixel is affected by the first feedthrough voltage △V1 in the second sub-pixel 1220 and the second feedthrough voltage △V2 in the third sub-pixel. However, when the fourth scan line is subsequently turned on, the fourth sub-pixel will charge its own preset signal, and the final charging effect of the fourth sub-pixel is not affected by the feedthrough voltage (Feedthrough △V) generated by the parasitic capacitance Cgs of the second scan line 130b and the parasitic capacitance Cgs of the third scan line.

[0088] In this way, the novel pixel architecture in the present application is not affected by the feedthrough voltage (Feedthrough △V) generated by the parasitic capacitance Cgs of adjacent scan lines, thereby reducing the brightness difference between adjacent sub-pixels and better alleviating the shaking head wrinkle problem.

[0089] In some embodiments of this application, see Figure 2 and Figure 4 As shown, the display panel 100 further includes a first pixel electrode 1213 and a second pixel electrode 1223. The first pixel electrode 1213 can be connected to the first source electrode 12112 via a first through hole 140, so that a data signal on the data line 160 is written into the first pixel electrode 1213. The second pixel electrode 1223 can be connected to the second source electrode 12212 via a second through hole 150, so that a data signal on the data line 160 described below is written into the second pixel electrode 1223.

[0090] The first pixel electrode 1213 and the second pixel electrode 1223 of the embodiment of the present application may be transparent electrodes. For example, they may be made of ITO (indium tin oxide) material to improve light transmittance, but are not limited thereto and may also be made of other transparent conductive materials.

[0091] For example, the first pixel electrode 1213 may be formed after the first source 12112 and the first drain 12113 of the first transistor 1211 are formed, and the second pixel electrode 1223 may be formed after the second source 12212 and the second drain 12213 of the second transistor 1221 are formed. Furthermore, an insulating layer may be provided between the first pixel electrode 1213 and the second pixel electrode 1223 and the metal layer where the source and drain of the transistor are located. The first pixel electrode 1213 may be connected to the first source 12112 of the first transistor 1211 via a first through-hole 140 penetrating this insulating layer, and the second pixel electrode 1223 may be connected to the second source 12212 of the second transistor 1221 via a second through-hole 150 penetrating this insulating layer.

[0092] Among them, see Figure 4 As shown, the first pixel electrode 1213 includes a first electrode connecting portion 12130, a first electrode body portion 12131, and a first electrode extension portion 12132 for connecting the first electrode connecting portion 12130 and the first electrode body portion 12131. The first electrode connecting portion 12130 is electrically connected to a side of the first source electrode 12112 away from the first drain electrode 12113 via a first through-hole 140, so that a data signal on the first source electrode 12112 is transmitted to the first electrode body portion 12131 through the first through-hole 140, the first electrode connecting portion 12130, and the first electrode extension portion 12132, thereby controlling the deflection angle of the liquid crystal molecules in the display panel 100.

[0093] See also Figure 2 As shown, the orthographic projection of the first electrode connection portion 12130 on the base substrate 110 is located within the orthographic projection of the first opening 131 on the base substrate 110, so as to avoid parasitic capacitance differences between sub-pixels due to process problems and ensure the quality and product yield of the display panel 100.

[0094] See also Figure 4 As shown, the first electrode body 12131 is a slit electrode, which includes a first column trunk 121310 extending in the column direction Y and a first row trunk 121311 extending in the row direction X. The first column trunk 121310 and the first row trunk 121311 intersect and divide the first electrode body 12131 into four first slit electrode parts (not shown in the figure). The first slit electrode part has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the first slit electrode part.

[0095] Accordingly, see Figure 2 and Figure 4As shown, the second pixel electrode 1223 includes a second electrode connecting portion 12230, a second electrode main body portion 12231 and a second electrode extension portion 12232 for connecting the second electrode connecting portion 12230 and the second electrode main body portion 12231. The second electrode connecting portion 12230 is electrically connected to the side of the second source 12212 away from the second drain 12213 through the second through hole 150, so that the data signal on the second source 12212 is transmitted to the second electrode main body portion 12231 through the second through hole 150, the second electrode connecting portion 12230 and the second electrode extension portion 12232 to control the deflection angle of the liquid crystal molecules in the display panel 100.

[0096] Among them, see Figure 2 As shown, the orthographic projection of the second electrode connection portion 12230 on the base substrate 110 is located within the orthographic projection of the second opening 132 on the base substrate 110, so as to avoid parasitic capacitance differences between sub-pixels due to process problems and ensure the quality and product yield of the display panel 100.

[0097] It can be understood that the parasitic capacitance generated by the first electrode connecting portion 12130 in the first opening 131 and the first scanning line 130a is the same as the parasitic capacitance generated by the second electrode connecting portion 12230 in the second opening 132 and the second scanning line 130b, so as to ensure that the parasitic capacitances between different sub-pixels are the same, thereby ensuring the quality and product yield of the display panel 100.

[0098] See also Figure 4 As shown, the second electrode body 12231 is a slit electrode, which includes a second column trunk 122310 extending in the column direction Y and a second row trunk 122311 extending in the row direction X. The second column trunk 122310 and the second row trunk 122311 intersect and divide the second electrode body 12231 into four second slit electrode parts (not shown in the figure). The second slit electrode part has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the second slit electrode part.

[0099] In some embodiments of this application, see Figure 2 and Figure 3 As shown, the first sub-pixel 1210 further includes a first common electrode 1212 , which can be arranged in the same layer as the first scan line 130 a , the second scan line 130 b , the first gate 12110 and the second gate 12210 , and can form a storage capacitor with the first pixel electrode 1213 .

[0100] Accordingly, see Figure 2 and Figure 3As shown, the second sub-pixel 1220 also includes a second common electrode 1222, which can be arranged in the same layer as the first scan line 130a, the second scan line 130b, the first gate 12110, the second gate 12210 and the first common electrode 1212, and can form a storage capacitor with the second pixel electrode 1223.

[0101] The first common electrode 1212 and the second common electrode 1222 between the adjacent first sub-pixel 1210 and the second sub-pixel 1220 may be extended in the same row direction, and the first common electrode 1212 is connected to the second common electrode 1222 .

[0102] In some embodiments of the present application, the sub-pixels in the same column direction Y have the same color, that is, the first sub-pixels 1210 in the same column have the same color, and the second sub-pixels 1220 in the same column have the same color.

[0103] In some embodiments of this application, see Figure 1 As shown, the data line 160 includes a data main line 161, a first data branch line 162 and a second data branch line 163. The first data branch line 162 and the second data branch line 163 are both connected to the data main line 161. The first data branch line 162 and the second data branch line 163 are respectively connected to the first drain 12113 in the first sub-pixel 1210 and the second drain 12213 in the second sub-pixel 1220.

[0104] For example, the first data branch line 162 is used to connect to the first drain 12113 of the Nth (N≥1) first sub-pixel 1210 in the first pixel unit 120a, and the second data branch line 163 is used to connect to the second drain 12213 of the Nth (N≥1) second sub-pixel 1220 in the second pixel unit 120b.

[0105] For example, the first data branch line 162 is connected to the first drain 12113 of the first first sub-pixel 1210 in the first pixel unit 120a, and the second data branch line 163 is connected to the second drain 12213 of the first second sub-pixel 1220 in the second pixel unit 120b. The first data branch line 162 is connected to the first drain 12113 of the second first sub-pixel 1210 in the first pixel unit 120a, and the second data branch line 163 is connected to the second drain 12213 of the second second sub-pixel 1220 in the second pixel unit 120b, and so on.

[0106] In this way, the number of data lines 160 can be reduced, the driving cost can be lowered, and the production cost can be reduced.

[0107] Example 2

[0108] The difference between the second embodiment of the present application and the first embodiment is that the first pixel electrode 1213 further includes a first electrode strip 12133 , and the second pixel electrode 1223 further includes a second electrode strip 12233 .

[0109] Figure 6 A schematic structural diagram is shown in which a first pixel electrode provided in an embodiment of the present application is provided with a first electrode strip and a second pixel electrode provided with a second electrode strip. Figure 7 A schematic structural diagram of a second pixel electrode provided in an embodiment of the present application is shown.

[0110] In some embodiments of this application, see Figure 6 and Figure 7 As shown, the length of the first electrode extension portion 12132 in the column direction Y is smaller than the length of the second electrode extension portion 12232 in the column direction Y.

[0111] See also Figure 6 and Figure 7 As shown, the first electrode strip 12133 is arranged on a side of the first electrode main body 12131 away from the first electrode extension portion 12132, and is extended in the direction from the second scanning line 130b to the first scanning line 130a, that is, the first electrode strip 12133 is extended upward, and the first electrode strip 12133 and the first electrode extension portion 12132 are located on the same column.

[0112] Accordingly, see Figure 6 and Figure 7 As shown, the second electrode strip 12233 is arranged on a side of the second electrode main body 12231 away from the second electrode extension portion 12232, and is extended in the direction from the second scanning line 130b to the first scanning line 130a, that is, the second electrode strip 12233 is extended upward, and the second electrode strip 12233 and the second electrode extension portion 12232 are located on the same column.

[0113] Among them, see Figure 6 and Figure 7 As shown, the length of the first electrode strip 12133 is greater than the length of the second electrode strip 12233, and the sum of the lengths of the first electrode strip 12133 and the first electrode extension 12132 in the column direction Y is equal to the sum of the lengths of the second electrode strip 12233 and the second electrode extension 12232 in the column direction Y.

[0114] It is worth mentioning that the first electrode strip 12133 , the first electrode extension portion 12132 , the second electrode strip 12233 , and the second electrode extension portion 12232 have the same width.

[0115] By ensuring that the sum of the lengths of the first electrode strips 12133 and the first electrode extensions 12132 in the column direction Y is equal to the sum of the lengths of the second electrode strips 12233 and the second electrode extensions 12232 in the column direction Y, each data line 160 is equally affected by the parasitic capacitance generated by adjacent pixel electrodes, thereby improving vertical stripes and crosstalk in the panel and enhancing the quality of the display panel 100.

[0116] Example 3

[0117] See also Figure 1 As shown, the fourth embodiment of the present application provides a display device 10, which includes a flexible circuit board 200, a chip-on-film 300 and the display panel 100 provided in the first or second embodiment. The display panel 100 can be electrically connected to the flexible circuit board 200 through the chip-on-film 300.

[0118] According to the embodiments of the present application, the specific type of the display device 10 is not particularly limited, and any type of display device 10 commonly used in the field can be used, such as liquid crystal displays, mobile phones, laptop computers and other mobile devices, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.

[0119] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0120] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A display panel comprising a base substrate and pixel units formed on the base substrate, wherein a plurality of the pixel units are arranged in an array in row and column directions, each of the pixel units comprises a plurality of sub-pixels arranged in an array, each of the sub-pixels comprises a transistor, the transistor comprising a gate, a semiconductor layer, and a source and a drain disposed at opposite ends of the semiconductor layer, the orthographic projection of the semiconductor layer on the base substrate being located within the orthographic projection of the gate on the base substrate; characterized in that: The display panel further includes: a scan line extending in the row direction, wherein the scan line is provided with a plurality of openings closed in the thickness direction thereof, and the openings correspond one-to-one to the sub-pixels; A pixel electrode comprising an electrode body portion, an electrode extension portion, and an electrode connection portion, wherein the electrode connection portion is connected to the electrode body portion via the electrode extension portion, and the electrode connection portion is connected to the source electrode via a through hole; The orthographic projection of the electrode connecting portion on the base substrate is located within the orthographic projection of the opening on the base substrate, and a gap is left between the orthographic projection of the electrode connecting portion on the base substrate and the inner edge of the orthographic projection of the opening on the base substrate; The display panel includes a first scan line and a second scan line arranged between two adjacent rows of pixel units, and the first scan line and the second scan line are arranged to be spaced apart from each other; The display panel includes a first pixel unit and a second pixel unit arranged at intervals in the row direction, the first pixel unit including a plurality of first sub-pixels sequentially arranged at intervals in the row direction, each of the first sub-pixels including a first transistor, the gate of the first transistor being connected to the first scan line; the second pixel unit including a plurality of second sub-pixels sequentially arranged at intervals in the row direction, each of the second sub-pixels including a second transistor, the gate of the second transistor being connected to the second scan line; The direction from the source electrode to the drain electrode in the first transistor is the same as the direction from the source electrode to the drain electrode in the second transistor.

2. The display panel according to claim 1, wherein: The orthographic projection of the electrode connecting portion on the base substrate is located at a center position of the orthographic projection of the opening on the base substrate.

3. The display panel according to claim 2, wherein: The scanning line includes a plurality of scanning units connected in sequence, each corresponding to each sub-pixel. The scanning unit includes a main portion, a first extension portion, a second extension portion, and a third extension portion. The first extension portion and the second extension portion are arranged parallel to each other. The main portion connects one end of the first extension portion and the second extension portion. The opposite ends of the third extension portion are respectively connected to the other ends of the first extension portion and the second extension portion. The main portion, the first extension portion, the second extension portion, and the third extension portion are arranged to enclose the opening. The main portion of a scanning unit is connected to the first extension portion of its adjacent scanning unit. Part of the main portion serves as the gate of the transistor. The display panel further includes a data line extending in the column direction, wherein the data line is connected to the drain electrode; The orthographic projection of the third extension portion on the base substrate is located between the orthographic projection of the electrode connection portion on the base substrate and the orthographic projection of the data line on the base substrate.

4. The display panel according to claim 1, wherein: The scanning direction is from the first scanning line to the second scanning line.

5. The display panel according to claim 1, wherein: The display panel further includes: a first pixel electrode comprising a first electrode body, a first electrode connecting portion, and a first electrode extension for connecting the first electrode body and the first electrode connecting portion, the first electrode connecting portion being connected to the source of the first transistor via a first through-hole, the first electrode body comprising a first column trunk extending in the column direction and a first row trunk extending in the row direction, the first column trunk and the first row trunk intersecting and dividing the first electrode body into four first slit electrode portions, the first slit electrode portion having a plurality of electrode branches spaced apart, with a slit formed between two adjacent electrode branches in the first slit electrode portion; The second pixel electrode includes a second electrode body portion, a second electrode connecting portion, and a second electrode extension portion for connecting the second electrode body portion and the second electrode connecting portion, the second electrode connecting portion is connected to the source of the second transistor through a second through hole, the second electrode body portion includes a second column trunk extending in the column direction and a second row trunk extending in the row direction, the second column trunk and the second row trunk intersect and divide the second electrode body portion into four second slit electrode portions, the second slit electrode portion has a plurality of electrode branches arranged at intervals, and the slit is formed between two adjacent electrode branches in the second slit electrode portion.

6. The display panel according to claim 5, wherein: The length of the second electrode extension portion in the column direction is greater than the length of the first electrode extension portion in the column direction; The first pixel electrode further includes a first electrode strip, the first electrode strip being disposed on a side of the first electrode body away from the first electrode extension portion and extending in a direction away from the first electrode body portion, and the first electrode strip and the first electrode extension portion being located in the same column; The second pixel electrode further includes a second electrode strip, the second electrode strip being provided on a side of the second electrode body away from the second electrode extension portion and extending in a direction away from the second electrode body portion, and the second electrode strip and the second electrode extension portion being located in the same column; The sum of the lengths of the first electrode strips and the first electrode extensions in the column direction is equal to the sum of the lengths of the second electrode strips and the second electrode extensions in the column direction.

7. The display panel according to claim 5, wherein: The display panel also includes data lines, which include a data main line, a first data branch line and a second data branch line. The first data branch line and the second data branch line are both connected to the data main line. The first data branch line is used to connect to the drain of the Nth (N≥1) first sub-pixel in the first pixel unit, and the second data branch line is used to connect to the drain of the Nth (N≥1) second sub-pixel in the second pixel unit.

8. The display panel according to claim 6, wherein: The colors of the first sub-pixels in the same column are the same; the colors of the second sub-pixels in the same column are the same.

9. A display device, characterized in that: include: Flexible circuit boards; A chip-on-film connected to the flexible circuit board; as well as The display panel according to any one of claims 1 to 8, wherein the display panel is electrically connected to the flexible circuit board via a chip-on-film.

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