Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes an n-th level gate driving circuit comprising a (2n-1)-th signal output terminal and a 2n-th signal output terminal. The (2n-1)-th signal output terminal is electrically connected to the (2n-1)-th scan line, and the 2n-th signal output terminal is electrically connected to the 2n-th scan line. A first pull-up module is electrically connected between the (2n-1)-th clock signal line and the (2n-1)-th signal output terminal, and a second pull-up module is electrically connected between the 2n-th clock signal line and the 2n-th signal output terminal. This allows the first-level gate driving circuit to output scan signals to two scan lines, enabling the original two-level gate driving circuit to share at least some transistors in the pull-up module, pull-down sustain module, and pull-down module, thereby reducing the space occupied by the gate driving circuit and thus reducing the bezel of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] GOA (Gate On Array) technology refers to a method of driving the gate row by row by fabricating the gate row scanning drive signal on the array substrate. Because GOA technology eliminates the need for a gate driver chip and circuit board, saving space and enabling narrow bezels, it is widely used in display panels. The gate driver circuit, in order to raise and lower the potential of the signal output terminal and internal nodes, includes pull-up control units, pull-up units, pull-down units, and pull-down sustaining units. Each unit has at least one transistor, and the units need to be connected by traces, resulting in a large space occupied by the gate driver circuit and a large bezel on the display panel.

[0003] Therefore, existing display panels have the technical problem of large space occupation by the gate driving circuit. Summary of the Invention

[0004] This application provides a display panel and a display device to solve the technical problem that existing display panels have a large space occupied by the gate driving circuit.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel including a plurality of cascaded gate driving circuits and a plurality of scan lines, each of the gate driving circuits including:

[0006] The pull-up control module is electrically connected to the internal nodes;

[0007] A pull-up module is electrically connected to the internal node, and the pull-up module includes a first pull-up module and a second pull-up module;

[0008] The gate drive circuit of the nth stage includes a (2n-1)th signal output terminal and a 2nth signal output terminal. The (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, and the 2nth signal output terminal is electrically connected to the 2nth scan line. The first pull-up module is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module is electrically connected between the 2nth clock signal line and the 2nth signal output terminal. n is greater than or equal to 1, and n is a positive integer.

[0009] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.

[0010] This application provides a display panel and a display device. The display panel includes multiple cascaded gate drive circuits and multiple scan lines. Each gate drive circuit includes a first pull-up module and a second pull-up module. The nth-stage gate drive circuit includes a (2n-1)th signal output terminal and a 2nth signal output terminal. The (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, and the 2nth signal output terminal is electrically connected to the 2nth scan line. The first pull-up module is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module is electrically connected between the 2nth clock signal line and the 2nth signal output terminal. This allows a single-stage gate drive circuit to output scan signals to two scan lines, enabling the original two-stage gate drive circuits to share at least some transistors in the pull-up module, pull-down sustain module, and pull-down module, thereby reducing the space occupied by the gate drive circuit and thus reducing the bezel of the display panel.

[0011] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0014] Figure 1 This is a plan view of the display panel provided in an embodiment of this application.

[0015] Figure 2 This is a schematic diagram showing the connection between the gate driving circuits at each stage and the scan lines in the display panel provided in the embodiments of this application.

[0016] Figure 3 This is a schematic diagram showing the connection of each module of the gate drive circuit provided in the embodiments of this application.

[0017] Figure 4 This is a first circuit diagram of a gate drive circuit provided in an embodiment of this application.

[0018] Figure 5 This is a second circuit diagram of the gate drive circuit provided in an embodiment of this application.

[0019] Figure 6Timing diagram of each signal line of the display panel provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "electrical connection" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] To illustrate the principle behind the technical problem of this application, the embodiments of this application illustrate the design of a contrast display device. It should be understood that the contrast display device cannot be considered prior art in the embodiments of this application. To reduce the bezel, contrast display devices use gate driving circuits instead of gate driving chips. Specifically, multiple levels of gate driving circuits are set up, connecting each level of gate driving circuit to each scan line. Each level of gate driving circuit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, and a bootstrap capacitor. Each unit contains at least one transistor, requiring each level of gate driving circuit to occupy a significant amount of space. The use of multiple levels of gate driving circuits results in a large space occupied by the gate driving circuits, leading to a large bezel in the contrast display device. Therefore, existing display panels suffer from the technical problem of large space occupied by the gate driving circuits.

[0023] This application provides a display panel and a display device to address the aforementioned technical problems.

[0024] Figure 1 This is a plan view of the display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram showing the connection between the gate driving circuits at each stage and the scan lines in the display panel provided in the embodiments of this application. Figure 3 This is a schematic diagram showing the connection of each module of the gate drive circuit provided in the embodiments of this application. Figure 4 This is a first circuit diagram of a gate drive circuit provided in an embodiment of this application. Figure 5This is a second circuit diagram of the gate drive circuit provided in an embodiment of this application. Figure 6 Timing diagram of each signal line of the display panel provided in the embodiments of this application.

[0025] like Figures 1 to 6 As shown in the figure, this application embodiment provides a display panel 1, which includes multiple cascaded gate driving circuits 21 and multiple scan lines 11. Each gate driving circuit 21 includes a pull-up control module 211 and a pull-up module 212. The pull-up control module 211 is electrically connected to an internal node Q. The pull-up module 212 is electrically connected to the internal node Q, and the pull-up module 212 includes a first pull-up module 212a and a second pull-up module 212b.

[0026] The gate drive circuit 21 of the nth stage includes a (2n-1)th signal output terminal G(2n-1) and a 2nth signal output terminal G(2n). The (2n-1)th signal output terminal G(2n-1) is electrically connected to the (2n-1)th scan line, and the 2nth signal output terminal is electrically connected to the 2nth scan line. The first pull-up module 212a is electrically connected between the (2n-1)th clock signal line CK(2n-1) and the (2n-1)th signal output terminal G(2n-1), and the second pull-up module 212b is electrically connected between the 2nth clock signal line CK(2n) and the 2nth signal output terminal G(2n). n is greater than or equal to 1, and n is a positive integer.

[0027] This application provides a display panel in which each gate driving circuit 21 includes a first pull-up module 212a and a second pull-up module 212b. The nth-level gate driving circuit includes a (2n-1)th signal output terminal and a 2nth signal output terminal. The (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, and the 2nth signal output terminal is electrically connected to the 2nth scan line. The first pull-up module 212a is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module 212b is electrically connected between the 2nth clock signal line and the 2nth signal output terminal. This allows the first-level gate driving circuit to output scanning signals to two scan lines, enabling the original two-level gate driving circuits to share at least some transistors in the pull-up module, pull-down sustain module, and pull-down module, thereby reducing the space occupied by the gate driving circuit and thus reducing the bezel of the display panel.

[0028] Specifically, such as Figure 1As shown, the display panel 1 includes a display area 101 and a non-display area 102. The non-display area 102 may surround the display area 101, but this embodiment is not limited to this. The non-display area 102 may be disposed on one side, two sides, or three sides of the display area 101, and the non-display area 102 may be bent to the back of the display area 101. The scan line 11 is disposed within the display area 101. The non-display area 102 may include a gate driving circuit setting area 102a. The gate driving circuit 21 may be disposed in the gate driving circuit setting area 102a. The gate driving circuit setting area 102a may be disposed on one side or both sides of the display area 101. Correspondingly, the gate driving circuit 21 may be disposed on one side or both sides of the display area 101.

[0029] Specifically, the non-display area 102 may also include a binding area (not shown).

[0030] Specifically, compared to current display devices where a single-stage gate drive circuit has one signal output terminal, allowing each stage of the gate drive circuit to output a scan signal to one scan line, this embodiment of the application provides a single-stage gate drive circuit with two signal output terminals. This allows the single-stage gate drive circuit to output scan signals to two scan lines. Furthermore, in this embodiment, the two signal output terminals of the single-stage gate drive circuit can share modules such as the pull-up control module, and can also share some transistors in the pull-down module and pull-down sustain module. As a result, the space occupied by the single-stage gate drive circuit in this embodiment is smaller than the space occupied by the two-stage gate drive circuits in current display devices, thereby reducing the bezel size.

[0031] Specifically, when setting two signal output terminals in a first-stage gate drive circuit, to facilitate the connection between the gate drive circuit and the scan lines, reduce the number of cross-line crossings, and shorten the trace length, the current stage gate drive circuit can be connected to the two nearest scan lines. For example, taking a display panel with 1000 scan lines as an example, only 500 stages of gate drive circuits are needed (when the gate drive circuits are set on both sides of the display area, 500 stages of gate drive circuits can be set on one side of the display area, and 500 stages of gate drive circuits can also be set on the other side of the display area, with each scan line connected to the same stage of gate drive circuits on both sides). The circuits are arranged from top to bottom. The first-stage gate driving circuit is located at the top of the display panel, and the 500th-stage gate driving circuit is located at the bottom of the display panel. At the same time, the scan lines are also arranged from top to bottom. The first scan line is located at the top of the display panel, and the 1000th scan line is located at the bottom of the display panel. This allows the first-stage gate driving circuit to connect to the first and second scan lines, the second-stage gate driving circuit to connect to the third and fourth scan lines, and so on. The 500th-stage gate driving circuit connects to the 999th and 1000th scan lines, reducing the number of lines and the length of the traces.

[0032] Specifically, such as Figure 2 As shown, taking a maximum value of n as N, k greater than 2 and less than N, and k being a positive integer as an example, the first-stage gate driving circuit 21a is connected to the first scan line Scan1 and the second scan line Scan2; the second-stage gate driving circuit 21b is connected to the third scan line Scan3 and the fourth scan line Scan4, ..., the k-th stage gate driving circuit 21c is connected to the (2k-1)-th scan line Scan(2k-1) and the 2k-th scan line Scan2k, ..., the N-th stage gate driving circuit 21c is connected to the (2N-1)-th scan line Scan(2N-1) and the 2N-th scan line Scan2N. It can be seen that by connecting each stage of the gate driving circuit to each scan line sequentially, crossing lines between traces is avoided, and excessive trace length is avoided, thus reducing impedance.

[0033] Specifically, when setting up clock signal lines, multiple gate drive circuits reuse clock signal lines. For example, a display panel might have four clock signal lines. The first-stage gate drive circuit connects the first and second clock signal lines; the second-stage gate drive circuit connects the third and fourth clock signal lines; the third-stage gate drive circuit connects the first and second clock signal lines; and the fourth-stage gate drive circuit connects the third and fourth clock signal lines. Similarly, the connection relationships between other gate drive circuits and clock signal lines can be determined. Based on the four clock signal lines, it can be determined that the (2n-1)th clock signal line is either the first or third clock signal line, and the (2n)th clock signal line is either the second or fourth clock signal line. The specific clock signal lines corresponding to the (2n-1)th and (2n)th clock signal lines are determined according to the number of stages of the gate drive circuit.

[0034] Specifically, the above embodiment is illustrated by taking a display panel with 4 clock signal lines as an example, but the embodiments of this application are not limited to this, and the display panel may include 8 clock signal lines or other numbers of clock signal lines.

[0035] In some embodiments, such as Figures 3 to 5As shown, the first pull-up module 212a includes a first pull-up transistor T21a, the first electrode of which is electrically connected to the (2n-1)th clock signal line CK(2n-1), and the second electrode of which is electrically connected to the (2n-1)th signal output terminal G(2n-1); the second pull-up module 212b includes a second pull-up transistor T21b, the first electrode of which is electrically connected to the 2nth clock signal line CK(2n), and the second electrode of which is electrically connected to the 2nth signal output terminal G(2n). By electrically connecting the first electrode of the first pull-up transistor to the (2n-1)th clock signal line CK(2n-1), the second electrode of the first pull-up transistor T21a to the (2n-1)th signal output terminal G(2n-1), the first electrode of the second pull-up transistor T21b to the 2nth clock signal line CK(2n), and the second electrode of the second pull-up transistor T21b to the 2nth signal output terminal G(2n), the first and second pull-up transistors can control the (2n-1)th clock signal line CK(2n-1) and the 2nth clock signal line CK(2n) to output signals to the (2n-1)th signal output terminal G(2n-1) and the 2nth signal output terminal G(2n), respectively, thereby turning on each scan line sequentially and driving the pixels.

[0036] In some embodiments, such as Figure 4 As shown, the gate of the first pull-up transistor T21a is electrically connected to the internal node Q, and the gate of the second pull-up transistor T21b is electrically connected to the internal node Q. By electrically connecting the gate of the first pull-up transistor T21a to the internal node Q and the gate of the second pull-up transistor T21b to the internal node Q, the first and second pull-up transistors are controlled by the potential of the internal node, thereby connecting the clock signal line and the signal output terminal when the internal node Q outputs an effective potential.

[0037] In some embodiments, such as Figure 5 As shown, at least one of the first pull-up transistor T21a and the second pull-up transistor T21b has a first gate and a second gate. The display panel 1 also includes a gate control module 216, which is configured to turn off the first pull-up transistor T21a according to the signal of the 2n signal output terminal G(2n), and / or turn off the second pull-up transistor T21b according to the signal of the (2n+1) signal output terminal G(2n+1).

[0038] In this configuration, the first gate of at least one of the first pull-up transistor T21a and the second pull-up transistor T21b is electrically connected to the internal node Q, and the second gate of at least one of the first pull-up transistor T21a and the second pull-up transistor T21b is electrically connected to the gate control module 216. By including a first gate and a second gate in at least one of the first and second pull-up transistors, and by further including the gate control module in the display panel, the first gate of at least one of the first and second pull-up transistors is electrically connected to the internal node, and the second gate of at least one of the first and second pull-up transistors is electrically connected to the gate control module. This allows the previous signal output terminal to stop inputting signals when the next signal output terminal outputs a signal, thereby avoiding display abnormalities such as panel flickering.

[0039] Specifically, the first pull-up transistor may include a first gate and a second gate, the first gate of the first pull-up transistor being electrically connected to an internal node, the second gate of the first pull-up transistor being connected to a gate control module, and the gate of the second pull-up transistor being electrically connected to an internal node; or the gate of the first pull-up transistor may be electrically connected to an internal node, the second pull-up transistor may include a first gate and a second gate, the first gate of the second pull-up transistor being electrically connected to an internal node, and the second gate of the second pull-up transistor being connected to a gate control module.

[0040] Specifically, compared to a gate drive circuit without a gate control module, because the internal node simultaneously controls the first pull-up transistor T21a and the second pull-up transistor T21 to turn on or off, after the signal output is completed at the (2n-1)th signal output terminal, the internal node Q still needs to maintain a high potential to enable the 2nth signal output terminal to output a signal. This results in the first pull-up transistor T21a remaining on, affecting the display effect. This embodiment of the application, by setting a gate control module, allows the first pull-up transistor T21a to be turned off after the signal output is completed at the (2n-1)th signal output terminal, thus avoiding display abnormalities.

[0041] In some embodiments, such as Figure 5 As shown, the gates of the first pull-up transistor T21a and the second pull-up transistor T21b both include a first gate and a second gate, and the gate control module 216 includes a first gate control module 216a and a second gate control module 216b.

[0042] In this configuration, the first gate of the first pull-up transistor T21a is electrically connected to the internal node Q, and the second gate of the first pull-up transistor T21a is electrically connected to the first gate control module 216a. Similarly, the first gate of the second pull-up transistor T21b is electrically connected to the internal node Q, and the second gate of the second pull-up transistor T21b is electrically connected to the second gate control module 216b. By including both a first gate and a second gate in both the first and second pull-up transistors, and by including both a first gate control module and a second gate control module, the pull-up transistor connected to the signal output terminal of the previous scan line can be turned off when a signal is output from the signal output terminal of the next scan line, thus avoiding display interference.

[0043] Specifically, the first gate and the second gate can be regarded as the top gate and the bottom gate of the pull-up transistor, respectively. It can be understood that the first gate and the second gate can also be regarded as the bottom gate and the top gate of the pull-up transistor, respectively.

[0044] In some embodiments, such as Figure 5 As shown, the first gate control module 216a includes a first gate control transistor T211a. The gate of the first gate control transistor T211a is electrically connected to the 2n signal output terminal. The first electrode of the first gate control transistor T211a is electrically connected to the low-potential power supply terminal VSS. The second electrode of the first gate control transistor T211a is electrically connected to the second gate of the first pull-up transistor T21a. By configuring the first gate control transistor T211a such that its gate is electrically connected to the 2n signal output terminal, its first electrode is electrically connected to the low-potential power supply terminal VSS, and its second electrode is electrically connected to the second gate of the first pull-up transistor T21a, when a signal is output at the 2n signal output terminal, the first gate control transistor can be turned on, causing the low-potential power supply terminal VSS to output a low-potential signal to the second gate of the first pull-up transistor T21a, thus turning off the first pull-up transistor.

[0045] In some embodiments, such as Figure 5As shown, the second gate control module 216b includes a second gate control transistor T211b. The gate of the second gate control transistor T211b is electrically connected to the (2n+1)th signal output terminal G(2n+1). The first electrode of the second gate control transistor T211b is electrically connected to the low-potential power supply terminal VSS. The second electrode of the second gate control transistor T211b is electrically connected to the second gate of the second pull-up transistor T21b. By configuring the second gate control transistor T211b, with its gate electrically connected to the (2n+1)th signal output terminal, its first electrode electrically connected to the low-potential power supply terminal VSS, and its second electrode electrically connected to the second gate of the second pull-up transistor T21b, when a signal is output at the (2n+1)th signal output terminal, the second gate control transistor can be turned on, causing the low-potential power supply terminal VSS to output a low-potential signal to the second gate of the second pull-up transistor T21b, thus turning off the second pull-up transistor.

[0046] In some embodiments, such as Figure 5 As shown, the gate drive circuit 21 further includes a storage module 215 and an anti-coupling transistor Tq. The storage module 215 is connected to the internal node Q. The gate and first electrode of the anti-coupling transistor Tq are electrically connected to the storage module 215. The second electrode of the anti-coupling transistor Tq is electrically connected to the gate of the first pull-up transistor T21a, and the second electrode of the anti-coupling transistor Tq is electrically connected to the gate of the second pull-up transistor T21b. By setting the anti-coupling transistor, when the first and second pull-up transistors are turned off, the discharge of the storage module to the gates of the first and second pull-up transistors can be prevented, thus better turning off the first and second pull-up transistors.

[0047] Specifically, since the storage module is connected to the internal node, when the internal node outputs a low potential, the storage module may output a potential to the gate of the first pull-up transistor and the gate of the second pull-up transistor, causing the first pull-up transistor and the second pull-up transistor to fail to turn off completely. In this embodiment, by setting an anti-coupling transistor, the anti-coupling transistor can block the potential when the storage capacitor outputs a potential to the gate of the first pull-up transistor and the gate of the second pull-up transistor, thus preventing the first pull-up transistor and the second pull-up transistor from turning on and making the first pull-up transistor and the second pull-up transistor turn off better.

[0048] In some embodiments, such as Figure 3As shown, the gate drive circuit 21 further includes a pull-down module 213, a pull-down sustaining module 214, and a storage module 215. The pull-down module 213 is electrically connected to the internal node Q, the (2n-1)th signal output terminal G(2n-1), and the 2nth signal output terminal G(2n). The pull-down sustaining module is electrically connected to the internal node Q, the (2n-1)th signal output terminal G(2n-1), and the 2nth signal output terminal G(2n).

[0049] In some embodiments, such as Figure 4 , Figure 5 As shown, the pull-up control module 211 includes a pull-up control transistor T11. The gate and the first electrode of the pull-up control transistor T11 are configured to receive a pull-up control signal, and the second electrode of the pull-up control transistor T11 is electrically connected to the internal node Q.

[0050] Specifically, such as Figure 4 , Figure 5 As shown, the gate of the pull-up control transistor T11 is connected to the start signal line STV or the (2n-5)th signal output terminal G(2n-5).

[0051] In some embodiments, such as Figure 4 , Figure 5 As shown, the pull-down module 213 includes a first pull-down transistor T31a, a second pull-down transistor T31b, and a third pull-down transistor T41. The gate of the first pull-down transistor T31a is configured to receive a first pull-down control signal. The first electrode of the first pull-down transistor T31a is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the first pull-down transistor T31a is electrically connected to the (2n-1)th signal output terminal G(2n-1). The gate of the second pull-down transistor T31b is configured to receive a second pull-down control signal. The first electrode of the second pull-down transistor T31b is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second pull-down transistor T31b is electrically connected to the 2nth signal output terminal G(2n). The gate of the third pull-down transistor T41 is configured to receive a third pull-down control signal. The first electrode of the third pull-down transistor T41 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the third pull-down transistor T41 is electrically connected to the internal node Q. By electrically connecting the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor to the (2n-1)th signal output terminal G(2n-1), the 2nth signal output terminal G(2n), and the internal node Q, respectively, a single pull-down module can perform the functions of two pull-down modules in the two-stage gate drive circuit of the current display device, thereby reducing the space occupied by the gate drive circuit.

[0052] Specifically, such as Figure 4 , Figure 5 As shown, the gate of the first pull-down transistor T31a is connected to the (2n+3)th signal output terminal G(2n+3), the gate of the second pull-down transistor T31b is connected to the (2n+4)th signal output terminal G(2n+4), and the gate of the third pull-down transistor T41 is connected to the (2n+5)th signal output terminal G(2n+5).

[0053] In some embodiments, such as Figure 4 , Figure 5As shown, the pull-down sustaining module 214 includes a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53, a first pull-down sustaining transistor T32a, a second pull-down sustaining transistor T32b, and a third pull-down sustaining transistor T42. The gate of the first inverting transistor T51 is electrically connected to the high-potential power supply terminal VGH, and the first electrode of the first inverting transistor T51 is electrically connected to the high-potential power supply terminal VGH. The gate of the second inverting transistor T52 is electrically connected to the internal node Q. The first electrode is electrically connected to the low-potential power supply terminal VSS; the second electrode of the second inverting transistor T52 is electrically connected to the second electrode of the first inverting transistor T51; the gate of the third inverting transistor T53 is electrically connected to the second electrode of the first inverting transistor T51; the first electrode of the third inverting transistor T53 is electrically connected to the high-potential power supply terminal VGH; the second electrode of the third inverting transistor T53 is connected to the gate of the first pull-down sustaining transistor T32a; the gate of the fourth inverting transistor T54 is electrically connected to the internal node Q. The first electrode of the fourth inverting transistor T54 is electrically connected to the low-potential power supply terminal VSS; the gate of the first pull-down sustaining transistor T32a is electrically connected to the second electrode of the fourth inverting transistor T54; the first electrode of the first pull-down sustaining transistor T32a is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the first pull-down sustaining transistor T32a is electrically connected to the (2n-1)th signal output terminal G(2n-1); the gate of the second pull-down sustaining transistor T32b is electrically connected to the (2n-1)th signal output terminal G(2n-1). The second electrode is electrically connected; the first electrode of the second pull-down sustaining transistor T32b is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the second pull-down sustaining transistor T32b is electrically connected to the 2n-th signal output terminal G(2n); the gate of the third pull-down sustaining transistor T42 is electrically connected to the second electrode of the fourth inverting transistor T54; the first electrode of the third pull-down sustaining transistor T42 is electrically connected to the low-potential power supply terminal VSS, and the second electrode of the third pull-down sustaining transistor T42 is electrically connected to the internal node Q. By electrically connecting the first pull-down sustaining transistor, the second pull-down sustaining transistor, and the third pull-down sustaining transistor to the (2n-1)-th signal output terminal G(2n-1), the 2n-th signal output terminal G(2n), and the internal node Q respectively, a single pull-down sustaining module can achieve the function of two pull-down sustaining modules in the two-stage gate drive circuit of the current display device, reducing the space occupied by the gate drive circuit.

[0054] In some embodiments, such as Figure 4 , Figure 5As shown, the storage module 215 includes a first storage capacitor Cbt1 and a second storage capacitor Cbt2. One plate of the first storage capacitor Cbt1 is electrically connected to the internal node Q, and the other plate of the first storage capacitor Cbt1 is electrically connected to the (2n-1)th signal output terminal G(2n-1). One plate of the second storage capacitor Cbt2 is electrically connected to the internal node Q, and the other plate of the second storage capacitor Cbt2 is electrically connected to the 2nth signal output terminal G(2n). By connecting the first storage capacitor to the internal node and the second storage capacitor to the internal node, the potential of the internal node can be increased, enabling the (2n-1)th signal output terminal G(2n-1) and the 2nth signal output terminal G(2n) to output normally.

[0055] Specifically, the above embodiment uses the electrical connection of the first electrode of the first gate-controlled transistor T211a to the low-potential power supply terminal VSS as an example for illustration. However, the embodiments of this application are not limited to this. The first electrode of the first gate-controlled transistor T211a can be connected to other low-potential signal lines, and the potential of the low-potential signal lines is lower than the potential of the low-potential power supply terminal VSS. It can be understood that since the internal node Q is still at a high potential when the gate drive circuit needs to turn off the first pull-up transistor T21a and keep the second pull-up transistor T21b in the open state, in order to turn off the first pull-up transistor T21a, the potential of the second gate of the first pull-up transistor T21a needs to be lower, so that the potential of the low-potential signal line connected to the first electrode of the first gate-controlled transistor T211a is lower than the potential of the low-potential power supply terminal VSS.

[0056] Specifically, the potential of the trace connected to the first electrode of the first gate transistor T211a can be lower than the potential of the trace connected to the first electrode of the second gate transistor T211b.

[0057] Specifically, the response speed of the first gate transistor T211a can be made faster than that of the second gate transistor T211b, so that when the first pull-up transistor needs to be turned off, the speed of turning off the first pull-up transistor can be accelerated. Specifically, the width-to-length ratio of the channel of the first gate transistor T211a can be greater than that of the channel of the second gate transistor T211b.

[0058] At the same time, such as Figure 6As shown, taking a display panel with eight clock signal lines as an example, a timing sequence for each signal line of a display panel is provided. The display panel includes a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, a fourth clock signal line CK4, a fifth clock signal line CK5, a sixth clock signal line CK6, a seventh clock signal line CK7, and an eighth clock signal line CK8. The connection relationship between each clock signal line and the gate drive circuit can be found in the description of the above embodiment. Figure 6 As shown, the first clock signal line CK1 to the eighth clock signal line CK8 sequentially output high-level signals, the low-level power supply line VSS continuously outputs low-level signals, and the high-level power supply line VGH outputs high-level signals. This causes each signal output terminal to output signals to the scan lines in sequence, so that each scan line scans each row of pixel units in sequence, enabling the display panel to work normally.

[0059] Specifically, the above embodiments use the effective level of each clock signal line ( Figure 6 The example given is a high level for the effective level of the clock signal line, but the embodiments of this application are not limited to this. The effective level can be a low level. The example given is an overlapping area. For example, the time when the first clock signal line CK1 outputs an effective level overlaps with the time when the second clock signal line CK2 outputs an effective level. However, the embodiments of this application are not limited to this. The time when each clock signal line outputs an effective level may not overlap.

[0060] Specifically, this application embodiment uses an N-type transistor in the gate drive circuit as an example for illustration. Accordingly, each transistor is turned on when the gate is at a high input potential. However, this application embodiment is not limited to this. Each transistor can be a P-type transistor, or some transistors can be N-type transistors and some transistors can be P-type transistors.

[0061] Specifically, the transistor in the gate drive circuit can be an oxide semiconductor transistor or a silicon semiconductor transistor, specifically a low-temperature polycrystalline silicon thin-film transistor or a metal oxide thin-film transistor.

[0062] Specifically, when a transistor has only one gate, the gate of the transistor refers to its unique gate; when a transistor has two gates, unless otherwise specified, the gate of the transistor refers to its first gate.

[0063] Specifically, the above embodiments have provided a detailed description of the display panel from aspects such as circuitry, timing, and transistor design. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, at least one of the first pull-up transistor and the second pull-up transistor includes a first gate and a second gate. The display panel also includes a gate control module, which is configured to turn off the first pull-up transistor according to the signal at the 2n-th signal output terminal, and / or turn off the second pull-up transistor according to the signal at the (2n+1)-th signal output terminal. The first gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the internal node, and the second gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the gate control module. The gate driving circuit also includes a storage module and an anti-coupling transistor. The storage module is connected to the internal node, the gate of the anti-coupling transistor and the first electrode of the anti-coupling transistor are electrically connected to the storage module, the second electrode of the anti-coupling transistor is electrically connected to the gate of the first pull-up transistor, and the second electrode of the anti-coupling transistor is electrically connected to the gate of the second pull-up transistor.

[0064] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0065] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0066] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0067] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0068] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized by, It includes multiple cascaded gate drive circuits and multiple scan lines, each of the gate drive circuits comprising: The pull-up control module is electrically connected to the internal nodes; A pull-up module is electrically connected to the internal node, and the pull-up module includes a first pull-up module and a second pull-up module; The gate drive circuit of the nth stage includes a (2n-1)th signal output terminal and a 2nth signal output terminal. The (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, and the 2nth signal output terminal is electrically connected to the 2nth scan line. The first pull-up module is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module is electrically connected between the 2nth clock signal line and the 2nth signal output terminal. n is greater than or equal to 1, and n is a positive integer. The first pull-up module includes a first pull-up transistor, the second pull-up module includes a second pull-up transistor, and the gates of the first pull-up transistor and the second pull-up transistor both include a first gate and a second gate. The display panel also includes a gate control module, which is configured to turn off the first pull-up transistor according to the signal at the 2nth signal output terminal and turn off the second pull-up transistor according to the signal at the (2n+1)th signal output terminal. The gate control module includes a first gate control module and a second gate control module; wherein, the first gate of the first pull-up transistor is electrically connected to the internal node, and the second gate of the first pull-up transistor is electrically connected to the first gate control module; the first gate of the second pull-up transistor is electrically connected to the internal node, and the second gate of the second pull-up transistor is electrically connected to the second gate control module.

2. The display panel of claim 1, wherein, The first electrode of the first pull-up transistor is electrically connected to the (2n-1)th clock signal line, and the second electrode of the first pull-up transistor is electrically connected to the (2n-1)th signal output terminal; The first electrode of the second pull-up transistor is electrically connected to the 2n clock signal line, and the second electrode of the second pull-up transistor is electrically connected to the 2n signal output terminal.

3. The display panel of claim 1, wherein, The first gate control module includes a first gate control transistor, the gate of the first gate control transistor is electrically connected to the 2n signal output terminal, the first electrode of the first gate control transistor is electrically connected to the low potential power supply terminal, and the second electrode of the first gate control transistor is electrically connected to the second gate of the first pull-up transistor.

4. The display panel of claim 1, wherein, The second gate control module includes a second gate control transistor, the gate of the second gate control transistor is electrically connected to the (2n+1)th signal output terminal, the first electrode of the second gate control transistor is electrically connected to the low potential power supply terminal, and the second electrode of the second gate control transistor is electrically connected to the second gate of the second pull-up transistor.

5. The display panel of any of claims 1 to 4, wherein, The gate drive circuit further includes a memory module and an anti-coupling transistor. The memory module is connected to the internal node. The gate of the anti-coupling transistor and the first electrode of the anti-coupling transistor are electrically connected to the memory module. The second electrode of the anti-coupling transistor is electrically connected to the gate of the first pull-up transistor. The second electrode of the anti-coupling transistor is electrically connected to the gate of the second pull-up transistor.

6. The display panel of any one of claims 1 to 4, wherein, The gate driving circuit further includes: The pull-down module is electrically connected to the internal node, the (2n-1)th signal output terminal, and the 2nth signal output terminal; The pull-down sustaining module is electrically connected to the internal node, the (2n-1)th signal output terminal, and the 2nth signal output terminal; The storage module includes a first storage capacitor and a second storage capacitor. One plate of the first storage capacitor is electrically connected to the internal node, and the other plate of the first storage capacitor is electrically connected to the (2n-1)th signal output terminal. One plate of the second storage capacitor is electrically connected to the internal node, and the other plate of the second storage capacitor is electrically connected to the 2nth signal output terminal.

7. A display device, characterized by comprising: Includes the display panel as described in any one of claims 1 to 6.

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