Data transmission rate conversion method and system based on FPGA

Abstract

The invention relates to an FPGA (Field Programmable Gate Array)-based data transmission rate conversion method, which comprises the following steps of: acquiring original data received by a PHY (Physical Layer) transceiver and a first transmission protocol corresponding to the original data; analyzing the original data according to the first transmission protocol, and determining a second transmission protocol for subsequent transmission according to an analysis result; extracting feature data of the original data according to the second transmission protocol, and performing secondary packaging on the original data according to an identifier corresponding to the feature data to generate a plurality of final data packets; and sending each data packet to a target address from a high-speed serial interface according to the second transmission protocol. By performing feature analysis and secondary packaging on the original data, the data transmission rate can be effectively changed so as to meet the requirements of conversion of different rates.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a data transmission rate conversion method and system based on FPGA. Background Art

[0002] With the rapid growth of Internet traffic, especially the growth of high-definition video streaming, large-scale online games and cloud storage, the demand for high-speed network communication is increasing. Traditional routers and switches have been unable to meet the requirements of high bandwidth and low latency. As a flexible and efficient hardware platform, field programmable gate arrays (FPGAs) have shown significant advantages in high-speed data processing.

[0003] However, when using FPGA for data transmission, the transmission is often performed based on the transmission rate received by the receiver, which cannot meet the requirements of high-speed transmission. Summary of the invention

[0004] The purpose of the present invention is to provide a data transmission rate conversion method based on FPGA to solve the problems in the background technology.

[0005] A first aspect of the present invention provides a data transmission rate conversion method based on FPGA, comprising:

[0006] Acquire original data received by the PHY transceiver and a first transmission protocol corresponding to the original data;

[0007] Parsing the original data according to the first transmission protocol, and determining a second transmission protocol for subsequent transmission according to the parsing result;

[0008] Extracting characteristic data of the original data according to the second transmission protocol, and repackaging the original data according to identifiers corresponding to the characteristic data to generate a plurality of final data packets;

[0009] Each of the data packets is sent from the high-speed serial interface to a target address according to the second transmission protocol.

[0010] In a possible implementation manner, the acquiring original data received by the PHY transceiver and a first transmission protocol corresponding to the original data includes:

[0011] Acquire attribute information of a receiving optical module connected to the PHY transceiver, extract key bytes in the attribute information, and determine the first transmission protocol according to the key bytes.

[0012] In a possible implementation manner, the acquiring original data received by the PHY transceiver and a first transmission protocol corresponding to the original data includes:

[0013] Obtain the receiving time of the original data, classify the original data according to the receiving time to generate several original data packets, count the amount of data contained in each of the original data packets, take the average as the data amount per unit time, and determine the first transmission protocol corresponding to the original data according to the data amount per unit time.

[0014] In a possible implementation manner, before obtaining the original data received by the PHY transceiver, the method further includes:

[0015] The received data is arranged in time sequence using the buffer area of ​​the PHY transceiver to generate a data sequence, where the data sequence is the original data.

[0016] In a possible implementation, parsing the original data according to the first transmission protocol, and determining a second transmission protocol for subsequent transmission according to the parsing result includes:

[0017] Determining whether the original data conforms to the effective load of the target address;

[0018] If yes, determining the second transmission protocol according to the data format of the original data;

[0019] Otherwise, the second transmission protocol is determined according to the maximum value of the effective load.

[0020] In a possible implementation manner, extracting feature data of the original data according to the second transmission protocol includes:

[0021] Obtain a mathematical model formula of the second transmission protocol, determine key parameters of the second transmission protocol according to the mathematical model formula, and determine feature data to be extracted according to the key parameters.

[0022] In a possible implementation, extracting the characteristic data of the original data, and secondary packaging the original data according to the identifier corresponding to the characteristic data to generate multiple final data packets includes:

[0023] According to the time when the characteristic data appears, each characteristic is assigned a time identifier, and data units with the same time identifier are packaged to generate the final data packet.

[0024] A second aspect of the present invention provides a data transmission rate conversion system based on FPGA, comprising:

[0025] PHY transceiver, used for receiving data that needs to be converted in transmission rate;

[0026] A service FPGA, used for parsing the data received by the PHY transceiver and determining a second transmission protocol for transmission;

[0027] MAC controller, used to repack the data and generate the final data packet;

[0028] A high-speed serial interface is used to send the final data packet to a target address.

[0029] In a possible implementation manner, the service FPGA includes:

[0030] A monitoring module, used for error checking and service quality filtering of data received by the PHY transceiver to obtain data to be parsed;

[0031] The processing module is used to determine whether the original data conforms to the effective load of the target address.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. By analyzing the characteristics of the original data and repackaging it, the data transmission rate can be effectively changed to meet the needs of different rate conversions.

[0034] 2. Through the coordinated cooperation of PHY transceiver, business FPGA and MAC controller, the data transmission is stable, without packet loss and low latency during the transmission rate conversion process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a flow chart of the data transmission rate conversion method based on FPGA of the present invention;

[0036] Figure 2 It is a schematic diagram of the architecture of the data transmission rate conversion device based on FPGA of the present invention. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] It should be noted that the serial numbers assigned to the components in the embodiments of the present invention, such as "first" and "second", are only used to distinguish the objects being described and do not have any order or technical meaning.

[0039] Combine the following Figure 1The data transmission rate conversion method based on FPGA of the present invention is described.

[0040] A first aspect of the present invention provides a data transmission rate conversion method based on FPGA, comprising:

[0041] S1. Acquire original data received by a PHY transceiver and a first transmission protocol corresponding to the original data;

[0042] In one embodiment, the first transmission protocol may be obtained by using the following steps, specifically:

[0043] Obtain the receiving time of the original data, classify the original data according to the receiving time to generate several original data packets, count the amount of data contained in each of the original data packets, take the average as the data amount per unit time, and determine the first transmission protocol corresponding to the original data according to the data amount per unit time.

[0044] The original data enters the PHY transceiver in chronological order. In the present invention, the PHY transceiver has a cache function, and the original data can be stored in the aforementioned chronological order to generate an original data sequence. The original data can also be stored in different areas of the buffer of the PHY transceiver according to the different times when they arrive at the PHY transceiver.

[0045] In this embodiment, a fixed time interval can be used as a threshold for generating an original data packet, for example, the original data within 1 second is packaged to form an original data packet. Since there will be a certain error in the amount of data per second during the transmission process, the average is used as a standard for measuring the transmission rate. As for the transmission protocol, different transmission protocols correspond to different transmission rate standards, and each transmission rate corresponds to a transmission protocol, such as IP protocol, UDP protocol, TCP protocol, etc.

[0046] In another embodiment, the first transmission protocol may be obtained by using the following steps, specifically:

[0047] Acquire attribute information of a receiving optical module connected to the PHY transceiver, extract key bytes in the attribute information, and determine the first transmission protocol according to the key bytes.

[0048] Each optical module corresponds to a different transmission rate. For example, if the transmission rate is 100G, the optical modules used are 4 25G SEP28 optical modules. If the transmission rate is 10G, the SFP+ optical module is used. Different optical modules correspond to different transmission rates. SEP28 and SFP are the attribute information of the optical module. As long as these attribute information are extracted, the data transmission rate can be determined, and then the first transmission protocol can be determined according to the transmission rate.

[0049] S2. parsing the original data according to the first transmission protocol, and determining a second transmission protocol for subsequent transmission according to the parsing result;

[0050] Specifically, the second transmission protocol may be determined in the following manner: first, determining whether the original data conforms to the effective load of the target address;

[0051] If yes, determining the second transmission protocol according to the data format of the original data;

[0052] Otherwise, the second transmission protocol is determined according to the maximum value of the effective load.

[0053] The effective load of the target address is limited by its network bandwidth, network congestion, etc. For example, when the target address is in a high-concurrency data processing state, the effective load is small, while when it is low-concurrency, the effective load is relatively large. Therefore, when the original data does not meet the effective load of the target address, the data output rate of the transmission needs to be determined according to the effective load.

[0054] S3. Extracting characteristic data of the original data according to the second transmission protocol, and repackaging the original data according to identifiers corresponding to the characteristic data to generate multiple final data packets;

[0055] When acquiring data features of original data, the following method may be used: acquiring a mathematical model formula of the second transmission protocol, determining key parameters of the second transmission protocol based on the mathematical model formula, and determining feature data to be extracted based on the key parameters.

[0056] Different transmission protocols have different mathematical model formulas, such as:

[0057] The mathematical model formula of the UDP protocol is as follows:

[0058] P=1-e -r*t

[0059] Among them, P represents the probability of successful transmission, r represents the sending rate, and T represents time.

[0060] The mathematical model formula of the IP protocol is as follows:

[0061] T=L / R

[0062] Among them, T represents the transmission time, L represents the packet length, and R represents the transmission rate.

[0063] The mathematical model formula of the Ethernet protocol is as follows:

[0064] C=B / L

[0065] Among them, C represents bandwidth, B represents channel width, and L represents packet length.

[0066] It can be seen that different protocols have different parameters required for transmission. For UDP and IP protocols, the transmission time can be used as the key parameter. For example, if the transmission time is 5S, the original data within the 5S time interval is repackaged to generate the final data packet for transmission. For Ethernet protocol, the length of the data packet is used as the key parameter to determine the characteristic data of the secondary package and generate the final data packet.

[0067] S4. Send each of the data packets from the high-speed serial interface to a target address according to the second transmission protocol.

[0068] High-Speed ​​Serial Interface (HSSI) is a serial interface standard jointly launched by Cisco System and T3plus Networking. It is similar to the RS-232 and V.35 interfaces that commonly connect computers and modems, but with a higher transmission speed.

[0069] In one embodiment, before performing step S1, the following steps may also be included:

[0070] The received data is arranged in time sequence using the buffer area of ​​the PHY transceiver to generate a data sequence, where the data sequence is the original data.

[0071] Prioritizing data processing in the cache area can transform irregular data into data with a certain arrangement order, which can improve processing efficiency when processing the original data.

[0072] In one embodiment, the step S4 comprises:

[0073] According to the time when the characteristic data appears, each characteristic is assigned a time identifier, and data units with the same time identifier are packaged to generate the final data packet.

[0074] The characteristic data is data with a data type in a string of data, such as a numeric type, a time type, or a character string type. In the present invention, numeric data can be used as characteristic data. For example, if the numeric data in a string of data is 123, then the data is characteristic data, and the time when it appears is a time identifier. According to the required data length and other indicators, data units with the same time identifier are packaged to generate the final data packet.

[0075] A second aspect of the present invention provides a data transmission rate conversion system based on FPGA, comprising:

[0076] PHY transceiver, used for receiving data that needs to be converted in transmission rate;

[0077] A service FPGA, used for parsing the data received by the PHY transceiver and determining a second transmission protocol for transmission;

[0078] MAC controller, used to repack the data and generate the final data packet;

[0079] A high-speed serial interface is used to send the final data packet to a target address.

[0080] As a key component of the Ethernet physical layer, the PHY transceiver can connect the digital world such as processors, FPGAs (field programmable gate arrays) and ASICs (application-specific integrated circuits) with the analog world. It is responsible for converting digital signals into analog signals suitable for transmission on physical media (such as optical fibers, copper cables, etc.), and converting received analog signals into digital signals.

[0081] In the present invention, the business FPGA includes:

[0082] A monitoring module, used for error checking and service quality filtering of data received by the PHY transceiver to obtain data to be parsed;

[0083] The processing module is used to determine whether the original data conforms to the effective load of the target address.

[0084] For the present invention, two business FPGAs can also be used as a monitoring module and a processing module respectively. Business FPGA 1 as a monitoring module only needs to perform simple verification on the transmitted data and filter according to preset indicators, which can reduce the load of business FPGA 1. Business FPGA 2 is used to analyze the data volume, data length, etc. of the original data to determine whether it meets the effective load of the target address. Using two business FPGAs can effectively improve the efficiency of data transmission rate conversion. At the same time, if one of the business FPGAs fails, the task performed by the other business FPGA that handles the failure can be enabled to ensure the stability of data transmission.

[0085] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules, sub-modules and units as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data transmission rate conversion method based on FPGA, characterized in that: include: Acquire original data received by the PHY transceiver and a first transmission protocol corresponding to the original data; Parsing the original data according to the first transmission protocol, and determining a second transmission protocol for subsequent transmission according to the parsing result; Extracting characteristic data of the original data according to the second transmission protocol, and repackaging the original data according to identifiers corresponding to the characteristic data to generate a plurality of final data packets; Each of the data packets is sent from the high-speed serial interface to a target address according to the second transmission protocol.

2. The data transmission rate conversion method based on FPGA according to claim 1, characterized in that: The obtaining of original data received by the PHY transceiver and a first transmission protocol corresponding to the original data includes: Acquire attribute information of a receiving optical module connected to the PHY transceiver, extract key bytes in the attribute information, and determine the first transmission protocol according to the key bytes.

3. The data transmission rate conversion method based on FPGA according to claim 1, characterized in that: The obtaining of original data received by the PHY transceiver and a first transmission protocol corresponding to the original data includes: Obtain the receiving time of the original data, classify the original data according to the receiving time to generate several original data packets, count the amount of data contained in each of the original data packets, take the average as the data amount per unit time, and determine the first transmission protocol corresponding to the original data according to the data amount per unit time.

4. The data transmission rate conversion method based on FPGA according to claim 3, characterized in that: Before obtaining the original data received by the PHY transceiver, the method further includes: The received data is arranged in time sequence using the buffer area of ​​the PHY transceiver to generate a data sequence, where the data sequence is the original data.

5. The data transmission rate conversion method based on FPGA according to claim 1, characterized in that: The step of parsing the original data according to the first transmission protocol and determining a second transmission protocol for subsequent transmission according to the parsing result includes: Determining whether the original data conforms to the effective load of the target address; If yes, determining the second transmission protocol according to the data format of the original data; Otherwise, the second transmission protocol is determined according to the maximum value of the effective load.

6. The data transmission rate conversion method based on FPGA according to claim 1, characterized in that: The step of extracting characteristic data of the original data according to the second transmission protocol includes: Obtain a mathematical model formula of the second transmission protocol, determine key parameters of the second transmission protocol according to the mathematical model formula, and determine feature data to be extracted according to the key parameters.

7. The data transmission rate conversion method based on FPGA according to claim 1, characterized in that: The step of extracting the characteristic data of the original data and repackaging the original data according to the identifier corresponding to the characteristic data to generate a plurality of final data packets includes: According to the time when the characteristic data appears, each characteristic is assigned a time identifier, and data units with the same time identifier are packaged to generate the final data packet.

8. A data transmission rate conversion device based on FPGA, a data transmission rate conversion system based on FPGA, comprising: PHY transceiver, used for receiving data that needs to be converted in transmission rate; A service FPGA, used for parsing the data received by the PHY transceiver and determining a second transmission protocol for transmission; MAC controller, used to repack the data and generate the final data packet; A high-speed serial interface is used to send the final data packet to a target address.

9. The data transmission rate conversion device based on FPGA according to claim 8, characterized in that: The business FPGA includes: A monitoring module, used for error checking and service quality filtering of data received by the PHY transceiver to obtain data to be parsed; The processing module is used to determine whether the original data conforms to the effective load of the target address.

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