Power distribution network cable terminal surface partial discharge detection device and method

Abstract

The invention provides a power distribution network cable terminal surface partial discharge detection device and method, and belongs to the technical field of partial discharge detection. The problem that partial discharge information is extracted mistakenly due to signal fluctuation caused by various interferences when an existing detection device is applied on site is solved. The device comprises a power supply module, a frequency division filtering module, an analog-to-digital conversion module and a CPU module. The frequency division filtering module collects partial discharge original signals on the surface of a cable, separates effective partial discharge signals and phase signals in the partial discharge original signals, converts the effective partial discharge signals and the phase signals into digital signals through the analog-to-digital conversion module, and transmits the digital signals to the CPU module. The CPU module is used for circularly collecting and processing the digital signals, wherein the signal processing comprises triggering signal zero-phase detection, split-phase window discharge capacity peak searching and phase counting; the method is applied to cable partial discharge detection.

Description

Technical Field

[0001] The present application relates to the technical field of partial discharge detection, and in particular to a device and method for detecting partial discharge on the surface of a distribution network cable terminal. Background Art

[0002] High-voltage switchgear is widely used in my country's 35kV and below distribution networks. It is an important bridge link for power transmission and distribution nodes. The structure inside the switchgear is complex, and the components in different switchgears vary greatly, which leads to condensation and contamination in the switchgear, causing insulation surface discharge. In particular, insulation surface discharge at the cable terminal will cause insulation corrosion, and as the degree of corrosion increases, carbonization grooves and composition changes will appear on the insulation surface, the surface conductivity will gradually increase, and the surface hydrophobicity will weaken, eventually leading to the failure of cable insulation in the switchgear.

[0003] Therefore, how to detect partial discharge on the surface of cable insulation in high-voltage switchgear has attracted widespread attention, but the existing partial discharge detection devices for cable insulation surface used in switchgear still have certain limitations. This is mainly reflected in the fact that when collecting partial discharge signals on site, various interferences and noises will cause fluctuations in partial discharge signals, which can easily lead to inaccurate extraction of partial discharge phase information. If the phase information of partial discharge cannot be accurately obtained, errors will occur when drawing the partial discharge phase angle analysis diagram, and the resulting diagram will not be able to truly reflect the discharge type, making it difficult to identify the subsequent partial discharge type, or even impossible to identify the partial discharge type.

[0004] Among the research results on partial discharge detection on the surface of cable insulation in switch cabinets related to the present application, for example, the patent "CN119375642A- A method and system for online monitoring of partial discharge in high-voltage switch cabinets" introduces how to achieve early warning of partial discharge in target parts of high-voltage switch cabinets; the patent "CN119375641A- Partial discharge and positioning device based on core phase hole of switch cabinet" introduces a method for measuring partial discharge through the core phase hole of switch cabinet and realizing cable defect positioning by using PRPD spectrum; the patent "CN119471261A- A method, system and medium for partial discharge detection of high-voltage cables" introduces a high-voltage cable partial discharge detection system, which includes a detection acquisition module and a diagnosis module; the partial discharge monitoring device designed in the patent "CN119125807A- An intelligent online monitoring system and device for partial discharge of switch cabinets" includes a data temporary storage module, a data analysis module, a real-time data monitoring module, etc. In summary, these existing patents tend to reuse partial discharge data and the overall design of partial discharge detection devices or systems. They do not provide targeted designs of partial discharge zero-phase detection, discharge peak finding, phase counting and other methods based on the developed device hardware. They cannot avoid the problem of erroneous extraction of partial discharge information caused by signal fluctuations due to various interferences in field applications, and cannot meet the requirements for partial discharge detection on site in switch cabinets. Summary of the invention

[0005] In order to solve the above technical problems, the present application proposes a device and method for detecting partial discharge on the surface of a distribution network cable terminal.

[0006] The technical solution adopted in the present application is: a device for detecting partial discharge on the surface of a cable terminal in a distribution network, comprising a power supply module, a frequency division filter module, an analog-to-digital conversion module and a CPU module, wherein the input port of the frequency division filter module is respectively connected to a partial discharge sensor provided on each phase of a cable under test in a switch cabinet, the phase output port of the frequency division filter module is connected to a low-speed port of an analog-to-digital conversion module, the partial discharge output port of the frequency division filter module is connected to a high-speed port of an analog-to-digital conversion module; the parallel digital output port of the analog-to-digital conversion module is connected to the CPU module; The frequency division filtering module collects the original partial discharge signal on the surface of the tested cable, and separates the effective partial discharge signal and phase signal in the original partial discharge signal. The above effective partial discharge signal and phase signal are converted into digital signals by the analog-to-digital conversion module and then transmitted to the CPU module. The CPU module is used for cyclic acquisition and signal processing of the digital signal, wherein the signal processing includes trigger signal zero phase detection, phase window discharge peak search and phase counting. The trigger signal zero phase detection completes the zero-crossing rising edge detection of the phase signal. After the zero-crossing rising edge is detected, the phase window discharge peak search and phase counting are performed, and finally the phase-discharge data starting from the zero point of the rising edge of the phase signal is output.

[0007] Furthermore, the frequency division filtering module is composed of three identical signal processing circuits, namely signal processing circuit A, signal processing circuit B and signal processing circuit C, wherein the input ports of signal processing circuit A, signal processing circuit B and signal processing circuit C are respectively connected to the partial discharge sensors installed on phase A, phase B and phase C of the measured cable, and the input port of each signal processing circuit includes two branch circuits, one of which uses two operational amplifiers and their connected capacitors and resistors to realize the acquisition of phase signals, and the phase signal is used to provide a synchronous clock; the other branch circuit uses four operational amplifiers and their connected capacitors and resistors to realize the acquisition of partial discharge pulse signals and record the occurrence of discharge events.

[0008] Furthermore, the analog-to-digital conversion module consists of a low-speed analog-to-digital conversion unit and three high-speed analog-to-digital conversion units, wherein the three input ports of the low-speed analog-to-digital conversion unit are respectively connected to the phase signal output ends of the signal processing circuit A, the signal processing circuit B and the signal processing circuit C, and the three high-speed analog-to-digital conversion units are respectively connected to the partial discharge signal output ends of the signal processing circuit A, the signal processing circuit B and the signal processing circuit C.

[0009] Furthermore, it also includes a communication module, and the CPU module communicates with the communication module in a two-way manner.

[0010] Furthermore, it also includes a display module, which is connected to the CPU module. The CPU module has built-in software for drawing the phase-discharge data into a PRPD spectrum corresponding to the partial discharge, and the display module visualizes the drawn PRPD spectrum.

[0011] Furthermore, the CPU module has a built-in data storage module, which is composed of two FIFO read-write control modules and an SDRAM storage area.

[0012] A method for detecting partial discharge on the surface of a distribution network cable terminal comprises the following steps: S1: The operator first connects the distribution network cable terminal surface partial discharge detection device to the incoming cable in the switch cabinet according to the pulse current method, and then starts the discharge detection; S2: The original partial discharge signal generated in the detection circuit is first input into the detection device through the frequency division filter module. After filtering and voltage conditioning, the partial discharge data originally coupled to the power frequency sinusoidal voltage is output to the analog-to-digital conversion module through two channels, one of which is the power frequency trigger voltage phase reference signal for providing a synchronous clock; the other is the partial discharge pulse signal for recording the occurrence of the discharge event; then, the two signals are converted into binary digital quantities in the analog-to-digital conversion module and input into the CPU module; the trigger signal zero phase detection, phase window discharge peak search, and phase counting program in the CPU module process and calculate the partial discharge data to obtain partial discharge data with phase information and single-phase window discharge peak value, namely phase-discharge data; S3: After being processed and handled by the software in the CPU module, the collected phase-discharge data is finally visualized on the display module in the form of a PRPD spectrum and presented to the operator.

[0013] Furthermore, the process of triggering signal zero phase detection is as follows: first, the rising edge flag flag_start of the phase signal is cleared to 0 for initialization, and the phase signal data interval after analog-to-digital conversion is adjusted to -512~511, and the adjusted phase signal data is named ad0_data; then, ad0_data is beat twice along the rising edge of the clock signal, the first beat is named zero_st1, and the second beat is named zero_st2, that is, zero_st1 lags behind zero_st2 by one clock cycle; then, the highest bit of zero_st1 and zero_st2 data is determined. Whether the result after the XOR operation is 1, if it is 1, then proceed to the next step; if not 1, the phase signal rising edge flag flag_start is cleared to 0 and the process ends; then, after a delay of 5 clock cycles, determine whether the logical AND operation result of the highest bit of zero_st1 being 0 and the highest bit of zero_st2 being 1 is 1. If the result is 1, it means that the process of the digital quantity of the phase signal changing from negative to positive, that is, the phase zero point, is detected, and then the phase signal rising edge flag flag_start is set to 1 and the process ends; otherwise, the phase signal rising edge flag flag_start is cleared to 0 and the process ends.

[0014] Furthermore, the process of finding the peak of the phase window discharge is as follows: first, determine whether the phase signal is the rising edge zero point. After the rising edge zero point is detected, the maximum discharge amount of the phase window, the sampling point sequence number and the phase window sequence number are all set to 0 for initialization; then determine whether the current discharge amount is greater than the maximum discharge amount of the phase window. If it is greater, the current discharge amount is assigned to the maximum discharge amount of the phase window, and the sampling point sequence number is increased by one; otherwise, the sampling point sequence number is directly increased by one; then the above comparison process is repeated until all sampling points of the current phase window are traversed; when a phase window is compared in a loop, the maximum discharge amount of the phase window is saved and the phase window sequence number is increased by one.

[0015] Furthermore, the phase counting process is as follows: first determine whether the rising edge zero point of the phase signal is reached. If reached, the phase window number, single-phase window phase span, current phase, and current phase window sequence number are initialized and set; if the phase signal does not reach the rising edge zero point, continue to detect until the rising edge zero point arrives; then, wait for the discharge peak to traverse each local discharge sampling point in the phase window, and after the traversal, update the current phase window sequence number and current phase, and then repeat the above process for the next phase window until all phase windows in the entire trigger cycle complete the phase calculation.

[0016] The beneficial effects of the present application compared to the prior art are as follows: the present application adopts a high sampling rate hardware design and a streamlined processing method for partial discharge data, which can accurately capture and analyze the partial discharge signals occurring on the surface of cable insulation in the switch cabinet. By real-time monitoring of partial discharge conditions, abnormal conditions on the surface of cable insulation can be discovered in time, and corresponding maintenance measures can be taken to ensure the safe operation of the cable. Compared with traditional partial discharge detection methods, the present application has a higher sampling rate and detection accuracy, and can effectively improve the cable insulation performance and service life of the switch cabinet. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present application is further described below with reference to the accompanying drawings: Figure 1 An overall block diagram of a partial discharge detection device provided in an embodiment of the present application; Figure 2 A circuit schematic diagram of a frequency division filtering module provided in an embodiment of the present application; Figure 3 A circuit schematic diagram of an AD conversion module provided in an embodiment of the present application; Figure 4 A flowchart of a trigger signal zero phase detection program provided in an embodiment of the present application; Figure 5 A flow chart of peak finding of the phase window discharge amount provided in the embodiment of the present application; Figure 6 A phase counting flow chart provided for an embodiment of the present application; Figure 7 This is a PRPD spectrum of surface discharge detected by the device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0018] like Figures 1 to 7As shown, the present application provides a partial discharge detection device for the surface of a cable terminal in a distribution network, which can accurately detect partial discharge on the surface of cable insulation in a switch cabinet, including a power supply module, a frequency division filter module, an analog-to-digital conversion module, a CPU module, a communication module and a display module, wherein the input port of the frequency division filter module is respectively connected to the partial discharge sensor on each phase of the cable under test in the switch cabinet, the phase output port of the frequency division filter module is connected to the low-speed port of the analog-to-digital conversion module, and the partial discharge output port of the frequency division filter module is connected to the high-speed port of the analog-to-digital conversion module; the parallel digital output port of the analog-to-digital conversion module is connected to the SPI port and the GPIO port of the CPU module; the display module is connected to the I 2 The communication module is connected to the Ethernet interface of the CPU module, which can realize the communication between the CPU module and the host computer. The power module is used to supply power to the frequency division filter module, analog-to-digital conversion module, CPU module, communication module and display module.

[0019] The CPU module may use FPGA. In this embodiment, the CPU module uses a minimum system with XC7Z020-2CLG400C as a processor, which is used to read, analyze and store partial discharge signals. It has a built-in data storage module that can be used to store partial discharge signals.

[0020] The frequency division and filtering module is used to collect the original partial discharge signal on the cable surface and separate the effective partial discharge signal and phase signal from the original partial discharge signal. Figure 2 As shown, the frequency division filter module is composed of three identical signal processing circuits, namely signal processing circuit A, signal processing circuit B and signal processing circuit C. The input ports of signal processing circuit A, signal processing circuit B and signal processing circuit C are U PDA , U PDB , U PDC The input capacitors of the signal processing circuit A are connected to the partial discharge sensors on the A phase, B phase and C phase of the tested cable. C 0 One end of the signal processing circuit A is used as the input port U PDA , input capacitance C 0 The other end of the resistor R 0 , R 1 , R 5 Connect one end of the resistor R 0 The other end of the resistor is connected to the ground terminal of the power module.R 1 The other end of the capacitor C 1 One end of the resistor R 2 One end of the capacitor is connected C 1 The other end of the operational amplifier U 1 The inverting input, output, and resistor R 3 Connect one end of the resistor R 2 The other end of the operational amplifier U 1 The non-inverting input terminal and capacitor C 2 Connect one end of the capacitor. C 2 The other end of the resistor is connected to the ground terminal of the power module. R 3 The other end of the capacitor C 3 One end of the resistor R 4 Connect one end of the capacitor. C 3 The other end of the operational amplifier U 2 The inverting input and output of the filter module are connected and used as the phase signal output of the frequency division filter module. U φAo , output the phase signal of the original partial discharge signal of phase A. R 4 The other end of the operational amplifier U 2 The non-inverting input terminal and capacitor C 4 Connect one end of the capacitor. C 4 The other end of the resistor is connected to the ground terminal of the power module. R 5 The other end of the capacitor C 5 One end of the resistor R 6 Connect one end of the capacitor. C 5 The other end of the operational amplifier U 3 The inverting input, output, and resistor R 7 Connect one end of the resistor R 6 The other end of the operational amplifier U3 The non-inverting input terminal and capacitor C 6 Connect one end of the capacitor. C 6 The other end of the resistor is connected to the ground terminal of the power module. R 7 The other end of the capacitor C 7 One end of the resistor R 8 Connect one end of the capacitor. C 7 The other end of the operational amplifier U 4 The inverting input, output, and capacitor C 9 Connect one end of the resistor R 8 The other end of the operational amplifier U 4 The non-inverting input terminal and capacitor C 8 Connect one end of the capacitor. C 8 The other end of the capacitor is connected to the ground terminal of the power module. C 9 The other end of the resistor R 12 One end of the capacitor C 10 Connect one end of the resistor R 12 The other end of the operational amplifier U 5 The output terminal, resistor R 11 One end and the capacitor C 11 Connect one end of the resistor R 11 The other end of the operational amplifier U 5 The inverting input terminal, resistor R 9 Connect one end of the resistor R 9 The other end of the capacitor is connected to the ground terminal of the power module. C 10 The other end of the operational amplifier U 5 The non-inverting input terminal and resistor R 10 Connect one end of the resistor R 10 The other end of the capacitor is connected to the ground terminal of the power module. C11 The other end of the resistor R 13 One end of the capacitor C 12 One end of the capacitor C 13 Connect one end of the resistor R 13 The other end of the operational amplifier U 6 The inverting input and output of the filter module are connected and used as the partial discharge signal output terminal of the frequency division filter module. U PDAo .capacitance C 12 The other end of the operational amplifier U 5 The non-inverting input terminal and resistor R 14 Connect one end of the resistor R 14 The other end of the capacitor C 13 The other end is connected to the ground terminal of the power module.

[0021] In this embodiment, the operational amplifier U 1 , U 2 , U 3 , U 4 , U 5 , U 6 Both are TLV9361. The output ends of the signal processing circuit B and the signal processing circuit C of the frequency division filter module are: partial discharge signal output end U PDBo and U PDCo , and phase signal output U φBo and U φCo .

[0022] The analog-to-digital conversion module is used to convert analog signals into digital signals, that is, to convert the partial discharge signal and phase signal of the frequency division filter module into digital signals. Figure 3 As shown, the analog-to-digital conversion module consists of a low-speed analog-to-digital conversion unit U 7 and three high-speed conversion units U 9 , U 11 , U13 In this embodiment, the low-speed analog-to-digital conversion unit adopts AD7606-4, and the high-speed conversion unit adopts 3PA1030. U φAo , U φBo and U φCo Low-speed analog-to-digital conversion unit U 7 Input port V 1 , V 2 and V 3 Connection, low speed analog to digital conversion unit U 7 The SPI port outputs the digital quantity of the three-phase phase signal A, B, and C D φo . U PDAo With capacitor C 14 and resistor R 15 One end of the operational amplifier U 8 The capacitor is connected to the non-inverting input terminal. C 14 The other end of the capacitor C 15 One end of the resistor R 15 The other end of the resistor R 16 Connect one end of the capacitor. C 15 The other end and the resistor R 16 The other end of each is connected to the ground terminal of the power module. U 8 The inverting input terminal and the resistor R 17 Connect one end of the resistor R 17 The other end of the operational amplifier U 8 The output terminal is connected to the high-speed conversion unit U 9 High-speed conversion unit U 9 Output port D 1~9 Output digital quantity of phase A partial discharge signal D PDAo . U PDBoWith capacitor C 16 One end of the resistor R 18 one end, and the operational amplifier U 10 The capacitor is connected to the non-inverting input terminal. C 16 The other end of the capacitor C 17 One end of the resistor R 18 One end of the capacitor R 19 Connect one end of the capacitor. C 17 The other end and the resistor R 19 The other end of each is connected to the ground terminal of the power module. U 10 The inverting input terminal and the resistor R 20 Connect one end of the resistor R 20 The other end of the operational amplifier U 10 The output terminal is connected to the high-speed conversion unit U 11 High-speed conversion unit U 11 Output port D 1~9 Output digital quantity of phase B partial discharge signal D PDBo . U PDCo With capacitor C 18 One end of the resistor R 21 one end, and the operational amplifier U 12 The capacitor is connected to the non-inverting input terminal. C 18 The other end of the capacitor C 19 One end of the resistor R 21 One end of the resistor R 22 Connect one end of the capacitor. C 19 The other end and the resistor R 22 The other end of each is connected to the ground terminal of the power module. U 12 The inverting input terminal and the resistor R23 Connect one end of the resistor R 23 The other end of the operational amplifier U 12 The output terminal is connected to the high-speed conversion unit U 13 High-speed conversion unit U 13 Output port D 1~9 Output digital quantity of phase C partial discharge signal D PDCo . D φo Connect to the SPI port of the CPU module, D PDAo , D PDBo , D PDCo Connect to the GPIO port of the CPU module.

[0023] The logic operation unit in the CPU module is used to complete the digital signal D φo , D PDAo , D PDBo , D PDCo The calculation and processing includes signal acquisition and signal processing. The function of signal acquisition is to cyclically collect the phase and partial discharge signals of the three phases A, B, and C. Signal processing includes trigger signal zero phase detection, phase window discharge peak finding and phase counting. Trigger signal zero phase detection is used to complete the zero-crossing rising edge detection of the phase signal. After detecting the zero-crossing rising edge, the phase window discharge peak finding and phase counting are performed. The phase counting program exists to provide a reference phase for the above-mentioned phase window discharge peak finding process, ensuring that each section of discharge data after the phase window discharge peak finding has a corresponding phase point, so as to draw the PRPD spectrum of the insulation surface discharge in the subsequent upper computer. The specific design process of each of the above-mentioned programs is as follows.

[0024] like Figure 4The flowchart of the trigger signal zero phase detection program provided by the embodiment of the present application is shown. In this process, the rising edge flag flag_start of the phase signal is first cleared to 0 and initialized, and the 10-bit phase signal data interval after analog-to-digital conversion is adjusted from the original 0~1023 to -512~511, and the adjusted phase signal data is named ad0_data. Then, along the rising edge of the clock signal, ad0_data is played twice, the first beat is named zero_st1, and the second beat is named zero_st2, which means that zero_st1 lags behind zero_st2 by one clock cycle. Next, it is determined whether the result of the "XOR" operation of the highest bit of zero_st1 and zero_st2 data (0 means the data is negative, and 1 means the data is positive) is 1. If it is 1, then proceed to the next step; if it is not 1, the rising edge flag flag_start of the phase signal is cleared to 0 and the process is ended. The purpose of this step is to determine whether the phase signals of the two adjacent moments before and after the rising edge zero point are in the same positive and negative half cycle. Then, after a delay of 5 clock cycles, it is determined whether the result of the "logical AND" operation of "zero_st1's highest bit is 0" and "zero_st2's highest bit is 1" is 1. If the result is 1, it means that the process of the phase signal digital quantity changing from negative to positive is detected, that is, the phase zero point, and then the phase signal rising edge flag flag_start is set to 1 and the process ends. Otherwise, the phase signal rising edge flag flag_start is cleared to 0 and the process ends. In this process, the phase signal undergoes two judgments, with an interval of 5 clock cycles in between, which can avoid misjudgment caused by signal fluctuations to a certain extent and increase the fault tolerance of the program.

[0025] like Figure 5 The figure shows the peak finding flow chart of the phase window discharge amount provided by the embodiment of the present application. In this process, it is first determined whether the phase signal is the rising edge zero point. After the rising edge zero point is detected, the maximum discharge amount PD of the phase window is imax , sampling point sequence number β i Sum window number i All are reset to 0. Then determine the current discharge amount PD in_data Is it greater than the maximum discharge capacity PD of this phase window? imax If it is greater than, the current discharge amount PD in_data Assign the maximum discharge amount PD to this phase window imax , sampling point number β i Add one; otherwise, directly increase the sampling point sequence number β i Add 1. Then loop the above comparison process 2000 times until all sampling points of the current phase window are traversed. After looping and comparing a phase window, save the maximum discharge amount PD of the phase windowimax , the phase window number i Plus one. In this embodiment, the sampling rate of the analog-to-digital conversion module is set to 50Msps, and each sampling channel will generate 50 million partial discharge data per second, so the above process will be executed 500 times in one trigger cycle to ensure that all phase windows in the trigger cycle participate in the discharge peak search. The trigger cycle is related to the frequency. At present, the AC frequency of my country's power grid is 50Hz, and one cycle is fixed at 20 milliseconds. Therefore, in this embodiment, the entire trigger cycle can be 20ms. If it is other frequencies, the trigger cycle can be modified accordingly according to the specific frequency.

[0026] like Figure 6 The figure shows a phase counting flow chart provided by an embodiment of the present application. In this process, it is first determined whether the rising edge zero point of the phase signal is reached. If reached, the phase window number is n , single-phase window phase span a , Current Phase p ( i ), current phase window number i Perform initialization settings; if the phase signal does not reach the rising edge zero point, continue to detect until the rising edge zero point arrives. The phase count should be consistent with the phase window number of the discharge peak, so the phase window number n is uniformly set to 500. Next, wait for the discharge peak to traverse each local discharge sampling point in the phase window, and then traverse the current phase window sequence number. i and the current phase p ( i ) to update, phase p ( i ) is updated according to formula (1). Then, the above process is repeated for the next phase window until all phase windows in the entire trigger cycle have completed phase calculation.

[0027] (1).

[0028] After the above-mentioned trigger signal zero phase detection, phase window discharge peak search, phase counting and other processes, the partial discharge digital signal has been converted into phase-discharge data starting from the zero point of the phase signal rising edge when it is output from the CPU module. Therefore, it is only necessary to transmit these data back to the host computer to obtain the PRPD spectrum corresponding to the partial discharge, and then analyze the discharge phenomenon.

[0029] The data storage module is used to save some phase-discharge data, and can calculate some partial discharge parameters offline, such as the average discharge per minute, discharge frequency, etc. The module consists of two FIFO read-write control modules and a 256Mbit SDRAM storage area. The two FIFO read-write control modules cooperate with each other, one writes while the other reads, to achieve uninterrupted data storage; and the 256Mbit SDRAM storage area can store about 671s of phase-window partial discharge data under the condition that the sampling rate of the analog-to-digital conversion module is 50Msps.

[0030] The communication module is used to transmit phase-discharge data to the host computer or server connected to the device. The module communicates based on the UDP protocol, with a maximum transmission rate of 10Mbps and a single-packet data transmission capacity of up to 1472Byte. When communicating, the communication module must cooperate with the physical interface transceiver PHY chip to complete data transmission and reception. The PHY chip is responsible for establishing a signal transmission channel, converting the serial analog signal into a physical signal and outputting it through the RJ45 network port; the communication module is responsible for packaging the partial discharge data, so that the transmitted data complies with the UDP protocol and completes the batch transmission of data.

[0031] The display module is used to receive the phase-discharge data collected by the device, and to visualize and analyze partial discharge events by drawing the PRPD spectrum and triggering sinusoidal signal corresponding to partial discharge in the software of the CPU module. Figure 7 The figure shows the PRPD spectrum of surface discharge collected by this device and drawn in the display module. Analyzing the above figure, the PRPD spectrum drawn conforms to the typical surface discharge characteristics and the drawing effect is good, which can be used to analyze the insulation status and discharge degree of the switch cabinet. Therefore, it is believed that the discharge detection function of this device is normal and the display effect is good.

[0032] The embodiment of the present application also proposes a method for detecting partial discharge on the surface of a cable terminal of a distribution network, using the above-mentioned device, mainly comprising the following steps: S1: The operator first connects the partial discharge detection circuit of the device according to the pulse current method to the incoming cable in the switch cabinet, and then starts the partial discharge detection.

[0033] S2: The original partial discharge signal generated in the detection circuit is first input into the detection device through the frequency division filter module. After filtering and voltage conditioning, the partial discharge data originally coupled to the power frequency sinusoidal voltage is output to the analog-to-digital conversion module through two channels. One of them is the power frequency trigger voltage phase reference signal, which is used to provide a synchronous clock to ensure the accuracy of data acquisition; the other is a partial discharge pulse signal, which is used to record the occurrence of discharge events. Then, the two signals are converted into 10-bit binary digital quantities in the analog-to-digital conversion module and input into the CPU module. The trigger signal zero phase detection, phase window discharge peak search, phase counting and other programs in the CPU module process and calculate the partial discharge data to obtain partial discharge data with phase information and single-phase window discharge peak value, namely phase-discharge data, and then output to the FIFO read-write control module in the data storage module. In the reading and writing of the FIFO read-write control module, the phase-discharge data is written into the actual data storage area, namely the SDRAM storage area and the communication module respectively.

[0034] S3: After being processed and handled by the software in the CPU module, the collected phase-discharge data is finally visualized on the display module in the form of a PRPD spectrum and presented to the operator. The operator can analyze and judge the characteristics of the discharge spectrum, and then timely evaluate the operating status of the switch cabinet equipment or issue equipment failure warnings. The communication module can also send the phase-discharge data to the host computer or server side connected to the device according to the UDP protocol for further processing.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A partial discharge detection device for a distribution network cable terminal surface, characterized in that: It includes a power supply module, a frequency division filter module, an analog-to-digital conversion module and a CPU module. The input port of the frequency division filter module is respectively connected to the partial discharge sensor set on each phase of the measured cable in the switch cabinet, the phase output port of the frequency division filter module is connected to the low-speed port of the analog-to-digital conversion module, and the partial discharge output port of the frequency division filter module is connected to the high-speed port of the analog-to-digital conversion module; the parallel digital output port of the analog-to-digital conversion module is connected to the CPU module; The frequency division filtering module collects the original partial discharge signal on the surface of the tested cable, and separates the effective partial discharge signal and phase signal in the original partial discharge signal. The above effective partial discharge signal and phase signal are converted into digital signals by the analog-to-digital conversion module and then transmitted to the CPU module. The CPU module is used for cyclic acquisition and signal processing of the digital signal, wherein the signal processing includes trigger signal zero phase detection, phase window discharge peak search and phase counting. The trigger signal zero phase detection completes the zero-crossing rising edge detection of the phase signal. After the zero-crossing rising edge is detected, the phase window discharge peak search and phase counting are performed, and finally the phase-discharge data starting from the zero point of the rising edge of the phase signal is output.

2. A distribution network cable terminal surface partial discharge detection device according to claim 1, characterized in that: The frequency division filtering module is composed of three identical signal processing circuits, namely signal processing circuit A, signal processing circuit B and signal processing circuit C, wherein the input ports of signal processing circuit A, signal processing circuit B and signal processing circuit C are respectively connected to the partial discharge sensors installed on the A phase, B phase and C phase of the measured cable, and the input port of each signal processing circuit includes two branch circuits, one of which adopts two operational amplifiers and the capacitors and resistors connected thereto to realize the acquisition of the phase signal, and the phase signal is used to provide a synchronous clock; the other branch circuit adopts four operational amplifiers and the capacitors and resistors connected thereto to realize the acquisition of the partial discharge pulse signal and record the occurrence of the discharge event.

3. A distribution network cable terminal surface partial discharge detection device according to claim 2, characterized in that: The analog-to-digital conversion module consists of a low-speed analog-to-digital conversion unit and three high-speed analog-to-digital conversion units, wherein the three input ports of the low-speed analog-to-digital conversion unit are respectively connected to the phase signal output ends of the signal processing circuit A, the signal processing circuit B and the signal processing circuit C, and the three high-speed analog-to-digital conversion units are respectively connected to the partial discharge signal output ends of the signal processing circuit A, the signal processing circuit B and the signal processing circuit C.

4. A distribution network cable terminal surface partial discharge detection device according to any one of claims 1 to 3, characterized in that: It also includes a communication module, and the CPU module communicates with the communication module in a two-way manner.

5. A distribution network cable terminal surface partial discharge detection device according to claim 4, characterized in that: It also includes a display module, which is connected to the CPU module. The CPU module has built-in software for drawing phase-discharge data into a PRPD spectrum corresponding to partial discharge. The display module visualizes the drawn PRPD spectrum.

6. A distribution network cable terminal surface partial discharge detection device according to claim 5, characterized in that: The CPU module has a built-in data storage module, which consists of two FIFO read-write control modules and an SDRAM storage area.

7. A method for detecting partial discharge on the surface of a cable terminal in a distribution network, characterized in that: The following steps are involved: S1: The operator first connects the distribution network cable terminal surface partial discharge detection device as claimed in claim 6 to the incoming cable in the switch cabinet according to the pulse current method, and then starts the discharge detection; S2: The original partial discharge signal generated in the detection circuit is first input into the detection device through the frequency division filter module. After filtering and voltage conditioning, the partial discharge data originally coupled to the power frequency sinusoidal voltage is output to the analog-to-digital conversion module through two channels, one of which is the power frequency trigger voltage phase reference signal for providing a synchronous clock; the other is the partial discharge pulse signal for recording the occurrence of the discharge event; then, the two signals are converted into binary digital quantities in the analog-to-digital conversion module and input into the CPU module; the trigger signal zero phase detection, phase window discharge peak search, and phase counting program in the CPU module process and calculate the partial discharge data to obtain partial discharge data with phase information and single-phase window discharge peak value, namely phase-discharge data; S3: After being processed and handled by the software in the CPU module, the collected phase-discharge data is finally visualized on the display module in the form of a PRPD spectrum and presented to the operator.

8. A method for detecting partial discharge on the surface of a cable terminal in a distribution network according to claim 7, characterized in that: The process of triggering signal zero phase detection is as follows: first, clear the rising edge flag flag_start of the phase signal to 0 and initialize it, and adjust the phase signal data interval after analog-to-digital conversion to -512~511, and name the adjusted phase signal data ad0_data; then, beat ad0_data twice along the rising edge of the clock signal, the first beat is named zero_st1, and the second beat is named zero_st2, that is, zero_st1 lags behind zero_st2 by one clock cycle; then, determine whether the result of the exclusive OR operation of the highest bit of zero_st1 and zero_st2 data is 1, if it is 1, then proceed to the next step; If it is not 1, the phase signal rising edge flag flag_start is cleared to 0 and the process ends; Subsequently, after a delay of 5 clock cycles, determine whether the result of the logical AND operation of the highest bit of zero_st1 being 0 and the highest bit of zero_st2 being 1 is 1. If the result is 1, it indicates that the process of the digital quantity of the phase signal changing from negative to positive, that is, the phase zero point, is detected, and then the phase signal rising edge flag flag_start is set to 1 and the process ends; otherwise, the phase signal rising edge flag flag_start is cleared to 0 and the process ends.

9. A method for detecting partial discharge on the surface of a cable terminal in a distribution network according to claim 7, characterized in that: The process of peak-finding for phase-splitting window discharge is as follows: first, determine whether the phase signal is at the rising edge zero point. After the rising edge zero point is detected, the maximum discharge amount of the phase window, the sampling point sequence number, and the phase window sequence number are all set to 0 for initialization; then determine whether the current discharge amount is greater than the maximum discharge amount of the phase window. If so, assign the current discharge amount to the maximum discharge amount of the phase window, and increase the sampling point sequence number by one; Otherwise, the sampling point sequence number is directly increased by one; then the above comparison process is looped until all sampling points of the current phase window are traversed; when a phase window is compared in a loop, the maximum discharge amount of the phase window is saved and the phase window sequence number is increased by one.

10. A method for detecting partial discharge on the surface of a cable terminal in a distribution network according to claim 7, characterized in that: The phase counting process is as follows: first determine whether the rising edge zero point of the phase signal is reached. If reached, the number of phase windows, the single-phase window phase span, the current phase, and the current phase window sequence number are initialized and set; if the phase signal does not reach the rising edge zero point, continue to detect until the rising edge zero point arrives; then, wait for the discharge peak to traverse each local discharge sampling point in the phase window, and after the traversal, update the current phase window sequence number and the current phase, and then repeat the above process for the next phase window until all phase windows in the entire trigger cycle have completed the phase calculation.

Images