Control method and circuit for suppressing light-load turn-off stress of synchronous rectifier tube

Abstract

The invention provides a control method for suppressing light-load turn-off stress of a synchronous rectifier tube. The control method comprises the following steps: determining a control module setting end level based on a preset high-level threshold voltage and a control module setting end voltage; receiving a power supply fault signal, and determining a control module data end level based on the power supply fault signal; receiving a clock signal, and determining the driving end level of the control module based on the clock signal; determining a control module output end level based on the control module data end level, the control module driving end level and the control module setting end level so as to generate a PWM closing signal based on the control module output end level; and controlling the main control module to close PWM output at a preset safety moment based on the PWM closing signal, thereby realizing suppression of the turn-off stress of the synchronous rectifier tube. According to the control method and circuit for suppressing the light-load turn-off stress of the synchronous rectifier tube, the power supply fault signal and the clock signal are combined to control the main control module to turn off PWM output at the safe moment, and the stress problem of the synchronous rectifier tube is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly to a control method and circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes. Background Art

[0002] In recent years, switching power supplies have been continuously developing towards the direction of miniaturization, high efficiency, and high power density, and synchronous rectification technology has become very mature. Compared with ordinary diode rectification, synchronous rectification can greatly improve efficiency and is very suitable for applications with low-voltage and high-power outputs, but it also brings certain problems. Due to the unidirectional conduction characteristic of the diode in diode rectification, the output inductor in the converter will not have a negative current. However, during synchronous rectification, the current in the output inductor will have a negative current under no-load or light-load conditions. This negative current may cause stress problems for the synchronous rectifier tube when the converter shuts down. This phenomenon exists in various topologies. In applications with low-voltage and high-power outputs, due to the large negative current in the output inductor, the resulting voltage stress problem will be particularly prominent.

[0003] Currently, there are two common methods to solve the turn-off stress problem of synchronous rectifier converters: (1) Adopt the soft turn-off method, that is, after detecting the shutdown signal, the reference voltage of the converter gradually decreases, and the output also gradually decreases under the regulation of the loop, and the energy returns to the primary side until the output drops to 0V and the PWM is turned off. At this time, there is no energy in the inductor and no stress problem will occur. However, this method does not quite conform to the actual engineering application. When the converter triggers many protections, the PWM should be immediately turned off to avoid damaging the subsequent circuit; (2) Increase the absorption capacitor, which can suppress the magnitude of ΔVa, but increases the volume of the converter. At the same time, this capacitor also works during normal operation, which will affect the peak stress under heavy load conditions, and the absorption circuit will also heat up, resulting in high cost, low efficiency, and poor effect. Summary of the Invention

[0004] The present invention aims to provide a control method and circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes to solve the above technical problems. By controlling the PWM to turn off at a preset safe moment, the stress problem of the synchronous rectifier tube caused by the negative current of the output inductor under no-load and light-load conditions is avoided.

[0005] To solve the above technical problems, the present invention provides a control method for suppressing the light-load turn-off stress of synchronous rectifier tubes, which is applied to a control circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes, and includes the following steps:

[0006] Determine the level of the set terminal of the control module based on a preset high-level threshold voltage and the voltage of the set terminal of the control module;

[0007] Receive a power failure signal and determine the level of the data terminal of the control module based on the power failure signal;

[0008] Receive a clock signal and determine the level of the driving end of the control module based on the clock signal;

[0009] Determine the level of the output end of the control module based on the level of the data end of the control module, the level of the driving end of the control module, and the level of the setting end of the control module, so as to generate a PWM shutdown signal based on the level of the output end of the control module;

[0010] Control the main control module to turn off the PWM output at a preset safe time based on the PWM shutdown signal, so as to suppress the turn-off stress of the synchronous rectifier tube.

[0011] The above solution receives the power supply fault signal detected by the fault detection module and combines the clock signal of the main control module for signal integration and transformation, so as to control the main control module to turn off the PWM output at a preset safe time, avoiding the stress problem of the synchronous rectifier tube caused by the negative current of the output inductor under no-load and light-load conditions.

[0012] Further, determining the level of the output end of the control module based on the level of the data end of the control module, the level of the driving end of the control module, and the level of the setting end of the control module, so as to generate a PWM shutdown signal based on the level of the output end of the control module, includes: when the power supply fault signal exists, when determining that the clock signal is at the rising edge based on the level of the driving end of the control module, determining the level of the output end of the control module based on the level of the data end of the control module, the level of the driving end of the control module, and the level of the setting end of the control module, so as to generate a PWM shutdown signal based on the level of the output end of the control module.

[0013] In the above solution, by controlling the power supply fault signal and the clock signal of the control module interface, a level change is generated, correspondingly causing a corresponding change in the level of the output end, so that when there is a power supply fault signal, a PWM shutdown signal is generated by the level signal of the output end that appears when the clock signal is at the rising edge. Furthermore, based on this signal, the main control module can be controlled to turn off the PWM output at a preset safe time, simply and effectively solving the stress problem that occurs when turning off at a non-preset safe time.

[0014] Further, when the power supply fault signal does not exist, determine the level of the output end of the control module based on the level of the data end of the control module, the level of the driving end of the control module, and the level of the setting end of the control module, so as to generate a release signal based on the level of the output end of the control module, and based on the release signal, the main control module continues the original working state.

[0015] The present invention provides a control method for suppressing the light-load shutdown stress of a synchronous rectifier. The method receives a power fault signal detected by a fault detection module, and combines the clock signal of a main control module to realize signal integration transformation through a simple level trigger, so as to control the main control module to turn off the PWM output at a preset safety moment, thereby avoiding the stress problem of the synchronous rectifier caused by the negative current of the output inductor under no-load and light-load conditions. At the same time, when the power fault signal does not exist, a release signal is generated to release the control of the main control module, so that it can continue its original working state.

[0016] The present invention also provides a control circuit for suppressing the light-load shutdown stress of a synchronous rectifier tube, which is used to implement a control method for suppressing the light-load shutdown stress of a synchronous rectifier tube, including a fault detection module, a main control module and a PWM shutdown control module, wherein:

[0017] The receiving end of the fault detection module is electrically connected to the output end of the main control module, and the output end of the fault detection module is electrically connected to the fault receiving end of the PWM shutdown control module; the clock receiving end of the PWM shutdown control module is electrically connected to the clock output end of the main control module; the output end of the PWM shutdown control module is electrically connected to the receiving end of the main control module;

[0018] The fault module is used to output a power fault signal;

[0019] The main control module is used to output a clock signal and receive a PWM shutdown signal to shut down the PWM output at a preset safety moment based on the PWM shutdown signal;

[0020] The PWM shutdown control module is used to determine the set end level based on a preset high-level threshold voltage and the control module set end voltage; receive a power fault signal, and determine the control module data end level based on the power fault signal; receive a clock signal, and determine the control module drive end level based on the clock signal; and determine the control module output end level based on the control module data end level, the control module drive end level and the control module set end level, so as to generate a PWM shutdown signal based on the control module output end level; thereby controlling the main control module to shut down the PWM output at a preset safety moment based on the PWM shutdown signal, so as to suppress the shutdown stress of the synchronous rectifier tube.

[0021] The control circuit provided by the above scheme receives the power fault signal detected by the fault detection module through the PWM shutdown control module, and performs signal integration and transformation in combination with the clock signal of the main control module to control the main control module to shut down the PWM output at a preset safety moment, thereby avoiding the synchronous rectifier tube stress problem caused by the negative current of the output inductor under no-load and light-load conditions.

[0022] Further, the PWM shutdown control module is also used to determine the level of the output terminal of the control module based on the level of the data terminal of the control module, the level of the drive terminal of the control module, and the level of the set terminal of the control module when the power failure signal does not exist, so as to generate a release signal based on the level of the output terminal of the control module, and to make the main control module continue the original working state based on the release signal.

[0023] In the above solution, the PWM shutdown control module releases the control of the main control module by generating a release signal when the power failure signal does not exist, enabling it to continue its original working state and ensuring that the normal working state of the main control module is not affected.

[0024] Further, the PWM shutdown control module includes: a trigger, a switching transistor, an initial capacitor, an initial resistor, and an auxiliary power supply, where:

[0025] The drive terminal of the trigger serves as the clock receiving terminal of the PWM shutdown control module and is used to be electrically connected to the output terminal of the main control module; the data terminal of the trigger serves as the fault receiving terminal of the PWM shutdown control module and is used to be electrically connected to the output terminal of the fault detection module; the data terminal of the trigger is electrically connected to the auxiliary power supply, the output terminal of the trigger is electrically connected to the receiving terminal of the switching transistor, the set terminal of the trigger is electrically connected to the output terminal of the initial resistor, and the reset terminal of the trigger is electrically connected to the data terminal;

[0026] The input terminal of the initial resistor is electrically connected to the auxiliary power supply;

[0027] The first output terminal of the switching transistor serves as the output terminal of the PWM shutdown control module and is used to be electrically connected to the receiving terminal of the main control module, and the second output terminal of the switching transistor is grounded;

[0028] The output terminal of the initial resistor is electrically connected to the input terminal of the initial capacitor, and the output terminal of the initial capacitor is grounded;

[0029] The auxiliary power supply is used to charge the initial capacitor through the initial resistor to determine the level of the set terminal of the control module based on a preset high-level threshold voltage and the voltage of the set terminal of the control module;

[0030] The trigger is used to receive a clock signal to determine the level of the drive terminal of the control module based on the clock signal; receive a power failure signal to determine the level of the data terminal of the control module based on the power failure signal; and thus determine the level of the output terminal of the control module based on the level of the data terminal of the control module, the level of the drive terminal of the control module, and the level of the set terminal of the control module;

[0031] The switching transistor is used to generate a PWM shutdown signal based on the level of the output terminal of the control module, and to control the main control module to turn off the PWM output at a preset safe moment based on the PWM shutdown signal, so as to suppress the turn-off stress of the synchronous rectifier tube.

[0032] In the above scheme, the circuit structure of the PWM shutdown control module is designed. Through the trigger, the switch tube and some resistor and capacitor components, the signal integration based on the power fault signal and the clock signal is realized based on the asynchronous clearing and setting functions of the trigger, that is, the level conversion. Finally, the output level of the control module generates a PWM shutdown signal, thereby controlling the main control module to shut down the PWM output at a preset safety time, thereby suppressing the shutdown stress of the synchronous rectifier tube.

[0033] Furthermore, when the power fault signal does not exist: the trigger is also used to determine the output terminal level of the control module based on the data terminal level of the control module, the drive terminal level of the control module and the set terminal level of the control module; the switch tube is also used to generate a release signal based on the output terminal level of the control module, so as to enable the main control module to continue the original working state based on the release signal.

[0034] In the above scheme, when the power failure signal does not exist, a release signal is generated by changing the trigger level to release the control of the main control module so that it can continue its original working state, ensuring that the normal working state of the main control module is not affected.

[0035] Furthermore, the PWM shutdown control module also includes a pull-up resistor, an input end of the pull-up resistor is electrically connected to the initial resistor input end, and an output end of the pull-up resistor is electrically connected to the trigger data end.

[0036] In the above scheme, a pull-up resistor is added to prevent the trigger set terminal from being in an unstable state, thereby maintaining the stability of the circuit working state.

[0037] Furthermore, the PWM shutdown control module also includes a protection resistor, a first end of the protection resistor is electrically connected to the trigger output end, and a second end of the protection resistor is electrically connected to the switch tube receiving end.

[0038] In the above scheme, the protection resistor is set to maintain the stability of the circuit current and voltage to avoid device damage.

[0039] Furthermore, the PWM shutdown control module also includes a NOT gate, wherein: the NOT gate output end is electrically connected to the trigger driving end, and the NOT gate receiving end serves as the PWM shutdown control module receiving end, and is used to be electrically connected to the clock output end of the main control module; the NOT gate is used to receive the clock signal and invert it to generate a driving signal, so as to determine the driving end level of the control module based on the driving signal.

[0040] In the above solution, another processing method is provided by adding a NOT gate. In this case, the trigger is triggered by a falling edge to control the generation of a PWM shutdown signal at a preset safety moment.

[0041] The present invention provides a control circuit for suppressing the light-load shutdown stress of a synchronous rectifier. The circuit transmits a power fault signal detected by a fault detection module to a PWM shutdown control module, and combines the clock signal of a main control module to perform signal integration transformation through a simple level triggering situation, so as to control the main control module to output a PWM shutdown signal at a preset safety moment, so that the main control module turns off the PWM output at the preset safety moment, thereby avoiding the stress problem of the synchronous rectifier caused by the negative current of the output inductor under no-load and light-load conditions; at the same time, when the power fault signal does not exist, a release signal is generated to release the control of the main control module, so that it can continue its original working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of a control method for suppressing light-load turn-off stress of a synchronous rectifier tube provided by an embodiment of the present invention;

[0043] Figure 2 A schematic diagram of a control circuit for suppressing light-load turn-off stress of a synchronous rectifier tube provided by an embodiment of the present invention;

[0044] Figure 3 A schematic diagram of a full-bridge topology converter circuit provided by an embodiment of the present invention;

[0045] Figure 4 A schematic diagram of operating mode waveforms of a full-bridge topology converter circuit in a no-load steady state provided by an embodiment of the present invention;

[0046] Figure 5 A circuit diagram of a non-isolated Buck converter with a single-ended topology is provided as a synchronous rectification converter according to an embodiment of the present invention;

[0047] Figure 6 A schematic diagram of operating mode waveforms of a non-isolated Buck converter with a single-ended topology, provided by an embodiment of the present invention;

[0048] Figure 7 A schematic diagram of a voltage waveform at the front end of an inductor and a VDS waveform of MOS tubes SR1 and SR2 when PWM is turned off during the t0-t1 period provided by an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of a voltage waveform at the front end of an inductor and a VDS waveform of MOS tubes SR1 and SR2 when PWM is turned off during the t1-t2 period provided by an embodiment of the present invention;

[0050] Figure 9 A schematic diagram of a voltage waveform at the front end of an inductor and a VDS waveform of MOS tubes SR1 and SR2 when PWM is turned off during the t2-t3 period provided by an embodiment of the present invention;

[0051] Figure 10 Schematic diagram of the voltage waveform at the front end of the inductor and the VDS waveforms of MOS transistors SR1 and SR2 when PWM is turned off in the t3-t4 stage provided by an embodiment of the present invention;

[0052] Figure 11 Schematic diagram of a control system for suppressing the light-load turn-off stress of synchronous rectifier tubes provided by an embodiment of the present invention;

[0053] Figure 12 Schematic diagram of a PWM turn-off control circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes provided by an embodiment of the present invention;

[0054] Figure 13 Schematic diagram of the timing sequence of the working process of a control circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes provided by an embodiment of the present invention;

[0055] Figure 14 Schematic diagram of a control circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes using a NOT gate provided by an embodiment of the present invention;

[0056] Figure 15 Schematic diagram of the working timing sequence of a control circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes using a NOT gate provided by an embodiment of the present invention. Detailed implementation manners

[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0058] Embodiment 1:

[0059] This embodiment provides a control method for suppressing the light-load turn-off stress of synchronous rectifier tubes, which is applied to a control circuit for suppressing the light-load turn-off stress of synchronous rectifier tubes. As Figure 1 shown, it includes the following steps:

[0060] S1: Determine the level of the set terminal of the control module based on the preset high-level threshold voltage and the voltage of the set terminal of the control module;

[0061] S2: Receive the power failure signal and determine the level of the data terminal of the control module based on the power failure signal;

[0062] S3: Receive the clock signal and determine the level of the drive terminal of the control module based on the clock signal;

[0063] S4: Determine the level of the output terminal of the control module based on the levels of the data terminal, drive terminal, and set terminal of the control module, so as to generate a PWM off signal based on the level of the output terminal of the control module;

[0064] S5: Control the main control module to turn off the PWM output at a preset safe moment based on the PWM off signal, so as to suppress the turn-off stress of the synchronous rectifier tube.

[0065] The above solution receives the power supply fault signal detected by the fault detection module, and combines the clock signal of the main control module for signal integration and transformation, so as to control the main control module to turn off the PWM output at a preset safe moment, avoiding the stress problem of the synchronous rectifier tube caused by the negative current of the output inductor under no-load and light-load conditions.

[0066] Optionally, step S4 includes: when the power supply fault signal exists, determine the level of the output terminal of the control module based on the level of the drive terminal of the control module when the clock signal is at the rising edge, based on the levels of the data terminal, drive terminal, and set terminal of the control module, so as to generate a PWM off signal based on the level of the output terminal of the control module.

[0067] In the specific implementation process, by controlling the power supply fault signal and the clock signal of the control module interface, the level changes are generated, correspondingly causing the level of the output terminal to change accordingly, so that when the power supply fault signal exists, the output terminal level signal that appears when the clock signal is at the rising edge generates a PWM off signal, and then the main control module can be controlled to turn off the PWM output at a preset safe moment based on this signal, simply and effectively solving the stress problem that occurs when turning off at non-preset safe moments.

[0068] Optionally, when the power supply fault signal does not exist, determine the level of the output terminal of the control module based on the levels of the data terminal, drive terminal, and set terminal of the control module, so as to generate a release signal based on the level of the output terminal of the control module, and make the main control module continue the original working state based on the release signal.

[0069] A control method for suppressing the light-load turn-off stress of a synchronous rectifier tube provided in this embodiment receives the power supply fault signal detected by the fault detection module, and combines the clock signal of the main control module to realize signal integration and transformation through a simple level trigger situation, so as to control the main control module to turn off the PWM output at a preset safe moment, avoiding the stress problem of the synchronous rectifier tube caused by the negative current of the output inductor under no-load and light-load conditions; at the same time, when the power supply fault signal does not exist, a release signal is generated to release the control of the main control module, so that it can continue its original working state.

[0070] Embodiment 2:

[0071] This embodiment provides a control circuit for suppressing the turn-off stress of a synchronous rectifier tube, which is used to implement a control method for suppressing the turn-off stress of a synchronous rectifier tube, such as Figure 2 shown, including a fault detection module, a main control module, and a PWM shutdown control module, where:

[0072] The receiving end of the fault detection module is electrically connected to the output end of the main control module, and the output end of the fault detection module is electrically connected to the fault receiving end of the PWM shutdown control module; the clock receiving end of the PWM shutdown control module is electrically connected to the clock output end of the main control module; the output end of the PWM shutdown control module is electrically connected to the receiving end of the main control module;

[0073] The fault module is used to output a power fault signal;

[0074] The main control module is used to output a clock signal, receive a PWM shutdown signal, and turn off the PWM output at a preset safe time based on the PWM shutdown signal;

[0075] The PWM shutdown control module is used to determine the set terminal level based on a preset high-level threshold voltage and the voltage of the control module set terminal; receive a power fault signal and determine the data terminal level of the control module based on the power fault signal; receive a clock signal and determine the drive terminal level of the control module based on the clock signal; and determine the output terminal level of the control module based on the data terminal level, drive terminal level, and set terminal level of the control module, so as to generate a PWM shutdown signal based on the output terminal level of the control module; thereby controlling the main control module to turn off the PWM output at a preset safe time based on the PWM shutdown signal, and realizing the suppression of the turn-off stress of the synchronous rectifier tube.

[0076] The control circuit provided by the above solution receives the power fault signal detected by the fault detection module through the PWM shutdown control module, and combines the clock signal of the main control module for signal integration and transformation, so as to control the main control module to turn off the PWM output at a preset safe time, avoiding the stress problem of the synchronous rectifier tube caused by the negative inductor current under no-load and light-load conditions.

[0077] In the specific implementation process, such as Figure 3As shown in the figure, taking a full-bridge topology converter as an example for the switching power supply converter, the secondary side adopts the full-bridge synchronous rectification method. The input voltage is Vin, the output voltage is Vo, and the operating mode in half a cycle under no-load steady state is as follows: (1) In the t0-t1 stage, the primary switching tubes S1 and S4 are turned on, the synchronous rectifier tubes SR1 and SR4 on the secondary side are turned on, and SR2 and SR3 are turned off. Energy is transferred from the input end to the output end. At this time, it is the rectification stage 1, and the output inductor current (iL) decreases gradually in the negative direction; (2) In the t1-t2 stage, the states of the switching tubes remain unchanged. At this time, it is the rectification stage 2, and the output inductor current turns positive and gradually increases; (3) In the t2-t3 stage, all the primary switching tubes are turned off, and all the secondary switching tubes are turned on. At this time, it is the freewheeling stage 1, and the output inductor current decreases to zero in the positive direction; (4) In the t3-t4 stage, the states of the switching tubes remain unchanged. At this time, it is the freewheeling stage 2, and the output inductor current turns negative and gradually increases; The second half cycle is the same as the above (1) to (4), and the waveform at the front end of the inductor (VFF point) is as Figure 4 shown. As Figure 5 shown, when the synchronous rectification converter is a non-isolated Buck converter with a single-ended topology (including the primary switching tube S1 and the synchronous rectifier tube SR1), the waveform of its output inductor current is as Figure 6 shown. Similar to the full-bridge converter, it is divided into 4 stages. The inductor current is positive in the t1-t3 interval. Turning off the PWM in this interval will not cause stress problems. The difference is that the Buck converter completes one current cycle in one period, while the full-bridge converter does it in half a period; The synchronous rectification topology can be a single-ended topology, such as a forward converter, a BUCK converter, or a double-ended topology, such as a full-bridge converter, a half-bridge converter, a push-pull converter, etc. The scheme of this embodiment can be used for PWM control.

[0078] When the power converter triggers protection and needs to turn off the PWM, the turn-off point of the PWM is random and may occur at any moment in the four stages within the period. Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 are the voltage waveforms at the front end of the inductor (VFF point), the waveforms of MOS tubes SR1_VDS / V, SR2_VDS / V, and iL / A and time / mSecs when the PWM is turned off in different stages. The horizontal coordinate value interval is selected as 5, and the vertical coordinate value interval is selected as 10; (1) As Figure 7As shown in the figure, during the t0 - t1 stage, the PWM is turned off. Before the PWM is turned off, the VDS voltage of SR2 is Vin / N (N is the transformer turns ratio), the VDS voltage of SR1 is 0, and the inductor current is negative. At this time, when the PWM is turned off, the negative current will charge the parasitic capacitance and snubber capacitance of the MOS transistor. The voltage at the VFF point rises from Vin / N until all the negative inductor current is discharged. The increased voltage is called ΔVa. Since the initial VDS voltage of SR2 is Vin / N, its stress is Vin / N + ΔVa / 2, while the VDS of SR1 rises from 0 to ΔVa / 2. Next is the resonance process of the magnetizing inductor, output inductor, and MOS parasitic capacitance. Turning off during this interval will cause excessive stress problems, especially when turning off the PWM near the initial stage of t0, where the negative current is large and the stress is the greatest; (2) As Figure 8 shown in the figure, during the t1 - t2 stage, the PWM is turned off. Before the PWM is turned off, the VDS voltage of SR2 is Vin / N (N is the transformer turns ratio), the VDS voltage of SR1 is 0, and the output inductor current is positive. At this time, when the PWM is turned off, due to the existence of the magnetizing inductor and magnetizing current, and at this time iL > im*N, the output inductor enters the freewheeling stage, and the VDS of both SR1 and SR2 is 0. When iL = im*N, the VDS voltage of SR1 rises and is clamped at Vin / N, and the VDS voltage of SR2 remains 0. Then both the inductor current and the magnetizing current slowly decrease to 0. During this period, the output inductor and the MOS parasitic capacitance are always in resonance. Then the output inductor, the parasitic capacitances of each MOS transistor, and the magnetizing inductor resonate together. The stress of the synchronous rectifier is low and there is no risk when turning off the PWM within this interval; (3) As Figure 9 shown in the figure, during the t2 - t3 stage, the PWM is turned off. Before the PWM is turned off, the VDS voltage of SR2 is 0, the VDS voltage of SR1 is 0, and the inductor current is decreasing in the positive direction. At this time, when the PWM is turned off, due to the existence of the magnetizing inductor and magnetizing current, the VDS voltage of SR1 is clamped at Vin / N, the VDS voltage of SR2 is 0, the voltage across the inductor is still positive, and the current rises again. When iL = im*N, both the inductor current and the magnetizing current slowly decrease to 0. During this period, the output inductor and the MOS parasitic capacitance are always in resonance. Then the output inductor, the parasitic capacitances of each MOS transistor, and the magnetizing inductor resonate together. The stress of the synchronous rectifier is low and there is no risk when turning off the PWM within this interval; (4) As Figure 10As shown in the figure, PWM is turned off during the t3 - t4 stage. Before PWM is turned off, the VDS voltage of SR2 is 0, the VDS voltage of SR1 is 0, and the inductor current is rising negatively. At this time, when PWM is turned off, the negative current will charge the parasitic capacitance and snubber capacitance of the MOS transistor, and the voltage at the VFF point rises from 0 until all the negative inductor current is discharged. The increased voltage is called ΔVa. In an ideal state, the stress on both SR1 and SR2 is ΔVa / 2. However, in reality, due to the existence of the transformer excitation current, when all MOS transistors are turned off, the excitation current still needs to establish a conduction path, resulting in the stress on SR1 being Vin / N + ΔVa / 2 and the stress on SR2 being ΔVa / 2. Turning off during this interval will cause excessive stress problems, especially when PWM is turned off close to the t4 moment, where the negative current is large and the stress is the greatest. In summary, it can be seen that when the converter operates under no - load or light - load conditions, during the t0 - t1 and t3 - t4 time periods, there will be negative current in the output inductor. At this time, turning off the PWM output will cause a relatively high stress on the DS of one of the synchronous rectifier MOS transistors, which is likely to lead to over - stress and damage. That is, the preset safe moment can be selected as the t2 moment, and the key to solving the problem is to control PWM to turn off at a suitable and controllable point, rather than randomly.

[0079] In the specific implementation process, the fault - detection module can be built with analog circuits or implemented through a single - chip microcomputer. It is mainly used to detect over - voltage, under - voltage, over - temperature, over - current and other protections of the power supply module, and based on the detection results, send out a power - supply fault signal to cause the main - control module to turn off the PWM output. The traditional method is that the fault - detection signal directly goes to the main - control chip, resulting in a random moment to turn off the PWM, which is likely to cause stress problems. In this embodiment, the power - supply fault signal is processed first and then transmitted to the main - control module, so that PWM is turned off at the preset safe moment.

[0080] In the specific implementation process, a control system for suppressing the light - load turn - off stress of the synchronous rectifier tube is built through the control circuit for suppressing the light - load turn - off stress of the synchronous rectifier tube in this embodiment, to control the power supply to turn off at a safe moment, such as Figure 11 As shown in the figure, the system includes an auxiliary power - supply circuit, a fault - detection circuit, a PWM turn - off control circuit, a main - control IC, a drive circuit, and an auxiliary power - supply circuit. The auxiliary power - supply circuit is used to supply power to each module. The fault - detection circuit is used to detect the power - supply fault signal (Fault_signal) based on the main - control IC and transmit it to the PWM turn - off control circuit. The PWM turn - off control circuit is also used to receive the clock signal from the main - control IC (the clock signal is the drive signal sent by the main - control IC to the synchronous rectifier tube SR1 or SR2: PWM_SR1 or PWM_SR2), so as to obtain the PWM turn - off signal (Shutdown) based on the clock signal and the power - supply fault signal, thereby controlling the main - control IC to turn off the PWM output (PWM_S1 or PWM_S2) to the drive circuit.

[0081] Optionally, the PWM shutdown control module is further configured to, when the power failure signal does not exist, determine the level of the output terminal of the control module based on the level of the data terminal of the control module, the level of the drive terminal of the control module, and the level of the set terminal of the control module, so as to generate a release signal based on the level of the output terminal of the control module, and to cause the main control module to continue the original working state based on the release signal.

[0082] In the specific implementation process, the PWM shutdown control module releases the control of the main control module by generating a release signal when the power failure signal does not exist, enabling it to continue its original working state and ensuring that the normal working state of the main control module is not affected.

[0083] Optionally, the PWM shutdown control module includes: a trigger, a switching transistor, an initial capacitor, an initial resistor, and an auxiliary power supply, where:

[0084] The drive terminal of the trigger serves as the clock receiving terminal of the PWM shutdown control module and is used to be electrically connected to the output terminal of the main control module; the data terminal of the trigger serves as the fault receiving terminal of the PWM shutdown control module and is used to be electrically connected to the output terminal of the fault detection module; the data terminal of the trigger is electrically connected to the auxiliary power supply, the output terminal of the trigger is electrically connected to the receiving terminal of the switching transistor, the set terminal of the trigger is electrically connected to the output terminal of the initial resistor, and the reset terminal of the trigger is electrically connected to the data terminal;

[0085] The input terminal of the initial resistor is electrically connected to the auxiliary power supply;

[0086] The first output terminal of the switching transistor serves as the output terminal of the PWM shutdown control module and is used to be electrically connected to the receiving terminal of the main control module, and the second output terminal of the switching transistor is grounded;

[0087] The output terminal of the initial resistor is electrically connected to the input terminal of the initial capacitor, and the output terminal of the initial capacitor is grounded;

[0088] The auxiliary power supply is used to charge the initial capacitor through the initial resistor to determine the level of the set terminal of the control module based on the preset high-level threshold voltage and the voltage of the set terminal of the control module;

[0089] The trigger is configured to receive a clock signal to determine the level of the drive terminal of the control module based on the clock signal; receive a power failure signal to determine the level of the data terminal of the control module based on the power failure signal; and thus determine the level of the output terminal of the control module based on the level of the data terminal of the control module, the level of the drive terminal of the control module, and the level of the set terminal of the control module;

[0090] The switching transistor is configured to generate a PWM shutdown signal based on the level of the output terminal of the control module, and to control the main control module to turn off the PWM output at a preset safe moment based on the PWM shutdown signal, so as to suppress the turn-off stress of the synchronous rectifier tube.

[0091] In the specific implementation process, the trigger can be a rising-edge-triggered D-type flip-flop, and the switching transistor can be a bipolar junction transistor or a MOS transistor; the PWM shutdown control module has two input signals, one power supply, and one output signal. The auxiliary power supply is the supply Vcc for the trigger, generally 3.3V, which is determined according to the specific selected chip model; the output signal is the output signal of the collector of the bipolar junction transistor or the drain of the MOS transistor, which is generally connected to the UVLO pin or the SS pin of the main control module, that is, the receiving end of the main control module. Pulling down these pins can turn off the PWM output, that is, based on the PWM shutdown signal, the main control module is controlled to turn off the PWM output at a preset safe moment, so as to suppress the turn-off stress of the synchronous rectifier tube.

[0092] Optionally, when the power failure signal does not exist: the trigger is further configured to determine the level of the output terminal of the control module based on the level of the data terminal of the control module, the level of the drive terminal of the control module, and the level of the set terminal of the control module; the switching transistor is further configured to generate a release signal based on the level of the output terminal of the control module, so that the main control module continues its original working state based on the release signal.

[0093] In the specific implementation process, when the power failure signal does not exist, a release signal is generated through the change of the trigger level to release the control of the main control module, so that it can continue its original working state, ensuring that the normal working state of the main control module is not affected.

[0094] Optionally, the PWM shutdown control module further includes a pull-up resistor, the input end of the pull-up resistor is electrically connected to the input end of the initial resistor, and the output end of the pull-up resistor is electrically connected to the data terminal of the trigger.

[0095] In the specific implementation process, adding a pull-up resistor can prevent the set terminal of the trigger from being in an indeterminate state and maintain the stability of the circuit working state.

[0096] Optionally, the PWM shutdown control module further includes a protection resistor, the first end of the protection resistor is electrically connected to the output terminal of the trigger, and the second end of the protection resistor is electrically connected to the receiving terminal of the switching transistor.

[0097] In the specific implementation process, setting a protection resistor can maintain the stability of the circuit current and voltage conditions and avoid device damage.

[0098] In the specific implementation process, the circuit diagram of the PWM shutdown control module is as Figure 12As shown in the figure, D-type flip-flop IC1 is adopted. After power-on, the D pin (data terminal) and the RST\ pin are at high level. Vcc (auxiliary power supply) charges C1 (initial capacitor) through R1 (initial resistor). Before the voltage reaches the preset high-level threshold voltage, the PRE\ (set terminal) is determined to be at low level. Fault_signal is indeed at high level during the power-on initialization process and is set to low (L) only after the power supply module detects that all voltages, temperatures, etc. are normal, and then the main control IC starts. According to the function table shown in Table 1 below (X represents any state), the input terminal (INPUTS) controls the level change of the output terminal (OUTPUTS): the Q pin (output terminal) outputs a high level (H). The functions of R1 and C1 are to initialize the output of the flip-flop to a high level during power-on. Q1 is pulled low, and the main control module does not start and waits for the initialization of the fault detection module and the detection of the power fault signal; when PRE\ is higher than the threshold voltage, it is determined to be at high level and remains so. Since the device has not been powered on yet, there is no signal on PWM_SR1 and PWM_SR2. When the fault detection module detects no fault, Fault_signal becomes low level. Since RST\ is at low level, Q is at low level, and Q1 is disconnected, and the main control IC can start, and PWM_SR1 and PWM_SR2 start to have signals; during the normal operation of the module, if a fault occurs, the fault detection module sets the Fault_signal signal to high level. When both RST\ and PRE\ are at high level, the output Q is determined by D and is updated when the rising edge (↑) of CLK arrives. When the rising edge of PWM_SR1 or PWM_SR2 arrives, Q is set to high level, and Q1 is pulled low, turning off the PWM output of the main control IC. The rising edge of PWM_SR1 or PWM_SR2 corresponds to time t2. At this time, turning off the PWM synchronous rectifier tube will not cause the problem of excessive stress. When the fault is eliminated, Fault_signal becomes low level, Q is cleared again, Q1 is turned off, a release signal is generated, and the main control IC is released and can be powered on again. The timing diagram of this working process is as shown in Figure 13 shown in the figure.

[0099] Table 1 Flip-flop Function Table

[0100]

[0101] Optionally, the PWM shutdown control module further includes a NOT gate, where: the output terminal of the NOT gate is electrically connected to the driving terminal of the flip-flop, and the receiving terminal of the NOT gate serves as the receiving terminal of the PWM shutdown control module and is used to be electrically connected to the clock output terminal of the main control module; the NOT gate is used to receive the clock signal and invert it to generate a driving signal to determine the level of the driving terminal of the control module based on the driving signal.

[0102] In the specific implementation process, if the trigger is a falling edge triggered D-type trigger, since the falling edge of PWM_S1 or PWM_S2 is also the corresponding t2 moment, the driving signal PWM_S1 or PWM_S2 of the primary MOS can be used as the clock signal of the D trigger; similarly, when using PWM_S1 or PWM_S2 to trigger a D trigger that is also a rising edge triggered D trigger, a NOT gate (IC2) or a resistor combined with a MOS can be used to invert PWM_S1 or PWM_S2 and then connect it to the CLK pin. The circuit schematic diagram is as follows: Figure 14 shown.

[0103] In the specific implementation process, when the rising edge trigger is adopted, when the power supply fault signal comes, it will wait until the next rising edge comes to trigger the PWM shutdown. In this way, the maximum delay time is one cycle. Although the time is very short, the delay time can be further reduced after the improvement of this embodiment. The input of the PWM shutdown control module is 3 signals, the fault signal Fault_signal output by the fault detection module, the drive PWM_SR1 sent by the main control IC to the synchronous rectifier SR1, and the drive PWM_SR2 sent by the main control IC to the synchronous rectifier SR2. The signal generated by PWM_SR1 and PWM_SR2 after passing through an AND gate is connected to the CLK pin. This signal can fuse the rising edges of the two signals to reduce the delay time to half a cycle; the timing diagram of the specific working process is as follows Figure 15 There are many ways to generate the signal of the CLK pin, such as using PWM_S1 and PWM_S2 through an NOR gate, as long as the PWM can be turned off at time t2.

[0104] The present embodiment provides a control circuit for suppressing the light-load shutdown stress of a synchronous rectifier. The power fault signal detected by the fault detection module is first transmitted to the PWM shutdown control module, and the signal integration transformation is performed in combination with the clock signal of the main control module through a simple level triggering situation, so as to control the main control module to output the PWM shutdown signal at a preset safety moment, so that the main control module turns off the PWM output at the preset safety moment, avoiding the stress problem of the synchronous rectifier caused by the negative current of the output inductor under no-load and light-load conditions; at the same time, when the power fault signal does not exist, a release signal is generated to release the control of the main control module, so that it can continue its original working state.

[0105] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A control method for suppressing light-load turn-off stress of a synchronous rectifier, characterized in that: The control circuit is applied to suppress the light-load turn-off stress of the synchronous rectifier tube, and includes the following steps: Determining a control module set terminal level based on a preset high level threshold voltage and a control module set terminal voltage; receiving a power failure signal, and determining a level of a data terminal of a control module based on the power failure signal; Receiving a clock signal, and determining a driving terminal level of a control module based on the clock signal; Determine the control module output terminal level based on the control module data terminal level, the control module drive terminal level and the control module set terminal level, so as to generate a PWM shutdown signal based on the control module output terminal level; Based on the PWM shutdown signal, the main control module is controlled to shut down the PWM output at a preset safety moment to suppress the shutdown stress of the synchronous rectifier tube.

2. A control method for suppressing light-load turn-off stress of a synchronous rectifier according to claim 1, characterized in that: The step of determining the control module output terminal level based on the control module data terminal level, the control module drive terminal level and the control module set terminal level, so as to generate a PWM shutdown signal based on the control module output terminal level, comprises: When a power failure signal exists, the control module output terminal level is determined based on the control module drive terminal level. When the clock signal is a rising edge, the control module data terminal level, the control module drive terminal level and the control module set terminal level are determined to generate a PWM shutdown signal based on the control module output terminal level.

3. A control method for suppressing light-load turn-off stress of a synchronous rectifier according to claim 1, characterized in that: Also includes: When the power failure signal does not exist, the control module output terminal level is determined based on the control module data terminal level, the control module drive terminal level and the control module set terminal level, so as to generate a release signal based on the control module output terminal level, so as to enable the main control module to continue the original working state based on the release signal.

4. A control circuit for suppressing the light-load turn-off stress of a synchronous rectifier, characterized in that: A control method for suppressing the light-load turn-off stress of a synchronous rectifier tube according to any one of claims 1 to 3, comprising a fault detection module, a main control module and a PWM turn-off control module, wherein: The receiving end of the fault detection module is electrically connected to the output end of the main control module, and the output end of the fault detection module is electrically connected to the fault receiving end of the PWM shutdown control module; the clock receiving end of the PWM shutdown control module is electrically connected to the clock output end of the main control module; the output end of the PWM shutdown control module is electrically connected to the receiving end of the main control module; The fault detection module is used to output a power failure signal; The main control module is used to output a clock signal and receive a PWM shutdown signal to shut down the PWM output at a preset safety moment based on the PWM shutdown signal; The PWM shutdown control module is used to determine the set end level based on a preset high-level threshold voltage and the control module set end voltage; receive a power fault signal, and determine the control module data end level based on the power fault signal; receive a clock signal, and determine the control module drive end level based on the clock signal; and determine the control module output end level based on the control module data end level, the control module drive end level and the control module set end level, so as to generate a PWM shutdown signal based on the control module output end level; thereby controlling the main control module to shut down the PWM output at a preset safety moment based on the PWM shutdown signal, so as to suppress the shutdown stress of the synchronous rectifier tube.

5. A control circuit for suppressing light-load turn-off stress of a synchronous rectifier according to claim 4, characterized in that: The PWM shutdown control module is also used to determine the control module output terminal level based on the control module data terminal level, the control module drive terminal level and the control module set terminal level when the power fault signal does not exist, so as to generate a release signal based on the control module output terminal level, so as to enable the main control module to continue the original working state based on the release signal.

6. A control circuit for suppressing light-load turn-off stress of a synchronous rectifier according to claim 4, characterized in that: The PWM shutdown control module includes: a trigger, a switch tube, an initial capacitor, an initial resistor and an auxiliary power supply, wherein: The driving end of the trigger is used as a clock receiving end of the PWM shutdown control module, and is used to be electrically connected to the output end of the main control module; the data end of the trigger is used as a fault receiving end of the PWM shutdown control module, and is used to be electrically connected to the output end of the fault detection module; the data end of the trigger is electrically connected to the auxiliary power supply, the output end of the trigger is electrically connected to the switch tube receiving end, the set end of the trigger is electrically connected to the initial resistance output end, and the reset end of the trigger is electrically connected to the data end; The initial resistance input terminal is electrically connected to the auxiliary power supply; The first output end of the switch tube is used as the output end of the PWM shutdown control module, and is used to be electrically connected to the receiving end of the main control module, and the second output end of the switch tube is grounded; The initial resistance output terminal is electrically connected to the initial capacitance input terminal; The output terminal of the initial capacitor is grounded; The auxiliary power supply is used to charge the initial capacitor via the initial resistor to determine the control module set terminal level based on the preset high level threshold voltage and the control module set terminal voltage; The trigger is used to receive a clock signal to determine the level of the control module drive terminal based on the clock signal; receive a power failure signal to determine the level of the control module data terminal based on the power failure signal; thereby determining the level of the control module output terminal based on the control module data terminal level, the control module drive terminal level and the control module set terminal level; The switch tube is used to generate a PWM shutdown signal based on the output terminal level of the control module, so as to control the main control module to shut down the PWM output at a preset safety moment based on the PWM shutdown signal, thereby suppressing the shutdown stress of the synchronous rectifier tube.

7. A control circuit for suppressing light-load turn-off stress of a synchronous rectifier according to claim 6, characterized in that: When the power failure signal is not present: The trigger is also used to determine the control module output terminal level based on the control module data terminal level, the control module drive terminal level and the control module set terminal level; The switch tube is also used to generate a release signal based on the level of the output terminal of the control module, so as to enable the main control module to continue the original working state based on the release signal.

8. A control circuit for suppressing light-load turn-off stress of a synchronous rectifier according to claim 6, characterized in that: The PWM shutdown control module further includes a pull-up resistor, an input end of the pull-up resistor is electrically connected to the initial resistor input end, and an output end of the pull-up resistor is electrically connected to the trigger data end.

9. A control circuit for suppressing light-load turn-off stress of a synchronous rectifier according to claim 6, characterized in that: The PWM shutdown control module further includes a protection resistor, a first end of the protection resistor is electrically connected to the trigger output end, and a second end of the protection resistor is electrically connected to the switch tube receiving end.

10. A control circuit for suppressing light-load turn-off stress of a synchronous rectifier according to claim 6, characterized in that: The PWM shutdown control module further includes a NOT gate, wherein: The NOT gate output end is electrically connected to the trigger driving end, and the NOT gate receiving end serves as the PWM shutdown control module receiving end, and is used to be electrically connected to the main control module clock output end; The NOT gate is used to receive and invert a clock signal to generate a driving signal, so as to determine the driving terminal level of the control module based on the driving signal.

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