Tag with advanced clock extraction function
By introducing new clock extraction stages and threshold adaptation circuits into the receiver, the problem that the receiver in the prior art cannot provide a stable internal clock signal when receiving antenna signal distortion is solved, and robust and stable clock signal extraction is achieved to ensure the correctness and timeliness of data processing.
Patent Information
- Application Number
- CN202411717120.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-27
- Filing Date
- 2024-11-27
- Publication Date
- 2025-05-27
AI Technical Summary
The prior art receivers cannot provide a robust and stable internal clock signal when receiving antenna signal distortion, resulting in incorrect and untimely data processing.
By introducing a new clock extraction stage in the receiver, which uses both the first received signal and the second received signal and defines three threshold levels to ensure that the internal clock signal can be extracted stably when the distorted signal is received. The clock extraction stage further includes a threshold adaptation circuit for adjusting the threshold level to adapt to changes in the signal.
It realizes that the robust and stable internal clock signal can still be provided when the antenna signal is distorted, ensuring the correctness and timeliness of data processing.
Smart Images
Figure CN120049916A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a receiver, which is exposed to a magnetic field having a specified carrier frequency in an RF frequency region and is constructed to extract an internal clock signal for processing data with a receiver IC of the receiver, the receiver comprising: an antenna, which is constructed to receive an antenna signal; and a tuning circuit, which is constructed to provide a first reception signal at a first pin of the receiver IC and a second receiver signal at a second pin of the receiver IC, the receiver IC comprising: an acquisition stage, which is constructed to rectify a differential reception signal provided between the first pin and the second pin of the receiver IC and is constructed to provide a supply voltage for the receiver IC with a ground potential as a reference; a clock extraction stage, which is constructed to provide a first threshold level to switch an internal clock signal having a rectangular signal shape between a high potential and a low potential. Background Art
[0002] Known radio frequency identification communication systems use integrated circuits such as the ST25R3916 in an RFID reader or transmitter to communicate with an active or passive receiver. In a typical application, a passive receiver (such as a transponder or tag) stores item identification information of the item to which it is connected, and a transmitter (such as a reader) is used to obtain the item information. The transmitter is powered and generates a magnetic radio frequency field that is emitted by its antenna. When the transmitter and tag are close to each other, the radio frequency field generated by the transmitter is induced into the tag's antenna and used to power the passive tag. The tag also has a transceiver that receives signals from the reader and sends the response back to the transmitter as a load modulated receiver data signal.
[0003] There are various standards such as ISO / IEC18000-3 or ISO / IEC 14.443 Class A and Class B or ISO15.693 or ECMA-340 13.56MHz Near Field Communication (NFC) or NFC Forum, or company standards such as Sony's Felica that define the protocols and modulation types used to transmit information between tags and readers. Some or all of these standards define the use of amplitude modulation to transmit an amplitude modulated data signal with digital data within an RF field over the air to a tag. For example, ISO14.443 Class A also defines the use of modified Miller coding to encode the data signal into an encoded data signal for transmission.
[0004] Figure 1 A system 1 of a reader 2 and a passive tag 3 according to the prior art is disclosed in a symbolic manner, which is simplified to the stages relevant to the present invention. The reader 2 comprises a reader IC 4, which processes the communication data and is connected to a tuning circuit 5 and an antenna 6 to transmit a NFC (Near Field Communication) resonant frequency f having a frequency of 13.56 MHz. resThe tag 3 is a receiver exposed to the magnetic field of the reader 2 and is constructed to extract an internal clock signal CLK for processing communication data with the receiver IC 7 of the tag 3. The tag 3 also includes an antenna 8, which is constructed to receive an antenna signal AS at two antenna connections and provide it to a tuning circuit 9, the size of which is designed to receive the antenna AS in resonance to provide a first received signal RS1 at a first pin 10 of the receiver IC 7 and a second receiver signal RS2 at a second pin 11 of the receiver IC 7. Although Figure 1 The other connections in are shown symbolically with only one line, but the connection from the tuning circuit 8 to the receiver IC 7 is shown as two separate connections to explain in detail the processing of the receiver signal RS for generating the internal supply voltage VDD and the internal clock signal CLK.
[0005] The receiver IC 7 comprises a collection stage 12 which is designed to rectify a differential reception signal U provided between a first pin 10 and a second pin 11 of the receiver IC 7. DIF (U DIF =U RS1 -U RS2 ),like Figure 2 The acquisition stage 12 includes a full-wave rectifier 13 and an amplifier 14, and is constructed to provide a supply voltage VDD referenced to the ground potential GND for the receiver IC 7. The supply voltage VDD can be fixed at 5V or 3V, which are just two examples.
[0006] The receiver IC 7 further comprises a data processing stage 15, which is provided with a supply voltage VDD and an internal clock signal CLK, and is connected to a first pin 10 to receive a first received signal RS1, and to a second pin 11 to receive a second received signal RS2. The data processing stage 15 is constructed to demodulate data received from the reader 2 in the magnetic field, and is constructed to process these received data and modulate the magnetic field using load modulation to transmit the data back to the reader 2.
[0007] The receiver IC 7 further comprises a clock extraction stage 16 and a PLL (Phase Locked Loop) stage 17 according to the prior art. The clock extraction stage 6 is constructed to store, provide and use a first threshold level TH to switch an internal clock signal CLK having a rectangular signal shape between a high potential (e.g. 1.5V) and a low potential (e.g. 0V). Figure 2 The middle time diagram of FIG. 1 shows the voltage U of the first received signal RS1 based on the ground potential GRD. RS1 and the voltage U of the second received signal RS2 based on the ground potential GRD RS2 The clock extraction stage 16 is constructed to use the voltage U of the first received signal RS1 RS1To switch Figure 2 The internal clock signal CLK shown in the lower timing diagram of FIG. Other prior art clock extraction stages are known to use a voltage U of the second received signal RS2 having a first threshold level TH. RS2 To switch the internal clock signal CLK. But always only two voltages U RS1 and U RS2 one of the.
[0008] A disadvantage of this prior art receiver 3 with clock extraction stage 16 is that it is not robust to any kind of distortion of the antenna signal AS, which may lead, as an example, to Figure 3 The first receiving signal RS1, the second receiving signal RS2 and the differential receiving signal U shown in DIF These distortions may occur due to the interaction of the tuning circuit 9 with the full-wave rectifier 13, or if the antenna 8 is exposed to a weak magnetic field, when the coupling between the antenna 6 of the reader 2 and the antenna 8 of the tag 3 is poor. Figure 3 As shown in the middle time diagram, the voltage U of the first received signal RS1 RS1 The distortion of the second pulse results in two short internal clock signal CLK pulses, such as Figure 3 In addition, the high and low time periods of the internal clock signal CLK provided by the clock extraction stage 16 are different. The PLL stage 17 will not be able to lock into such a signal provided by the clock extraction stage 16. As a result, the data processing stage 15 will not be able to process data in a correct and / or timely manner using such an internal clock signal CLK. Summary of the invention
[0009] The object of the present invention is to provide a receiver having a clock extraction stage which provides a robust and stable internal clock signal even in case of distortion of the received antenna signal. This object is achieved by a receiver further comprising a clock extraction stage as claimed in claim 1.
[0010] The clock extraction stage of the present invention uses both the first received signal and the second received signal and defines three threshold levels to enable robust extraction of the internal clock signal. Only a logical combination of two of the three threshold levels can ensure the preservation criteria of setting the internal clock signal (switching from a low potential to a high potential) and resetting the internal clock signal (switching from a high potential to a low potential). The details of this logical combination will be explained in the description of the embodiment shown in the accompanying drawings.
[0011] Furthermore, it is advantageous, and in some implementations even desirable, to adjust two of the three threshold levels with a threshold adaptation circuit to account for varying peak amplitudes of the received signal distorting the antenna signal. Specific time constants are used to continuously track two of the three thresholds.
[0012] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.It will be appreciated by those skilled in the art that the various embodiments may be combined. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 A receiver with a clock extraction stage according to the prior art is shown.
[0014] Figure 2 Shows good quality received signal and Figure 1 The clock extraction stage of the prior art extracts the internal clock signal.
[0015] Figure 3 shows the distorted received signal and the Figure 1 The prior art clock extraction stage extracts an internal clock signal of poor quality.
[0016] Figure 4 An embodiment of a receiver IC of a clock extraction stage according to the present invention is shown.
[0017] Figure 5 Show Figure 4 Example signals of how the clock extraction stage of an MCU sets and resets the internal clock signal.
[0018] Figure 6 Show Figure 4 The first computer simulated signal of how the clock extraction circuit sets and resets the internal clock signal even when receiving antenna signals with distortion.
[0019] Figure 7 Shown by Figure 1 The clock extraction circuit of the prior art extracts the internal clock signal and Figure 4 The clock extraction circuit of the present invention extracts the internal clock signal for comparison with the second computer simulated signal. DETAILED DESCRIPTION
[0020] Figure 4 The clock extraction stage 18 of the receiver 19 is shown, which is exposed to a magnetic field having a specified carrier frequency in the RF frequency region and is constructed to extract an internal clock signal CLK for processing data using a receiver IC 20 of the receiver 19. Figure 1The explanation of the prior art receiver 3 in FIG. 1 is omitted because all the circuits and stages disclosed and explained therein with the same technical functions will be used to illustrate the receiver 19 of the present invention. The receiver 19 of the present invention differs from the prior art receiver 3 in that Figure 4 The concept of the clock extraction stage 18 shown in FIG. 1 is shown in FIG. 1 , and the clock extraction stage 18 includes a first input pin 21 connected to the first pin 10 of the receiver IC 20 , and includes a second output pin 22 connected to the second input pin 11 of the receiver IC 20 .
[0021] The clock extraction stage 18 is constructed to provide a first threshold level TH1 to switch the internal clock signal CLK having a rectangular signal shape between a high potential and a low potential, thereby setting and resetting the internal clock signal CLK. The clock extraction stage 18 is also constructed to provide a second threshold level TH2 and a low threshold level THL, which is closer to the ground potential GRD than the first threshold level TH1 and the second threshold level TH2. The clock extraction stage 18 is constructed so that if the voltage U of the first received signal RS1 referenced to the ground potential GRD RS1 The voltage U of the second receiving signal RS2 is higher than or exceeds the first threshold level TH1 and is based on the ground potential GRD. RS2 The clock extraction stage is also constructed such that if the voltage U of the first received signal RS1 referenced to the ground potential GRD is lower than or less than the low threshold level THL, the internal clock signal CLK is switched from a low potential to a high potential (setting CLK). RS1 The voltage U of the second receiving signal RS2 is lower than or less than the low threshold level THL and is based on the ground potential GRD. RS2 If the internal clock signal CLK is higher than or exceeds the second threshold level TH2, the internal clock signal CLK is switched from a high potential to a low potential (CLK is reset). The logic of setting and resetting the internal clock signal CLK is shown in the following table:
[0022] condition Internal clock signal CLK <![CDATA[(U RS1 >U TH1 ) and (U RS2 <U THL )]]> set up <![CDATA[(U RS2 >U TH2 ) and (U RS1 <U THL )]]> Reset
[0023] Figure 4 A specific implementation of the logic is shown using six inverters 23 to 28, two NAND gates 29 and 30, a flip-flop 31 and a buffer 32 to set and reset the internal clock signal CLK. Figure 5 The function of this embodiment is explained by referring to the first received signal RS1 and the second received signal RS2 shown in FIG. 1 and the internal clock signal CLK extracted therefrom.
[0024] The clock extraction stage 18 further includes a threshold adaptation circuit 33 which is configured to adjust the threshold value if the peak voltage U PEEK RS1The first threshold level TH1 is adjusted over time and / or is constructed such that if the peak voltage U of the second received signal RS2 PEEK RS2 As time goes by, the second threshold level TH2 is adjusted. Figure 5 As shown, the actual peak voltage U of these received signals RS PEEK It is the highest peak value of the amplitude during the past cycle of the received signal RS.
[0025] In order to adjust the first threshold level TH1, the threshold adaptation circuit 33 is constructed so that if the actual peak voltage U PEEK RS1 The actual voltage U is higher than the first threshold level TH1 TH1 Adding a fixed first voltage P1, the voltage U of the first threshold level TH1 is TH1 Increased to a value higher than the actual peak voltage U of the first received signal RS1 PEEK RS1 The fixed first voltage P1 and / or the fixed second voltage P2 may be, for example, 0.1V or 0.3V or 0.5V or 0.75V or 1V, and ensure that the voltage U of the first threshold level TH1 TH1 is lower than the peak voltage U of the first received signal RS1 PEEK RS1 , and the voltage U of the second threshold level TH2 TH2 is lower than the peak voltage U of the second received signal RS2 PEEK RS2 ,like Figure 5 shown. Figure 5 The voltage U increasing the first threshold level TH1 is shown in TH1 mechanism, in which the first threshold level TH1 continuously adjusts the voltage U TH1 The dashed line is parallel to the peak voltage U at a fixed distance from the first voltage P1. PEEK RS1 Similarly, the threshold adaptation circuit 33 is constructed so that if the actual peak voltage U PEEK RS2 The actual voltage U is higher than the second threshold level TH2 TH2 Adding a fixed second voltage P2, the voltage U of the second threshold level TH2 is TH2 Increased to a value higher than the actual peak voltage U of the second received signal RS2 PEEK RS2 The mechanism ensures that if the magnetic field becomes stronger as the amplitude of the first reception signal RS1 and the second reception signal RS2 increases, the first threshold level TH1 and the second threshold level TH2 increase.
[0026] The threshold adaptation circuit 33 is also constructed to continuously reduce the first threshold level TH1 and the second threshold level TH2 based on a time constant. For each threshold level, the time constant can be implemented by an RC stage in the threshold adaptation circuit 33, wherein the peak voltage U PEEK RS For loading a capacitor, the capacitor is unloaded over time at an ohmic resistor. Figure 5 This unloading is shown, which reduces and thus adjusts the voltage U of the first threshold level TH1. TH1 And adjust the voltage U of the second threshold level TH2 TH2 This ensures that if the magnetic field becomes weaker as the amplitude of the first received signal RS1 and the second received signal RS2 becomes smaller, the first threshold level TH1 and the second threshold level TH2 decrease over time. The time constant for the continuous decrease of the threshold level must be selected based on the clock frequency of the internal clock signal CLK and the reaction speed of the threshold level to the peak amplitude / voltage changes of the received signals RS1 and RS2.
[0027] The functionality of the implementation of the clock extraction stage 18 will now be explained. The first received signal RS1 is input to the clock extraction stage 18 at the first input pin 21 and is provided to the inverter 23 and the inverter 26 and the threshold adaptation circuit 33. The second received signal RS2 is input to the clock extraction stage 18 at the second input pin 22 and is provided to the inverter 24 and the inverter 25 and the threshold adaptation circuit 33. The threshold adaptation circuit 33 evaluates the voltage U of the first threshold level TH1. TH1 and the voltage U of the second threshold level TH2 TH2 , as described above, and continue to increase and decrease the voltage, such as Figure 5 Inverter 25 and inverter 26 together with NAND gate 30 realize the logic equation (U RS1 >U TH1 )AND(U RS2 <U THL ) to set the internal clock signal CLK. In addition, inverter 23 and inverter 24 together with NAND gate 29 realize the logic equation (U RS2 >U TH2 )AND(U RS1 <U THL ) to reset the internal clock signal CLK. The inverters 27 and 28 supplied with VDD will depend on the change voltage U of the threshold levels TH1 and TH2. TH1 and U TH2The output voltage levels of the inverters 24 and 26 are converted to voltages of logic levels used in the clock extraction circuit 18. The set and reset output voltages of the NAND gates 29 and 30 are used to set or reset a flip-flop 31, and a buffer 32 amplifies the current output level of the flip-flop 31 to provide an internal clock signal CLK at the output pin of the clock extraction stage 18.
[0028] Figure 5 This embodiment of the clock extraction stage 18 shows how to set and reset the internal clock signal CLK. At time point t1, the condition (U RS1 >U TH1 )AND(U RS2 <U THL ), and sets the internal clock signal CLK. At time point t2, the first receiver signal RS1 and the second receiver signal RS2 have distortion, but no condition for setting or resetting the internal clock signal CLK is given, which enables a robust internal clock signal CLK. At time point t3, the condition (U RS2 >U TH2 )AND(U RS1 <U THL ) and reset the internal clock signal CLK.
[0029] Figure 6 Show Figure 4 The clock extraction circuit 18 sets and resets the first computer simulated signal of the internal clock signal CLK even with the distorted first received signal RS1 and the distorted second received signal RS2. Figure 6 The upper time diagram shows the voltage U of the first received signal RS1 RS1 and the voltage U of the second received signal RS2 RS2 , both signals are distorted, Figure 6 The lower timing diagram of exemplifies the internal clock signal CLK extracted by the clock extraction circuit 18 . Figure 6 The middle and lower parts of the timing diagram show the input signals of NAND gates 29 and 30, where the logic equation (U RS1 >U TH1 ) and (U RS2 THL ) and (U RS2 >U TH2 ) and (U RS1 THL ) is used to set or reset the internal clock signal CLK. At time point t1, the condition (U RS1 >U TH1 )AND(U RS2 <U THL ) and sets the internal clock signal CLK. At time point t2, the condition (URS2 >U TH2 )AND(U RS1 THL ), and reset the internal clock signal CLK. Figure 6 As shown, the voltage U of the receiving signal RS1 and RS2 RS1 and U RS2 There are several distortions, but the internal clock signal CLK is stable and of high quality.
[0030] Figure 7 Shown by Figure 1 The prior art clock extraction circuit 16 and Figure 4 The clock extraction circuit 18 of the present invention extracts the internal clock signal CLK for comparison with the second computer simulated signal. Figure 7 The upper time diagram shows the voltage U of the first received signal RS1 RS1 and the voltage U of the second received signal RS2 RS2 , both signals are distorted. Figure 7 The middle part of the timing diagram shows the robust and correct internal clock signal CLK extracted by the clock extraction circuit 18 of the present invention. Figure 7 The lower part of the timing diagram shows the internal clock signal CLK extracted by the clock extraction circuit 16 of the prior art, in which there is only one threshold level U TH , and there are several clock failures.
[0031] Furthermore, the receiver 19 advantageously comprises a PLL stage 17 connected to the output of the clock extraction stage 18 in order to improve the quality of the internal clock signal CLK extracted by the clock extraction circuit 18 of the invention.
[0032] The above-mentioned RF frequency region must be understood as covering the frequency region from kHz to GHz.
Claims
1. A receiver (19) exposed to a radio frequency having a specified carrier frequency (f res ) and is configured to extract an internal clock signal (CLK) for processing data by a receiver IC (20) of the receiver (19), the receiver (19) comprising: an antenna (8) configured to receive an antenna signal (AS); and a tuning circuit (9) configured to provide a first received signal (RS1) at a first pin (10) of the receiver IC (20) and a second received signal (RS2) at a second pin (11) of the receiver IC (20), the receiver IC (20) comprising: The acquisition stage (12) is constructed to receive a differential reception signal (U) provided between a first pin (10) and a second pin (11) of the receiver IC (20). DIF ) is rectified and configured to provide a supply voltage (VDD) for the receiver IC (20) with reference to a ground potential (GRD); A clock extraction stage (18) constructed to provide a first threshold level (TH1) for switching an internal clock signal (CLK) having a rectangular signal shape between a high potential and a low potential, characterized in that The clock extraction stage (18) is constructed to provide a second threshold level (TH2) and to provide a low threshold level (THL), wherein the low threshold level (THL) is closer to a ground potential (GRD) than the first threshold level (TH1) and the second threshold level (TH2), and the clock extraction stage (18) is constructed to, If the voltage (U RS1 ) is higher than or exceeds the first threshold level (TH1) and the voltage (U) of the second received signal (RS2) is referenced to the ground potential (GRD) RS2 ) is lower than or less than the low threshold level (THL), the internal clock signal (CLK) is switched from a low potential to a high potential, and the clock extraction stage (18) is constructed as follows, If the voltage (U RS1 ) is lower than or less than the lower threshold level (THL) and is based on the ground potential (GRD) as the reference of the second receiving signal (RS2) voltage (U RS2 ) is higher than or exceeds the second threshold level (TH2), the internal clock signal (CLK) is switched from a high potential to a low potential.
2. The receiver (19) according to claim 1, wherein: The receiver IC (20) includes a threshold adaptation circuit (33) configured to: PEEKRS1 ) changes over time, adapting the first threshold level (TH1), and / or adapting the second threshold voltage (TH2) if the second received signal (RS2) changes over time.
3. The receiver (19) according to claim 2, wherein: The threshold adaptation circuit (33) is constructed so that if the actual peak voltage (U PEEKRS1 ) is higher than the actual voltage (U TH1 ) plus a fixed first voltage (P1), the voltage (U TH2 ) increases to a value greater than the actual peak voltage (U PEEKRS1 ) is lower than the fixed first voltage (P1), and / or wherein the threshold adaptation circuit (33) is constructed so that if the actual peak voltage (U PEEKRS2 ) is higher than the actual voltage (U TH2 ) plus a fixed second voltage (P2), the voltage (U TH2 ) increases to a value greater than the actual peak voltage (U PEEKRS2 )lower the fixed second voltage (P2).
4. A receiver (19) according to claim 2 or 3, wherein: The threshold adaptation circuit (33) is constructed to continuously reduce the voltage (U) of the first threshold level (TH1) based on a time constant. TH1 ) and / or the voltage (U TH2 ).
5. The receiver (19) according to any one of claims 1 or 4, wherein: The low threshold level (THL) is fixed and is not adjusted over time.
6. The receiver (19) according to any one of claims 2 to 5, wherein: The clock extraction stage (18) is implemented with a first threshold inverter (26) to observe the first threshold level (TH1), the first threshold inverter (26) being connected via its input to the first pin (10) of the receiver IC (20) and connected via its supply to the first threshold level (TH1) referenced to a ground level (GRD) and / or the clock extraction stage (18) is implemented with a second threshold inverter (24) to observe the second threshold level (TH2), the second threshold inverter (24) being connected via its input to the second pin (11) of the receiver IC (20) and connected via its supply to a voltage (U) at the second threshold level (TH2) referenced to the ground level (GRD). TH2 ).
7. The receiver (19) according to any one of claims 1 to 6, wherein: The receiver (18) comprises a PLL stage (17) connected to the output of the clock extraction stage (18).
8. The receiver (19) according to any one of claims 1 to 7, wherein: The antenna (8) and the tuning circuit (9) are configured to receive a system-defined NFC resonant frequency (f res )'s carrier frequency.