An interrupt device and an interrupt reporting method

Abstract

The application provides an interrupt device and an interrupt reporting method. The device comprises a timer, an expiration register, at least one storage unit and an interrupt adjustment mechanism timing logic unit. The at least one storage unit is used for storing expiration trigger values of all interrupt timing trigger events bound to an interrupt vector and scanning timing values. The interrupt adjustment mechanism timing logic unit is used for scanning the at least one storage unit once every time the timer timing meets a scanning period, and when the expiration trigger value of the interrupt timing trigger event is greater than 0, the corresponding scanning timing value is added by 1. If the scanning timing value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set as a first setting value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported. The first setting value indicates that the interrupt timing trigger event has expired.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of network communication, and particularly relates to an interrupt device and an interrupt reporting method. BACKGROUND

[0002] A high-speed network card implements data receiving and sending in the manner of reporting interrupts to a host. MSI-X (Message Signaled Interrupts eXtended, a kind of interrupt mechanism in PCIE specification) can reach thousands in the MSI-X capability structure of PCI configuration space, and triggers interrupts to the host in series with interrupt vectors. SUMMARY

[0003] The present application aims to provide an interrupt device and an interrupt reporting method, and aims to solve the technical problems of excessive register bit width of an expiration trigger value, excessive area of an adapter, and high requirements of middle and back end timing convergence and layout routing.

[0004] According to a first aspect of the present application, an interrupt device is provided, comprising a timer, an expiration register, at least one storage unit, and an interrupt adjustment mechanism timing logic unit.

[0005] The at least one storage unit is configured to store expiration trigger values of all interrupt timing trigger events bound to interrupt vectors and scan timing values.

[0006] The interrupt adjustment mechanism timing logic unit is configured to scan the at least one storage unit once after each scan period of the timer, and if the expiration trigger value of the interrupt timing trigger event is greater than 0, the corresponding scan timing value is increased by 1, and if the scan timing value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set to a first setting value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported. The first setting value indicates that the interrupt timing trigger event has expired.

[0007] In an optional embodiment, the interrupt adjustment mechanism timing logic unit resets the corresponding scan timing value to 0 after setting the value in the expiration register to the first setting value.

[0008] In an optional implementation, the interrupt adjustment mechanism timing logic unit does not add 1 to the scan timing value if the value of the expiration register corresponding to the interrupt timing trigger event is the first set value and the scan timing value is 0 in the subsequent scan, and continues to add 1 to the scan timing value if the value of the expiration register corresponding to the interrupt timing trigger event becomes the second set value; the second set value indicates that the interrupt timing trigger event is not expired.

[0009] In an optional implementation, all the interrupt timing trigger events share one timer; the bit width of the timer is greater than the maximum bit width in the scan timers of all the interrupt timing trigger events.

[0010] In an optional implementation, the interrupt device further comprises an interrupt vector register, a mapping register, an interrupt source record logic unit register and an interrupt vector logic unit;

[0011] The interrupt vector register is configured to store an interrupt enable signal of each interrupt vector;

[0012] The mapping register is configured to store an interrupt vector number bound by each interrupt event and an index number of an interrupt timing trigger event;

[0013] After receiving an interrupt event, the interrupt vector number bound by the interrupt event and the index number of the interrupt timing trigger event are queried from the mapping register, and the interrupt vector number and the index number of the interrupt timing trigger event are recorded in the interrupt source record logic unit register;

[0014] The interrupt vector logic unit is configured to report the interrupt vector corresponding to the interrupt timing trigger event to a host when the value of the expiration register of the interrupt timing trigger event is the first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the interrupt source record logic unit register.

[0015] In an optional implementation, after reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the interrupt adjustment mechanism timing logic unit sets the value in the expiration register of all the interrupt timing trigger events corresponding to the interrupt vector to the second set value.

[0016] According to a second aspect of the present application, an interrupt reporting method is provided, comprising:

[0017] The method further comprises: after detecting that the timer of the interrupt device reaches a scan period, triggering the interrupt adjustment mechanism timer logic unit of the interrupt device to scan at least one storage unit of the interrupt device; the at least one storage unit stores expiration trigger values of all interrupt timing trigger events bound to an interrupt vector and scan timer values;

[0018] If the expiration trigger value of one of the interrupt timing trigger events is greater than 0, the corresponding scan timer value is increased by 1;

[0019] If the scan timer value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set to a first setting value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported; the first setting value indicates that the interrupt timing trigger event has expired.

[0020] In an optional embodiment, after the value in the expiration register corresponding to the interrupt timing trigger event is set to the first setting value, the method further comprises:

[0021] The interrupt adjustment mechanism timer logic unit clears the scan timer value corresponding to the interrupt timing trigger event.

[0022] In an optional embodiment, in the next scan period, the method further comprises:

[0023] If the value in the expiration register corresponding to the interrupt timing trigger event is the first setting value and the corresponding scan timer value is 0, the interrupt adjustment mechanism timer logic unit does not increase the scan timer value by 1; if the value in the expiration register corresponding to the interrupt timing trigger event changes to a second setting value, the interrupt adjustment mechanism timer logic unit continues to increase the scan timer value by 1; the second setting value indicates that the interrupt timing trigger event has not expired.

[0024] In an optional embodiment, all the interrupt timing trigger events share the timer; the bit width of the timer is greater than the maximum bit width of the scan timers of all the interrupt timing trigger events.

[0025] In an optional embodiment, the method further comprises:

[0026] After receiving an interrupt event, the interrupt vector number and the index number of the interrupt timing trigger event bound to the interrupt vector are queried from the mapping register of the interrupt device, and the interrupt vector number and the index number of the interrupt timing trigger event are recorded in the interrupt source recording logic unit register of the interrupt device;

[0027] The interrupt vector logic unit of the interrupt device detects that the value of the expiration register of the interrupt timing trigger event is a first set value, and the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the interrupt source record logic unit register, and reports the interrupt vector corresponding to the interrupt timing trigger event to the host.

[0028] In an optional implementation, after the interrupt vector corresponding to the interrupt timing trigger event is reported to the host, the method further comprises:

[0029] The interrupt adjustment mechanism timing logic unit sets the value in the expiration register of all interrupt timing trigger events corresponding to the interrupt vector to a second set value.

[0030] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0031] With the increasing demand of high-speed network cards for the number of ITRs or the number of interrupt vectors, the number of expiration trigger values of ITRs also increases. If a register is used to store the expiration trigger values of ITRs, assuming that there are 2k interrupt vectors, 3 ITRs share the same interrupt vector, and all ITRs share a 16-bit timer, the total bit width of the ITR trigger values is nearly 10k (2k x 3 x 16). With the increasing demand of the same interrupt vector for the number of ITRs, the total bit width of the ITR trigger values will far exceed 10k. The huge register bit width will bring great challenges to the area of the adapter. The use of the present application can greatly reduce the area of the adapter. In addition, the use of the present application can reduce the chip resource occupation and power consumption. It can be observed by the number of instances after synthesis, which is conducive to the timing convergence and wiring of the middle and back ends.

[0032] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and obtained by the structures and processes indicated in the specification and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiment or related art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative labor.

[0034] Figure 1 It is a structure block diagram of the interrupt device according to the exemplary embodiment of the present application.

[0035] Figure 2 is a schematic diagram of a storage unit storing data according to an example embodiment of the present application.

[0036] Figure 3A is a schematic diagram of a scanning effect of a storage unit according to an example embodiment of the present application.

[0037] Figure 3B is a schematic diagram of a scanning state of a storage unit according to an example embodiment of the present application.

[0038] Figure 4 is a schematic diagram of a system structure of a host reporting an interrupt vector according to an example embodiment of the present application.

[0039] Figure 5 is a schematic diagram of a flow of a method of reporting an interrupt according to an example embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0041] In a high-speed network card, multiple ITRs (Interrupt throttling) share the same interrupt vector, all the ITRs are separately timed, each ITR corresponds to a separate ITR expiration trigger value, and parallel timing is realized by register storage.

[0042] Timing of all the ITRs (assuming a total of N) sharing the same interrupt vector is realized by sharing one timer (bit width M), and the expiration trigger value of each ITR is: expiration trigger value = current timer value + (ITR interval x time granularity). ITR interval x time granularity is the timing time of the ITR, so the total bit width of the registers of the expiration trigger values of all the ITRs is N x M, and the ITR expires when the value of the timer is equal to the expiration trigger value of the ITR.

[0043] The above related technologies have the following problems:

[0044] With the increasing demand of high speed network card on the number of ITR or the number of interrupt vectors, the number of expiration trigger values of ITR also increases. If the expiration trigger values of ITR are stored in registers, assuming that there are 2k interrupt vectors, 3 ITRs share the same interrupt vector, and the timer shared by all ITRs is 16 bits, then the total bit width of the expiration trigger values of ITR is 2k×3×16, which is close to 10k. With the increasing demand of the same interrupt vector on the number of ITR, the total bit width of the expiration trigger values of ITR will exceed 10k, and the huge register bit width of the expiration trigger values will bring great challenges to the area of the adapter. At the same time, the huge bit width of the ITR expiration trigger values caused by the sharp increase in the number of ITR will also bring great challenges to the timing convergence and layout routing of the middle and back end.

[0045] Therefore, the application proposes a scheme for storing ITR related information by using RAM. In the scheme, each ITR no longer depends on the expiration trigger value of ITR and the value of the current timer to determine whether the ITR is expired. The RAM is scanned and read once every tus, and when the scan reading interval cnt of the ITR is the expiration trigger value ITR interval, it means that the ITR is expired. At this time, the hardware clears 0 the interval cnt of the ITR, and sets the expiration identifier ITR_time_out in the expiration register of the ITR to 1. When the subsequent scan reading is performed, if the interval cnt of the ITR is 0, and the ITR_time_out is 1, it means that the ITR is in the expiration state and waits for the interrupt event, and the interval cnt of the ITR is not operated. If the ITR_time_out is 0, it means that the interrupt has been reported and needs to be re-timed, and the operation of adding 1 to the interval cnt of the ITR is started.

[0046] Since all ITRs share one timer, the bit width of the timer depends on the maximum ITR interval value corresponding to all ITRs, so the value of the timer must be greater than the maximum ITR interval value × time granularity, and the bit width of the timer must be greater than the maximum bit width of the ITR interval cnt value. Assuming that the total bit width of the storage of the ITR interval cnt values of all interrupt vectors (N) is W, and the bit width of the timer for timing the ITR interval values of N ITRs is M, the total bit width of the storage of the ITR interval cnt values and the ITR interval values in the related art is W+N×M. After the register is replaced by RAM in the application, the actual bit width is 2W, and since 2W<<W+N×M, the application obviously effectively reduces the area of the adapter.

[0047] As Figure 1As shown, the present application exemplarily proposes an interrupt device, comprising: a timer, an expiration register, at least one storage unit and an interrupt adjustment mechanism timing logic unit;

[0048] The at least one storage unit is used to store expiration trigger values of all interrupt timing trigger events bound to an interrupt vector and scan timing values;

[0049] The interrupt adjustment mechanism timing logic unit is used to scan the at least one storage unit once after the timer timing meets a scan period, and if the expiration trigger value of the interrupt timing trigger event is greater than 0, the corresponding scan timing value is added by 1, and if the scan timing value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set as a first setting value, so that after the interrupt event comes, the interrupt vector corresponding to the interrupt timing trigger event is reported. The first setting value indicates that the interrupt timing trigger event has expired.

[0050] Exemplarily, all interrupt timing trigger events (described as ITR in the present application for the convenience of understanding) of the interrupt device share one timer, each interrupt timing trigger event corresponds to an expiration register, which is used to store the value ITR_time_out indicating whether the interrupt timing trigger event has expired, the ITR_time_out is the first setting value such as 1, indicating that the ITR has expired, and if the ITR_time_out is the second setting value such as 0, indicating that the ITR has not expired.

[0051] Exemplarily, one interrupt vector can bind one or more interrupt timing trigger events, each interrupt timing trigger event corresponds to an expiration trigger value ITR interval and a scan timing value ITR interval cnt. One storage unit RAM can store the expiration trigger value ITR interval and the scan timing value ITR interval cnt of all interrupt timing trigger events bound by one interrupt vector.

[0052] Exemplarily, the timer interrupts the adjustment mechanism timing logic unit to scan the storage unit every time t us (i.e., one scanning period, which can also be referred to as one time granularity), and the adjustment mechanism timing logic unit continues the next scanning operation after the next scanning period arrives. During one scanning operation, if the expiration trigger value of the interrupt timing trigger event is greater than 0, the scanning timing value of the interrupt timing trigger event (the initial value of the scanning timing value is 0) is increased by 1. After the scanning timing value is increased by 1, if the scanning timing value is equal to the expiration trigger value, it indicates that the interrupt timing trigger event expires, and at this time, the value in the expiration register corresponding to the interrupt timing trigger event can be set to a first setting value, such as 1. In this way, after the corresponding hardware detects that the value in the expiration register is the first setting value, it can be determined that the corresponding interrupt timing trigger event has expired, and thus whether to report the interrupt vector corresponding to the interrupt timing trigger event can be determined by determining whether the corresponding interrupt event arrives.

[0053] In some optional embodiments, after the adjustment mechanism timing logic unit sets the value in the expiration register to the first setting value, the corresponding scanning timing value is cleared to 0.

[0054] Exemplarily, after the value in the expiration register is set to the first setting value, it indicates that the interrupt timing trigger event has expired, and then the timing can be restarted, so the scanning timing value can be cleared to 0.

[0055] In some optional embodiments, during the subsequent scanning, if the value in the expiration register corresponding to the interrupt timing trigger event is the first setting value and the corresponding scanning timing value is 0, the scanning timing value is not increased by 1, and if the value in the expiration register corresponding to the interrupt timing trigger event changes to a second setting value, the scanning timing value is continued to be increased by 1; the second setting value indicates that the interrupt timing trigger event does not expire.

[0056] Exemplarily, the adjustment mechanism timing logic unit scans the storage unit every time a scanning period arrives, and during the scanning, if the value in the expiration register corresponding to a certain interrupt timing trigger event is set to the first setting value and the scanning timing value is cleared to 0, it indicates that the interrupt timing trigger event expires and waits for the arrival of the corresponding interrupt event, at this time, the timing can not be performed, so the scanning timing value is not increased by 1. If the value in the expiration register corresponding to the interrupt timing trigger event changes from the first setting value to the second setting value, it indicates that the interrupt event of the interrupt timing trigger event has arrived and has been reported, at this time, the timing can be restarted, so the scanning timing value can be increased by 1.

[0057] In some optional embodiments, all interrupt timing trigger events share one timer; the bit width of the timer is greater than the maximum bit width of the scanning timing value of all interrupt timing trigger events.

[0058] As described above, only one timer can be provided in the present application for timing the scanning period, and no timer needs to be provided for each interrupt timing trigger event.

[0059] The embodiments of the present application are described below taking the process of reporting an interrupt to a host via an interrupt vector as an example.

[0060] As shown in Figure 2 , exemplary, itr0~itrN-1 are N interrupt timing trigger events ITRs bound to one interrupt vector, and intrl cnt and intrl are the scanning timing value ITR interval cnt and the expiration trigger value ITR interval of each interrupt timing trigger event ITR.

[0061] As shown in Figure 2 , exemplary, the data stored in each RAM storage unit contains all ITR interval values (expiration trigger values) of the shared interrupt vector and the scanning timing value interval cnt corresponding to each ITR, and the bit width of the interval cnt value of each ITR is consistent with the interval value.

[0062] As shown in Figure 3A , exemplary, the vertical coordinate is the timing value of the timer shared by all ITRs, which is incremented by 1 every 1us, and the read-write scanning of all ITR RAMs is performed every tus, all RAM addresses correspond to the interrupt vector number, if the number of interrupt vectors is too large, the entire RAM may not be scanned and read-write within the time granularity tus, so the depth of the RAM needs to be split, that is, split into multiple RAMs, so that each RAM can be scanned and read-write in parallel within tus. Since each ITR interval value stored in the RAM needs to be open to software read-write access, the RAM involves software read-write access in addition to the above traversal scanning read-write. As shown in Figure 3B , exemplary, the traversal scanning read operation of the RAM and the read-write access operation of the software can be completed in tus, and the specific interval can be set according to actual needs, which is not limited by the present application, as long as the RAM can be scanned and read-write within tus.

[0063] The time granularity tus is the scanning period of the scanning reading RAM, and the scanning reading is performed on all the split RAMs in parallel. When the ITR interval stored in a certain address is greater than 0, the corresponding ITR interval cnt is increased by 1 and then written into the same address of the RAM. The adjacent beat of the scanning reading is the clock signal of the ITR interval in the RAM when the software reads and writes the ITR interval. When the software initiates a read request, the value of the ITR interval is returned to the software. When the software initiates a write access, the hardware writes the value of the ITR interval carried by the write access into the specified data bit field of the RAM. Each ITR no longer depends on the expiration trigger value of the ITR and the value of the current timer to determine whether the ITR is expired. The RAM is scanned and read once every tus. When the scanning reading is performed on the ITR interval cnt value of the ITR, the ITR interval cnt is cleared to 0 and the value ITR_time_out stored in the ITR expiration register is set to 1. When the interval cnt of the ITR is 0 in the subsequent scanning reading, if the ITR_time_out is 1, the increase by 1 is not performed, which indicates that the ITR is in the expiration state and waits for the interrupt event. If the ITR_time_out is 0, the increase by 1 is started, which indicates that the interrupt vector has been reported and needs to be re-timed.

[0064] All the ITRs share one timer, and the bit width of the timer depends on the maximum ITR interval value. Therefore, the value of the timer must be greater than the maximum ITR interval value x time granularity, and the bit width of the timer must be greater than the maximum bit width of the ITR. Assuming that the total bit width of the storage of the ITR (N) interval cnt values of all the interrupt vectors is W, and the bit width of the timer for timing the N ITR interval values is M, the total bit width of the storage of the ITR interval cnt values and the ITR interval values in the related art is W+NxM. After the register is replaced by the RAM in the present application, the actual bit width is 2W. Since 2W< W+NxM, the present application obviously effectively reduces the adapter area.

[0065] In some optional embodiments, the interrupt device further comprises an interrupt vector register, a mapping register, an interrupt source record logic unit register and an interrupt vector logic unit.

[0066] The interrupt vector register is used to store the interrupt enable signal of each interrupt vector.

[0067] The mapping register is used to store the interrupt vector number bound to each interrupt event and the index number of the interrupt timing trigger event.

[0068] Upon receiving an interrupt event, the interrupt vector number bound to the interrupt event and the index number of the interrupt timer trigger event are queried from the mapping register, and the interrupt vector number and the index number of the interrupt timer trigger event are recorded in the interrupt source record logic unit register;

[0069] The interrupt vector logic unit is configured to report the interrupt vector corresponding to the interrupt timer trigger event to the host when the value of the expiration register of the interrupt timer trigger event is a first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timer trigger event in the interrupt vector register is enabled, and the index number and the corresponding interrupt vector number of the interrupt timer trigger event are recorded in the interrupt source record logic unit register.

[0070] Exemplarily, Figure 4 An example structure of the interrupt device is shown, 101 is an interrupt vector register, used for receiving and storing a software configured interrupt vector enable signal, and the interrupt vector enable signal is 1 to have a condition of reporting an interrupt request, each interrupt vector corresponds to an interrupt vector register. 102 is an interrupt adjustment mechanism timing logic unit, the implementation function is shown in Figure 2 、 Figure 3A 、 Figure 3B .

[0071] 103 is a mapping register, used for storing an interrupt vector number msix ind and an ITR index identifier ITR indx bound to each interrupt event, after the arrival of the interrupt event, the mapping register will first query the content of the mapping register bound to the interrupt event in advance, to determine the interrupt vector number msix ind and the ITR index identifier indx bound to the interrupt event.

[0072] Exemplarily, 104 is an interrupt source record logic unit register of an interrupt vector, used to store the received interrupt event binding interrupt vector number msix indx and ITR index identification indx. The bit width of each interrupt vector is consistent with the number of ITRs bound by the interrupt vector, i.e., eicr[N-1:0], the interrupt device reads the mapping register 103 bound by the interrupt event after receiving the interrupt event, to obtain the ITR indx and msix indx bound by the interrupt event. If there are M interrupt vectors, each of which corresponds to N ITRs, the M interrupt vectors are represented as eicr[M-1:0][N-1:0], if the ITR indx is 1 and the interrupt vector number msix indx is 0, then the interrupt vector eicr[M-1:0][N-1:0] UI corresponds to N'h1. 106 is an interrupt vector logic unit, each interrupt vector will be sent to the host to report the corresponding interrupt request after meeting the following three conditions:

[0073] 1) The interrupt enable signal of the interrupt vector register 101 of the software interrupt vector is 1;

[0074] 2) The value of the expiration register of the ITR bound by the interrupt vector is a first set value, such as 1;

[0075] 3) The interrupt event bound by the interrupt vector is recorded in the interrupt source record logic unit register, and the ITR indx bound by the interrupt event is 1.

[0076] In the case of meeting the above three conditions, the interrupt vector logic unit 105 sends the interrupt vector to the host, and after sending, the interrupt adjustment mechanism timing logic unit clears all ITR_time_out of the interrupt vector corresponding ITR, that is, sets the ITR_time_out corresponding to the interrupt vector to a second set value, such as 0.

[0077] Therefore, in some embodiments, after reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the interrupt adjustment mechanism timing logic unit sets the value in the expiration register of all interrupt timing trigger events corresponding to the interrupt vector to a second set value.

[0078] Exemplarily, after the value in the expiration register returns to the second set value, the interrupt adjustment mechanism timing logic unit can continue to operate the scan timing value corresponding to the interrupt timing trigger event by 1 in the subsequent scan.

[0079] The above interrupt device proposed in the application has at least the following advantages:

[0080] With the increasing demand of high-speed network card on the number of ITR or interrupt vector, the number of expiration trigger value of ITR is also increased. If the register is used to store the expiration trigger value of ITR, assuming that there are 2k interrupt vectors, 3 ITRs share the same interrupt vector, and all ITRs share a 16-bit timer, the total bit width of ITR trigger value is nearly 10k (2k×3×16). With the increasing demand of the same interrupt vector on the number of ITR, the total bit width of ITR trigger value will be far more than 10k. The huge register bit width will bring great challenge to the area of adapter. The application can greatly reduce the area of adapter. In addition, the method of the application can reduce the chip resource occupation and power consumption. The number of instances after synthesis can be observed, which is conducive to the timing convergence and wiring of the middle and back end.

[0081] Correspondingly, as shown in Figure 5 The application exemplarily further provides an interrupt reporting method, comprising:

[0082] In step S501, after detecting that the timing of the timer of the interrupt device reaches a scan period, the interrupt adjustment mechanism timing logic unit of the interrupt device scans at least one storage unit of the interrupt device; the at least one storage unit stores expiration trigger values of all interrupt timing trigger events bound to an interrupt vector and a scan timing value;

[0083] In step S502, if the expiration trigger value of one of the interrupt timing trigger events is greater than 0, the corresponding scan timing value is increased by 1;

[0084] In step S503, if the scan timing value is equal to the expiration trigger value, the value in the expiration register corresponding to the interrupt timing trigger event is set to a first setting value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported; the first setting value indicates that the interrupt timing trigger event has expired.

[0085] In some optional embodiments, after setting the value in the expiration register corresponding to the interrupt timing trigger event to the first setting value, the method further comprises:

[0086] The interrupt adjustment mechanism timing logic unit clears the scan timing value corresponding to the interrupt timing trigger event to 0.

[0087] In some optional embodiments, in the next scan period, the method further comprises:

[0088] If the value of the expiration register corresponding to the interrupt timing trigger event is the first set value, and the corresponding scan timing value is 0, the interrupt adjustment mechanism timing logic unit does not add 1 to the scan timing value, and if the value of the expiration register corresponding to the interrupt timing trigger event becomes the second set value, the scan timing value continues to be added by 1; the second set value indicates that the interrupt timing trigger event is not expired.

[0089] In some optional embodiments, all interrupt timing trigger events share a timer; the bit width of the timer is greater than the maximum bit width among the scan timers of all interrupt timing trigger events.

[0090] In some optional embodiments, the method further comprises:

[0091] After receiving an interrupt event, the interrupt vector number and the index number of the interrupt timing trigger event bound by the interrupt event are queried from the mapping register of the interrupt device, and the interrupt vector number and the index number of the interrupt timing trigger event are recorded in the interrupt source record logic unit register of the interrupt device;

[0092] When the interrupt vector logic unit of the interrupt device detects that the value of the expiration register of the interrupt timing trigger event is the first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the interrupt source record logic unit register, the interrupt vector corresponding to the interrupt timing trigger event is reported to the host.

[0093] In some optional embodiments, after the interrupt vector corresponding to the interrupt timing trigger event is reported to the host, the method further comprises:

[0094] The interrupt adjustment mechanism timing logic unit sets the value in the expiration register of all interrupt timing trigger events corresponding to the interrupt vector to the second set value.

[0095] The above method can be implemented on the interrupt device provided in the above embodiments, and the specific implementation manner can be referred to the description of the interrupt device in the above embodiments, which will not be described here.

[0096] It can be understood that the circuit structure, name and parameter described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to the use needs, and the concept of the present application should not be limited to the specific details of the above examples.

[0097] Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood that modifications can be made to the foregoing embodiments, or additional implementations can be implemented, without departing from the spirit and scope of the embodiments.

Claims

1. An interrupting device characterized by The interrupt device comprises: a timer, an expiration register, at least one storage unit and an interrupt adjustment mechanism timing logic unit; the at least one storage unit is used for storing expiration trigger values of all interrupt timing trigger events bound to an interrupt vector and scanning timing values; the interrupt adjustment mechanism timing logic unit is used for scanning the at least one storage unit once after each scanning period of the timer, and if the expiration trigger value of the interrupt timing trigger event is greater than 0, adding 1 to the corresponding scanning timing value, and if the scanning timing value is equal to the expiration trigger value, setting the value in the expiration register corresponding to the interrupt timing trigger event to a first setting value, so that after the interrupt event arrives, the interrupt vector corresponding to the interrupt timing trigger event is reported; the first setting value indicates that the interrupt timing trigger event has expired; wherein, in the subsequent scanning, if the value in the expiration register corresponding to the interrupt timing trigger event is the first setting value and the scanning timing value corresponding to the interrupt timing trigger event is 0, the scanning timing value is not added by 1, and if the value in the expiration register corresponding to the interrupt timing trigger event becomes a second setting value, the scanning timing value is continuously added by 1; the second setting value indicates that the interrupt timing trigger event has not expired.

2. The interrupting device of claim 1, wherein, After the value in the expiration register is set to the first setting value, the scanning timing value corresponding to the expiration register is cleared to 0.

3. The interrupt device of claim 1, wherein, All the interrupt timing trigger events share one timer; the bit width of the timer is greater than the maximum bit width of the scanning timers of all the interrupt timing trigger events.

4. An interrupting device according to any one of claims 1-3, characterised in that The interrupt device further comprises an interrupt vector register, a mapping register, an interrupt source record logic unit register and an interrupt vector logic unit; the interrupt vector register is used for storing an interrupt enable signal of each interrupt vector; the mapping register is used for storing an interrupt vector number bound by each interrupt event and an index number of an interrupt timing trigger event; after receiving an interrupt event, the interrupt vector number bound by the interrupt event and the index number of the interrupt timing trigger event are inquired from the mapping register, and the interrupt vector number and the index number of the interrupt timing trigger event are recorded in the interrupt source record logic unit register; the interrupt vector logic unit is used for reporting the interrupt vector corresponding to the interrupt timing trigger event to the host when the value in the expiration register of the interrupt timing trigger event is the first setting value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the interrupt source record logic unit register.

5. The interrupting device of claim 4, wherein, After the interrupt vector corresponding to the interrupt timing trigger event is reported to the host, the interrupt adjustment mechanism timing logic unit sets the value in the expiration register of all the interrupt timing trigger events corresponding to the interrupt vector to the second setting value.

6. A method for reporting an interruption, the method comprising: The interrupt device comprises: The method further comprises: If the value of the expiration register corresponding to the interrupt timing trigger event is the first set value and the scan timing value corresponding to the interrupt timing trigger event is 0, the interrupt adjustment mechanism timing logic unit does not add 1 to the scan timing value, and if the value of the expiration register corresponding to the interrupt timing trigger event becomes the second set value, the interrupt adjustment mechanism timing logic unit continues to add 1 to the scan timing value. The second set value indicates that the interrupt timing trigger event has not expired. After setting the value in the expiration register corresponding to the interrupt timing trigger event to the first set value, the method further comprises: The interrupt adjustment mechanism timing logic unit clears the scan timing value corresponding to the interrupt timing trigger event to 0. All of the interrupt timing trigger events share the timer; the bit width of the timer is greater than the maximum bit width of the scan timers of all of the interrupt timing trigger events.

7. The method of reporting interrupts according to claim 6, wherein, The method further comprises: After receiving an interrupt event, the method further comprises:

8. The method of reporting interrupts according to claim 6, wherein, The interrupt vector logic unit of the interrupt device reports the interrupt vector corresponding to the interrupt timing trigger event to the host when the value of the expiration register corresponding to the interrupt timing trigger event is the first set value, the interrupt enable signal of the interrupt vector corresponding to the interrupt timing trigger event in the interrupt vector register is enabled, and the index number of the interrupt timing trigger event and the corresponding interrupt vector number are recorded in the interrupt source record logic unit register.

9. The interrupt reporting method according to any of claims 6-8, characterized by, After reporting the interrupt vector corresponding to the interrupt timing trigger event to the host, the method further comprises: The interrupt adjustment mechanism timing logic unit sets the value in the expiration register corresponding to all of the interrupt timing trigger events of the interrupt vector to the second set value. ​ 10. The method of reporting interrupts according to claim 9, wherein, ​ ​

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