Methods, apparatus, and articles of manufacture for transmitting multiple signals through isolated channels

Abstract

The present disclosure relates to methods, apparatus, and articles of manufacture for transmitting multiple signals over an isolated channel. An example apparatus includes a first die (136) having a first terminal. The apparatus includes a second die (138) having a second terminal. The apparatus includes an isolation channel (240) coupled between the first terminal of the first die (136) and the second terminal of the second die (138). The apparatus includes control circuitry (202) disposed on the first die (136), the control circuitry (202) for transmitting a power signal through the isolation channel (240), and for transmitting a control data signal through the isolation channel (240), and / or for detecting a feedback data signal through the isolation channel (240). Other examples are described.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of and priority to U.S. Provisional Patent Application No. 63 / 605,737, filed on December 4, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present description relates generally to communication systems and, more particularly, to methods, apparatus, and articles of manufacture for transmitting multiple signals over isolated channels. Background Art

[0004] Isolated communication includes data transfer through an isolation barrier. An isolated communication system provides isolation between circuits operating at different voltages on opposite sides of an isolation barrier. An isolated communication system may include multiple passive or active components on either side of an isolation barrier. In some examples, the isolation barrier includes an isolation channel, such as a magnetic channel (e.g., an inductively coupled coil, one or more coreless transformers, etc.) or a capacitive channel. Summary of the invention

[0005] For methods, apparatus, and articles of manufacture for transmitting multiple signals through an isolation channel, an example apparatus includes a first die having a first terminal. The apparatus includes a second die having a second terminal. The apparatus includes an isolation channel coupled between the first terminal of the first die and the second terminal of the second die. The apparatus includes control circuitry disposed on the first die, the control circuitry for transmitting a power signal through the isolation channel, and for transmitting a control data signal through the isolation channel, and / or detecting a feedback data signal through the isolation channel. Other examples are described.

[0006] For methods, apparatus, and articles of manufacture for transmitting multiple signals through an isolation channel, an example system includes a processor integrated circuit (IC) having an output terminal and an input terminal. The system includes a gate driver IC having an isolation channel, a first output terminal on a first side of the isolation channel, a second output terminal on a second side of the isolation channel, and an input terminal on the first side of the isolation channel, the first output terminal of the gate driver IC coupled to the input terminal of the processor IC, and the input terminal of the gate driver IC coupled to the output terminal of the processor IC. The system includes a power switch having a control terminal coupled to the second output terminal of the gate driver IC, the gate driver IC for: (a) transmitting a control data signal for the power switch through the isolation channel, and / or (b) providing a feedback data signal received from the second side of the isolation channel to the processor IC, the feedback data signal indicating a state associated with the power switch; and transmitting a power signal for driving the power switch through the isolation channel. Other examples are described.

[0007] For methods, apparatus, and articles of manufacture for transmitting multiple signals through an isolation channel, an example apparatus includes a first die having a first terminal. The apparatus includes a second die having a second terminal. The apparatus includes an isolation channel coupled between the first terminal of the first die and the second terminal of the second die. The apparatus includes control circuitry disposed on the first die, the control circuitry being configured to: transmit a control data signal through the isolation channel during a first portion of a communication period; detect a feedback data signal during a second portion of the communication period; and transmit a power signal through the isolation channel during a third portion of the communication period. Other examples are described. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example system including an example gate driver circuit.

[0009] Figure 2A and Figure 2B yes Figure 1 A block diagram of an example implementation of a gate driver circuit.

[0010] Figure 3 Shown by Figure 2A and 2B The isolated channels of the gate driver circuit of the embodiment perform example transmission of forward direction (FWD) data, backward direction (BWD) data, and power in a time multiplexed manner.

[0011] Figure 4is a flowchart representing at least one of example machine-readable instructions or example operations that may be performed using Figure 2A and 2B The example programmable circuitry implementation of the first die of the gate driver circuit may be performed, instantiated and / or performed.

[0012] Figure 5 is a flowchart representing at least one of example machine-readable instructions or example operations that may be used Figure 2A and 2B The example programmable circuitry implementation of the second die of the gate driver circuit may be performed, instantiated and / or performed.

[0013] Figure 6 is a block diagram of an example processing platform including programmable circuitry configured to execute, instantiate, and / or perform Figure 4 and 5 At least one of the example machine readable instructions or example operations to implement Figure 2A and 2B The gate driver circuit.

[0014] The drawings are not necessarily drawn to scale. In general, the same reference numerals in the drawings and the specification refer to at least one of the same or similar (at least one of functional or structural) features or components. Although the drawings show regions with clean lines and borders, some or all of these lines and borders may be idealized. In reality, borders or lines may not be observable, blended, or irregular. DETAILED DESCRIPTION

[0015] In a motor vehicle, a relay is used to control at least one of a high current circuit or a high voltage circuit using at least one of a low current circuit or a low voltage circuit. For example, an electromechanical relay includes electrical contacts that can be coupled to at least one of a high current circuit or a high voltage circuit, an armature, and a coil that can be energized by at least one of a low current circuit or a low voltage circuit to control the armature to open and / or close the electrical contacts, and to complete and / or disconnect at least one of a high current circuit or a high voltage circuit.

[0016] In other examples, the relay can be used to control at least one of a low current circuit or a low voltage circuit using at least one of another low current circuit or another low voltage circuit. In additional examples, the relay can be used to control at least one of a high current circuit or a high voltage circuit using at least one of another high current circuit or another high voltage circuit.

[0017] In some cases, electromechanical relays have been replaced by solid-state relays that include transistors. For example, manufacturers of electric vehicles (EVs) and hybrid electric vehicles (HEVs) have used solid-state relays to replace electromechanical relays. In the examples described herein, the solid-state relay includes at least one gate driver circuit and at least one transistor (e.g., at least one power field effect transistor (FET)). In order to meet the safety standards for automotive applications, the solid-state relay includes an isolation gate driver circuit. For example, the isolation gate driver circuit includes an isolation barrier that implements galvanic isolation to isolate at least one of a low current circuit or a low voltage circuit from at least one of a high current circuit or a high voltage circuit. Therefore, the isolation barrier electrically isolates the low current domain or the low voltage domain from the high current domain or the high voltage domain. Therefore, by implementing the isolation barrier, the isolation gate driver circuit prevents current from flowing between at least one of (1) a low current circuit or a low voltage circuit and at least one of (2) a high current circuit or a high voltage circuit.

[0018] The isolation barrier can be implemented at the board level or in an integrated circuit. To maintain isolation, the isolated gate driver circuit contains a dedicated floating power supply. Some isolated gate driver circuits contain an integrated floating power supply, which reduces the footprint and monetary cost of implementing the isolated gate driver circuit.

[0019] In addition, to maintain isolation, the isolated gate driver circuit includes an isolation channel for transmitting signals through the isolation barrier. Such an isolation channel is unidirectional. For example, a unidirectional isolation channel from a low voltage circuit to a high voltage circuit allows the low voltage circuit to transmit signals only to the high voltage circuit or receive signals only from the high voltage circuit, but not both. An example isolation channel includes at least one of a transformer, an optical isolator, a capacitor, a Hall effect sensor, or a magnetic coupler. Therefore, the isolated gate driver circuit includes a separate isolation channel for each signal transmitted through the isolation barrier.

[0020] Therefore, the isolated gate driver circuit will include three isolation channels to pass three signals through the isolation barrier. For example, the isolated gate driver circuit includes a first dedicated isolation channel for passing a power signal from a low voltage circuit to a high voltage circuit through the isolation barrier. In addition, the isolated gate driver circuit includes a second dedicated isolation channel for transmitting a first data signal from a low voltage circuit to a high voltage circuit through the isolation barrier. In addition, the isolated gate driver circuit includes a third dedicated isolation channel for transmitting a secondary data signal from a high voltage circuit to a low voltage circuit through the isolation barrier. Therefore, the isolated gate driver circuit includes three isolation channels to pass three signals through the isolation barrier. More generally, an isolated gate driver circuit that passes N signals through the isolation barrier includes N isolation channels.

[0021] Since each signal requires a separate channel, passing more signals through the isolation barrier increases the footprint and monetary cost of implementing the isolated gate driver circuit. For example, each additional isolation channel increases the total monetary cost of the isolated gate driver circuit by 15-20%. In addition, increasing the number of isolation channels across the isolation barrier increases the difficulty of implementing the isolated gate driver as an integrated circuit. Some isolation channel types (e.g., transformers, Hall effect sensors, magnetic couplers, etc.) are physically large. For example, a single isolation channel may occupy 20% of the footprint of the integrated isolated gate driver circuit. Therefore, it is difficult to integrate multiple isolation channels into a single package.

[0022] The examples described herein include an isolated gate driver circuit capable of transmitting multiple signals through a single bidirectional isolation channel (e.g., a bidirectional communication channel). For example, a bidirectional isolation channel from a low voltage circuit to a high voltage circuit allows the low voltage circuit to transmit signals to the high voltage circuit and receive signals from the high voltage circuit. Therefore, the examples described herein include an isolated gate driver circuit that transmits a power signal from a low voltage circuit to a high voltage circuit through an isolation channel, transmits a control data signal from a low voltage circuit to a high voltage circuit through an isolation channel, and transmits a feedback data signal from a high voltage circuit to a low voltage circuit through an isolation channel. For example, the feedback data signal includes fault diagnostic data. Therefore, the examples described herein include an industrial isolated gate driver circuit that includes integrated diagnostic feedback and has a reduced footprint and monetary cost relative to other isolated gate driver circuits that transmit multiple signals over an isolation barrier. For example, the example isolated gate driver circuit described herein is industrial because the example isolated gate driver circuit is used in enterprise-level applications (e.g., automotive applications, manufacturing applications, etc.).

[0023] Figure 1 is a block diagram of an example system 100 including an example gate driver circuit 102. The example system 100 also includes an example processor circuit 104, an example switch 106, a first example capacitor 108, a first example resistor 110, a second example resistor 112, and an example chassis ground terminal 114. Figure 1 In the example of , the system 100 also includes an example current sensor 116, a second example capacitor 118, a third example capacitor 120, a third example resistor 122, a fourth example resistor 124, a fifth example resistor 126, a sixth example resistor 128, an example power source 130, an example load 132, and an example signal ground terminal 134. Figure 1 In the example of , the isolated gate driver circuit 102 includes a first example die 136 , a second example die 138 , and an example isolation barrier 140 .

[0024] exist Figure 1In the example shown, the first die 136 operates as the primary side of the gate driver circuit 102, and the second die 138 operates as the secondary side of the gate driver circuit 102. Figure 1 In the example of FIG. 1 , the first die 136 has a driver enable terminal (DRIVER ENABLE), a chip enable terminal (CHIP ENABLE), a first primary side ground terminal (VSS P_1 )、Primary side power supply terminal (VDD P )、Power status terminal (P STATUS ), fault terminal (FAULT), alarm terminal (ALARM) and the second primary side ground terminal (VSS P_2 ).exist Figure 1 In the example of FIG. 1 , the second die 138 has a driver terminal (DRIVER), a first secondary side power supply terminal (VDD S_1 )、First secondary side ground terminal (VSS S_1 )、Second secondary power supply terminal (VDD S_2 ), fault comparator terminal (FAULT CMP ) and the alarm comparator terminal (ALARM CMP )、Response control terminal (RESPONSE CONTROL ) and the second secondary side ground terminal (VSS S_2 ).exist Figure 1 In the example of the processor circuit 104, the first output terminal (O 1 )、The second output terminal (O 2 )、The first input terminal (I 1 )、The second input terminal (I 2 ) and the ground terminal (GND).

[0025] exist Figure 1 In the example shown, the switch 106 has a gate terminal (G), a drain terminal (D), and a source terminal (S). Figure 1 In the example of , each of the first capacitor 108, the first resistor 110, the second resistor 112, the second capacitor 118, the third capacitor 120, the third resistor 122, the fourth resistor 124, the fifth resistor 126, the sixth resistor 128, and the load 132 has a first terminal and a second terminal. Figure 1 In the example of FIG. 1 , the current sensor 116 has a power supply terminal (VDD), a ground terminal (GND), a positive input terminal (I P )、Negative input terminal (I N ) and output terminal (O). In addition, Figure 1 In the example of , the power source 130 has a positive terminal (P) and a negative terminal (N).

[0026] exist Figure 1 In the example shown, the gate driver circuit 102 is implemented as an integrated circuit (IC) including a first die 136 and a second die 138. Therefore, the gate driver circuit 102 can be referred to as a gate driver IC. In some examples, the first die 136 and the second die 138 are implemented in separate ICs. Figure 1 In the example of , the first die 136 of the gate driver circuit 102 is implemented by a semiconductor die (eg, a silicon (Si) die). In addition, a driver enable terminal of the gate driver circuit 102 is coupled to a first output terminal of the processor circuit 104. Figure 1 In the example of FIG. 1 , the chip enable terminal of the gate driver circuit 102 is coupled to the primary side power supply terminal of the gate driver circuit 102 and the second output terminal of the processor circuit 104. In addition, the chip enable terminal of the gate driver circuit 102 is coupled to the first terminal of the first capacitor 108, the first terminal of the first resistor 110, and the first terminal of the second resistor 112.

[0027] exist Figure 1 In the example shown, the first primary side ground terminal of the gate driver circuit 102 is coupled to the second primary side ground terminal of the gate driver circuit 102 and the power state terminal. Figure 1 In the example of , the first primary side ground terminal of the gate driver circuit 102 is coupled to the ground terminal of the processor circuit 104 and the chassis ground terminal 114. In addition, the first primary side ground terminal of the gate driver circuit 102 is coupled to the second terminal of the first capacitor 108.

[0028] exist Figure 1 In the example shown, the primary side power supply terminal of the gate driver circuit 102 is coupled to a chip enable terminal of the gate driver circuit 102 and a second output terminal of the processor circuit 104. In addition, the primary side power supply terminal of the gate driver circuit 102 is coupled to a first terminal of the first capacitor 108, a first terminal of the first resistor 110, and a first terminal of the second resistor 112. Figure 1 In the example of , the power state terminal of the gate driver circuit 102 is coupled to the first primary side ground terminal and the second primary side ground terminal of the gate driver circuit 102. Figure 1 In the example of , the power state terminal of the gate driver circuit 102 is coupled to the ground terminal of the processor circuit 104 and the chassis ground terminal 114. In addition, the power state terminal of the gate driver circuit 102 is coupled to the second terminal of the first capacitor 108.

[0029] exist Figure 1In the example shown, the fault terminal of the gate driver circuit 102 is coupled to the first input terminal of the processor circuit 104 and the second terminal of the first resistor 110. In addition, the alarm terminal of the gate driver circuit 102 is coupled to the second input terminal of the processor circuit 104 and the second terminal of the second resistor 112. Figure 1 In the example of , the second primary side ground terminal of the gate driver circuit 102 is coupled to the first primary side ground terminal and the power state terminal of the gate driver circuit 102. In addition, the second primary side ground terminal of the gate driver circuit 102 is coupled to the ground terminal of the processor circuit 104 and the chassis ground terminal 114. Figure 1 In the example of , the second primary side ground terminal of the gate driver circuit 102 is coupled to the second terminal of the first capacitor 108 .

[0030] exist Figure 1 In the example shown, the second die 138 of the gate driver circuit 102 is implemented by a semiconductor die (eg, a Si die). Figure 1 In the example of , the driver terminal of the gate driver circuit 102 is coupled to the gate terminal of the switch 106. In addition, the first secondary side power supply terminal of the gate driver circuit 102 is coupled to the first terminal of the second capacitor 118. Figure 1 In the example of , the first secondary-side ground terminal of the gate driver circuit 102 is coupled to the first terminal of the third capacitor 120. In addition, the first secondary-side ground terminal of the gate driver circuit 102 is coupled to the second secondary-side ground terminal of the gate driver circuit 102, the ground terminal of the current sensor 116, the negative input terminal of the current sensor 116, the second terminal of the fourth resistor 124, the second terminal of the fifth resistor 126, the second terminal of the sixth resistor 128, and the first terminal of the load 132.

[0031] exist Figure 1 In the example shown, the second secondary-side power supply terminal of the gate driver circuit 102 is coupled to the power supply terminal of the current sensor 116, the second terminal of the second capacitor 118, and the second end of the third capacitor 120. Figure 1 In the example of , the fault comparator terminal of the gate driver circuit 102 is coupled to the first terminal of the third resistor 122 and the first terminal of the fourth resistor 124. In addition, the alarm comparator terminal of the gate driver circuit 102 is coupled to the output terminal of the current sensor 116 and the second terminal of the third resistor 122.

[0032] exist Figure 1 In the example shown, the responsive control terminal of the gate driver circuit 102 is coupled to the first terminal of the fifth resistor 126. Figure 1In the example of , the second secondary-side ground terminal of the gate driver circuit 102 is coupled to the first secondary-side ground terminal of the gate driver circuit 102, the ground terminal of the current sensor 116, and the negative input terminal of the current sensor 116. In addition, the second secondary-side ground terminal of the gate driver circuit 102 is coupled to the first terminal of the third capacitor 120, the second terminal of the fourth resistor 124, the second terminal of the fifth resistor 126, the second terminal of the sixth resistor 128, and the first terminal of the load 132.

[0033] exist Figure 1 In the example shown, the processor circuit 104 is implemented by a microcontroller. In some examples, the processor circuit 104 is implemented as an IC. Thus, the processor circuit 104 may be referred to as a processor IC or a processor integrated circuit. Figure 1 In the example of , a first output terminal of the processor circuit 104 is coupled to a driver enable terminal of the gate driver circuit 102. In addition, a second output terminal of the processor circuit 104 is coupled to a chip enable terminal and a primary side power supply terminal of the gate driver circuit 102. Figure 1 In the example of , the second output terminal of the processor circuit 104 is coupled to a first terminal of the first capacitor 108 , a first terminal of the first resistor 110 , and a first terminal of the second resistor 112 .

[0034] exist Figure 1 In the example shown, a first input terminal of the processor circuit 104 is coupled to a fault terminal of the gate driver circuit 102. Figure 1 In the example of , the first input terminal of the processor circuit 104 is coupled to the second terminal of the first resistor 110. In addition, the second input terminal of the processor circuit 104 is coupled to the alarm terminal of the gate driver circuit 102. Figure 1 In the example of , the second input terminal of the processor circuit 104 is coupled to the second terminal of the second resistor 112. In addition, the ground terminal of the processor circuit 104 is coupled to the chassis ground terminal 114 and the second terminal of the first capacitor 108. Figure 1 In the example of , a ground terminal of the processor circuit 104 is coupled to the first primary side ground terminal, the second primary side ground terminal, and the power state terminal of the gate driver circuit 102 .

[0035] exist Figure 1 In the example shown, switch 106 is implemented by an n-channel metal oxide semiconductor field effect transistor (MOSFET). Alternatively, switch 106 may be implemented by an n-channel field effect transistor (FET), an n-channel insulated gate bipolar transistor (IGBT), an n-channel junction field effect transistor (JFET), a negative-positive-negative (NPN) bipolar junction transistor (BJT), or a slightly modified p-type equivalent device. Figure 1In the example of, switch 106 can be a depletion mode device, a drain extension device, an enhancement mode device, a native transistor, or other type of device structure transistor. In addition, switch 106 can be implemented in and / or on a Si substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0036] exist Figure 1 In the example shown, the gate terminal of the switch 106 is coupled to the driver terminal of the gate driver circuit 102. Figure 1 In the example of , the drain terminal of the switch 106 is coupled to the positive terminal of the power source 130. In addition, the source terminal of the switch 106 is coupled to the first terminal of the sixth resistor 128. Figure 1 In the example of , the source terminal of the switch 106 is also coupled to the positive input terminal of the current sensor 116 and the first terminal of the sixth resistor 128 .

[0037] exist Figure 1 In the example shown, a first terminal of the first capacitor 108 is coupled to a chip enable terminal and a primary side power supply terminal of the gate driver circuit 102. Figure 1 In the example of , a first terminal of the first capacitor 108 is coupled to the second output terminal of the processor circuit 104. In addition, a first terminal of the first capacitor 108 is coupled to a first terminal of the first resistor 110 and a first terminal of the second resistor 112. Figure 1 In the example of , the second terminal of the first capacitor 108 is coupled to the first primary side ground terminal, the second primary side ground terminal, and the power state terminal of the gate driver circuit 102. In addition, the second terminal of the first capacitor 108 is coupled to the ground terminal of the processor circuit 104 and the chassis ground terminal 114.

[0038] exist Figure 1 In the example shown, a first terminal of the first resistor 110 is coupled to a chip enable terminal and a primary side power supply terminal of the gate driver circuit 102. Figure 1 In the example of , the first terminal of the first resistor 110 is coupled to the second output terminal of the processor circuit 104. In addition, the first terminal of the first resistor 110 is coupled to the first terminal of the first capacitor 108 and the first terminal of the second resistor 112. Figure 1 In the example of , the second terminal of the first resistor 110 is coupled to the fault terminal of the gate driver circuit 102 and the first input terminal of the processor circuit 104 .

[0039] exist Figure 1 In the example shown, a first terminal of the second resistor 112 is coupled to a chip enable terminal and a primary side power supply terminal of the gate driver circuit 102. Figure 1In the example of , the first terminal of the second resistor 112 is coupled to the second output terminal of the processor circuit 104. In addition, the first terminal of the second resistor 112 is coupled to the first terminal of the first capacitor 108 and the first terminal of the first resistor 110. Figure 1 In the example of , the second terminal of the second resistor 112 is coupled to the alarm terminal of the gate driver circuit 102 and the second input terminal of the processor circuit 104 .

[0040] exist Figure 1 In the example shown, chassis ground terminal 114 is a common terminal to which electrical components on the primary side of isolation barrier 140 are coupled. Figure 1 In the example of , chassis ground terminal 114 may or may not be coupled to the earth. For example, if system 100 is implemented in an automotive application (e.g., an EV or HEV application), chassis ground terminal 114 may be the chassis of a vehicle whose chassis is not connected to the earth. Additionally or alternatively, if system 100 is implemented in a non-automotive application, chassis ground terminal 114 may be the chassis of an electrical system whose chassis is coupled to the earth. Figure 1 In the example of , the chassis ground terminal 114 is coupled to the first primary side ground terminal, the second primary side ground terminal, and the power state terminal of the gate driver circuit 102. In addition, the chassis ground terminal 114 is coupled to the ground terminal of the processor circuit 104 and the second terminal of the first capacitor 108.

[0041] exist Figure 1 In the example shown, the current sensor 116 is implemented by at least one of analog circuitry or digital circuitry. Figure 1 In the example of , the power supply terminal of the current sensor 116 is coupled to the second terminal of the second capacitor 118, the second terminal of the third capacitor 120, and the second secondary power supply terminal of the gate driver circuit 102. Figure 1 In the example of , the ground terminal of the current sensor 116 is coupled to the first secondary-side ground terminal and the second secondary-side ground terminal of the gate driver circuit 102. In addition, the ground terminal of the current sensor 116 is coupled to the negative input terminal of the current sensor 116, the first terminal of the third capacitor 120, the second terminal of the fourth resistor 124, the second terminal of the fifth resistor 126, the second terminal of the sixth resistor 128, and the first terminal of the load 132.

[0042] exist Figure 1In the example shown, the positive input terminal of the current sensor 116 is coupled to the source terminal of the switch 106 and the first terminal of the sixth resistor 128. In addition, the negative input terminal of the current sensor 116 is coupled to the first secondary-side ground terminal and the second secondary-side ground terminal of the gate driver circuit 102. In addition, the negative input terminal of the current sensor 116 is coupled to the ground terminal of the current sensor 116, the first terminal of the third capacitor 120, the second terminal of the fourth resistor 124, the second terminal of the fifth resistor 126, the second terminal of the sixth resistor 128, and the first terminal of the load 132. Figure 1 In the example of , the output terminal of the current sensor 116 is coupled to the alarm comparator terminal of the gate driver circuit 102 and the second terminal of the third resistor 122 .

[0043] exist Figure 1 In the example shown, a first terminal of the second capacitor 118 is coupled to the first secondary power supply terminal of the gate driver circuit 102. In addition, a second terminal of the second capacitor 118 is coupled to the second secondary power supply terminal of the gate driver circuit 102, a power supply terminal of the current sensor 116, and a second terminal of the third capacitor 120. Figure 1 In the example of , a first terminal of the third capacitor 120 is coupled to a first secondary-side ground terminal and a second secondary-side ground terminal of the gate driver circuit 102. In addition, a first terminal of the third capacitor 120 is coupled to a ground terminal of the current sensor 116, a negative input terminal of the current sensor 116, a second terminal of the fourth resistor 124, a second terminal of the fifth resistor 126, a second terminal of the sixth resistor 128, and a first terminal of the load 132.

[0044] exist Figure 1 In the example shown, a first terminal of the third resistor 122 is coupled to the fault comparator terminal of the gate driver circuit 102. In addition, a first terminal of the third resistor 122 is coupled to a first terminal of the fourth resistor 124. Figure 1 In the example of , the second terminal of the third resistor 122 is coupled to the alarm comparator terminal of the gate driver circuit 102. In addition, the second terminal of the third resistor 122 is coupled to the output terminal of the current sensor 116.

[0045] exist Figure 1 In the example shown, a first terminal of the fourth resistor 124 is coupled to the fault comparator terminal of the gate driver circuit 102 and a first terminal of the third resistor 122. Figure 1In the example of , the second terminal of the fourth resistor 124 is coupled to the first secondary-side ground terminal and the second secondary-side ground terminal of the gate driver circuit 102. In addition, the second terminal of the fourth resistor 124 is coupled to the ground terminal of the current sensor 116, the negative input terminal of the current sensor 116, the first terminal of the third capacitor 120, the second terminal of the fifth resistor 126, the second terminal of the sixth resistor 128, and the first terminal of the load 132.

[0046] exist Figure 1 In the example shown, a first terminal of the fifth resistor 126 is coupled to a corresponding control terminal of the gate driver circuit 102. Figure 1 In the example of , the second terminal of the fifth resistor 126 is coupled to the first secondary-side ground terminal and the second secondary-side ground terminal of the gate driver circuit 102. In addition, the second terminal of the fifth resistor 126 is coupled to the ground terminal of the current sensor 116, the negative input terminal of the current sensor 116, the first terminal of the third capacitor 120, the second terminal of the fourth resistor 124, the second terminal of the sixth resistor 128, and the first terminal of the load 132.

[0047] exist Figure 1 In the example shown, a first terminal of the sixth resistor 128 is coupled to the source terminal of the switch 106 and the positive input terminal of the current sensor 116. Figure 1 In the example of , the second terminal of the sixth resistor 128 is coupled to the first secondary-side ground terminal and the second secondary-side ground terminal of the gate driver circuit 102. In addition, the second terminal of the sixth resistor 128 is coupled to the ground terminal of the current sensor 116, the negative input terminal of the current sensor 116, the first terminal of the third capacitor 120, the second terminal of the fourth resistor 124, the second terminal of the fifth resistor 126, and the first terminal of the load 132.

[0048] exist Figure 1 In the example shown, power source 130 is implemented by one or more batteries. Example batteries include lithium-ion batteries, nickel-cadmium batteries, nickel-metal hydride batteries, and lead-acid batteries. In some examples, power source 130 is implemented by one or more supercapacitors. In some examples, power source 130 is implemented by an alternating current (AC) to direct current (DC) power converter (e.g., an AC to DC converter, a rectifier, etc.). Figure 1 In the example of FIG. 1 , the positive terminal of the power supply 130 is coupled to the drain terminal of the switch 106 . Additionally, the negative terminal of the power supply 130 is coupled to the second terminal of the load 132 and the signal ground terminal 134 .

[0049] exist Figure 1In the example shown, load 132 is an electrical load, such as a resistive load, an inductive load, or a capacitive load. Example resistive loads include household appliances, such as incandescent lamps, toasters, ovens, space heaters, and coffee makers. Example inductive loads include motors, solenoids, contactor coils, compressors, speakers, relays, transformers, inductors, and generators. Example capacitive loads include capacitor banks, cables, and batteries.

[0050] exist Figure 1 In the example shown, a first terminal of the load 132 is coupled to a first secondary-side ground terminal and a second secondary-side ground terminal of the gate driver circuit 102. In addition, a first terminal of the load 132 is coupled to a ground terminal of the current sensor 116, a negative input terminal of the current sensor 116, a first terminal of the third capacitor 120, a second terminal of the fourth resistor 124, a second terminal of the fifth resistor 126, and a second terminal of the sixth resistor 128. Figure 1 In the example of , the second terminal of the load 132 is coupled to the negative terminal of the power supply 130 and the signal ground terminal 134 .

[0051] exist Figure 1 In the example shown, the signal ground terminal 134 is the common terminal from which the signal is measured on the secondary side of the isolation barrier 140. Figure 1 In the example of , the signal ground terminal 134 is coupled to a printed circuit board (PCB) or substrate on which the system 100 is implemented. Figure 1 In the example of , the signal ground terminal 134 is coupled to the negative terminal of the power supply 130 and the second terminal of the load 132 .

[0052] exist Figure 1 In the example shown, the processor circuit 104 utilizes the gate driver circuit 102 to control the switch 106. As described above, the gate driver circuit 102 includes the isolation barrier 140. Figure 1 In the example of , the isolation barrier 140 provides galvanic isolation between the first die 136 and the second die 138. Thus, the processor circuit 104 is galvanically isolated from the switch 106. Figure 1 In the example of FIG. 1 , the gate driver circuit 102 transmits a power signal and one or more data signals through the isolation barrier 140 .

[0053] exist Figure 1 In the example shown, the processor circuit 104 provides primary data signals (eg, forward data) and power signals to the first die 136 at the driver enable terminal and primary side power supply terminal of the gate driver circuit 102, respectively. Figure 1In some examples, the primary data signal corresponds to a control signal for causing the gate driver circuit 102 to drive the switch 106 at a driver terminal of the gate driver circuit 102. For example, the gate driver circuit 102 passes the power signal to the power circuitry of the second die 138 through the isolation barrier 140 and passes the control signal through the isolation barrier 140 to cause the circuitry of the second die 138 to drive the switch 106. In some examples, the primary data signal is serialized using a clock signal generated by an internal clock of the first die 136 of the gate driver circuit 102.

[0054] exist Figure 1 In the example shown, the processor circuit 104 uses the gate driver circuit 102 to control the switch 106 to provide overcurrent protection for the switch 106. For example, the gate driver circuit 102 is interfaced with the current sensor 116. Figure 1 In the example of , the gate driver circuit 102 provides a power signal to the current sensor 116 and supporting circuitry at the second secondary power supply terminal of the gate driver circuit 102. Figure 1 In the example of FIG. 1 , the current sensor 116 amplifies the voltage across the sixth resistor 128 under load conditions to generate an output indicative of the current flowing through the sixth resistor 128 .

[0055] exist Figure 1 In the example shown, the gate driver circuit 102 monitors the output of the current sensor 116. Figure 1 In an example of the present invention, based on the output of the current sensor 116, the gate driver circuit 102 passes a secondary data signal (e.g., backward data) from the second die 138 to the first die 136 through the isolation barrier 140. For example, the secondary data signal may include diagnostic data, data specifying one or more operating parameters at the second die 138, data required for power control at the first die 136, DC-DC regulation control, etc. In some examples, the secondary data signal is serialized using a clock signal generated by an internal clock implemented on the second die 138 of the gate driver circuit 102. Therefore, the gate driver circuit 102 can provide an alarm to the processor circuit 104 via the alarm terminal. In some examples, the gate driver circuit 102 monitors the output of the current sensor 116 to detect an overcurrent event. Therefore, when the output of the current sensor 116 meets (e.g., exceeds) an overcurrent threshold, the gate driver circuit 102 can disable (e.g., disconnect) the switch 106. In addition, the gate driver circuit 102 notifies the processor circuit 104 via at least one of the alarm terminal or the fault terminal.

[0056] Advantageously, the gate driver circuit 102 transmits the power signal, the primary data signal, and the secondary data signal through the isolation barrier 140 via a single isolation channel. Figure 1 In the example of, the gate driver circuit 102 transmits the power signal, the primary data signal and the secondary data signal via a single isolation channel in a time multiplexed manner. For example, the transmission of the primary data signal (e.g., forward data), the power signal and the secondary data signal (e.g., background data) through the single isolation channel of the isolation barrier 140 is synchronized in time. Therefore, the circuit system of the first die 136 is configured to drive the isolation channel when the primary data signal (e.g., forward data) is to be transmitted from the first die 136 to the second die 138 and at other times when the power signal is to be transmitted from the first die 136 to the second die 138. In addition, the circuit system of the second die 138 is configured to synchronize the transmission timing of the secondary data signal (e.g., backward data) through the same isolation channel with respect to the timing of the primary data signal (e.g., forward data) and the power signal, for example, according to a prescribed timing arrangement. By utilizing a single isolation channel, both data (e.g., forward data and backward data) and power are transmitted through the same isolation channel, thereby eliminating the multiple isolation channels required to transmit multiple signals.

[0057] Figure 2A and 2B yes Figure 1 1 is a block diagram of an example implementation of a gate driver circuit 102. As described above, the gate driver circuit 102 includes a first die 136, a second die 138, and an isolation barrier 140. Figure 2A and 2B In the example, the first die 136 includes a first example control circuit system 202, a first example modulator circuit system 204, an example carrier signal generator circuit system 206, an example excitation driver circuit system 208, a first example demodulator circuit system 210, an example decoder circuit system 212 and a first example ground terminal 214.

[0058] exist Figure 2A and 2B In the example shown, the second die 138 includes a second example demodulator circuit system 216, a second example ground terminal 218, a second example control circuit system 220, an example rectifier circuit system 222, an example voltage sensing circuit system 224, an example gate driver circuit system 226, a first example comparator 228, a second example comparator 230, an example reference voltage source 232, an example encoder circuit system 234, a second modulator circuit system 236, and an example capacitor 238. Figure 2A and 2B In the example of , the isolation barrier 140 includes an example isolation channel 240. In addition, Figure 2A and 2B In the example of FIG. 2 , the isolation channel 240 is implemented by a transformer and has an example primary coil 242 and an example secondary coil 244 .

[0059] exist Figure 2A and 2B In the example shown, at least one of the first die 136 or the second die 138 may be instantiated (e.g., created as an instance, generated for any length of time, materialized, implemented, etc.) by (i) an application specific integrated circuit (ASIC) or (ii) a field programmable gate array (FPGA) constructed or configured in response to executing instructions to perform operations. Thus, Figure 2A and 2B Some or all of the circuitry may be instantiated at the same or different times. Additionally or alternatively, at least one of first die 136 or second die 138 may be instantiated (e.g., created as an instance, implemented for any length of time, materialized, implemented, etc.) by programmable circuitry (e.g., a central processing unit (CPU)) that executes instructions. For example, Figure 2A and 2B Some or all of the circuitry of may be instantiated in one or more threads that execute concurrently on hardware or serially on hardware.

[0060] exist Figure 2A and 2B In the example shown, the first control circuit system 202 has a first input terminal, a second input terminal, a third input terminal, a first output terminal, a second output terminal, a positive power supply terminal, and a negative power supply terminal. Figure 2A and 2B In the example of , the first modulator circuit system 204 has a first input terminal, a second input terminal, and an output terminal. Figure 2A and 2B In the example of , the carrier signal generator circuit system 206 has a positive terminal and a negative terminal. In addition, the excitation driver circuit system 208 has a first input terminal, a second input terminal, a positive output terminal, a negative output terminal, a positive power supply terminal, and a negative power supply terminal. Figure 2A and 2B In the example of , the first demodulator circuit system 210 has a positive input terminal, a negative input terminal, and an output terminal. Figure 2A and 2B In the example of , decoder circuitry 212 has an input terminal, a first output terminal, a second output terminal, and a third output terminal.

[0061] exist Figure 2A and 2B In the example shown, the second demodulator circuit system 216 has a positive input terminal, a negative input terminal, and an output terminal. In addition, the second control circuit system 220 has a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a first output terminal, and a second output terminal. Figure 2A and2B In the example of , the rectifier circuit system 222 has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. In addition, the voltage sensing circuit system 224 has a positive input terminal, a negative input terminal, and an output terminal. Figure 2A and 2B In the example of , the gate driver circuit system 226 has an input terminal, an output terminal, a positive power supply terminal, and a negative power supply terminal.

[0062] exist Figure 2A and 2B In the example shown, each of the first comparator 228 and the second comparator 230 has a non-inverting input terminal, an inverting input terminal, and an output terminal. In addition, the reference voltage source 232 has a positive terminal and a negative terminal. Figure 2A and 2B In the example of , each of the encoder circuit system 234 and the second modulator circuit system 236 has an input terminal and an output terminal. In addition, the capacitor 238 has a first terminal and a second terminal. Figure 2A and 2B In the example of , each of the primary coil 242 and the secondary coil 244 has a first terminal and a second terminal.

[0063] exist Figure 2A and 2B In the example shown, the first control circuit system 202 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , the first input terminal of the first control circuit system 202 is coupled to the chip enable terminal of the gate driver circuit 102. In addition, the second input terminal of the first control circuit system 202 is coupled to the driver enable terminal of the gate driver circuit 102. Figure 2A and 2B In the example of , the third input terminal of the first control circuitry 202 is coupled to the output terminal of the first demodulator circuitry 210 and the input terminal of the decoder circuitry 212 .

[0064] exist Figure 2A and 2B In the example shown, a first output terminal of the first control circuit system 202 is coupled to a first input terminal of the excitation driver circuit system 208. Figure 2A and 2B In the example of , the second output terminal of the first control circuit system 202 is coupled to the first input terminal of the first modulator circuit system 204. In addition, the positive power supply terminal of the first control circuit system 202 is coupled to the primary side power supply terminal of the gate driver circuit 102 and the positive power supply terminal of the excitation driver circuit system 208. Figure 2A and 2BIn the example, the negative power terminal of the first control circuit system 202 is coupled to the first primary side ground terminal of the gate driver circuit 102, the second primary side ground terminal of the gate driver circuit 102, the negative terminal of the carrier signal generator circuit system 206, the negative power terminal of the excitation driver circuit system 208, and the first ground terminal 214.

[0065] exist Figure 2A and 2B In the example shown, the first modulator circuitry 204 is implemented by at least one of analog circuitry or digital circuitry. Figure 2A and 2B In the example of , the first input terminal of the first modulator circuit system 204 is coupled to the second output terminal of the first control circuit system 202. In addition, the second input terminal of the first modulator circuit system 204 is coupled to the positive terminal of the carrier signal generator circuit system 206. Figure 2A and 2B In the example of , the output terminal of the first modulator circuit system 204 is coupled to the second input terminal of the excitation driver circuit system 208.

[0066] exist Figure 2A and 2B In the example shown, the carrier signal generator circuit system 206 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , the positive terminal of the carrier signal generator circuit system 206 is coupled to the second input terminal of the first modulator circuit system 204. In addition, the negative terminal of the carrier signal generator circuit system 206 is coupled to the first primary side ground terminal of the gate driver circuit 102, the second primary side ground terminal of the gate driver circuit 102, the negative power supply terminal of the first control circuit system 202, the negative power supply terminal of the excitation driver circuit system 208, and the first ground terminal 214.

[0067] exist Figure 2A and 2B In the example shown, the excitation driver circuit system 208 is implemented by at least one of analog circuit system or digital circuit system. For example, the excitation driver circuit system 208 is configured to operate as a pass-through circuit and a converter based on the control signal from the first control circuit system 202 to convert the DC power signal at the primary side power terminal of the gate driver circuit 102 into an AC power signal. Figure 2A and 2B In the example of , a first input terminal of the excitation driver circuit system 208 is coupled to a first output terminal of the first control circuit system 202. In addition, a second input terminal of the excitation driver circuit system 208 is coupled to an output terminal of the first modulator circuit system 204. Figure 2A and 2B In the example of FIG. 2 , the positive output terminal of the excitation driver circuit system 208 is coupled to the positive input terminal of the first demodulator circuit system 210 and the first terminal of the primary coil 242. In addition, the negative output terminal of the excitation driver circuit system 208 is coupled to the negative input terminal of the first demodulator circuit system 210 and the second terminal of the primary coil 242.

[0068] exist Figure 2A and 2B In the example shown, the positive power supply terminal of the excitation driver circuit system 208 is coupled to the primary side power supply terminal of the gate driver circuit 102 and the positive power supply terminal of the first control circuit system 202. Figure 2A and 2B In the example of FIG. 2 , the negative power supply terminal of the excitation driver circuit system 208 is coupled to the first primary side ground terminal of the gate driver circuit 102 and the second primary side ground terminal of the gate driver circuit 102. In addition, the negative power supply terminal of the excitation driver circuit system 208 is coupled to the negative power supply terminal of the first control circuit system 202, the negative terminal of the carrier signal generator circuit system 206, and the first ground terminal 214.

[0069] exist Figure 2A and 2B In the example shown, the first demodulator circuitry 210 is implemented by at least one of analog circuitry or digital circuitry. Figure 2A and 2B In the example of , the positive input terminal of the first demodulator circuit system 210 is coupled to the positive output terminal of the excitation driver circuit system 208 and the first terminal of the primary coil 242. In addition, the negative input terminal of the first demodulator circuit system 210 is coupled to the negative output terminal of the excitation driver circuit system 208 and the second terminal of the primary coil 242.

[0070] exist Figure 2A and 2B In the example shown, decoder circuitry 212 is implemented by at least one of analog circuitry or digital circuitry. Figure 2A and 2B In the example of , an input terminal of the decoder circuit system 212 is coupled to the output terminal of the first demodulator circuit system 210 and the third input terminal of the first control circuit system 202. In addition, a first output terminal of the decoder circuit system 212 is coupled to the power state terminal of the gate driver circuit 102.

[0071] exist Figure 2A and 2B In the example shown, the second output terminal of the decoder circuitry 212 is coupled to the fault terminal of the gate driver circuit 102. Figure 2Aand 2B In the example of , the third output terminal of the decoder circuit system 212 is coupled to the alarm terminal of the gate driver circuit 102. In addition, the first ground terminal 214 is coupled to the first primary side ground terminal of the gate driver circuit 102, the second primary side ground terminal of the gate driver circuit 102, the negative power supply terminal of the first control circuit system 202, the negative terminal of the carrier signal generator circuit system 206, and the negative power supply terminal of the excitation driver circuit system 208.

[0072] exist Figure 2A and 2B In the example shown, the second demodulator circuitry 216 is implemented by at least one of analog circuitry or digital circuitry. Figure 2A and 2B In the example of , the positive input terminal of the second demodulator circuit system 216 is coupled to the first terminal of the secondary coil 244 and the positive input terminal of the rectifier circuit system 222. In addition, the negative input terminal of the second demodulator circuit system 216 is coupled to the first secondary side ground terminal of the gate driver circuit 102, the second secondary side ground terminal of the gate driver circuit 102, the second ground terminal 218, the negative input terminal of the rectifier circuit system 222, the negative terminal of the reference voltage source 232, the first terminal of the capacitor 238, and the second terminal of the secondary coil 244. Figure 2A and 2B In the example of , the output terminal of the second demodulator circuitry 216 is coupled to the first input terminal of the second control circuitry 220. In addition, the second ground terminal 218 is coupled to the first secondary side ground terminal of the gate driver circuitry 102, the second secondary side ground terminal of the gate driver circuitry 102, the negative input terminal of the second demodulator circuitry 216, the negative input terminal of the rectifier circuitry 222, the negative terminal of the reference voltage source 232, the first terminal of the capacitor 238, and the second terminal of the secondary coil 244.

[0073] exist Figure 2A and 2B In the example shown, the second control circuit system 220 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , a first input terminal of the second control circuit system 220 is coupled to an output terminal of the second demodulator circuit system 216. In addition, a second input terminal of the second control circuit system 220 is coupled to an output terminal of the voltage sensing circuit system 224. Figure 2A and 2B In the example of , the third input terminal of the second control circuit system 220 is coupled to the output terminal of the first comparator 228. In addition, the fourth input terminal of the second control circuit system 220 is coupled to the output terminal of the second comparator 230. Figure 2A and 2B In the example of , the first output terminal of the second control circuit system 220 is coupled to the input terminal of the gate driver circuit system 226. Figure 2A and 2B In the example of , the second output terminal of the second control circuit system 220 is coupled to the input terminal of the encoder circuit system 234.

[0074] exist Figure 2A and 2B In the example shown, the rectifier circuit system 222 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , the positive input terminal of the rectifier circuit system 222 is coupled to the first terminal of the secondary coil 244 and the positive input terminal of the second demodulator circuit system 216. In addition, the negative input terminal of the rectifier circuit system 222 is coupled to the first secondary side ground terminal of the gate driver circuit 102, the second secondary side ground terminal of the gate driver circuit 102, the negative input terminal of the second demodulator circuit system 216, the second ground terminal 218, the negative terminal of the reference voltage source 232, the first terminal of the capacitor 238, and the second terminal of the secondary coil 244. Figure 2A and 2B In the example of , the positive output terminal of the rectifier circuit system 222 is coupled to the positive input terminal of the voltage sensing circuit system 224, the positive power supply terminal of the gate driver circuit system 226, and the first secondary power supply terminal of the gate driver circuit 102. In addition, the negative output terminal of the rectifier circuit system 222 is coupled to the negative input terminal of the voltage sensing circuit system 224 and the negative power supply terminal of the gate driver circuit system 226.

[0075] exist Figure 2A and 2B In the example shown, the voltage sensing circuit system 224 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , the positive input terminal of the voltage sensing circuit system 224 is coupled to the positive output terminal of the rectifier circuit system 222, the positive power supply terminal of the gate driver circuit system 226, and the first secondary power supply terminal of the gate driver circuit 102. In addition, the negative input terminal of the voltage sensing circuit system 224 is coupled to the negative output terminal of the rectifier circuit system 222 and the negative power supply terminal of the gate driver circuit system 226. Figure 2A and 2B In the example of , the output terminal of the voltage sensing circuitry 224 is coupled to the second input terminal of the second control circuitry 220 .

[0076] exist Figure 2A and2B In the example shown, the gate driver circuit system 226 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , the input terminal of the gate driver circuit system 226 is coupled to the first output terminal of the second control circuit system 220. In addition, the output terminal of the gate driver circuit system 226 is coupled to the driver terminal of the gate driver circuit 102. Figure 2A and 2B In the example of FIG. 1 , the positive power supply terminal of the gate driver circuit system 226 is coupled to the positive output terminal of the rectifier circuit system 222, the positive input terminal of the voltage sensing circuit system 224, and the first secondary power supply terminal of the gate driver circuit 102. In addition, the negative power supply terminal of the gate driver circuit system 226 is coupled to the negative output terminal of the rectifier circuit system 222 and the negative input terminal of the voltage sensing circuit system 224.

[0077] exist Figure 2A and 2B In the example shown, the first comparator 228 is implemented by at least one of analog circuitry or digital circuitry. In some examples, the first comparator 228 is referred to as first comparator circuitry. Figure 2A and 2B In the example of , the non-inverting input terminal of the first comparator 228 is coupled to the fault comparator terminal of the gate driver circuit 102. In addition, the inverting input terminal of the first comparator 228 is connected to the positive terminal of the reference voltage source 232 and the inverting input terminal of the second comparator 230. Figure 2A and 2B In the example of , the output terminal of the first comparator 228 is coupled to the third input terminal of the second control circuit system 220 .

[0078] exist Figure 2A and 2B In the example shown, the second comparator 230 is implemented by at least one of analog circuitry or digital circuitry. In some examples, the second comparator 230 is referred to as second comparator circuitry. Figure 2A and 2B In the example of , the non-inverting input terminal of the second comparator 230 is coupled to the alarm comparator terminal of the gate driver circuit 102. In addition, the inverting input terminal of the second comparator 230 is coupled to the positive terminal of the reference voltage source 232 and the inverting input terminal of the first comparator 228. Figure 2A and 2B In the example of , the output terminal of the second comparator 230 is coupled to the fourth input terminal of the second control circuit system 220 .

[0079] exist Figure 2A and2B In the example shown, the reference voltage source 232 is implemented by at least one of analog circuitry or digital circuitry. Figure 2A and 2B In the example of , the positive terminal of the reference voltage source 232 is coupled to the inverting input terminal of the first comparator 228 and the inverting input terminal of the second comparator 230. In addition, the negative terminal of the reference voltage source 232 is coupled to the first secondary side ground terminal of the gate driver circuit 102, the second secondary side ground terminal of the gate driver circuit 102, the negative input terminal of the second demodulator circuit system 216, the second ground terminal 218, the negative input terminal of the rectifier circuit system 222, the first terminal of the capacitor 238, and the second terminal of the secondary coil 244.

[0080] exist Figure 2A and 2B In the example shown, encoder circuitry 234 is implemented by at least one of analog circuitry or digital circuitry. Figure 2A and 2B In the example of , an input terminal of encoder circuitry 234 is coupled to a second output terminal of second control circuitry 220. Additionally, an output terminal of encoder circuitry 234 is coupled to an input terminal of second modulator circuitry 236.

[0081] exist Figure 2A and 2B In the example shown, the second modulator circuit system 236 is implemented by at least one of analog circuit system or digital circuit system. Figure 2A and 2B In the example of , the input terminal of the second modulator circuit system 236 is coupled to the output terminal of the encoder circuit system 234. In addition, the output terminal of the second modulator circuit system 236 is coupled to the second terminal of the capacitor 238. Figure 2A and 2B In the example of , a first terminal of capacitor 238 is coupled to a first secondary-side ground terminal of gate driver circuit 102, a second secondary-side ground terminal of gate driver circuit 102, a negative input terminal of second demodulator circuitry 216, second ground terminal 218, a negative input terminal of rectifier circuitry 222, a negative terminal of reference voltage source 232, and a second terminal of secondary coil 244. Additionally, a second terminal of capacitor 238 is coupled to an output terminal of second modulator circuitry 236.

[0082] As described above, the isolation channel 240 is implemented by a transformer having a primary coil 242 and a secondary coil 244. Figure 2A and 2BIn the example of , the primary coil 242 and the secondary coil 244 are inductively coupled to each other. In addition, the first terminal of the primary coil 242 is coupled to the positive output terminal of the excitation driver circuit system 208 and the positive input terminal of the first demodulator circuit system 210. Figure 2A and 2B In the example of , the second terminal of the primary coil 242 is coupled to the negative output terminal of the excitation driver circuitry 208 and the negative input terminal of the first demodulator circuitry 210 .

[0083] exist Figure 2A and 2B In the example shown, a first terminal of the secondary coil 244 is coupled to a positive input terminal of the second demodulator circuitry 216 and a positive input terminal of the rectifier circuitry 222. Figure 2A and 2B In the example of , the second terminal of the secondary coil 244 is coupled to the first secondary side ground terminal of the gate driver circuit 102, the second secondary side ground terminal of the gate driver circuit 102, the second ground terminal 218, and the negative terminal of the reference voltage source 232. In addition, the second terminal of the secondary coil 244 is coupled to the negative input terminal of the second demodulator circuit system 216, the negative input terminal of the rectifier circuit system 222, and the first terminal of the capacitor 238.

[0084] exist Figure 2A and 2B In the example shown, during initial startup of the gate driver circuit 102, power is transmitted across the isolation barrier 140 to charge at least one capacitor (e.g., the second capacitor 118 and the third capacitor 120) coupled to the second die 138. Thus, as described above, the second die 138 remains powered on during the period in which data is transmitted across the isolation barrier 140. During nominal operation, the first control circuit system 202 operates based on signals at the driver enable terminal, the primary side power supply terminal, and the chip enable terminal of the gate driver circuit 102. For example, the first control circuit system 202 is enabled when the signal at the chip enable terminal is a logic high value (e.g., 5 volts (V)) and the signal at the primary side power supply terminal is at a power supply voltage (e.g., 5 V).

[0085] exist Figure 2A and 2BIn the example shown, when enabled, the first control circuit system 202 causes periodic communication between the first die 136 and the second die 138 based on the signal at the driver enable terminal of the gate driver circuit 102. For example, each communication period includes a first sub-period during which the primary data signal is transmitted from the first die 136 to the second die 138, a second sub-period during which the secondary data signal is transmitted from the second die 138 to the first die 136, a third sub-period during which the power signal is transferred from the first die 136 to the second die 138, and a fourth sub-period during which the isolation channel 240 is idle. Figure 2A and 2B In the example of , the first control circuit system 202 maintains one or more timers corresponding to the first sub-period, the second sub-period, the third sub-period, and the fourth sub-period. For example, the first control circuit system 202 maintains a first timer indicating the end of the first sub-period, a second timer indicating the end of the second sub-period, a third timer indicating the end of the third sub-period, and a fourth timer indicating the end of the fourth sub-period.

[0086] exist Figure 2A and 2B In the example shown, when the primary side power supply terminal is at the power supply voltage (e.g., 5V), the excitation driver circuit system 208 is enabled and energizes the primary coil 242 based on a signal (e.g., a carrier signal, a modulated carrier signal, a power signal, etc.). Figure 2A and 2B In an example of, based on a logic high value (e.g., 5V) at the driver enable terminal of the gate driver circuit 102, the first control circuit system 202 initiates periodic communication between the first tube core 136 and the second tube core 138. For example, during a first sub-period of periodic communication, the first control circuit system 202 sends a primary data signal (e.g., a forward data signal, a control data signal, etc.) to the first modulator circuit system 204 to modulate it into a carrier signal generated by the carrier signal generator circuit system 206. For example, the primary data signal is a 1-bit signal. In addition, during the first sub-period, the first modulator circuit system 204 modulates the carrier signal based on the primary data signal to generate a modulated carrier signal. For example, the first modulator circuit system 204 modulates the carrier signal based on the primary data signal using amplitude modulation. In some examples, the first modulator circuit system 204 uses another type of modulation (e.g., frequency modulation, phase modulation, etc.).

[0087] exist Figure 2A and 2B In the example shown, after modulating the carrier signal, the first modulator circuit system 204 sends the modulated carrier signal to the excitation driver circuit system 208. Figure 2A and2B In the example of, based on the control signal generated by the first control circuit system 202, the excitation driver circuit system 208 energizes the primary coil 242 based on the modulated carrier signal to transmit the primary data signal (e.g., forward data signal, control data signal, etc.) to the second tube core 138. For example, the excitation driver circuit system 208 operates at a high frequency (e.g., the frequency of the carrier signal). For example, the excitation driver circuit system 208 operates at 80 megahertz (MHz). Figure 2A and 2B In some examples, the second demodulator circuit system 216 demodulates the signal received at the secondary coil 244 to obtain a primary data signal (e.g., a forward data signal, a control data signal, etc.). For example, the second demodulator circuit system 216 demodulates the signal received at the secondary coil 244 using amplitude modulation. In some examples, the second demodulator circuit system 216 uses another type of modulation (e.g., frequency modulation, phase modulation, etc.). After demodulating the signal received at the secondary coil 244 to obtain the primary data signal, the second demodulator circuit system 216 transmits the primary data signal to the second control circuit system 220.

[0088] exist Figure 2A and 2B In the example shown, the primary data signal indicates to the second control circuit system 220 whether the switch is to be driven (eg, whether the gate terminal of the switch is to be energized). For example, the primary data signal conveys switch enable (EN) state information of the switch 106. Figure 2A and 2B In the example of , the second control circuit system 220 sends a control signal to the gate driver circuit system 226 to cause the gate driver circuit system 226 to assert a signal at the driver terminal of the gate driver circuit 102 based on the state information contained in the primary data signal. In addition, the second control circuit system 220 maintains a timer corresponding to the primary data signal. Figure 2A and 2B In an example, the timer indicates the end of the first sub-period of the communication period. For example, the timer measures the period between the start of the second sub-period of the first communication period and the end of the first sub-period of the second communication period. Based on the expiration of the timer, the second control circuit system 220 initiates the second sub-period of the periodic communication.

[0089] exist Figure 2A and 2B In the example shown, the second die 138 includes the voltage sensing circuitry 224, the first comparator 228, and the second comparator 230 as described above. Figure 2A and 2BIn some examples, the voltage sensing circuitry 224 monitors a voltage at a first secondary-side power supply terminal of the gate driver circuit 102. In some examples, the voltage sensing circuitry 224 monitors a voltage at a second secondary-side power supply terminal. Based on the voltage at one or more of the first secondary-side power supply terminal or the second secondary-side power supply terminal, the voltage sensing circuitry 224 generates a power status signal indicating whether the voltage at one or more of the first secondary-side power supply terminal or the second secondary-side power supply terminal satisfies (e.g., is less than, less than or equal to, etc.) a low voltage threshold.

[0090] For example, if the voltage at one or more of the first secondary-side power supply terminal or the second secondary-side power supply terminal satisfies the low voltage threshold, the voltage sensing circuit system 224 outputs the power status signal as a logic high value (e.g., 5V, 1, etc.) to indicate a low power condition associated with the gate driver circuit 102. For another example, if the voltage at one or more of the first secondary-side power supply terminal or the second secondary-side power supply terminal does not satisfy the low voltage threshold, the voltage sensing circuit system 224 outputs the power status signal as a logic low value (e.g., 0V, 0, etc.) to indicate the lack of a low power condition associated with the gate driver circuit 102. Based on the power status signal, the second control circuit system 220 communicates the power status to the encoder circuit system 234.

[0091] exist Figure 2A and 2B In the example shown, the non-inverting input terminal of the first comparator 228 monitors the voltage at the fault comparator terminal of the gate driver circuit 102. For example, the fault comparator terminal of the gate driver circuit 102 receives the signal output from the current sensor 116. Figure 2A and 2B In the example of , the first comparator 228 compares the voltage at the fault comparator terminal of the gate driver circuit 102 with the reference voltage generated by the reference voltage source 232. Based on the comparison, the first comparator 228 outputs a fault signal to the second control circuit system 220.

[0092] For example, if the voltage at the fault comparator terminal satisfies (e.g., is greater than, is greater than or equal to, etc.) the reference voltage, the first comparator 228 outputs the fault signal as a logic high value (e.g., 5V, 1, etc.) to indicate a fault condition associated with a power switch (e.g., switch 106) managed by the gate driver circuit 102. For another example, if the voltage at the fault comparator terminal does not satisfy (e.g., is less than) the reference voltage, the first comparator 228 outputs the fault signal as a logic low value (e.g., 0V, 0, etc.) to indicate the absence of a fault condition associated with the power switch. Based on the fault signal indicating the fault condition, the second control circuit system 220 causes the gate driver circuit system 226 to disable (e.g., turn off) the switch managed by the gate driver circuit 102, regardless of the state information conveyed by the primary data signal from the first die 136. Thus, the second control circuitry 220 can ensure that the switch (eg, switch 106 ) managed by the gate driver circuit 102 and any downstream circuitry (eg, load 132 ) is protected from hazardous conditions (eg, overcurrent events).

[0093] exist Figure 2A and 2B In the example shown, the non-inverting input terminal of the second comparator 230 monitors the voltage at the alarm comparator terminal of the gate driver circuit 102. For example, the alarm comparator terminal of the gate driver circuit 102 receives the signal output from the current sensor 116. Figure 2A and 2B In the example of , the second comparator 230 compares the voltage at the alarm comparator terminal of the gate driver circuit 102 with the reference voltage generated by the reference voltage source 232. Based on the comparison, the second comparator 230 outputs an alarm signal to the second control circuit system 220.

[0094] For example, if the voltage at the alarm comparator terminal satisfies (e.g., is greater than, is greater than or equal to, etc.) the reference voltage, the second comparator 230 outputs the alarm signal as a logic high value (e.g., 5V, 1, etc.) to indicate an alarm condition associated with a power switch (e.g., switch 106) managed by the gate driver circuit 102. For another example, if the voltage at the alarm comparator terminal does not satisfy (e.g., is less than) the reference voltage, the second comparator 230 outputs the alarm signal as a logic low value (e.g., 0V, 0, etc.) to indicate the lack of an alarm condition associated with the power switch. Based on the alarm signal, the second control circuit system 220 transmits the alarm status to the encoder circuit system 234. Figure 2A and 2B In the example of FIG. 2 , the second control circuit system 220 does not control the gate driver circuit system 226 based on the alarm signal.

[0095] As described above, the second control circuit system 220 maintains a timer corresponding to the primary data signal (e.g., indicating the end of the first sub-period of the communication period). Based on the expiration of the timer, the second control circuit system 220 sends at least one of power status information, fault status information, or alarm status information to the first die 136. For example, the second control circuit system 220 sends at least one of power status information, fault status information, or alarm status information to the encoder circuit system 234. Figure 2A and 2B In the example, the power status information, the fault status information and the alarm status information are based on the power status signal, the fault signal and the alarm signal, respectively.

[0096] exist Figure 2A and 2B In the example shown, the encoder circuit system 234 serializes at least one of the power state information, the fault state information, or the alarm state information to encode at least one of the power state information, the fault state information, or the alarm state information into a secondary data signal (e.g., a backward data signal, a feedback data signal, etc.). For example, the secondary data signal (e.g., the backward data signal, the feedback data signal, etc.) is a serialized data stream of three or four bits of data. For example, if the power state information indicates the voltage at one of the first secondary side power supply terminal or the second secondary side power supply terminal, the secondary data signal is a 3-bit signal, in which one bit indicates the power state information, one bit indicates the fault state information, and one bit indicates the alarm state information. For another example, if the power state information indicates the voltage at the first secondary side power supply terminal and the second secondary side power supply terminal, the secondary data signal is a 4-bit signal, in which two bits indicate the power state information, one bit indicates the fault state information, and one bit indicates the alarm state information.

[0097] exist Figure 2A and 2B In the example shown, encoder circuitry 234 utilizes synchronous communication based on the operating frequency of secondary coil 244. In some examples, encoder circuitry 234 utilizes asynchronous communication to encode at least one of power status information, fault status information, or alarm status information into a serialized data stream. Figure 2A and 2B In the example of , encoder circuitry 234 sends the secondary data signal to second modulator circuitry 236 .

[0098] exist Figure 2A and 2BIn the example shown, the second modulator circuit system 236 modulates the impedance of the circuit coupled to the secondary coil 244 over time based on the secondary data signal (e.g., the serialized data stream) from the encoder circuit system 234. For example, the second modulator circuit system 236 includes a switch coupled to the second terminal of the capacitor 238, and the switch is enabled (e.g., closed) or disabled (e.g., opened) based on the secondary data signal (e.g., the serialized data stream). Figure 2A and 2B In the example of , when the second modulator circuit system 236 enables the switch, the impedance of the circuit coupled to the secondary coil 244 is a first value, and when the second modulator circuit system 236 disables the switch, the resistance of the circuit coupled to the secondary coil 244 is a second value. In this way, the second modulator circuit system 236 modulates the impedance of the circuit coupled to the secondary coil 244 over time based on the secondary data signal (e.g., the serialized data stream) from the encoder circuit system 234.

[0099] As described above, the primary coil 242 and the secondary coil 244 are inductively coupled to each other. Therefore, changes in the load impedance on the secondary coil 244 are reflected in changes in the input impedance of the primary coil 242. Therefore, the current on the primary side of the isolation channel 240 changes based on the secondary data signal (e.g., serialized data stream) from the encoder circuit system 234. On the first die 136, the first demodulator circuit system 210 includes a resistor and measures the voltage across the resistor over time. By tracking the voltage across the resistor of the first demodulator circuit system 210 over time, the first demodulator circuit system 210 demodulates the signal received at the primary coil 242 to obtain the secondary data signal (e.g., serialized data stream). After obtaining the secondary data signal, the first demodulator circuit system 210 transmits the secondary data signal to the first control circuit system 202 and the decoder circuit system 212.

[0100] exist Figure 2A and 2B In the example shown, based on the secondary data signal, the first control circuit system 202 adjusts control of a power switch (e.g., switch 106) managed by the gate driver circuit 102. In addition, based on the secondary data signal, the decoder circuit system 212 deserializes the secondary data signal to obtain at least one of power status information, fault status information, or alarm status information. For example, the decoder circuit system 212 utilizes synchronous communication based on the operating frequency of the primary coil 242. In some examples, the decoder circuit system 212 utilizes asynchronous communication to decode at least one of the power status information, fault status information, or alarm status information from the secondary data signal. Figure 2A and 2BIn the example, the decoder circuit system 212 outputs signals (eg, feedback data signals) at the power state terminal, the fault terminal, and the alarm terminal of the gate driver circuit 102 based on the power state information, the fault state information, and the alarm state information, respectively.

[0101] As described above, the first control circuit system 202 maintains a timer corresponding to the second sub-period (e.g., indicating the end of the second sub-period). Based on the expiration of the timer corresponding to the second sub-period, the first control circuit system 202 initiates a third sub-period of periodic communication between the first die 136 and the second die 138. For example, during the third sub-period of periodic communication, the first control circuit system 202 sends a control signal to the excitation driver circuit system 208. Figure 2A and 2B In the example of FIG. 1 , based on the control signal generated by the first control circuit system 202, the excitation driver circuit system 208 operates as a converter to convert a DC power signal at the primary side power terminal of the gate driver circuit 102 into an AC power signal. Based on the AC power signal, the excitation driver circuit system 208 energizes the primary coil 242 to transfer power (e.g., a power signal) to the second die 138.

[0102] exist Figure 2A and 2B In the example shown, the second die 138 includes the rectifier circuitry 222 as described above. Figure 2A and 2B In the example of, the rectifier circuit system 222 rectifies the AC power signal received at the secondary coil 244 into a DC power signal. Therefore, the circuit disposed on the second die 138 or coupled to the second die is powered. For example, based on the DC power signal output from the rectifier circuit system 222, the circuit system on the second die 138 is powered. For another example, based on the DC power signal output from the rectifier circuit system 222, at least one capacitor (e.g., the second capacitor 118 and the third capacitor 120) coupled to the second die 138 is charged or recharged. Therefore, as described above, during the period of transmitting data through the isolation channel 240, the second die 138 remains powered.

[0103] exist Figure 2A and 2BIn the example shown, after power has been delivered through the isolation channel 240 (e.g., after the timer corresponding to the third sub-period has expired), the first control circuit system 202 causes the excitation driver circuit system 208 to energize the primary coil 242 based on the carrier signal (e.g., without modulation) for the fourth sub-period for periodic communication. For example, the fourth sub-period for periodic communication is a reset period during which the circuit systems on the first die 136 and the second die 138 can be reset for a subsequent communication period. Figure 2A and 2B In the example of FIG. 5 , after the timer corresponding to the fourth sub-period expires, the first control circuit system 202 initiates the first sub-period of the subsequent communication period.

[0104] Figure 3 Shown by Figure 2A and 2B The isolated channels of the gate driver circuit 102 of the embodiment of the present invention perform example transmission 300 of forward direction (FWD) data, backward direction (BWD) data and power in a time multiplexed manner. Figure 3 In the example, the FWD data corresponds to Figure 1 and the primary data signal described in 2. For example, the BWD data corresponds to Figure 1 and the secondary data signals described in 2. Figure 3 In the example of Figure 1 and the power signal described in 2.

[0105] exist Figure 3 In the example shown, transmission 300 occurs within a time period T (e.g., T=25 microseconds (μs)). Figure 3 In some examples, FWD data is transferred from the first die 136 to the second die 138 during a first portion of T (e.g., a first sub-period), BWD data is transferred from the second die 138 to the first die 136 during a second portion of T (e.g., a second sub-period), and power is transferred from the first die 136 to the second die 138 during a third portion of T (e.g., a third sub-period). After the power transfer, T has an idle portion (e.g., a fourth sub-period) until the end of time period T. In some examples, the FWD data, BWD data, and power are switched and / or modulated at a clock frequency (e.g., 85 MHz). Figure 3 Also shown is a magnified view of BWD data shown at 302 that is transmitted from the second die 138 at the clock frequency during a second portion of T (eg, a second sub-period).

[0106] Figure 4 is a flow chart representing at least one of example machine readable instructions or example operations 400 that may be used Figure 2Aand 2B The gate driver circuit 102 of the first die 136 may be implemented, instantiated and / or performed in accordance with an example programmable circuitry implementation. Figure 4 At least one of the example machine readable instructions or example operations 400 begins at block 402, where, during a first portion of a communication period, control circuitry disposed on the first die 136 transmits a control data signal (e.g., a signal of a first type) from the first die 136 to the second die 138 via an isolation channel. For example, at block 402, during a first portion of the communication period, the first control circuitry 202 transmits (e.g., is used to) transmit the control data signal from the first die 136 to the second die 138 via the isolation channel 240.

[0107] exist Figure 4 In the example shown, at block 404, during the second portion of the communication period, the demodulator circuit system disposed on the first die 136 senses a feedback data signal (e.g., a second type of signal) from the second die 138 based on the impedance change of the isolation channel, the feedback data signal including the serialized data. For example, at block 404, during the second portion of the communication period, the first demodulator circuit system 210 senses the feedback data signal from the second die 138 based on the impedance change of the isolation channel 240. After sensing the feedback data signal, the first demodulator circuit system 210 transmits the feedback data signal to the first control circuit system 202 and the decoder circuit system 212. In this manner, the first control circuit system 202 detects the feedback data signal.

[0108] exist Figure 4 In the example shown, at block 406, a decoder circuit system disposed on the first die 136 decodes the serialized data into a first feedback data signal and a second feedback data signal. For example, at block 406, the decoder circuit system 212 decodes the serialized data into a first feedback data signal and a second feedback data signal. Figure 4 In the example, the first feedback data signal indicates the state of the power supply voltage of the second die 138, and the second feedback data signal indicates a state associated with the operation of the power switch to be controlled based on the control signal (e.g., fault state information, alarm state information, etc.).

[0109] exist Figure 4 In the example shown, at block 408, during a third portion of the communication period, the control circuit system disposed on the first die 136 transmits a power signal (e.g., a second type of signal, a third type of signal, etc.) through the isolation channel. For example, at block 408, during the third portion of the communication period, the first control circuit system 202 transmits a power signal through the isolation channel 240. Figure 4In the example of, at block 410, during a fourth portion of the communication period, the control circuitry disposed on the first die 136 keeps the isolation channel idle. For example, at block 410, during a fourth portion of the communication period, the first control circuitry 202 keeps the isolation channel 240 idle.

[0110] exist Figure 4 In the example shown, at block 412, the control circuitry disposed on the first die 136 determines whether there are additional communication periods. For example, at block 412, the first control circuitry 202 determines whether there are additional communication periods. Based on (e.g., in response to) the first control circuitry 202 determining that there are additional communication periods (block 412: Yes), at least one of the machine-readable instructions or operations 400 returns to block 402. Based on (e.g., in response to) the first control circuitry 202 determining that there are no additional communication periods (block 412: No), at least one of the machine-readable instructions or operations 400 terminates.

[0111] Figure 5 is a flow chart representing at least one of example machine readable instructions or example operations 500 that may be used Figure 2A and 2B The example programmable circuitry implementation of the second die 138 of the gate driver circuit 102 may be implemented, instantiated, and / or performed. Figure 5 At least one of the example machine readable instructions or example operations 500 begins at block 502, where the control circuitry disposed on the second die 138 resets a timer corresponding to a control data signal (e.g., a signal of the first type). For example, at block 502, the second control circuitry 220 resets a timer corresponding to the control data signal.

[0112] exist Figure 5 In the example shown, at block 504, based on receiving the control data signal from the first die 136 through the isolation channel, the control circuit system disposed on the second die 138 starts a timer. For example, at block 504, the second control circuit system 220 starts the timer based on receiving the control data signal through the isolation channel 240. At block 506, the encoder circuit system disposed on the second die 138 encodes the feedback data signal into serialized data. For example, at block 506, the encoder circuit system 234 encodes the feedback data signal into serialized data. At block 508, based on the expiration of the timer, the control circuit system disposed on the second die 138 adjusts the impedance of the isolation channel to transmit the feedback data signal to the first die 136 through the isolation channel. For example, based on the expiration of the timer, the second control circuit system 220 adjusts the impedance of the isolation channel 240 to transmit the feedback data signal to the first die 136 through the isolation channel 240.

[0113] exist Figure 5 In the example shown, at block 510, the control circuit system disposed on the second die 138 determines whether there are additional communication periods. For example, at block 510, the second control circuit system 220 determines whether there are additional communication periods. Based on (e.g., in response to) the second control circuit system 220 determining that there are additional communication periods (block 510: Yes), at least one of the machine-readable instructions or operations 500 returns to block 502. Based on (e.g., in response to) the second control circuit system 220 determining that there are no additional communication periods (block 510: No), at least one of the machine-readable instructions or operations 500 terminates.

[0114] Figure 6 is a block diagram of an example programmable circuit system platform 600 that is configured to execute and / or instantiate Figure 4 and 5 At least one of the example machine readable instructions or example operations to implement Figure 2A and 2B The first die 136 and the second die 138 are provided. The programmable circuit system platform 600 may be, for example, an electronic control unit of a vehicle, a control circuit system of a battery or a motor of a vehicle, or any other type of computing or electronic device.

[0115] The programmable circuit system platform 600 of the illustrated example includes a programmable circuit system 612. The programmable circuit system 612 of the illustrated example is hardware. For example, the programmable circuit system 612 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired series or manufacturer. The programmable circuit system 612 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 612 implements the first die 136, the second die 138, and the isolation channel 240. For example, the first die 136 includes the first control circuit system 202, the first modulator circuit system 204, the carrier signal generator circuit system 206, the excitation driver circuit system 208, the first demodulator circuit system 210, and the decoder circuit system 212. For another example, the second die 138 includes a second demodulator circuit system 216, a second control circuit system 220, a rectifier circuit system 222, a voltage sensing circuit system 224, a gate driver circuit system 226, a first comparator 228, a second comparator 230, a reference voltage source 232, an encoder circuit system 234, a second modulator circuit system 236, and a capacitor 238. Figure 6 In the example of FIG. 2 , the isolation channel 240 includes a primary coil 242 and a secondary coil 244 .

[0116] The programmable circuit system 612 of the illustrated example includes a local memory 613 (e.g., cache, registers, etc.). The programmable circuit system 612 of the illustrated example communicates with main memories 614, 616 including a volatile memory 614 and a non-volatile memory 616 via a bus 618. The volatile memory 614 may be composed of one or more synchronous dynamic random access memories (SDRAM), dynamic random access memories (DRAM), Dynamic Random Access Memory The non-volatile memory 616 may be implemented by one or a combination of flash memory or any other desired type of memory device. Access to the main memory 614, 616 of the illustrated example is controlled by a memory controller 617. In some examples, the memory controller 617 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry for managing data flow to and from the main memory 614, 616 from any desired family or manufacturer.

[0117] The programmable circuit system platform 600 of the illustrated example also includes an interface circuit system 620. The interface circuit system 620 can be implemented by hardware that complies with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, or a peripheral component interconnect express (PCIe) interface.

[0118] In the example shown, one or more input devices 622 are connected to the interface circuitry 620. The input devices 622 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry 612. The input devices 622 may be implemented by one or a combination of, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isopoint device, or a voice recognition system.

[0119] One or more output devices 624 are also connected to the interface circuit system 620 of the illustrated example. The output device 624 can be implemented, for example, by one or a combination of a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, or a speaker. Therefore, the interface circuit system 620 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuit system such as a GPU.

[0120] The interface circuitry 620 of the illustrated example also includes a communication device, such as one or a combination of a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, or a network interface, to facilitate the exchange of data with an external machine (e.g., any kind of computing device) over a network 626. Communications may occur over, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0121] The programmable circuit system platform 600 of the illustrated example also includes one or more mass storage disks or devices 628 for storing one or more of firmware, software, or data. Examples of such mass storage disks or devices 628 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices such as flash memory devices and SSDs.

[0122] can be Figure 4 and 5 The machine-readable instructions 632 implemented by the machine-readable instructions may be stored in one or a combination of the mass storage device 628, the volatile memory 614, the non-volatile memory 616, or at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0123] Although Figure 2A and 2B The implementation is shown in Figure 1 An example embodiment of at least one of the first die 136 or the second die 138, but Figure 2A and 2BOne or more of the elements, processes or devices shown in the example can be combined, divided, rearranged, omitted, eliminated or implemented in any other manner. In addition, the first example control circuit system 202, the first example modulator circuit system 204, the example carrier signal generator circuit system 206, the example excitation driver circuit system 208, the first example demodulator circuit system 210, the example decoder circuit system 212 or more generally the first tube core 136, or the second example demodulator circuit system 216, the second example control circuit system 220, the example rectifier circuit system 222, the example voltage sensing circuit system 224, the example gate driver circuit system 226, the first example comparator 228, the second example comparator 230, the example reference voltage source 232, the example encoder circuit system 234, the second example modulator circuit system 236, the example capacitor 238 or more generally the second tube core 138 can be implemented by hardware alone or by a combination of hardware and software and firmware. Thus, for example, the first example control circuit system 202, the first example modulator circuit system 204, the example carrier signal generator circuit system 206, the example excitation driver circuit system 208, the first example demodulator circuit system 210, the example decoder circuit system 212 or more generally the first die 136, or the second example demodulator circuit system 216, the second example control circuit system 220, the example rectifier circuit system 222, the example voltage sensing circuit system 224, the example gate driver circuit system 226, the first example comparator 228, the second example comparator 230, the example reference rectifier circuit system 232, the example voltage sensing circuit system 234, the example gate driver circuit system 23 ... Any of the voltage source 232, the example encoder circuit system 234, the second example modulator circuit system 236, the example capacitor 238, or more generally the second die 138, may be implemented by programmable circuit system in combination with one or more machine-readable instructions (e.g., firmware or software), processor circuit system, analog circuit, digital circuit, logic circuit, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic device (PLD), or field programmable logic device (FPLD) (e.g., FPGA). Further, Figure 2A and 2B At least one of the first example die 136 or the second example die 138 may also include in addition to or instead of Figure 2A and 2B One or more elements, processes or devices other than those shown, or more than one of any or all of the elements, processes and devices shown may be included.

[0124] Figure 4 and 5 The diagram shows a representation that can be executed by a programmable circuit system to implement and / or instantiate Figure 2A and 2BA flowchart of example machine-readable instructions or representations of instructions that may be performed by programmable circuitry to implement and / or instantiate at least one of the first die 136 or the second die 138 Figure 2A and 2B A flowchart of an example operation of at least one of the first die 136 or the second die 138. The machine-readable instructions may be for programmable circuitry (e.g., in conjunction with Figure 6 The machine-readable instructions may be one or more executable programs or a portion of one or more executable programs executed by the programmable circuit system 612 shown in the example programmable circuit system platform 600 described herein, and may be one or more functions or a portion of functions performed by the example programmable circuit system (e.g., FPGA). In some examples, the machine-readable instructions cause an operation, task, etc. to be performed or performed in an automated manner in the real world. As used herein, "automated" means without human intervention.

[0125] The program may be embodied in instructions (e.g., at least one of software or firmware) stored on one or more of at least one non-transitory computer-readable storage medium or at least one machine-readable storage medium, such as a cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or optical disk (e.g., a Blu-ray disk, a compact disk (CD), a digital versatile disk (DVD), etc.), a redundant array of independent disks (RAID), registers, ROM, a solid-state drive (SSD), SSD memory, a non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), a volatile memory (e.g., any type of random access memory (RAM), etc.), or one or a combination of any other storage devices or storage disks. The instructions of at least one of the non-transitory computer-readable or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated by one or more hardware devices other than the programmable circuit system or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with at least one of a human or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, a non-transitory computer-readable storage medium may include one or more media. In addition, although reference is made to Figure 4 and 5 The flowchart shown describes an example procedure, but an implementation may alternatively be used. Figure 2A and 2B Many other methods of at least one of the first example die 136 or the second example die 138 of the present invention. For example, the execution order of the blocks of the flowchart may be changed, or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete analog circuitry, discrete digital circuitry, integrated analog circuitry, integrated digital circuitry, FPGA, ASIC, comparator, operational amplifier (op-amp), logic circuit, etc.) configured to perform corresponding operations without executing software or firmware. The programmable circuitry may be distributed in different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.). For example, the programmable circuitry may be one or a combination of a CPU or an FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed on multiple servers in a server rack, multiple sub-processors distributed on one or more server racks, etc., or any combination thereof.

[0126] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bit stream (e.g., a computer-readable bit stream, a machine-readable bit stream, etc.), etc.), or a data structure (e.g., a portion of an instruction, a code, a representation of a code, etc.) that can be used to create, manufacture, or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located in the same or different locations (e.g., in the cloud, an edge device, etc.) of a network or collection of networks. The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, etc., so that they can be directly read, interpreted, and / or executed by a computing device or other machine. For example, machine-readable instructions may be stored in multiple parts that are separately compressed, encrypted, or stored on separate computing devices, and the parts, when decrypted, decompressed, or combined, form a computer-executable or machine-executable instruction set that implements one or more functions or operations that may together form, for example, the procedures described herein.

[0127] In another example, the machine-readable instructions may be stored in a state in which they can be read by the programmable circuit system, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., may need to be added in order to execute the machine-readable instructions on a particular computing device or another device. In another example, the machine-readable instructions or corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, machine-readable, computer-readable, or machine-readable media may include one or a combination of instructions and programs, regardless of the specific format or state of the machine-readable instructions or programs.

[0128] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0129] As mentioned above, Figure 4 and 5The example operations of may be implemented using executable instructions (e.g., at least one of the computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device or storage disk, and exclude propagating signals and exclude transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memories, read-only memories (ROMs), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, temporarily, temporarily buffered, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined to include any physical (mechanical, magnetic, electromechanical or electrical) hardware to retain information over a period of time, but exclude propagating signals and exclude transmission media. Examples of non-transitory computer-readable storage devices and non-transitory machine-readable storage devices include one or a combination of any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as one or a combination of a mechanical, electromechanical or electrical device, hardware, or circuit system, which may or may not be configured by computer-readable instructions, machine-readable instructions, etc., or is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0130] "Include" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of "includes" or "comprising" (e.g., comprises, comprising, includes, including, having, etc.) as a guide or in any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or reference. As used herein, when the phrase "at least" is used as a transitional term, such as in the guide of a claim, it is open in the same manner as the terms "includes" and "comprising" are open. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" refers to an embodiment that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A and B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" refers to embodiments that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0131] As used herein, singular references (e.g., "a / an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the objects. The terms "a" (or an), "one or more", and "at least one" are used interchangeably herein. In addition, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Moreover, although individual features may be included in different examples or technical solutions, these features may be combined, and the inclusion in different examples or technical solutions does not imply that the combination of features is not feasible and / or disadvantageous.

[0132] As used herein, unless otherwise indicated, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between elements referenced by at least one of a connection reference or relative movement between those elements. Thus, connection references do not necessarily infer that two elements are directly connected or in fixed relation to each other.

[0133] Unless otherwise specifically stated, descriptors such as "first", "second", "third", etc. are used herein without imposing or otherwise indicating a priority in a list, a physical order, a meaning of arrangement, or ordering in any way, but are merely used as at least one of a label or arbitrary name to distinguish elements to facilitate understanding of the described examples. In some examples, the descriptor "first" may be used to refer to an element in a specific implementation, while the same element may be referred to in the technical solution by a different descriptor such as "second" or "third". In such cases, such descriptors are only used to clearly identify those elements within the context of the discussion (e.g., within the technical solution), where the elements may, for example, otherwise share the same name.

[0134] As used herein, the phrase "communication," including variations thereof, encompasses one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-time events.

[0135] As used herein, "programmable circuitry" is defined as including: (i) one or more special-purpose circuits (e.g., application-specific circuits (ASICs)) that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include a programmable microprocessor, such as a central processor unit (CPU), which can execute a first instruction to perform one or more operations or functions; a field programmable gate array (FPGA), which can be programmed with a second instruction to configure and / or construct the FPGA to instantiate one or more operations or functions corresponding to the first instruction; a graphics processor unit (GPU), which can execute a first instruction to perform one or more operations or functions; a digital signal processor (DSP), which can execute a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers, which can execute a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application specific integrated circuit (ASIC). For example, the XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and orchestration technology (e.g., an application programming interface (API)) that can distribute computing tasks to any of the multiple types of programmable circuitry that is suitable and available to perform computing tasks.

[0136] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, a programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on a chip (SoC), etc.

[0137] In this specification, the term "coupled" may encompass connections, communications, or signal paths that support a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, but the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0138] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0139] In this specification and claims, a "circuitry" described may include one or more circuits. A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., at least one of a resistor, capacitor, or inductor), or one or more sources (e.g., at least one of a voltage source or a current source) may alternatively include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements or sources to form the described structure at the time of manufacture or after the manufacturing time, for example, by at least one of an end user or a third party.

[0140] The circuits described herein can be reconfigured to include replaced components to provide functions that are at least partially similar to the functions available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements that are coupled in series or in parallel to provide the impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described as a single component in this article may alternatively be a plurality of resistors or capacitors coupled in series between two nodes that are the same as a single resistor or capacitor. Although some elements of the described examples are included in the integrated circuit and other elements are outside the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit may be included in the integrated circuit, and some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in / on the same printed circuit board.

[0141] The use of the phrase "ground" in the foregoing description includes at least one of chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0142] The described embodiments can be modified and other embodiments are possible within the scope of the claims.

[0143] As can be understood from the foregoing, example systems, devices, articles, and methods for transmitting power signals, primary data signals, and secondary data signals through an isolation barrier via a single isolation channel in an integrated circuit have been described. For example, by time-division multiplexing the signals transmitted through the isolation channel, the examples described herein allow the isolation gate driver circuit to transmit control signals, fault diagnostic feedback, and power through the isolation barrier at a reduced footprint and monetary cost. By utilizing a single isolation channel, both data (e.g., forward data and backward data) and power are transmitted through the same isolation channel, thereby eliminating the need for multiple isolation channels for transmitting multiple signals. Therefore, relative to other isolation gate driver circuits that use multiple isolation channels to transmit multiple signals through an isolation barrier, the footprint and monetary cost of implementing an integrated isolation gate driver circuit are reduced. The described systems, devices, articles, and methods improve the efficiency of using computing devices by facilitating the implementation of an isolation gate driver circuit with a smaller footprint. For example, by reducing the footprint size of the isolation gate driver circuit, the examples described herein help to improve safety in a wider range of applications. The described systems, devices, articles, and methods also relate to one or more improvements in the operation of machines such as computers or other electronic, electromechanical, or mechanical devices.

Claims

1. A device comprising: a first die having a first terminal; a second die having a second terminal; an isolation channel coupled between the first terminal of the first die and the second terminal of the second die; as well as A control circuit system is arranged on the first tube core, and the control circuit system is used to transmit a power signal through the isolation channel, and to transmit a control data signal through the isolation channel, and / or to detect a feedback data signal through the isolation channel.

2. The apparatus of claim 1, wherein the isolation channel comprises a transformer.

3. The apparatus of claim 1, wherein the isolated channel comprises a bidirectional communication channel. 4 . The apparatus of claim 1 , wherein the feedback data signal indicates at least one of a first state of a supply voltage of the second die or a second state associated with operation of a power switch to be controlled based on the control data signal.

5. The apparatus of claim 1 , wherein the control circuitry is configured to: transmitting the control data signal through the isolation channel; and The power signal is transmitted through the isolation channel.

6. The apparatus of claim 1 , wherein the control circuitry is configured to transmit the control data signal through the isolation channel, and the apparatus further comprises a demodulator circuitry disposed on the first die, the demodulator circuitry being configured to: sensing the feedback data signal based on a change in impedance of the isolation channel; and The feedback data signal is transmitted to the control circuitry.

7. The apparatus of claim 6, wherein the feedback data signal comprises serialized data of a first feedback data signal and a second feedback data signal, and the apparatus further comprises a decoder circuit system disposed on the first die, the decoder circuit system being configured to decode the serialized data into the first feedback data signal and the second feedback data signal.

8. The apparatus of claim 1, wherein the control circuitry is configured to: transmitting the control data signal over the isolation channel during a first portion of a communication period; detecting the feedback data signal during a second portion of the communication period; and The power signal is transmitted over the isolation channel during a third portion of the communication period.

9. The apparatus of claim 1 , wherein the control circuitry is a first control circuitry, and the apparatus further comprises a second control circuitry disposed on the second die, the second control circuitry being configured to: resetting a timer at each communication period, the timer corresponding to the control data signal; and Based on expiration of the timer, an impedance of the isolation channel is adjusted to transmit the feedback data signal through the isolation channel.

10. The apparatus of claim 9, wherein the feedback data signal comprises serialized data of a first feedback data signal and a second feedback data signal, and the apparatus further comprises an encoder circuit system disposed on the second die, the encoder circuit system encoding the first feedback data signal and the second feedback data signal into the serialized data.

11. A system comprising: a processor integrated circuit IC having an output terminal and an input terminal; a gate driver IC having an isolation channel, a first output terminal on a first side of the isolation channel, a second output terminal on a second side of the isolation channel, and an input terminal on the first side of the isolation channel, the first output terminal of the gate driver IC being coupled to the input terminal of the processor IC, the input terminal of the gate driver IC being coupled to the output terminal of the processor IC; as well as a power switch having a control terminal coupled to the second output terminal of the gate driver IC, the gate driver IC being configured to: (a) transmitting a control data signal for the power switch through the isolation channel, and / or (b) providing a feedback data signal received from the second side of the isolation channel to the processor IC, the feedback data signal indicating a state associated with the power switch; as well as A power signal for driving the power switch is transmitted through the isolation channel.

12. The system of claim 11, wherein the gate driver IC is used to: transmitting the control data signal of the power switch through the isolation channel; and Subsequently, the power signal for driving the power switch is transmitted through the isolation channel.

13. The system of claim 11, wherein the gate driver IC is used to: sensing the feedback data signal based on a change in impedance of the isolation channel; and The feedback data signal is provided to the processor IC.

14. The system of claim 13, wherein the feedback data signal comprises serialized data of a first feedback data signal and a second feedback data signal, and the gate driver IC is configured to: decoding the serialized data into the first feedback data signal and the second feedback data signal; and The first feedback data signal is provided to the processor IC, and the second feedback data signal is provided to the processor IC.

15. The system of claim 11, wherein the gate driver IC is used to: transmitting the control data signal over the isolation channel during a first portion of a communication period; detecting the feedback data signal during a second portion of the communication period; and The power signal is transmitted over the isolation channel during a third portion of the communication period.

16. The system of claim 11, wherein the gate driver IC is used to: resetting a timer at each communication period, the timer corresponding to the control data signal; and Based on expiration of the timer, an impedance of the isolation channel is adjusted to transmit the feedback data signal through the isolation channel.

17. An apparatus comprising: a first die having a first terminal; a second die having a second terminal; an isolation channel coupled between the first terminal of the first die and the second terminal of the second die; as well as A control circuit system is disposed on the first die, wherein the control circuit system is used to: transmitting a control data signal through the isolation channel during a first portion of the communication period; detecting a feedback data signal during a second portion of the communication period; as well as A power signal is transmitted over the isolation channel during a third portion of the communication period.

18. The apparatus of claim 17, wherein the control circuitry is a first control circuitry, and the apparatus further comprises a second control circuitry disposed on the second die, the second control circuitry being configured to: resetting a timer at each communication period, the timer corresponding to the control data signal; and Based on expiration of the timer, an impedance of the isolation channel is adjusted to transmit the feedback data signal through the isolation channel.

19. The apparatus of claim 17, wherein the feedback data signal comprises serialized data of a first feedback data signal and a second feedback data signal, and the apparatus further comprises an encoder circuit system disposed on the second die, the encoder circuit system encoding the first feedback data signal and the second feedback data signal into the serialized data.

20. The apparatus of claim 17, wherein the feedback data signal indicates at least one of a first state of a supply voltage of the second die or a second state associated with operation of a power switch to be controlled based on the control data signal.

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