Interleaving method and communication device

Abstract

The invention provides an interleaving method and a communication device, and the method comprises the steps: carrying out the interleaving of an encoded bit sequence through a first indication sequence, mapping the interleaved bit sequence to a QAM (Quadrature Amplitude Modulation) symbol, and outputting the QAM symbol. Wherein the first indication sequence is used for indicating a corresponding relationship between M columns of the LDPC basis matrix and R energy levels contained in a quadrature amplitude modulation (QAM) symbol. Through the interleaving method provided by the embodiment of the invention, extra protection can be provided for the most unreliable bit, and the communication performance is improved.

Description

Technical Field

[0001] The present application relates to the field of channel coding, and more specifically, to an interleaving method in channel coding and a related communication device. Background Art

[0002] The key performance indicator (KPI) of current wireless communication is the block error rate (BLER), which is the probability that at least one of all transmitted bits is erroneous. The transmitted bits must be all correct, so the BLER is mainly determined by the least reliable bit. The existing information bit protection does not provide additional protection for the least reliable bit, so the BLER of wireless communication cannot be effectively improved. Summary of the invention

[0003] The present application provides an interleaving method and a communication device, which can improve the communication performance of wireless communications.

[0004] In a first aspect, an interleaving method is provided, the method comprising: obtaining an LDPC base matrix, the LDPC base matrix comprising M columns; encoding a first bit sequence according to the LDPC base matrix to obtain a second bit sequence; bit-interleaving the second bit sequence according to a first indicator sequence to obtain a third bit sequence, the first indicator sequence being used to indicate a correspondence between the M columns and R energy levels contained in a QAM symbol, M and R being positive integers; mapping bits in the third bit sequence to QAM symbols; and outputting modulated QAM symbols.

[0005] It should be noted that the present application uses the R energy levels contained in the QAM symbol as an example to illustrate the interleaving method of the present application, but the present application does not limit the first indication sequence to indicate the correspondence between the M columns and the R energy levels contained in the QAM symbol. The first indication sequence can also be used to indicate the correspondence between other multiple energy levels and bits. For example, the correspondence between streams (layers) with different reliability levels and bits in the multiple-input multiple-output (MIMO) technology, the correspondence between bits with different reliability levels in cascade coding, etc., can all use the interleaving method provided by the present application to correspond to the energy level. Alternatively, the interleaving method provided by the present application can also be used for scenarios where multiple technologies are applied simultaneously. For example, the high-order modulation scheme in the MIMO low-energy level stream can also correspond to the energy level and then use the interleaving method of the present application to correspond to the energy level and the bit.

[0006] Exemplarily, the M columns are columns corresponding to the lowest code rate supported by the LDPC base matrix or columns corresponding to the highest code rate supported by the LDPC base matrix.

[0007] Through the above method, the bit sequence can be interleaved and mapped according to the first indication sequence, the energy level of the QAM symbol mapped by the bits corresponding to the columns of the LDPC base matrix can be controlled, and the communication performance of wireless communication can be improved.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the first indication sequence may satisfy at least one of the following features:

[0009] The elements in the first indicator sequence correspond one-to-one to the columns of the LDPC base matrix; the number S of elements in the first indicator sequence is the same as the number of M columns excluding punctured columns; the smaller the sequence number of the element in the first indicator sequence, the higher the corresponding energy level.

[0010] Exemplarily, the serial number of the element in the first indication sequence may also be understood as the position of the element in the first indication sequence.

[0011] The smaller the sequence number of the element in the first indication sequence, the higher the corresponding energy level. Specifically, the smaller the sequence number of the element in the first indication sequence, the lower the column weight of the column corresponding to the element, and the higher the energy level corresponding to the column corresponding to the element.

[0012] It can be seen that the closer the position of an element in the first indication sequence is, the higher the energy level of the column corresponding to the element is.

[0013] In combination with the first aspect, in some implementations of the first aspect, the first indicator sequence is used to indicate the correspondence between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate the correspondence between K intervals and R energy levels, K is a positive integer greater than 2. The K intervals are re-divided according to the columns of the M columns.

[0014] For example, the K intervals mentioned above may be [d 1 ,d 2 ]、[d 3 ,d 4 ], …, [d 2k-5 ,d 2k-4 ]、[d 2k-3 ,d 2k-2 ]、[d 2k-1 ,d 2k ]; where [d 2k-3 ,d 2k-2 The maximum value d in ] 2k-2 Less than [d 2k-1 ,d2k ] is the minimum value d 2k-1 , and [d 2k-3 ,d 2k-2 ] is the minimum value d 2k-3 Greater than [d 2k-5 ,d 2k-4 The maximum value d in ] 2k-4 ,

[0015] Among them, the first interval [d 1 ,d 2 ] includes M1 columns of M1 columns, the second interval [d 3 ,d 4 ] includes M2 columns of M2 columns; ...; the K-2th interval [d 2k-5 ,d 2k-4 ]Including M K-2 M K-2 The K-1th interval [d 2k-3 ,d 2k-2 ]Including M K-1 M K-1 The Kth interval [d 2k-1 ,d 2k ]Including M K M K The M1 columns, the M2 columns, ..., the M K-2 Columns, the M K-1 Columns, the M K columns belong to the above M columns.

[0016] Specifically, the bits of the columns included in each of the K intervals are mapped to the same energy level of the QAM symbol.

[0017] Optionally, the above K intervals may also be K sets.

[0018] The above method performs bit mapping according to column weight, which can provide additional protection for the least reliable bits and improve communication performance.

[0019] In combination with the first aspect, in some implementations of the first aspect, the first indicator sequence is used to indicate the correspondence between the M columns and the R energy levels contained in the QAM symbol, including: the first indicator sequence is used to indicate the correspondence between P sets and R energy levels, where P is a positive integer greater than 2. The P sets are divided according to the types of the M columns, and the types of the M columns include: information columns, core check columns, and extended check columns.

[0020] Exemplarily, the P sets include the first set and / or the second set and / or the third set. For example, the first set includes information columns, the second set includes core check columns, and the third set includes extended check columns; or, the first set includes information columns and core check columns, and the second set includes extended check columns.

[0021] Specifically, the bits of the columns included in each of the P sets are mapped to the same energy level of the QAM symbol.

[0022] Optionally, the multiple columns included in the first set, the second set, or the third set in the above P sets are arranged in order from small to large column weights. Alternatively, it can be understood that the lower the column weight of the multiple columns included in the first set, the second set, or the third set in the above P sets, the higher the corresponding energy in the same energy level of the QAM symbol.

[0023] The above method can take into account the protection of information bits and always map the most important information to the highest energy level of the QAM symbol. In addition, the energy levels corresponding to the information bits can be further refined to provide additional protection for unreliable bits in the information bits, thereby improving communication performance.

[0024] In combination with the first aspect, in certain implementations of the first aspect, the above-mentioned bit interleaving of the second bit sequence according to the first indication sequence to obtain the third bit sequence includes: performing a first interleaving of the second bit sequence according to the first indication sequence to obtain a fourth bit sequence; and performing row-column interleaving of the fourth bit sequence to obtain the above-mentioned third bit sequence.

[0025] Exemplarily, the first interleaving is as follows:

[0026] Assume that the second bit sequence is e, the fourth bit sequence is e1, and e1 and e satisfy the following relationship:

[0027]

[0028] Where S represents the number of elements in the first indicator sequence, j represents the index of the sequence number of the element contained in the first indicator sequence, s(j) represents the jth element of the first indicator sequence, and Z c is the lift value of the LDPC basis matrix.

[0029] The first interleaving may be performed before or after the second bit sequence is circularly buffered.

[0030] In combination with the first aspect, in some implementations of the first aspect, the mapping of bits in the third bit sequence to QAM symbols includes: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, the at least one fourth column and the at least one fifth column belonging to the M columns. The column weight of the at least one fourth column is less than the column weight of the at least one fifth column and the first energy level is higher than the second energy level.

[0031] Through the above method, the bits of columns with low column weight are mapped to the high energy level of the QAM symbol, and the bits of columns with high column weight are mapped to the low energy level of the QAM symbol, which provides additional protection for the most unreliable bits, reduces the BLER of data transmission, and improves the wireless communication performance.

[0032] In a second aspect, an interleaving method is provided, the method comprising: obtaining a first LDPC base matrix, the first LDPC base matrix comprising M columns, the M columns being divided into K intervals according to a column variable, the column variable being a column weight or a column type of a first submatrix, the column type comprising an information column, a core check column, and an extended check column, the first submatrix being a partial or complete matrix of the above-mentioned first LDPC base matrix; encoding a first bit sequence according to the first LDPC base matrix to obtain a second bit sequence; performing bit interleaving on the second bit sequence to obtain a third bit sequence; mapping bits in the third bit sequence to QAM symbols; and outputting modulated QAM symbols.

[0033] It should be noted that the present application uses the R energy levels contained in the QAM symbol as an example to illustrate the interleaving method of the present application, but the present application does not limit the first indication sequence to indicate the correspondence between the M columns and the R energy levels contained in the QAM symbol. The first indication sequence can also be used to indicate the correspondence between other multiple energy levels and bits. For example, the correspondence between streams (layers) with different reliability levels and bits in the multiple-input multiple-output (MIMO) technology, the correspondence between bits with different reliability levels in cascade coding, etc., can all use the interleaving method provided by the present application to correspond to the energy level. Alternatively, the interleaving method provided by the present application can also be used for scenarios where multiple technologies are applied simultaneously. For example, the high-order modulation scheme in the MIMO low-energy level stream can also correspond to the energy level and then use the interleaving method of the present application to correspond to the energy level and the bit.

[0034] In combination with the second aspect, in certain implementations of the second aspect, when the above-mentioned column variable is the column weight of the first basis matrix, the K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of at least one second column of the second interval is less than the minimum column weight of at least one first column of the first interval, the minimum column weight of at least one second column of the second interval is greater than the maximum column weight of at least one third column of the third interval, the number of columns of any column in the at least one third column is greater than the number of columns of any column in the at least one second column, and the number of columns of any column in the at least one second column is greater than the number of columns of any column in the at least one first column.

[0035] Exemplarily, the smaller the column weight of the K intervals, the higher the corresponding energy level.

[0036] The first submatrix is ​​a matrix corresponding to the lowest code rate supported by the first LDPC base matrix or a matrix corresponding to the highest code rate supported by the first LDPC base matrix.

[0037] The column weight of the first LDPC base matrix shown in the above method presents a certain regularity. As the number of columns increases, the column weight decreases. After subsequent bit interleaving and mapping, the energy level of the QAM symbol mapped by the bits corresponding to the columns of the first LDPC base matrix can be controlled, thereby improving the communication performance of wireless communication.

[0038] In combination with the second aspect, in certain implementations of the second aspect, when the above-mentioned column variable is a column type, the above-mentioned K intervals include a first interval and / or a second interval and / or a third interval, and the column weight of at least one column included in the first interval and / or the second interval and / or the third interval decreases as the number of columns increases.

[0039] Exemplarily, the first interval includes an information column, the second interval includes a core check column, and the third interval includes an extended check column; or, the first interval includes an information column and a core check column, and the second interval includes an extended check column.

[0040] In conjunction with the second aspect, in some implementations of the second aspect, the first LDPC base matrix includes N rows, the i-th row of the N rows corresponds to an indicator sequence θ(i),

[0041] When θ(i)>0, it means that when the first LDPC base matrix is ​​expanded from a high code rate to a low code rate, the i-th row is related to the θ(i)-th row, and the i-th row is obtained by eliminating the θ(i)-th row. At this time, the expansion of the i-th row will not increase the column weight of the columns of the first LDPC base matrix; when θ(i)=0, it means that when the first LDPC base matrix is ​​expanded from a high code rate to a low code rate, the i-th row is independent of other rows of the first LDPC base matrix. At this time, the expansion of the i-th row will increase the column weight of the columns of the first LDPC base matrix. The rows of the above-mentioned first submatrix are all rows corresponding to θ(i)=0 in the above-mentioned N rows, and the columns of the above-mentioned first submatrix include information columns and core check columns.

[0042] By using the above method, the column weight of the first submatrix included in the expanded first LDPC base matrix can be quickly calculated, and the first LDPC base matrix that conforms to the above column weight variation rule can be reconstructed according to the column weight of the first submatrix.

[0043] Exemplarily, the extended check column may be a default column with the lowest column weight. For example, the extended check column is located in a region with the largest number of columns in the first LDPC base matrix.

[0044] In combination with the second aspect, in some implementations of the second aspect, the bit interleaving of the second bit sequence to obtain the third bit sequence includes:

[0045] Assume that the second bit sequence is e, the third bit sequence is f, and f and e satisfy the following relationship:

[0046]

[0047] Where, E represents the transmission length of the second bit sequence or the third bit sequence, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol.

[0048] The above bit interleaving can also be called reverse row-column interleaving.

[0049] In combination with the second aspect, in some implementations of the second aspect, the mapping of bits in the third bit sequence to QAM symbols includes: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, the at least one fourth column and the at least one fifth column belonging to the M columns. The column weight of the at least one fourth column is less than the column weight of the at least one fifth column and the first energy level is higher than the second energy level.

[0050] Through the above method, the bits of the columns with low column weight of the first LDPC base matrix are mapped to the high energy level of the QAM symbol, and the bits of the columns with high column weight are mapped to the low energy level of the QAM symbol, which provides additional protection for the most unreliable bits, reduces the BLER of data transmission, and improves the wireless communication performance.

[0051] In a third aspect, a communication device is provided, wherein the communication device has the function of implementing the method of the first aspect or the second aspect, or the method in any possible implementation of the first aspect or the second aspect. The function can be implemented by hardware, or can be implemented by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0052] In a fourth aspect, the present application provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, wherein the at least one memory is used to store a computer program or instruction, and the at least one processor is used to call and run the computer program or instruction from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation thereof, or executes the method in the second aspect or any possible implementation thereof.

[0053] In one example, the communication device described in the third aspect or the fourth aspect may be a coding device.

[0054] In a fifth aspect, the present application provides a communication device, including a communication interface and a circuit, wherein the communication interface is used to receive a first bit sequence to be encoded, and input the first bit sequence to the circuit; the circuit encodes and bit interleaves the first bit sequence based on the interleaving method provided by the present application, and maps a third bit sequence obtained by bit interleaving to a QAM symbol; the communication interface is also used to output the modulated QAM symbol. Exemplarily, the communication device in the fifth aspect is a coding device.

[0055] In a sixth aspect, a communication device is provided, comprising a communication interface and a circuit, wherein the communication interface is used to receive a QAM symbol to be demodulated and input the QAM symbol to the circuit. Exemplarily, the communication device in the sixth aspect is a decoding device.

[0056] In a seventh aspect, the present application provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer, the method in the first aspect or any possible implementation thereof is implemented, or the method in the second aspect or any possible implementation thereof is implemented.

[0057] In an eighth aspect, the present application provides a computer program product, comprising a computer program code, which, when executed on a computer, enables the method in the first aspect or any possible implementation thereof to be implemented, or enables the method in the second aspect or any possible implementation thereof to be implemented.

[0058] In a ninth aspect, the present application provides a wireless communication system, comprising a communication device as in any one of aspects 3 to 6, such as an encoding device and / or a decoding device. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Schematic diagram of an LDPC check matrix H.

[0060] Figure 2 is the Tanner graph of a LDPC check matrix H.

[0061] Figure 3 A schematic diagram of the structure of the LDPC base matrix.

[0062] Figure 4 A schematic diagram of the information transmission process.

[0063] Figure 5 This is an example of information bit protection for LDPC.

[0064] Figure 6 Schematic diagram of a system architecture 100 applicable to an embodiment of the present application.

[0065] Figure 7 A schematic flowchart of an interleaving method 200 provided in the present application.

[0066] Figure 8 A schematic diagram of a first indication sequence provided in the present application.

[0067] Fig. 9 A schematic diagram of another first indication sequence provided in the present application.

[0068] Fig.10 A schematic diagram of another first indication sequence provided in the present application.

[0069] Fig.11 A schematic flow chart of a communication method 300 provided in the present application.

[0070] Fig.12 A schematic diagram of a second LDPC base matrix provided in this application.

[0071] Fig.13 A schematic diagram of another second LDPC base matrix provided in this application.

[0072] Fig.14 This is a performance simulation comparison chart of the interleaving method 200, the communication method 300 and the row-column interleaving method provided in the present application.

[0073] Fig.15 A schematic structural diagram of a communication device provided in this application.

[0074] Fig.16 A schematic structural diagram of another communication device provided in this application.

[0075] Fig.17 A schematic structural diagram of yet another communication device provided in the present application. DETAILED DESCRIPTION

[0076] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0077] In order to facilitate understanding of the solution of the present application, the terms involved in the present application are first introduced.

[0078] 1. Low density parity check (LDPC) code

[0079] LDPC code is a linear block code, and its check matrix is ​​a sparse matrix. When the code length is long, the number of zero elements in the LDPC check matrix is ​​much greater than the number of non-zero elements, or in other words, the row weight and column weight of the check matrix are very small numbers compared to the LDPC code length. Among them, the LDPC code with an information bit sequence length equal to k and a code length equal to n can be uniquely determined by its check matrix or generator matrix. The information bit sequence can be a payload information bit or a bit sequence with CRC check bits added, which is not limited in this application.

[0080] In 1981, Tanner expressed the LDPC codeword in the form of a graph. This graph is now called a Tanner graph. The Tanner graph corresponds to the check matrix one by one. The Tanner graph consists of two types of vertices. One type of vertex represents the codeword bits, called variable nodes, and the other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. Figure 1 and Figure 2 Provide explanation.

[0081] Figure 1 Schematic diagram of the LDPC check matrix H.

[0082] Figure 1In , {Vi} represents a variable node set, and {Ci} represents a check node set. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. Figure 1 In the example, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0083] Figure 2 is the Tanner graph of the LDPC check matrix H.

[0084] like Figure 2 As shown, the Tanner graph represents the check matrix of LDPC. For example, for a check matrix H with a size of m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. Among them, the n variable nodes correspond to the n columns of the check matrix H respectively, and the m check nodes correspond to the m rows of the check matrix H respectively. The cycle in the Tanner graph is composed of vertices connected to each other. The cycle uses one vertex in this group of vertices as both the starting point and the end point, and only passes through each node once. The variable nodes in the Tanner graph correspond to each column of the check matrix H, that is, to each codeword bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, that is, to the check bits of the LDPC. The connection between the two types of nodes corresponds to the value of the elements in the H matrix. Exemplarily, if there is a connection between the i-th check node and the j-th variable node, the value of the element (i, j) in the H matrix is ​​1, and if there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. There is a connection between the check node and the variable node, which can also be described as: there is a connection relationship between the check node and the variable node.

[0085] 2. Quasi-cyclic low density parity check (QC-LDPC) code

[0086] QC-LDPC code is a type of structured LDPC code. Due to the unique structure of its check matrix, it can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC. When the code length is long, the check matrix H of LDPC will be very large, so H is usually represented in blocks: the complete check matrix H is regarded as a block consisting of multiple Z c ×Z c Specifically, the complete check matrix H can be generated by an indicator matrix H b Indicates that H bEach element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H. b The elements in can also be called quasi-cyclic (QC) blocks.

[0087] Based on the exponential matrix H b and the expansion factor Z c , the exponential matrix H b Expanded to a complete check matrix for encoding or decoding. c (lifting size) may also be called a lifting factor, a lifting value, an expansion value, an expansion coefficient, a lifting size, etc. The lifting value is used in this application.

[0088] For example, the exponential matrix H of QC-LDPC b As shown below:

[0089]

[0090] It can be seen that the exponential matrix H b The size is 4 rows and 24 columns, and the elements represents the cyclic permutation matrix, i represents the cyclic shift value, where 0≤i≤Z c -1, i is an integer. In addition, the exponential matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0091] For example, As shown below:

[0092]

[0093] It should be noted that the exponential matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0094] 3. Non-zero elements and zero elements

[0095] In the present application, a zero element in the check matrix indicates that there is no connection between the variable node and the check node. A non-zero element in the check matrix indicates that there is a connection between the variable node and the check node.

[0096] This application does not limit the specific representation of zero elements and non-zero elements. For example, in the exponential matrix H bIn the check matrix H, "-1" can be used to represent a zero element, and "non-negative value" can be used to represent a non-zero element. For another example, in the check matrix H, "0" can be used to represent a zero element, and "1" can be used to represent a non-zero element.

[0097] For the convenience of description, the LDPC base matrix below uses "0" to represent a zero element and uses "1" to represent a non-zero element.

[0098] 4. Column weight and row weight

[0099] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, Figure 1 As shown, the first column of the check matrix H has a column weight of 2 and the first row weight of 4. For another example, the exponential matrix H described above b The first column has a column weight of 4 and the first row has a row weight of 20.

[0100] 5. Basic structure of basis matrix

[0101] like Figure 3 As shown in (a), the base matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region may include Figure 3 Part A and part B shown in (b), where part A corresponds to information bits (or information bits, etc.), part B is a square matrix and corresponds to core check bits (or core check bits), and part B can also be the area corresponding to the check column with column weight greater than 1. The all-zero area can correspond to Figure 3 The C part of (b) is an all-zero matrix. The incremental redundancy region can correspond to Figure 3 Part D of (b). The Laputa-like region may correspond to Figure 3 The E part of (b) can be a unit matrix, corresponding to the parity bits of the low code rate extension.

[0102] Figure 3 The base matrix of the LDPC code shown in the figure adopts a "raptor-like" structure, which can be gradually expanded to low bit rates through a high bit rate kernel matrix, so that it can flexibly support encoding of various bit rates. Figure 3As shown in (a), the first X rows and Y columns of the base matrix can be intercepted. As the code rate decreases from high to low, X and Y gradually increase, and the area of ​​the matrix used gradually expands. The difference between X and Y is the number of information columns.

[0103] It should be noted that the LDPC base matrix can be represented by a check matrix, so the structure of the check matrix is ​​similar to that of the LDPC base matrix, which will not be described in detail here.

[0104] 6. Core matrix, core row, core column

[0105] Core row: is the row corresponding to the core check bit. In other words, the core row is the row corresponding to the high bit rate area.

[0106] Core columns: may include all information columns and all core check columns. In other words, core columns are columns corresponding to the high bit rate area, or columns corresponding to part A + part B.

[0107] Kernel Matrix: It is the part consisting of all core rows and all core columns of the LDPC base matrix or LDPC check matrix. In other words, the core matrix is ​​the high code rate region of the LDPC base matrix or LDPC check matrix, or the part consisting of part A and part B.

[0108] 7. Expanded columns, non-expanded columns, expanded rows, and non-expanded rows

[0109] For LDPC codes, each time an extended node is added, a row and a column are added. In this application, the added row and column are called extended columns and extended rows. The extended column is the column corresponding to the extended node. In other words, the extended column corresponds to the extended check bit. The columns outside the extended column are non-extended columns. The rows outside the extended row are non-extended rows. Figure 3 For example, the columns in C and E are extended columns, and the rows in D and E are extended rows.

[0110] In addition, in this application, the part composed of non-expanded columns can also be called the core part, and the part composed of expanded columns can also be called the expanded part. Figure 3 For example, the part composed of A, B and D is the core part, and the part composed of C and E is the extended part.

[0111] 8. Punch column

[0112] The punctured columns in the LDPC code may refer to columns that are not sent. The punctured columns may be information columns or check columns. In addition, the columns that are not punctured in the LDPC code may also be called non-punctured columns. Similarly, the non-punctured columns may be information columns or check columns.

[0113] Exemplarily, the Tanner graph corresponding to the base matrix is ​​the base graph (BG). Currently, 5G LDPC defines two base graphs, BG1 and BG2. The selection of BG1 and BG2 is based on the length of the code block (CB) and the target bit rate of the transmission. Generally speaking, the puncturing columns of BG1 and BG2 are the first column and the second column.

[0114] 9. Information transmission process

[0115] Figure 4 It is a schematic diagram of the information transmission process. Figure 4 As shown in the figure, information is sent from the source, and after source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, it reaches the destination, completing the transmission of information from the source to the destination. Figure 4 The processing shown in the upper layer (including source coding, channel coding and modulation, etc.) is performed at the transmitting end (that is, the encoding device described below), and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end (that is, the decoding device described below).

[0116] The embodiments of the present application mainly relate to Figure 4 Source coding, channel coding, channel decoding and source recovery are shown.

[0117] Among them, the above Figure 4 The modulation involved generally adopts quadrature amplitude modulation (QAM). QAM modulation is a high-order modulation, and a QAM symbol can carry multiple bits of information. For example, a 64QAM symbol carries 6 bits of information. In high-order modulation, the reliability of the bits carried by a QAM symbol is different, or the energy of the bits is different. For example, a 256QAM symbol can contain 8 bits, of which the first two bits have the highest energy and the highest reliability, the third bit and the fourth bit have the second highest reliability, the fifth bit and the sixth bit have the lower reliability, and the seventh bit and the eighth bit have the lowest reliability. It should be noted that the 256QAM symbol does not limit the first two bits to have the highest energy and the highest reliability, the third bit and the fourth bit have the second highest reliability, the fifth bit and the sixth bit have the lower reliability, and the seventh bit and the eighth bit have the lowest reliability. The reliability of the bits in the 256QAM symbol can also be distributed in other ways, which is not limited in this application.

[0118] Figure 5This is an example of information bit protection for LDPC. The purpose of information bit protection for LPDC is to map the information bits of LDPC to the bit positions of high energy levels of QAM symbols. For example, the information length of LDPC is 8448, and the transmission length is 12672, which is an LDPC with a code rate of 2 / 3. In the coding protocol of the new radio (NR), BG1 coding is used, and the selected lifting size is 384, so there are 22 information columns, each of which includes 384 bits. The NR protocol stipulates that the first two columns are punctured, so the number of check columns should be 12672 / 384-(22-2)=13 columns, such as Figure 5 As shown in Figure 1. The core check column includes 4 columns, and the extended check column includes 9 columns. These 13 columns are used as the check columns of the LDPC. After the first two columns are punctured and not sent, there are 20 columns of information bits left, plus 13 check columns, resulting in 33 columns for transmission. The column indexes of these 33 transmission columns are as follows: Figure 5 3 to 35. 22 information columns / 33 transmission columns = 2 / 3, which is the code rate of this LDPC.

[0119] In addition, 5G stipulates that rate matching is performed after LDPC encoding to obtain the transmission sequence, which usually needs to be bit interleaved. Bit interleaving is to scramble the bit order after rate matching in order to combat burst interference. After interleaving, the original burst interference may become a random single interference, which is conducive to decoding. In the modulation mode using high-order modulation, the effect of interleaving is more obvious.

[0120] The most commonly used interleaving method is row-column interleaving, which rearranges the bit order by writing rows and reading columns. Assume that the sequence obtained after rate matching is represented as e, and the sequence obtained after interleaving is recorded as sequence f. If row-column interleaving is used, the relationship between sequence f and sequence e can be as follows:

[0121]

[0122] Among them, E represents the sequence length, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol. For a bit sequence with a transmission length of E, the number of QAM symbols is E / Q m Therefore, the value of j ranges from 0 to E / Q m -1. If the number of bits contained in a QAM symbol is Q m , then the value of i ranges from 0 to Q m -1.

[0123] The relationship between sequence e and sequence f shows that the position index in sequence e is i*E / Qm +j bits, after bit interleaving, have position index i+j*Q in sequence f. m .

[0124] Based on the above introduction, if 64QAM modulation is used, Q m =6, then there are 3 energy levels. According to the relationship formula between the transmitted sequence e and the interleaved sequence f, it can be seen that the 3rd to 13th columns of the information bits are mapped to the 1st and 2nd bit positions of the QAM symbol, which are the two bit positions with the highest energy; the 14th to 24th columns of the information bits are mapped to the 3rd and 4th bit positions of the QAM symbol, which are the two bit positions with the second highest energy; the 3rd and 4th columns of the core check column and all the columns of the extended check column, that is, the 25th to 35th columns are mapped to the 5th and 6th bit positions of the QAM symbol, which are the two bit positions with the lowest energy. In other words, the 1st bit position of each QAM symbol is a bit from the first 192 bits from the 3rd to 8th columns, and the 2nd bit position is a bit from the 193rd to 13th bits from the 8th column. The 3rd bit position of each QAM symbol is a bit from the first 192 bits in columns 14 to 19, and the 4th bit position is a bit from the 193rd bit in column 19 to a bit in column 24. The 5th bit position of each QAM symbol is a bit from the first 192 bits in columns 25 to 30, and the 6th bit position is a bit from the 193rd bit in column 30 to a bit in column 35.

[0125] The key performance indicator (KPI) of current wireless communications is the block error rate (BLER), which is the probability that at least one of all transmitted bits is erroneous. The transmitted bits must be all correct, so the BLER is mainly determined by the least reliable bit. Figure 5 The information bit protection shown does not provide additional protection for the least reliable bits, so the BLER of wireless communication cannot be effectively improved.

[0126] Based on the above technical status, the present application provides an interleaving method and a corresponding communication device, which can provide additional protection for the least reliable bits, thereby improving the BLER of wireless communication.

[0127] Figure 6 FIG. 1 is a schematic diagram of a system architecture 100 applicable to an embodiment of the present application. Figure 6, the system architecture 100 may include an encoding device and a decoding device. The encoding device is not limited to one or more, and the decoding device is not limited to one or more. Exemplarily, one of the encoding device and the decoding device may be Figure 6 The network device shown, the other is Figure 6 The terminal device 1 or the terminal device 2 is shown.

[0128] The terminal device in the embodiment of the present application includes various communication kits (communication kits) with wireless communication functions, which may include, for example, antennas, power supply templates, cables, and wireless fidelity (WiFi) modules, etc.), handheld devices, vehicle-mounted devices, or other processing devices connected to a wireless modem, and may specifically refer to user equipment (UE), users, access terminals, user units, user stations, mobile stations, mobile stations, remote stations, remote terminals, mobile devices, user terminals, terminals, wireless communication devices, user agents, user devices, wireless modems, machine type communication devices, or other processing devices connected to wireless modems. It may also be a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a terminal in self-driving, a terminal in remote medical, a terminal in smart grid, a terminal in transportation safety, a terminal in smart city, a terminal in smart home, or a terminal device in a future communication network. Of course, the terminal device in this application may also refer to a chip, a modem, a system on a chip (SoC) that is mainly responsible for related communication functions in the device, or a communication platform that may include a radio frequency (RF) part, etc.

[0129] The network device in the embodiment of the present application may include, but is not limited to: a next-generation base station (gNodeB, gNB) in a fifth-generation (5th generation, 5G) communication system, a base station in a sixth-generation (6th generation, 6G) mobile communication system, a base station in a future mobile communication system, an access point (AP) in a wireless fidelity (WiFi) system, a wireless relay node, a wireless backhaul node, a transmission point (TP) or a transmission reception point (TRP), an evolved node B (evolved node B, eNB) in a long-term evolution (LTE) system, a network device in a non-terrestrial network (NTN) communication system, etc. The network device may also be one or a group (i.e., multiple) antenna panels of a base station. In addition, the network device may also be a network node constituting a gNB or TP, such as a baseband unit (BBU), a centralized unit (CU), a distributed unit (DU), or a radio unit (RU). Alternatively, the network device may also be a device-to-device (D2D) communication system, a machine-to-machine (M2M) communication system, an Internet of Things (IoT), an Internet of Vehicles communication system, or a device that performs network-side functions in other communication systems, without limitation.

[0130] In the embodiments of the present application, the device for realizing the function of the terminal device may be a terminal device, or a device capable of supporting the terminal device to realize the corresponding function, such as a chip (or a chip system) or a circuit, which may be installed in the terminal device. In addition, the device for realizing the function of the network device may be a network device, or a device capable of supporting the network device to realize the corresponding function, such as a chip (or a chip system) or a circuit, which may be installed in the network device. Optionally, the chip system may include a chip, or include a chip and other discrete devices.

[0131] exist Figure 6 In the system architecture shown, in uplink communication, the encoding device is terminal device 1 or terminal device 2, and the decoding device is a network device. In downlink communication, the encoding device is a network device, and the decoding device is terminal device 1 or terminal device 2.

[0132] Figure 7 This is a schematic flow chart of the interleaving method 200 provided in the present application. Among them, steps 210 to 218 in the method 200 can be performed by an encoding device, or by a device (such as a chip, a chip system or a circuit, etc.) applied to the encoding device; steps 220 to 226 can be performed by a decoding device, or by a device (such as a chip, a chip system or a circuit, etc.) applied to the decoding device. The following is an example of an encoding device and a decoding device.

[0133] In addition, the technical solution of the present application can be applied to QAM modulation, but it is also applicable to some other modulation methods. For example, pulse amplitude modulation (PAM), phase shift keying (PSK) modulation, etc. The following is an example of the application of the technical solution of the present application in QAM modulation.

[0134] Step S210: The encoding device obtains an LDPC base matrix, where the LDPC base matrix includes M columns.

[0135] Specifically, the encoding device may select an LDPC base matrix based on the length of the CB and the target code rate of the transmission. For example, the BG corresponding to the selected LDPC base matrix may be BG1 or BG2, which is not limited in this application.

[0136] Step S212: The encoding device encodes the first bit sequence according to the LDPC base matrix to obtain a second bit sequence.

[0137] Exemplarily, the first bit sequence is a bit sequence to be encoded, and the second bit sequence is a bit sequence to be sent.

[0138] Exemplarily, the encoding device can divide the information sequence to be encoded into groups of w bits, and then the encoder performs linear operations on the w information bits to obtain g check bits, and then combines the w information bits with the g check bits to obtain a codeword of length v=w+g. The mapping relationship from w-bit information bits to a codeword of length v bits can be represented by the above-mentioned LDPC base matrix. According to the above-mentioned LDPC base matrix, a codeword sequence can be generated accordingly to complete the encoding process.

[0139] Optionally, the second bit sequence may be a bit sequence that has undergone rate matching.

[0140] Step S214: The encoding device interleaves the second bit sequence according to the first indicator sequence to obtain a third bit sequence.

[0141] Specifically, the first indicator sequence is used to indicate the corresponding relationship between the M columns and the R energy levels included in the QAM symbol, where M and R are positive integers.

[0142] Exemplarily, the first indication sequence satisfies at least one of the following characteristics:

[0143] Feature 1: The elements in the first indicator sequence correspond one-to-one to the columns of the above LDPC base matrix.

[0144] Feature 2: The number S of elements in the first indication sequence is the same as the number of the above-mentioned M columns excluding the punctured columns.

[0145] It should be noted that when rate matching is not required, there may be no puncturing column, and S=M at this time; when rate matching is required, puncturing is required, and S<M at this time.

[0146] Feature 3: The smaller the sequence number of an element in the first indicator sequence, the higher the energy level corresponding to the element.

[0147] Exemplarily, the first indication sequence is used to indicate the correspondence between the M columns and the R energy levels included in the QAM symbol, including the following three indication modes:

[0148] Indication method 1: The first indication sequence is used to indicate the correspondence between the M columns and the R energy levels contained in the QAM symbol.

[0149] The corresponding relationship between the M columns and the R energy levels contained in the QAM symbol may be: the smaller the column weight of the M columns, the higher the corresponding energy level.

[0150] Here the above Figure 5 For example, the number of elements in the first indication sequence is 33 (the punched columns of the first and second columns are deleted). Assume that, as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the first indication sequence may be indication sequence #1: { 35 ,34, 33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3}, wherein the i-th element (sequence number is i) of the indicator sequence #1 indicates that the i-th priority of the column corresponding to the element corresponds to the high energy level of the QAM symbol. For example, the first element "35" of the indicator sequence #1 indicates that the first priority of the bits in the 35th column corresponds to the high energy level of the QAM symbol, and the third element "33" of the indicator sequence #1 indicates that the third priority of the bits in the 33rd column corresponds to the high energy level of the QAM symbol. Alternatively, the first indicator sequence may be indicator sequence #2: {32, 34, 33, 35, 27, 31, 29, 30, 28, 24, 26, 23, 25, 21, 22, 19, 18, 20, 15, 17, 16, 14, 13, 12, 10, 9, 11, 8, 7, 6, 5, 3, 4}, and the positions of columns with the same column weight in indicator sequence #1 may be interchanged.

[0151] The example of indicator sequence #1 above can be considered as a complete indicator sequence. When bits of a part of the columns need to be interleaved, the first indicator sequence used is a subsequence of the complete indicator sequence. For example, if the bits of columns 10 to 20 need to be interleaved, the subsequence corresponding to columns 10 to 20 in the indicator sequence #1 above is selected as the first indicator sequence. In this case, the first indicator sequence is indicator sequence #1A: { 20 ,19, 18 ,17,16,15,14,13,12,11,10}, wherein the first element "20" of the indicator sequence #1A indicates that the first priority of the bits in the 20th column corresponds to the high energy level of the QAM symbol, and the third element "18" of the indicator sequence #1A indicates that the third priority of the bits in the 18th column corresponds to the high energy level of the QAM symbol.

[0152] In addition, in the above example, the QAM symbol of the 64QAM modulation mode has 3 energy levels, but the first indication sequence indicates 33 columns. At this time, priority is given to ensuring the bit mapping of the high energy level. For example, the bits of the 35th column can be mapped to the highest energy level first. If the bits of the 35th column occupy all the bits of the highest energy level of the QAM symbol, then the bits of the 34th column are mapped to the second highest energy level; if the bits of the 35th column occupy part of the bits of the highest energy level of the QAM symbol, then the bits of the 34th column continue to be mapped to the highest energy level of the QAM symbol, and so on.

[0153] Indication method 2: M columns are divided into K intervals according to the columns, and the first indication sequence is used to indicate the corresponding relationship between the K intervals and the R energy levels included in the QAM symbol.

[0154] Among them, the above K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of the second interval is less than the minimum column weight of the third interval, and the minimum column weight of the second interval is greater than the maximum column weight of the first interval.

[0155] Exemplarily, the correspondence between the K intervals and the R energy levels contained in the QAM symbol can be: the smaller the column weight of the K intervals, the higher the corresponding energy level. Exemplarily, the column weight of the K intervals can be the maximum column weight, the minimum column weight, or the average column weight of the first interval, the second interval, or the third interval, etc., which is not limited in this application.

[0156] Here we still use the above Figure 5 For example, the number of elements in the first indication sequence is 33 (the punched columns of the first and second columns are deleted). Assume that, as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the column weights of the 33 columns are divided into three intervals: [1], [4, 7], and [8, 11]. These three intervals can be an example of the first interval, the second interval, and the third interval. The first indication sequence can be divided into three sections according to these three intervals, such as Figure 8 The first, second, third and fourth segments of the indication sequence #3 shown in (a) Figure 8 (b) shows the 1st, 2nd and 3rd segments of the indication sequence #4.

[0157] Figure 8 The first segment shown contains columns corresponding to the column weight in the first interval [1], the second segment contains columns corresponding to the column weight in the second interval [4,7], and the third segment contains columns corresponding to the column weight in the third interval [8,11]. The i-th segment of the indicator sequence #3 and the indicator sequence #4 indicates that the i-th priority of the column corresponding to the element of the i-th segment corresponds to the high energy level of the QAM symbol. For example, the element "35" of the first segment of the indicator sequence #3 indicates that the first priority of the bit of the 35th column corresponds to the high energy level of the QAM symbol, the element "33" of the first segment of the indicator sequence #3 indicates that the first priority of the bit of the 33rd column corresponds to the high energy level of the QAM symbol, and the element "19" of the second segment of the indicator sequence #3 indicates that the second priority of the bit of the 19th column corresponds to the high energy level of the QAM symbol.

[0158] The elements contained in each segment in the indication sequence #3 can be arranged arbitrarily within the segment, as shown in the indication sequence #4.

[0159] Optionally, the positions of columns with the same column weight contained in each segment of indication sequence #3 may be interchanged within the segment.

[0160] In the above example, the QAM symbol of the 64QAM modulation method has 3 energy levels. Figure 8 The bits of the columns contained in the first interval are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second interval are mapped to the second highest energy level of the QAM symbol, and the bits corresponding to the columns contained in the third interval are mapped to the lowest energy level of the QAM symbol.

[0161] For example, the QAM symbol of the 16QAM modulation method has two energy levels. Figure 8 The bits of the columns contained in the first interval shown are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the third interval are mapped to the lowest energy level of the QAM symbol, and the bits of the columns contained in the second interval can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0162] Optionally, the columns of the above 33 columns can also be re-divided into two intervals [1,7] and [8,11], which can be examples of the first interval and the second interval. The first indication sequence can be divided into two sections according to the two intervals. The present application does not limit the number of the above K intervals.

[0163] Another implementation of the second indication method is: the M columns are divided into K sets according to the columns, and the first indication sequence is used to indicate the corresponding relationship between the K sets and the R energy levels included in the QAM symbol.

[0164] Here we still use the above Figure 5 For example, the number of elements in the first indicator sequence is 33 (the punched columns of the first and second columns are deleted). Assume that as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the column weights of the 33 columns are divided into three sets: {1}, {4, 5, 7}, and {8, 9, 10, 11}. The first indicator sequence can be divided into three segments according to these three sets, such as Figure 8 The first, second, third and fourth segments of the indication sequence #3 shown in (a) Figure 8 (b) shows the 1st, 2nd and 3rd segments of the indication sequence #4.

[0165] Figure 8The first segment shown contains columns corresponding to the column weights in the first set {1}, the second segment contains columns corresponding to the column weights in the second set {4,5,7}, and the third segment contains columns corresponding to the column weights in the third set {8,9,10,11}. The i-th segment of the indicator sequence #3 and the indicator sequence #4 indicates that the i-th priority of the column corresponding to the element of the i-th segment corresponds to the high energy level of the QAM symbol. For example, the element "35" of the first segment of the indicator sequence #3 indicates that the first priority of the bit of the 35th column corresponds to the high energy level, the element "33" of the first segment of the indicator sequence #3 indicates that the first priority of the bit of the 33rd column corresponds to the high energy level of the QAM symbol, and the element "19" of the second segment of the indicator sequence #3 indicates that the second priority of the bit of the 19th column corresponds to the high energy level of the QAM symbol.

[0166] The elements contained in each segment in the indication sequence #3 can be arranged arbitrarily within the segment, as shown in the indication sequence #4.

[0167] Optionally, the positions of columns with the same column weight contained in each segment of indication sequence #3 may be interchanged within the segment.

[0168] In the above example, the QAM symbol of the 64QAM modulation method has 3 energy levels. Figure 8 The bits of the columns contained in the first set shown are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second set are mapped to the second highest energy level of the QAM symbol, and the bits corresponding to the columns contained in the third set are mapped to the lowest energy level of the QAM symbol.

[0169] For example, the QAM symbol of the 16QAM modulation method has two energy levels. Figure 8 The bits of the columns contained in the first set shown are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the third set are mapped to the lowest energy level of the QAM symbol, and the bits of the columns contained in the second set can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0170] Optionally, the columns of the above 33 columns may be re-divided into two sets {1, 4, 5, 7} and {8, 9, 10, 11}. The first indication sequence may be divided into two sections according to the two sets. The present application does not limit the number of the above K sets.

[0171] The above indication method 1 and the above indication method 2 perform bit mapping according to column weight, which can provide additional protection for the least reliable bits and improve communication performance.

[0172] Indication method three: M columns are divided into P sets according to type, and the first indication sequence is used to indicate the correspondence between the P sets and the R energy levels contained in the QAM symbol. Exemplarily, the types of the M columns include information columns, core check columns, and extended check columns. Among them, the multiple columns included in the first set and / or the second set and / or the third set in the P sets are arranged in order from small to large column weight.

[0173] The P sets include a first set and / or a second set and / or a third set. The first set may include an information column, the second set may include a core check column, and the third set may include an extended check column. Alternatively, the first set may include an information column and a core check column, and the second set may include an extended check column.

[0174] Here we still use the above Figure 5 For example, the number of elements in the first indication sequence is 33 (the punctured columns of the first and second columns are deleted). Assume that as the number of columns of the 33 columns increases, the column weights of the 33 columns are 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, and the 33 columns are divided into Fig. 9 The indication sequence of (a) #5 is the same as Fig. 9 The first set, the second set, and the third set shown in the indication sequence #6 of (b).

[0175] Exemplarily, the first set includes information columns from column 3 to column 22, the second set includes core check columns from column 23 to column 26, and the third set includes extended check columns from column 27 to column 35. The i-th set of indicator sequence #5 and indicator sequence #6 indicates that the i-th priority of the column corresponding to the element of the i-th set corresponds to the high energy level of the QAM symbol. For example, the element "22" of the first set of indicator sequence #5 indicates that the first priority of the bit of the 22nd column corresponds to the high energy level, the element "20" of the first set of indicator sequence #5 indicates that the first priority of the bit of the 20th column corresponds to the high energy level of the QAM symbol, and the element "25" of the second set of indicator sequence #5 indicates that the second priority of the bit of the 25th column corresponds to the high energy level of the QAM symbol.

[0176] The columns included in each of the first set, the second set, and the third set are arranged in ascending order of column weight. Fig. 9As shown in (a), the column weight of the 22nd column corresponding to the element "22" of the first set is 4, and the column weight of the 20th column corresponding to the element "20" of the first set is 5. Therefore, the index of the serial number of the element "22" of the first set in the indication sequence #5 is smaller than the index of the serial number of the element "20" of the first set in the indication sequence #5. In other words, the position of the element "22" of the first set in the indication sequence #5 is closer to the front relative to the position of the element "20" of the first set in the indication sequence #5.

[0177] Optionally, the elements contained in each set in indication sequence #5 may be arranged arbitrarily within the set, as shown in indication sequence #6.

[0178] Optionally, the positions of columns with the same column weight contained in each set in the indication sequence #5 may be interchanged within the set.

[0179] In the above example, the QAM symbol of the 64QAM modulation method has 3 energy levels. Fig. 9 The bits of the columns contained in the first set are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second set are mapped to the second highest energy level of the QAM symbol, and the bits of the columns contained in the third set are mapped to the lowest energy level of the QAM symbol.

[0180] For example, the QAM symbol of the 16QAM modulation method has two energy levels. Fig. 9 The bits of the columns contained in the first set shown are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the third set are mapped to the lowest energy level of the QAM symbol, and the bits of the columns contained in the second set can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0181] Optionally, the above 33 columns can also be divided into two sets, a first set and a second set, according to type. Exemplarily, the first set includes information columns from columns 3 to 22 and core check columns from columns 23 to 26, and the second set includes extended check columns from columns 27 to 35. This application does not limit the number of the above P sets and the division method of the P sets.

[0182] The above indication method 3 can take into account the protection of information bits and always map the most important information to the highest energy level of the QAM symbol. In addition, the energy levels corresponding to the information bits can be further refined to provide additional protection for unreliable bits in the information bits, thereby improving communication performance.

[0183] Another implementation of indication mode 3 is: the first set includes the extended check columns from column 27 to column 35, the second set includes the core check columns from column 23 to column 26, and the third set includes the information columns from column 3 to column 22, such as Fig.10 The indication sequence #7 shown in (a) and Fig.10 The first set, the second set, and the third set shown in the indicator sequence #8 shown in (b). The i-th set of indicator sequence #7 and indicator sequence #8 indicates that the i-th priority of the column corresponding to the element of the i-th set corresponds to the high energy level of the QAM symbol. For example, the element "35" of the first set of indicator sequence #7 indicates that the first priority of the bit of the 35th column corresponds to the high energy level, the element "33" of the first set of indicator sequence #7 indicates that the first priority of the bit of the 33rd column corresponds to the high energy level of the QAM symbol, and the element "25" of the second set of indicator sequence #7 indicates that the second priority of the bit of the 25th column corresponds to the high energy level of the QAM symbol.

[0184] The columns included in each of the first set, the second set, and the third set are arranged in ascending order of column weight. Fig.10 The column weight of the 22nd column corresponding to the element "22" of the third set shown in (a) is 4, and the column weight of the 20th column corresponding to the element "20" of the third set is 5. Therefore, the index of the serial number of the element "22" of the third set in the indication sequence #7 is smaller than the index of the serial number of the element "20" of the third set in the indication sequence #7. In other words, the position of the element "22" of the third set in the indication sequence #7 is closer to the front relative to the position of the element "20" of the third set in the indication sequence #7.

[0185] Optionally, the elements contained in each set in indication sequence #7 may be arranged arbitrarily within the set, as shown in indication sequence #8.

[0186] Optionally, the positions of columns with the same column weight contained in each set in the indication sequence #7 may be interchanged within the set.

[0187] In the above example, the QAM symbol of the 64QAM modulation method has 3 energy levels. Fig.10 The bits of the columns contained in the first set are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the second set are mapped to the second highest energy level of the QAM symbol, and the bits of the columns contained in the third set are mapped to the lowest energy level of the QAM symbol.

[0188] For example, the QAM symbol of the 16QAM modulation method has two energy levels. Fig.10The bits of the columns contained in the first set shown are mapped to the highest energy level of the QAM symbol, the bits of the columns contained in the third set are mapped to the lowest energy level of the QAM symbol, and the bits of the columns contained in the second set can be mapped to the highest energy level of the QAM symbol or the lowest energy level of the QAM symbol.

[0189] Optionally, the above 33 columns can also be divided into two sets, a first set and a second set, according to type. Exemplarily, the first set includes core check columns from columns 23 to 26 and extended check columns from columns 27 to 35, and the second set includes information columns from columns 1 to 22. This application does not limit the number of the above P sets and the division method of the P sets.

[0190] Exemplarily, the first indication sequence may be generated according to the rules described in the above indication mode 1, indication mode 2 or indication mode 3, or may be pre-stored, which is not limited in the present application.

[0191] As described above, the LDPC base matrix adopts a "raptor-like" structure, which can be gradually expanded to a low code rate through a high code rate core matrix, so that it can flexibly support encoding of various code rates. The code rates required in different communication scenarios are different, so the above-mentioned M columns involved in the first indication sequence may change during the expansion of the LDPC base matrix from a high code rate to a low code rate. The embodiments of the present application can provide the following methods for determining the M columns of the LDPC base matrix:

[0192] Mode 1: The M columns are columns corresponding to the lowest code rate supported by the LDPC base matrix.

[0193] Exemplarily, the number of information columns of the matrix corresponding to BG1 is 22, the number of core check columns and extended check columns is 46, and the minimum code rate supported by BG1 is 1 / 3. Therefore, it is considered that the number of M columns of the LDPC base matrix is ​​22+46=68. The first indication sequence can indicate the correspondence between the 68 columns and the R energy levels of the QAM symbol according to the above indication mode 1, indication mode 2, or indication mode 3.

[0194] Mode 2: The above M columns are columns corresponding to the highest code rate supported by the LDPC base matrix.

[0195] Exemplarily, the number of information columns of the matrix corresponding to BG1 is 22, the number of core check columns is 4, and the highest code rate supported by BG1 is 22 / 24. Therefore, it is considered that the number of M columns of the LDPC base matrix is ​​22+4=26. The first indication sequence can indicate the correspondence between the 26 columns and the R energy levels of the QAM symbol according to the above indication mode 1, indication mode 2, or indication mode 3.

[0196] Method three: Divide the code rate supported by the LDPC base matrix into multiple intervals, each code rate interval corresponds to a different number of columns, and one code rate interval corresponds to one first indicator sequence.

[0197] Exemplarily, the bit rate range supported by BG1 is [1 / 3, 22 / 24], which is divided into multiple bit rate ranges [1 / 3, 1 / 2], [1 / 2, 2 / 3], and [2 / 3, 22 / 24]. The number of columns of the matrix corresponding to each bit rate range may be the number of columns of the matrix corresponding to the lowest bit rate of the bit rate range, the number of columns of the matrix corresponding to the highest bit rate of the bit rate range, or the number of columns of the matrix corresponding to the intermediate bit rate of the bit rate range. This application does not limit this.

[0198] Exemplarily, the embodiment of the present application is explained by taking the example that the number of columns of the matrix corresponding to each bit rate interval can be the number of columns of the matrix corresponding to the lowest bit rate of the bit rate interval: the number of matrix columns corresponding to the bit rate interval [1 / 3, 1 / 2] is 68, the number of matrix columns corresponding to the bit rate interval [1 / 2, 2 / 3] is 56, and the number of matrix columns corresponding to the bit rate interval [2 / 3, 22 / 24] is 44. Therefore, the LDPC base matrix under mode three corresponds to three first indicator sequences. The first first indicator sequence can indicate the correspondence between 68 columns corresponding to the code rate interval [1 / 3, 1 / 2] and the R energy levels of the QAM symbol according to the above-mentioned indication mode one, indication mode two or indication mode three. The second first indicator sequence can indicate the correspondence between 56 columns corresponding to the code rate interval [1 / 2, 2 / 3] and the R energy levels of the QAM symbol according to the above-mentioned indication mode one, indication mode two or indication mode three. The third first indicator sequence can indicate the correspondence between 44 columns corresponding to the code rate interval [2 / 3, 22 / 24] and the R energy levels of the QAM symbol according to the above-mentioned indication mode one, indication mode two or indication mode three.

[0199] Alternatively, when the M columns involved in the first indicator sequence may change during the process of expanding the LDPC base matrix from a high code rate to a low code rate, the column weights of the M columns will also change, that is, the positions of the columns of the LDPC base matrix in the first indicator sequence will also change. Exemplarily, the embodiments of the present application may provide the following methods for determining the column weights of the M columns of the LDPC base matrix:

[0200] Mode 1: The column weight of the M columns is the column weight of the columns corresponding to the lowest code rate supported by the LDPC base matrix. Alternatively, the column weight of the M columns is the column weight of the entire matrix of the LDPC base matrix.

[0201] Exemplarily, the column weights of the M columns are Figure 3 The column weights of the columns of Part A+Part B+Part C+Part D+Part E are shown.

[0202] Mode 2: The column weights of the M columns are the column weights of columns corresponding to the highest code rate supported by the LDPC base matrix.

[0203] Exemplarily, the column weights of the M columns are Figure 3 Column weights for Part A+Part B columns are shown.

[0204] Method three: the code rate supported by the LDPC base matrix is ​​divided into multiple intervals, the column weights of the columns corresponding to each code rate interval are different, and one code rate interval can correspond to one first indicator sequence.

[0205] Exemplarily, the code rate interval supported by BG1 is [1 / 3, 22 / 24], and the code rate interval is divided into multiple code rate intervals [1 / 3, 1 / 2], [1 / 2, 2 / 3], [2 / 3, 22 / 24]. The column weight of the matrix corresponding to each code rate interval can be the column weight of the matrix corresponding to the lowest code rate in the code rate interval, or the column weight of the matrix corresponding to the highest code rate in the code rate interval, or the column weight of the matrix corresponding to the intermediate code rate in the code rate interval. This application does not limit this. In the above step S214, the encoding device interleaves the above second bit sequence according to the above first indication sequence to obtain a third bit sequence. Exemplarily, the above step S214 may specifically include: the encoding device performs a first interleaving on the second bit sequence according to the above first indication sequence to obtain a fourth bit sequence; the encoding device performs row-column interleaving on the fourth bit sequence to obtain the above third bit sequence.

[0206] Exemplarily, the first interleaving process described below may be performed before the encoding device performs circular buffering on the second bit sequence, or may be performed after the encoding device performs circular buffering on the second bit sequence, and this application does not limit this.

[0207] Exemplarily, the process of the first interleaving may be as follows: assuming that the transmission sequence obtained after rate matching is represented as e (which may be an example of the second bit sequence mentioned above), the sequence obtained after the first interleaving is recorded as sequence e1 (which may be an example of the fourth bit sequence mentioned above). Exemplarily, the relationship between sequence e1 and sequence e may be as follows:

[0208]

[0209] Wherein, S represents the number of elements in the first indicator sequence, j represents the index of the sequence number of the element contained in the first indicator sequence, s(j) represents the jth element of the first indicator sequence, and Z c is the lifting value of the LDPC base matrix, and can also be understood as the number of bits corresponding to each column indicated in the first indicator sequence.

[0210] From the relationship between sequence e and sequence e1, we can see that the position index in sequence e is s(j)*Z c +i bit, after bit interleaving, has position index j*Z in sequence e1 c +i.

[0211] Next, the sequence e1 may be further interleaved in rows and columns to obtain a sequence f (which may be an example of the third bit sequence mentioned above). For example, the relationship between the sequence f and the sequence e1 may be as follows:

[0212]

[0213] Among them, E represents the sending length, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol. For a bit sequence with a transmission length of E, the number of QAM symbols is E / Q m Therefore, the value of j ranges from 0 to E / Q m -1. If the number of bits contained in a QAM symbol is Q m , then the value of i ranges from 0 to Q m -1.

[0214] From the relationship between sequence e1 and sequence f, we can see that the position index in sequence e1 is i*E / Q m +j bits, after bit interleaving, have position index i+j*Q in sequence f. m .

[0215] It should be noted that the closer the position of the element in the first indicator sequence (that is, the column of the LDPC base matrix) is in the first indicator sequence, the lower the column weight of the column of the LDPC base matrix. The present application may also provide another way of representing the first indicator sequence: the closer the position of the element in the first indicator sequence (that is, the column of the LDPC base matrix) is in the first indicator sequence, the higher the column weight of the column of the LDPC base matrix. Exemplarily, changing the above indication sequence #1 to {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35} can also be used to represent the first indication sequence, or changing the above indication sequence #2 to {4, 3, 5, 6, 7, 8, 11, 9, 10, 12, 13, 14, 16, 17, 15, 20, 18, 19, 22, 21, 25, 23, 26, 24, 28, 30, 29, 31, 27, 35, 33, 34, 32} can also be used to represent the first indication sequence. In this case, the encoding device can interleave the second bit sequence by the method of the first interleaving + reverse row and column interleaving to obtain a third bit sequence.

[0216] Exemplarily, the first interleaving may be the same as above, and the sequence e1 obtained by the first interleaving is interleaved in reverse order to obtain a sequence f (which may be an example of the third bit sequence mentioned above). Exemplarily, the relationship between the sequence f and the sequence e1 may be as follows:

[0217]

[0218]

[0219] Among them, E represents the sending length, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol. For a bit sequence with a transmission length of E, the number of QAM symbols is E / Q m Therefore, j ranges from 0 to E / Qm-1. If the number of bits contained in a QAM symbol is Q m , then the value of i ranges from 0 to Q m -1.

[0220] From the relationship between sequence e1 and sequence f, we can see that the position index in sequence e1 is i*E / Q m +j bits, after bit interleaving, have position index Q in sequence f. m -1-i+j*Q m .

[0221] Step S216: The encoding device maps the bits in the third bit sequence to QAM symbols.

[0222] Specifically, the encoding device maps bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and maps bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol.

[0223] The at least one fourth column and the at least one fifth column belong to the M columns, the column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column, and the first energy level is higher than the second energy level.

[0224] It should be noted that if the first indication sequence is indicated using the third indication method, then the at least one fourth column and the at least one fifth column belong to the same set in the first set, the second set or the third set in the third indication method.

[0225] Step S218: the encoding device outputs the modulated QAM symbols.

[0226] The “output modulated QAM symbols” here can also be understood as sending the modulated QAM symbols to the decoding device.

[0227] Step S220: The decoding device obtains the QAM symbol to be demodulated and demodulates it to obtain a first information sequence.

[0228] The first information sequence is a sequence of LLR information obtained after demodulation, wherein each LLR information represents the probability that the bit at the corresponding bit position is 0 or 1.

[0229] Step S222: The decoding device deinterleaves the first information sequence to obtain a second information sequence.

[0230] The second information sequence is a sequence of LLR information.

[0231] Step S224: The decoding device decodes the second information sequence, determines the information bits, and obtains a third information sequence.

[0232] Step S226: the decoding device outputs a third information sequence.

[0233] In step S220 to step S226, the demodulation, deinterleaving and decoding processes performed by the decoding device are respectively the inverse processes of the modulation, interleaving and encoding performed by the encoding device, and the principle is the same as that of the encoding device. At the decoding device end, the LLR information obtained after demodulating the QAM symbol corresponds to the bits at the encoding device end, specifically including information bits and check bits. Based on the description of the encoding device side, those skilled in the art can know how to demodulate, deinterleave and decode at the decoding device side, which will not be repeated here.

[0234] The interleaving method 200 described above can map the least reliable bits to the high energy level of the QAM symbol, thereby providing additional protection for the least reliable bits, reducing the BLER of data transmission, and improving wireless communication performance.

[0235] The present application may also provide a communication method 300, which can omit the first interleaving process in the above interleaving method 200 by designing a suitable LDPC base matrix, thereby simplifying the above interleaving method 200.

[0236] Fig.11 This is a schematic flow chart of the communication method 300 provided in the present application. Among them, steps 310 to 318 in the communication method 300 can be performed by an encoding device, or by a device (such as a chip, a chip system or a circuit, etc.) applied to the encoding device; steps 320 to 326 can be performed by a decoding device, or by a device (such as a chip, a chip system or a circuit, etc.) applied to the decoding device. The following is an example of an encoding device and a decoding device.

[0237] Step S310: The encoding device obtains a first LDPC base matrix, where the first LDPC base matrix includes M columns, and the M columns are divided into K intervals according to column variables.

[0238] Optionally, the first LDPC base matrix may be generated based on the first indicator sequence.

[0239] Exemplarily, the above-mentioned column variable may be a column weight or a column type of the first submatrix, and the column type includes an information column, a core check column, and an extended check column.

[0240] The first submatrix is ​​a partial or complete matrix of the first LDPC base matrix. Exemplarily, the first submatrix may be a matrix corresponding to the lowest code rate supported by the first LDPC base matrix, or the first submatrix may be a matrix corresponding to the highest code rate supported by the first LDPC base matrix.

[0241] Exemplarily, when the column variable is the column weight of the first submatrix, the first LDPC base matrix may satisfy at least one of the following characteristics:

[0242] Feature 1: The column weight of the M columns of the first LDPC base matrix increases as the number of columns increases.

[0243] Specifically, the first LDPC base matrix having feature 1 does not distinguish between the arrangement of information columns and check columns.

[0244] Feature 2: The M columns of the first LDPC base matrix can be divided into K intervals, the K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of at least one second column of the second interval is less than the minimum column weight of at least one first column of the first interval, the minimum column weight of at least one second column of the second interval is greater than the maximum column weight of at least one third column of the third interval. The number of columns of any column in at least one third column of the third interval is greater than the number of columns of any column in at least one second column of the second interval, and the number of columns of any column in at least one first column of the first interval is greater than the number of columns of any column in at least one first column of the first interval.

[0245] Among them, the column weight of at least one first column in the first interval decreases as the number of columns increases, or the position (or the number of columns) of at least one first column in the first interval can be exchanged within the first interval; and / or, the column weight of at least one second column in the second interval decreases as the number of columns increases, or the position (or the number of columns) of at least one second column in the second interval can be exchanged within the second interval; and / or, the column weight of at least one third column in the third interval decreases as the number of columns increases, or the position (or the number of columns) of at least one third column in the third interval can be exchanged within the third interval.

[0246] The smaller the column weight of the K intervals, the higher the energy level of the bit mapping of the columns of the interval. Exemplarily, the column weight of the K intervals may be the maximum column weight, the minimum column weight, or the average column weight of the first interval, the second interval, or the third interval, etc., which is not limited in this application.

[0247] When the column variable is a column type, the first LDPC base matrix may satisfy the following feature 3:

[0248] Feature 3: The M columns of the first LDPC base matrix are divided into the above K intervals or P sets according to column type. The column weights of the multiple columns included in the first interval and / or the second interval and / or the third interval of the above K intervals decrease as the number of columns increases.

[0249] The column types include: information column, core check column, and extended check column. Exemplarily, the first interval may include an information column, the second interval may include a core check column, and the third interval may include an extended check column; or the first interval may include an information column and a core check column, and the second interval may include an extended check column.

[0250] Step S312: The encoding device encodes the first bit sequence according to the first LDPC base matrix to obtain a second bit sequence.

[0251] Exemplarily, the first bit sequence is an information sequence to be encoded, and the second bit sequence is an information sequence to be sent.

[0252] Exemplarily, the encoding device can divide the information sequence to be encoded into groups of w bits, and then the encoder performs linear operations on the w information bits to obtain g check bits, and then combines the w information bits with the g check bits to obtain a codeword of length v=w+g. The mapping relationship from w-bit information bits to a codeword of length v bits can be represented by the above-mentioned first LDPC base matrix. According to the above-mentioned first LDPC base matrix, a codeword sequence can be generated accordingly to complete the encoding process.

[0253] Alternatively, the second bit sequence may be a bit sequence that has undergone rate matching.

[0254] Step S314: The encoding device performs bit interleaving on the second bit sequence to obtain a third bit sequence.

[0255] Exemplarily, the encoding device may interleave the first bit sequence by the reverse row-column interleaving method to obtain a third bit sequence.

[0256] Step S316: The encoding device maps the third bit sequence to a QAM symbol.

[0257] Specifically, the encoding device maps bits corresponding to at least one fourth column in the third bit sequence to a first energy level of the QAM symbol, and maps bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol.

[0258] The at least one fourth column and the at least one fifth column belong to the M columns, the column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column, and the first energy level is higher than the second energy level.

[0259] Step S318: the encoding device outputs the modulated QAM symbols.

[0260] The “output modulated QAM symbols” here can also be understood as sending the modulated QAM symbols to the decoding device.

[0261] Step S320: The decoding device obtains the QAM symbol to be demodulated and demodulates it to obtain a first information sequence.

[0262] The first information sequence is a sequence of LLR information obtained after demodulation, wherein each LLR information represents the probability that the bit at the corresponding bit position is 0 or 1.

[0263] Step S322: The decoding device deinterleaves the first information sequence to obtain a second information sequence.

[0264] The second information sequence is a sequence of LLR information.

[0265] Step S324: The decoding device decodes the second information sequence, determines the information bits, and obtains a third information sequence.

[0266] Step S326: the decoding device outputs a third information sequence.

[0267] In step S320 to step S326, the demodulation, deinterleaving and decoding processes performed by the decoding device are respectively the inverse processes of the modulation, interleaving and encoding performed by the encoding device, and the principle is the same as that of the encoding device. At the decoding device end, the LLR information obtained after demodulating the QAM symbol corresponds to the bits at the encoding device end, specifically including information bits and check bits. Based on the description of the encoding device side, those skilled in the art can know how to demodulate, deinterleave and decode at the decoding device side, which will not be repeated here.

[0268] It should be noted that the closer the number of columns of the first LDPC base matrix is ​​to the front (that is, the higher the column weight of the column of the first LDPC base matrix is), the lower the energy level of the bit mapping of the column of the first LDPC base matrix is. The present application can also provide another first LDPC base matrix: the closer the number of columns of the first LDPC base matrix is ​​to the front (that is, the lower the column weight of the column of the first LDPC base matrix is), the higher the energy level of the bit mapping of the column of the first LDPC base matrix is. In this case, the encoding device can interleave the second bit sequence by the above-mentioned row-column interleaving method to obtain a third bit sequence.

[0269] The communication method 300 described above provides a first LDPC base matrix with better performance. The first LDPC base matrix can not only omit the first interleaving process in the above interleaving method 200 and simplify the above interleaving method 200, but also accelerate the convergence speed and improve the overall performance.

[0270] Specifically, the first LDPC base matrix also adopts a "raptor-like" structure, which can be gradually expanded to a low code rate through a high code rate core matrix, so that it can flexibly support encoding of various code rates. The code rates required in different communication scenarios are different, so the column weight of the above-mentioned first LDPC base matrix will change during the expansion of the first LDPC base matrix from a high code rate to a low code rate. Based on this, the present application provides a second LDPC base matrix, and the column weight of the second LDPC base matrix will basically not change during the expansion of the second LDPC base matrix from a high code rate to a low code rate.

[0271] For example, Fig.12 This is an example of the second LDPC. During the expansion process, a new check equation c2 (corresponding to an expanded row) will be added to the second LDPC base matrix. c2 is used to eliminate a check equation c1 (corresponding to a row in the high code rate region) in the high code rate region of the second LDPC base matrix to perform low code rate expansion. After elimination, an equivalent check equation c3 will be obtained. Check equation c3 is used to replace c1, so it can be understood that c1 is split into c2 and c3. In this expansion process, the column weight of each column of the second LDPC base matrix will not be increased.

[0272] For example, Fig.12 The second LDPC base matrix shown includes N rows, each of the N rows corresponds to an indicator sequence θ. Fig.12 The i in the leftmost θ(i) indicates the number of rows of the second LDPC basis matrix, and θ(i) indicates that the i-th row of the second LDPC basis matrix needs to be eliminated with the θ(i) row when expanding, so the i-th row is related to the θ(i)-th row. For example, θ(5)=3 corresponding to the 5th row indicates that the 3rd row needs to be eliminated with the 5th row, and the result of the elimination is used to replace the 3rd row; for another example, θ(6)=4 corresponding to the 6th row indicates that the 4th row of the second LDPC basis matrix needs to be eliminated with the 6th row, and the result of the elimination is used to replace the 4th row.

[0273] Exemplarily, the above-mentioned elimination process may not be performed at the encoding device end (ie, the transmitting end), and the elimination process may be performed by the decoding device (ie, the receiving end) during decoding.

[0274] Optionally, the protocol may store a base matrix and an indicator sequence θ corresponding to the base matrix.

[0275] from Fig.12 It can be seen that, except for the first 4 rows corresponding to the high code rate region, θ(i)=0 of the second LDPC base matrix, θ(i)>0 for other extended rows, so other extended rows are all expanded based on the core rows of the high code rate region.

[0276] Fig.12The design of the matrix corresponding to the row of θ(i)=0 of the second LDPC base matrix shown can refer to the design rules of the first LDPC base matrix in the above communication method 300, which will not be repeated here.

[0277] Fig.12 The second LDPC base matrix shown can always maintain the characteristics of fast convergence speed and good overall performance during the process of expanding from high code rate to low code rate.

[0278] Fig.12 The example shown is that the extended rows of the second LDPC base matrix are all extended from the core rows of the high code rate region. Another possible situation is that the extended rows of the second LDPC base matrix are not all extended from the core rows of the high code rate region, such as Fig.13 The second LDPC base matrix is ​​shown.

[0279] Fig.13 The second LDPC base matrix shown has θ(i)=0 for the first 4 rows corresponding to the high code rate region, and θ(i)=0 for the extended rows of the 9th row, the 13th row, the 18th row, and the 20th row, so the extended rows of the 9th row, the 13th row, the 18th row, and the 20th row are irrelevant to other rows of the second LDPC base matrix. At this time, the extended rows of the 9th row, the 13th row, the 18th row, and the 20th row will increase the column weight of the second LDPC base matrix.

[0280] One implementation method is to ensure that the column weight in the high-code rate area is monotonically increasing or monotonically decreasing. This method can give priority to meeting the needs of high-code rate data transmission.

[0281] Exemplarily, the rows corresponding to the high-code rate region in the above implementation are consecutive rows of the row with the smallest row number θ(i)=0.

[0282] Another implementation method is: the number of extended rows with θ(i)=0 can be controlled to be smaller than a first threshold, so as to keep the column weight of the second LDPC base matrix consistent with the change trend of the column weight of the core region.

[0283] Another implementation method is: calculate the column weights of all columns of the second LDPC base matrix corresponding to the lowest code rate, and re-sort them in a monotonically increasing or monotonically decreasing order to form a new second LDPC base matrix that can meet the data transmission requirements of various code rates.

[0284] Exemplarily, the rows of the first submatrix may be all rows of θ(i)=0 in the second LDPC base matrix, and the columns of the first submatrix include information columns and core check columns. If the column weight of the second LDPC base matrix decreases as the number of columns increases, the extended check columns are located in the region with the largest number of columns of the second LDPC base matrix; if the column weight of the second LDPC base matrix increases as the number of columns increases, the extended check columns are located in the region with the smallest number of columns of the second LDPC base matrix.

[0285] For example, when Fig.12 or Fig.13 The second LDPC base matrix shown is arranged in a manner that the larger the number of columns, the lower the column weight, and the extended check column can be placed in the area with the largest number of columns; when Fig.12 or Fig.13 The second base matrix shown is arranged in a manner that the larger the number of columns, the higher the column weight, and the extended check column can be placed in the area with the smallest number of columns. In other words, the extended check column can be defaulted to the column with the lowest column weight. It should be noted that the column weight of the second LDPC base matrix is ​​the column weight of the columns of the above-mentioned first submatrix composed of rows with θ(i)=0.

[0286] The above is a detailed description of the application of the technical solution provided by the present application in QAM high-order modulation. Compared with the prior art of mapping the bits of columns with high column weight to the high energy level of the QAM symbol, the bits of columns with low column weight are mapped to the high energy level of the QAM symbol in the embodiment of the present application. Specifically, it can be implemented by the interleaving method 200 for performing the first interleaving using the first indicator sequence and the communication method 300 for performing row-column interleaving using the first LDPC base matrix provided in the embodiment of the present application, thereby improving the communication performance of wireless communication and accelerating the convergence speed.

[0287] Fig.14 This is a performance simulation comparison chart of the interleaving method 200 and the communication method 300 provided in the present application and the row-column interleaving method of the prior art. Fig.14 The performance simulation comparison diagram under different code rates (22 / 24, 22 / 25, 22 / 26, 22 / 27, 22 / 28, 22 / 29, 22 / 30, 22 / 31) is shown in the figure, and the BLER-SNR performance curve of the "interleaving method 200" or "communication method 300" provided by the present application (such as the "proposed scheme" in the legend) and the "row-column interleaving" scheme of the prior art (such as the "row-column interleaving" in the legend) is shown under each code rate. It can be seen that compared with row-column interleaving, the convergence speed of the interleaving method 200 or communication method 300 of the present application is accelerated, and the performance is also increased. As the code rate decreases, the convergence speed of the interleaving method 200 or communication method 300 of the present application is faster and faster, and the performance gain is higher and higher.

[0288] The interleaving method provided by the present application is described in detail above. The communication device provided by the present application is introduced below.

[0289] See also Fig.15 , the present application provides a communication device 1000.

[0290] The communication device 1000 may be a coding device, or a device applied to a coding device and capable of realizing the corresponding functions of the coding device in the embodiment of the method of the present application, such as a chip, a chip system or a circuit, etc. Alternatively, the communication device 1000 may be a decoding device, or a device applied to a decoding device and capable of realizing the corresponding functions of the decoding device in the embodiment of the method of the present application, such as a chip, a chip system or a circuit, etc.

[0291] Optionally, the communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is a coding device or a device applied to a coding device, the processing module 1001 is used to perform bit interleaving on the second bit sequence according to the first indication sequence to obtain a third bit sequence. The specific process can refer to the detailed description of the interleaving process in the interleaving method 200, which will not be repeated here. When the communication device 1000 is a decoding device or a device applied to a decoding device, the processing module 1001 is used to demodulate the QAM symbol to be demodulated.

[0292] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, a transceiver, a transceiver, or a transceiver device, etc., for performing receiving (or inputting) and / or sending (or outputting) operations. For example, when the communication device 1000 is an encoding device or a device applied to an encoding device, the communication module 1002 may be used to obtain an LDPC base matrix, output modulated QAM symbols, etc. When the communication device 1000 is a decoding device or a device applied to a decoding device, the communication module 1002 may be used to obtain QAM symbols to be demodulated, etc.

[0293] In addition, it should be noted that the aforementioned communication module and / or processing module can be implemented by a virtual module, for example, the processing module can be implemented by a software function unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module can also be implemented by a physical device, for example, if the device is implemented using a chip / circuit (such as an integrated circuit or a logic circuit, etc.). The communication module can be an input-output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operations) and output operations (corresponding to the aforementioned sending operations); the processing module is an integrated processor or microprocessor or circuit (such as an integrated circuit, a logic circuit, etc.).

[0294] The division of modules in this application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each example of this application may be integrated into one processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0295] like Fig.16 The present application also provides a communication device 1100. The communication device 1100 includes at least one processor 1110, which implements the functions of the encoding device or decoding device described in the above method embodiments.

[0296] Optionally, the processor 1110 is coupled to a memory, and the memory may be located within the communication device, or the memory may be integrated with the processor, or the memory may be located outside the communication device. The communication device 1100 may also include at least one memory 1120. The memory 1120 stores the computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to complete the interleaving method or deinterleaving method of any of the above embodiments.

[0297] Optionally, the communication device 1100 may further include a communication interface 1130, and the communication device 1100 may exchange information with other devices through the communication interface 1130. Exemplarily, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other types of interfaces.

[0298] The coupling in this application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, and is used for information exchange between devices, units or modules. The processor 1110 may cooperate with the memory 1120 and the communication interface 1130. The specific connection medium between the above-mentioned processor 1110, memory 1120 and communication interface 1130 is not limited in this application.

[0299] like Fig.17 , the present application also provides a chip (or chip system). The chip (or chip system) 30 may include a circuit 31 and an input / input interface 32. The circuit 31 may be a logic circuit, an integrated circuit, etc., and the input / output interface 32 may also be an input / output circuit, or an interface circuit, which can input information (or receive information) and output information (or send information). Optionally, the chip system may be composed of chips, or may include chips and other discrete devices. The chip 30 may be used to execute the methods performed by the encoding device or the decoding device in each embodiment of the present application.

[0300] In addition, the present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are run on a computer, the operations and / or processing performed by the encoding device or decoding device in each method embodiment of the present application are executed.

[0301] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processing performed by the encoding device or decoding device in the various method embodiments of the present application are executed.

[0302] In addition, the present application also provides a chip, the chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, so that the operation and / or processing performed by the encoding device or the decoding device in any method embodiment is executed.

[0303] Furthermore, the chip may further include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may further include a memory.

[0304] The present application provides a communication system, including the encoding device and the decoding device in the above method embodiment.

[0305] In this application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in this application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in this application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0306] The memory may be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or a volatile memory, such as a random-access memory (RAM). The memory is any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory in the present application may also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0307] The technical solution provided in this application can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium, etc.

[0308] In the present application, under the premise of no logical contradiction, the examples may reference each other, for example, the methods and / or terms between method embodiments may reference each other, for example, the functions and / or terms between device embodiments may reference each other, for example, the functions and / or terms between device examples and method examples may reference each other.

[0309] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0310] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0311] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0312] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0313] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0314] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0315] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An interleaving method, It is characterized in that The method comprises: Obtaining an LDPC base matrix, wherein the LDPC base matrix includes M columns; Encoding the first bit sequence according to the LDPC base matrix to obtain a second bit sequence; bit-interleaving the second bit sequence according to a first indicator sequence to obtain a third bit sequence, wherein the first indicator sequence is used to indicate a correspondence between the M columns and R energy levels included in a quadrature amplitude modulation (QAM) symbol, where M and R are positive integers; Mapping bits in the third bit sequence onto QAM symbols; Output modulated QAM symbols.

2. The method according to claim 1, It is characterized in that The first indication sequence satisfies at least one of the following characteristics: The elements in the first indicator sequence correspond one-to-one to the columns of the LDPC base matrix; The number of elements S in the first indication sequence is the same as the number of the M columns excluding the punctured columns; The smaller the sequence number of the element in the first indication sequence is, the higher the corresponding energy level is.

3. The method according to claim 1 or 2, It is characterized in that The first indicator sequence is used to indicate the corresponding relationship between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate the corresponding relationship between K intervals and the R energy levels, K is a positive integer greater than 2, The K intervals are divided according to the columns of the M columns.

4. The method according to claim 3, It is characterized in that The corresponding relationship between the K intervals and the R energy levels includes: the smaller the column weight of the K intervals, the higher the corresponding energy level.

5. The method according to claim 1 or 2, It is characterized in that The first indicator sequence is used to indicate the corresponding relationship between the M columns and the R energy levels included in the QAM symbol, including: the first indicator sequence is used to indicate the corresponding relationship between P sets and the R energy levels, P is a positive integer greater than 2, The P sets are divided according to the types of the M columns, and the types of the M columns include: information columns, core check columns, and extended check columns.

6. The method according to claim 5, It is characterized in that The first set includes information columns, the second set includes core check columns, and the third set includes extended check columns; Alternatively, the first set includes information columns and core check columns, and the second set includes extended check columns.

7. The method according to claim 5 or 6, It is characterized in that The multiple columns included in the first set of the P sets are arranged in ascending order of column weight.

8. The method according to any one of claims 1 to 7, It is characterized in that The bit interleaving the second bit sequence according to the first indicator sequence to obtain a third bit sequence includes: Perform a first interleaving on the second bit sequence according to the first indicator sequence to obtain a fourth bit sequence; Perform row-column interleaving on the fourth bit sequence to obtain the third bit sequence.

9. The method according to claim 8, It is characterized in that Assume that the second bit sequence is e, the fourth bit sequence is e1, and e1 and e satisfy the following relationship: for j=0to S for i=0to Z c -1 end for end for Wherein, S represents the number of elements of the first indicator sequence, j represents the index of the sequence number of the element contained in the first indicator sequence, s(j) represents the jth element of the first indicator sequence, and Z c is the lifting value of the LDPC basis matrix.

10. The method according to claim 8 or 9, It is characterized in that The first interleaving is performed before circularly buffering the second bit sequence or after circularly buffering the second bit sequence.

11. The method according to any one of claims 1 to 10, It is characterized in that The M columns are columns corresponding to the lowest code rate supported by the LDPC base matrix, or the M columns are columns corresponding to the highest code rate supported by the LDPC base matrix.

12. The method according to any one of claims 1 to 10, It is characterized in that Mapping bits in the third bit sequence onto QAM symbols, comprising: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of a QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, the at least one fourth column and the at least one fifth column belonging to the M columns, The column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column and the first energy level is higher than the second energy level.

13. A communication method, It is characterized in that The method comprises: Obtain a first LDPC base matrix, where the first LDPC base matrix includes M columns, where the M columns are divided into K intervals according to a column variable, where the column variable is a column weight or a column type of a first submatrix, where the column type includes an information column, a core check column, and an extended check column, and the first submatrix is ​​a partial or complete matrix of the first LDPC base matrix; Encoding the first bit sequence according to the first LDPC base matrix to obtain a second bit sequence; performing bit interleaving on the second bit sequence to obtain a third bit sequence; Mapping bits in the third bit sequence onto QAM symbols; Output modulated QAM symbols.

14. The method according to claim 13, It is characterized in that When the column variable is the column weight of the first submatrix, the K intervals include the first interval and / or the second interval and / or the third interval, the maximum column weight of at least one second column of the second interval is less than the minimum column weight of at least one first column of the first interval, the minimum column weight of at least one second column of the second interval is greater than the maximum column weight of at least one third column of the third interval, the number of columns of any column in the at least one third column is greater than the number of columns of any column in the at least one second column, and the number of columns of any column in the at least one second column is greater than the number of columns of any column in the at least one first column.

15. The method according to claim 14, It is characterized in that The smaller the column weight of the K intervals, the higher the corresponding energy level.

16. The method according to any one of claims 13 to 15, It is characterized in that The first sub-matrix is ​​a matrix corresponding to the lowest code rate supported by the first LDPC base matrix or a matrix corresponding to the highest code rate supported by the first LDPC base matrix.

17. The method according to claim 13, It is characterized in that When the column variable is a column type, the K intervals include a first interval and / or a second interval and / or a third interval, and the column weight of the at least one first column of the first interval decreases as the number of columns increases. The first interval includes an information column, the second interval includes a core check column, and the third interval includes an extended check column; Alternatively, the first interval includes an information column and a core check column, and the second interval includes an extended check column.

18. The method according to any one of claims 13 to 17, It is characterized in that The first LDPC base matrix includes N rows, and the i-th row of the N rows corresponds to an indicator sequence θ(i). When θ(i)>0, it means that when the first LDPC basis matrix is ​​expanded from a high code rate to a low code rate, the i-th row is related to the θ(i)-th row, and the i-th row is obtained by eliminating the θ(i)-th row; When θ(i)=0, it means that when the first LDPC base matrix is ​​expanded from a high code rate to a low code rate, the i-th row is independent of other rows of the first LDPC base matrix; The rows of the first submatrix are all rows corresponding to θ(i)=0 in the N rows, and the columns of the first submatrix include information columns and core check columns.

19. The method according to claim 18, It is characterized in that The extended check column has the largest number of columns.

20. The method according to any one of claims 13 to 19, It is characterized in that The performing bit interleaving on the second bit sequence to obtain a third bit sequence includes: Assume that the second bit sequence is e, the third bit sequence is f, and f and e satisfy the following relationship: for j=0to E / Q m -1 for i=0to Q m -1 end for end for Wherein, E represents the transmission length of the second bit sequence or the third bit sequence, Q m represents the number of bits contained in each modulation symbol, j represents the index of the QAM symbol, and i represents the index of the bit position contained in each QAM symbol.

21. The method according to any one of claims 13 to 20, It is characterized in that Mapping bits in the third bit sequence onto QAM symbols, comprising: mapping bits corresponding to at least one fourth column in the third bit sequence to a first energy level of a QAM symbol, and mapping bits corresponding to at least one fifth column in the third bit sequence to a second energy level of the QAM symbol, the at least one fourth column and the at least one fifth column belonging to the M columns, The column weight of the at least one fourth column is smaller than the column weight of the at least one fifth column and the first energy level is higher than the second energy level.

22. A communication device, It is characterized in that It includes a communication interface and a circuit, the communication interface is used to obtain a first bit sequence to be encoded, and input the first bit sequence to the circuit; the circuit is used to execute the method as described in any one of claims 1-21, encode the first bit sequence, obtain a second bit sequence, and bit interleave the second bit sequence to obtain a third bit sequence, and map the third bit sequence to a QAM symbol; the communication interface is also used to output the modulated QAM symbol.

23. A communication device, It is characterized in that It includes a communication interface and a circuit, wherein the communication interface is used to receive QAM symbols to be demodulated and input the QAM symbols to be demodulated to the circuit; the circuit is used to demodulate the QAM symbols to be demodulated to obtain a first information sequence, deinterleave the first information sequence to obtain a second information sequence, and decode the second information sequence to obtain a third information sequence; the communication interface is also used to output the third information sequence.

24. A communication device, It is characterized in that The method comprises a module or a unit for executing the method as claimed in any one of claims 1 to 21.

25. A communication device, It is characterized in that include: A processor, the processor is coupled to a memory, and the processor is used to execute a computer program or instruction stored in the memory so that the communication device executes the method according to any one of claims 1 to 21.

26. A computer-readable storage medium, It is characterized in that The computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer, the method according to any one of claims 1 to 21 is implemented.

27. A wireless communication system, It is characterized in that Comprising a communication device as claimed in claim 22 and claim 23.

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