Precoding during link setup

Abstract

Examples described herein relate to an Ethernet Physical Layer Transceiver (PHY) circuitry module for frame communication with a remote link partner. In some examples, an Ethernet PHY circuit module may include a physical medium dependent (PMD) circuit module and transmitter and receiver circuit modules for frame communication. In some examples, a PMD circuit module is to perform link training with a partner transmitter and selectively request the partner transmitter to apply a modulation scheme and precoding during the link training based on a magnitude of one or more equalizer coefficient values.

Description

Related Applications

[0001] This application claims priority to U.S. Application No. 18 / 143,034, filed May 3, 2023, which in turn claims priority and the benefit of U.S. Provisional Application No. 63 / 433,647, filed Dec. 19, 2022. The entire contents of these applications are incorporated herein by reference in their entirety. Background Art

[0002] Link training is a process used by a device connected to another device via a copper cable, backplane, or other wired or wireless signal transmission medium, through which the transmitter and receiver communicate with each other to tune the equalizer settings to mitigate frequency-dependent signal attenuation. Link training can tune the finite impulse response (FIR) filter for a channel in an application-specific integrated circuit (ASIC) or other device to achieve a desired bit error rate (BER), eye size, signal-to-noise ratio (SNR), or link error rate (e.g., uncorrectable and correctable forward error correction (FEC) errors, pseudorandom bit sequence (PRBS) errors, physical coding sublayer (PCS) errors, etc.). Brief Description of the Drawings

[0003] FIG. 1 depicts an example of an equalizer.

[0004] FIG. 2 depicts an example training sequence.

[0005] Figure 3 Depicts an example process.

[0006] FIGS. 4A-4D depict example excerpts from IEEE 802.3-2022.

[0007] FIG. 5 depicts an example of a potential use of 800GMII (800 Gb / s Media Independent Interface).

[0008] Figures 6A - 6C Depicts an example system.

[0009] Figure 7 Depicts a system capable of performing link monitoring.

[0010] Figure 8 Depicts a network interface.

[0011] Figure 9 Depicts an example computing system.

[0012] Figure 10 Depicts an example computing system. Detailed Description

[0013] Precoding encodes the bitstream before transmission and can improve the performance of the equalizer at the receiver. Precoding is a mathematical technique used to decompose errors into incoming errors and outgoing errors. According to Clause 136 of IEEE 802.3-2022 and similar clauses, Ethernet links with a data rate of 50 Gbps per channel and higher are required to implement the precoding capability for 4-level pulse amplitude modulation (PAM-4) modulation of the transmitted bitstream to help reduce the likelihood of error bursts in the receiver due to feedback and sequence-dependent equalizers (e.g., decision feedback equalizer (DFE), maximum likelihood sequence estimation (MLSE), or others). Although forward error correction (FEC) is applied, error bursts may result in uncorrectable errors. If an error burst is expected, precoding at the transmitter can improve the performance of the equalizer at the receiver. If an error burst is not expected (e.g., the errors are randomly distributed), precoding at the transmitter may not be desirable because error multiplication may occur when resolving into incoming errors and outgoing errors.

[0014] Some examples provide circuit modules and / or software executed by a processor in the receiver to determine whether to request precoding during the training phase of link establishment based on measurements made by the receiver on the received training pattern. Precoding can be requested during the training phase of link establishment and can be completed before exiting the training phase. For example, the receiver can determine whether to request the transmitter to apply precoding based on the convergence response of the decision feedback equalizer (DFE) coefficients in the receiver. If the magnitude of the normalized value of the DFE tap coefficients at the equalizer of the receiver is equal to or higher than a predetermined threshold (e.g., 0.5 or other value), the risk of error bursts may be high enough, and the receiver can request the transmitter to apply precoding to the transmitted training or data signal. In some examples, the training protocol allows the receiver to request a partner transmitter (e.g., the transmitter that transmits the training signal to the receiver) such that precoding can be applied to the signal transmitted to the receiver. The receiver's precoding request to the transmitter can be enabled, disabled, or allowed to be automatically determined.

[0015] For example, in addition to, or as an alternative to, selecting to use precoding, a device may use link training to tune the equalizer settings of at least one serializer / deserializer (SerDes). For example, a transmitter (Tx) may generate training data and send the training data to a receiver (Rx), and based on an analysis of the training signal, the receiver may provide feedback to the transmitter to tune the equalizer settings of the transmitter. For example, when the receiver utilizes a decision feedback equalizer (DFE), a maximum likelihood sequence estimation (MLSE)-based equalizer, a continuous linear time equalizer (LTE), a feedforward equalizer (FFE), or other equalizer types, the receiver may choose to request the application of PAM-4 and precoding for transmission. Thus, the receiver may request adjustment of the transmitter equalizer coefficients (e.g., pre-cursor coefficients, main coefficients, or post-cursor coefficients), modulation schemes (e.g., PAM-2 or PAM-4), and precoding (e.g., such as using PAM-4 modulation). For example, the transmitter may apply precoding to the transmitted bit stream using 1 / (1 + D) mod 4 precoding, such as the precoding described in IEEE Standard 802.3-2022, Clause 135.5.7.2. The receiver may optionally provide the ability to decode the precoded data and request precoding during control function link training.

[0016] For a link trained to operate at 50 Gbps or higher speed per channel, an Ethernet link between two partners may use physical medium dependent (PMD) control functions based at least on IEEE Standard 802.3-2022, Clause 136.8.11 to perform a startup protocol. As part of the startup protocol, a local receiver may request a change in the operation of the partner's transmitter to adjust and potentially improve the quality of the received signal. If the receiver requests that its link partner transmitter change the preamble equalization settings, main cursor equalization settings, or post-cursor equalization settings, the eye diagram inspection process may be started again. In some examples, the receiver inspects the signal eye diagram after applying equalization to the signal and determines whether the eye diagram height and / or eye diagram width are within the configured parameters. The receiver may determine to terminate link training because the eye diagram is acceptable, or continue training to further adjust the eye diagram parameters. The receiver may analyze factors other than the signal to determine whether to continue or terminate link training.

[0017] Since both link partners include a transmitter and a receiver, the link partners may train the transmitters of the opposite partner simultaneously or after training the transmitter-receiver pair. After the link is trained, the two devices may use the applied precoding to send data traffic (e.g., non-training signals).

[0018] FIG. 1 shows an example of a receiver architecture. A signal received from a channel (e.g., a signal propagation medium) can be equalized and conditioned by a continuous-time linear equalizer (CTLE) and a variable gain amplifier (VGA), sampled by an analog-to-digital converter (ADC), and further equalized using a programmable circuit module. A slicer can be used to make a decision on the received bits (e.g., Data[n]), and an error between the equalized signal and the decision can be calculated (e.g., Error[n] = Equalized Signal[n] – Data[n]).

[0019] Equalizer 102 can include an equalizer such as FFE and / or DFE, and its output can be used to determine ISI. Link monitoring 104 of the PHY can calculate a measure of residual ISI (unequalized inter-symbol interference (ISI) and reflection-related ISI after reflections are detected on the impulse response) (based on the scans described previously). Link monitoring 104 of the physical layer interface (PHY) can perform ISI detection, and because it is used during task mode traffic, it operates non-destructively for the normal operation of the link. Link monitoring 104 can measure channel ISI caused by insertion loss and reflections. Link monitoring 104 can receive the receiver error signal and the detected data stream, and determine whether a change in the ISI tap value indicates degradation of the link or channel or a poor match in the connection. For example, link monitoring 104 can calculate the projection of the nth tap ISI on the error signal by integrating Error[n]*Data[n-k] for the nth tap of the ISI. For a measurement sequence with n values, different taps of the ISI can be measured, and the impulse response of the system can be plotted. The value of n can be negative or positive to estimate the leading ISI tap or the trailing ISI tap. To determine the span (n range) of the reflection, a threshold can be set, and the tap batch that exceeds the threshold can be counted or identified as reflection ISI. The tap batch that does not exceed the threshold can be considered noise. In some examples, link monitoring circuit module 104 can be implemented as a process executed by a processor or microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or other programmable hardware device.

[0020] The use of pre - coding can mitigate the likelihood of error bursts that result from making incorrect decisions (bit errors) about specific bits in a receiver and the amplification effect of the DFE and coefficients on this error. When a sample causes a bit error and this sample is multiplied by a DFE coefficient for subsequent bits as part of the echo cancellation function of the DFE, the application of the coefficient can cause the sampled bit to be mis - evaluated (e.g., recording a "0" instead of the true value "1"), and cause another bit error. This bit error can in turn cause another bit error, and so on until the coefficient decays.

[0021] Figure 2 depicts an example of a PMD control state diagram copied from IEEE 802.3 - 2022. Transmitter and receiver pairs can apply the operations of the state diagram to change the transmitter equalization coefficients, or change to predefined initial conditions, or through individual coefficient control.

[0022] Figure 3 A process is shown that can be used by a receiver to determine when a transmitter enables data pre - coding. This process can be used in conjunction with at least the control state diagram shown in Figure 2. For example, the PMD of a receiver implemented as one or more of firmware, software, and / or hardware can at least perform the training process of Figure 136 - 7 of IEEE 802.3 - 2022. Figure 136 - 7 of IEEE 802.3 - 2022 provides an example of the transmitter startup operation. However, the example can be applied to earlier or later versions of 802.3 - 2022 or its variants or other standards. Some examples utilize control function training, where the receiver can converge its equalizer to the input signal and adjust its DFE coefficients or other parameters. The receiver can request the transmitter to perform pre - coding and can re - train the receiver based on the monitored absolute magnitude of the DFE coefficients exceeding a programmable threshold.

[0023] This process assumes that the automatic determination of pre - coding is enabled. If pre - coding is persistently enabled or disabled at the start of this process, then this process can be completed after reaching the TX EQ settings. During the initialization phase of Figure 2, the PMD control function link training can be entered. For example, the initialization phase can refer to the state of the transmitter and receiver pair before the transmitter sends a training signal. During the SEND_TF phase of Figure 2, the receiver (RX) locks onto the input training signal sent by the transmitter. During SEND_TF, at 302, according to IEEE standard 802.3 - 2022 clause 136.8.11 and Figure 136 - 7, initial equalization and identification of the control frame for alignment can begin. For example, the SEND_TF phase can refer to the state where the transmitter is about to send a training signal to the receiver.

[0024] During the TRAIN_LOCAL phase of Figure 2, at 304, the receiver may request the transmission of a training signal encoded using a modulation scheme (e.g., PAM-4) without precoding the signals transmitted to the receiver via one or more channels. For example, the TRAIN_LOCAL phase may refer to a state where link training occurs for a specific amount of time. Example training signals include training signals generated by a pseudo-random binary sequence 13 (PRBS13) polynomial based on a seed value. During TRAIN_LOCAL, at 306, the receiver may adapt to the training signal by performing receiver equalization tap optimization. During TRAIN_LOCAL, the receiver may perform initial equalization and identify at least one control frame for alignment. Example control frames are defined at least in IEEE 802.3-2022, section 136.8.11.1.

[0025] During TRAIN_LOCAL, at 308, the receiver may determine whether to request the transmitter PMD to adjust one or more equalizer (EQ) settings based on an adaptation scheme. The adaptation scheme may determine whether to perform equalization at the receiver, transmitter, or both the receiver and transmitter to improve the quality of the signals received over the channel. Example adaptation schemes include least mean square (LMS) error indication to determine how to adjust the (one or more) transmitter equalizer settings to reduce the slope of the LMS error.

[0026] During TRAIN_LOCAL, based on the receiver determining to request the transmitter to adjust one or more equalizer (EQ) settings, at 310, the receiver may request a change to the transmitter coefficients and may use bits 4-2 of Table 136-9 (replicated in Figure 4B) to request a change to one or more transmitter FFE coefficients (such as C-1 or C+1). The process may return to 306, where the receiver may adapt to the training signal generated based on the adjusted transmitter coefficient settings.

[0027] During TRAIN_LOCAL, based on the receiver not determining to request the transmitter to adjust one or more equalizer (EQ) settings, at 320, it may be determined whether to request precoding of the training signal or the data signal based on the magnitude of the DFE coefficient values. For example, the DFE may include 8 taps or some other number of taps, and the taps may have associated coefficient values. For example, at 320, it may be determined whether |DFE coefficient| > a threshold, where the DFE coefficient may refer to one or more DFE coefficient values. If the magnitude of one or more DFE coefficient values is greater than the threshold, the current bit may affect the next bit, and incorrect decisions may propagate to affect future bits. There may be a correlation between DFE coefficient values greater than the threshold and the occurrence of error bursts. The threshold may be determined based on operator selection, system simulation, or laboratory characterization and may be based on a hysteresis margin.

[0028] For example, FIG. 4D depicts an example impulse response for channel equalization between two link partners at a receiver. The inter-symbol interference (ISI) contribution due to packaging and connectors is shown in the trailing pulses after the cursor. The DFE at the receiver can target the energy at the unit interval (UI) after the main cursor (sample position) and attempt to cancel that energy. If these coefficients are too large such that there is a risk of propagating an incorrect sample to subsequent bits via the applied coefficients, causing a burst of errors, then a control frame as shown in FIG. 4B can be used during 322 to request precoding.

[0029] Section 135.7.2 of IEEE 802.3-2022 (replicated in FIG. 4A) provides a non-limiting example of how precoding is applied. The precoded data can convert an error sequence into an in-error and an out-of-error. If the sequence is 1 bit long, then precoding can result in a 1-bit error, creating a 2-bit error (in and out). Thus, enabling precoding in the case of randomly scattered errors can result in a doubling of the number of errors. Bit error rate feedback from the receiver during training can further qualify whether precoding is to be enabled at the receiver. In the case of using a known pattern during training, forward error correction (FEC) at the receiver can compensate for errors to balance between enabling precoding or not and using only FEC to correct errors.

[0030] Return reference Figure 3 , during TRAIN_LOCAL, at 322, the receiver can request the transmitter to apply precoding. In some cases, precoding can be associated with PAM-4 or other signal modulation types (such as 6-level pulse amplitude modulation (PAM-6) or others). For example, the receiver can request the transmitter to apply PAM-4 and precoding by using bits 9 and 8 (modulation and precoding request (value 11)) in Table 136-9 (replicated in FIG. 4B). FIG. 4C depicts an example of the TX response to a request for PAM-4 and precoding using the information in bits 11:10 of Table 136-10 to indicate the use of PAM-4 and precoding.

[0031] Based on determining that the amplitude DFE coefficients are not greater than a threshold and that the transmitter is not to apply precoding, link training can be completed, and a local version of receiver ready occurs. During the TRAIN_REMOTE phase of FIG. 2, at 330, the receiver does not request the transmitter to apply precoding to the transmitted training signal. For example, TRAIN_REMOTE can refer to a state where link training has been completed.

[0032] In some examples, a receiver (RX) equalizer (EQ) and / or a transmitter (TX) EQ can be reconfigured, and another determination of whether to apply precoding can occur during another training phase. For example, the training phase can occur periodically or in response to a request from the receiver or system administrator.

[0033] FIG. 5 depicts an example of a potential use of 400GMII (400 Gb / s Media Independent Interface). The example is not limited to this scenario. The various examples described herein can utilize a PMD that can determine whether to apply precoding, and the determination can occur during another training phase, as described herein.

[0034] Figure 6A is a block diagram illustrating an Ethernet port circuit module in a network interface controller 600. The Ethernet port logic includes a Media Access Control (MAC) module 602, a reconciliation sublayer module 604, and a PHY module 606. The PHY module 606 can include a Physical Medium Attachment (PMA) sublayer module 612, a Physical Medium Dependent (PMD) sublayer 610, a Forward Error Correction (FEC) module 614, and a Physical Coding Sublayer (PCS) module 616.

[0035] The Auto-Negotiation (AN) circuit module 608 can perform AN in a manner consistent with FIG. 73-1 of IEEE 802.3-2022. For example, as described herein, the AN circuit module 608 can use the base page and next page of message code 2 to advertise technology and FEC capabilities to a link partner. In some examples, as described herein, the AN circuit module 608 can advertise the ability to support 800 GbE PHY.

[0036] The MAC module 620 is configured to transfer data to and from the PHY module 606. The Reconciliation Sublayer (RS) module 618 can provide a mapping operation that reconciles signals at the Media Independent Interface (MII) to the Media Access Control (MAC)-Physical Signaling Sublayer (PLS) service definition. The MAC module 620 can be configured to implement aspects of MAC layer operations, and the RS module 618 can be configured to implement reconciliation sublayer operations.

[0037] The Physical Medium Dependent (PMD) sublayer 610 can be responsible for connecting to the transmission medium through an interface, the Media Dependent Interface (MDI) 622. Some examples described herein that request the transmitter to use PAM-4 and precoding can be performed by the PMD 610.

[0038] The Physical Medium Attachment (PMA) sublayer 612 can perform transmission, reception, signal detection, clock recovery, and skew alignment. The PMD 610 and PMA 612 can be configured to transmit and receive serial data through the MDI 622.

[0039] In some examples, the PMD 610 and PMA 612 can include or use a serializer / deserializer (SerDes). In some examples, link training and retraining can be provided to adjust the filter parameters of the transmit and / or receive equalizers used by the SerDes. For example, a software SerDes driver executed by a processor in a network interface or host can be used to change the transmit equalizer parameters. In some examples, any combination of hardware, software, and / or firmware can be used to manage and perform link training and / or link retraining.

[0040] In some examples (e.g., for 100GBASE-CR1 or 100GBASE-KR1), the FEC module 614 can decode the data passed from the PMD 610 and PMA 612 to the PCS module 616, or encode the data passed from the PCS module 616 to the PMD 610 and PMA 612a, 612b. In some examples (e.g., for 200G and 400G modes), the PCS module 616 includes the FEC module 614. Forward error correction codes can improve the reliability of data transmission at higher line speeds.

[0041] In the transmit direction, the MAC module receives the data to be transmitted through the host interface 622. The MAC module 620 can receive the data to be transmitted through the host interface 622. Before passing the MAC frame to the PHY module 606, the MAC module 620 can generate a MAC frame that includes, in addition to the received data, an inter-packet gap (IPG), a preamble, a start frame delimiter (SFD), padding, and cyclic redundancy check (CRC) bits. The PHY module 606 can encode the MAC frame for reliable serial transmission through the MDI 624.

[0042] In the receive direction, the MAC module 620 can receive the MAC frame from the PHY module 606 through the data bus. The MAC module 620 can perform Ethernet frame detection and verification, cyclic redundancy check (CRC) verification, update statistical counters, remove the CRC, preamble detection and removal, and start frame delimiter (SFD) detection and removal, and forward the remaining portion of the MAC frame including headers of other protocols to the next layer (e.g., the Internet Protocol (IP) layer) for processing. The PHY module 606 can decode the MAC frame received through the MDI 624.

[0043] Figure 6B A simplified example of a transmitter-receiver pair between network interface controller 630 and device 640 is illustrated. MDI 635 provides a link between network interface controller 630 and device 640 by passing data in parallel over one or more channels. Device 640 can be any device, such as another NIC, switch, router, server, host computing platform, and so on. AN 632 and 642 can be used to perform AN.

[0044] Network interface controller 630 can include host receiver 634 and host transmitter 636 for at least one channel of the electrical link between network interface controller 630 and device 640. Device 640 can include module receiver 646 and module transmitter 644 for the electrical link between network interface controller 630 and device 640.

[0045] For example, link training controller 638 of NIC 630 can initiate or manage link establishment, link training, or link retraining operations as described herein. Link training controller 638 can be implemented as any one or a combination of a driver, microcontroller, or other software in the network interface or host.

[0046] Transmitter (Tx) 636 / 644 or receiver (Rx) 634 / 646 can use SerDes to serialize or deserialize signals. When SerDes is turned on and signals are received, Rx tuning can be used to improve signal quality. When there is a time limit for performing Rx tuning, the signals are to be delivered to the PCS layer within that time limit, and if the link is acceptable, the link comes up. If the link fails, training can be restarted. In some examples, Tx 636-Rx 646 and / or Tx 644-Rx 634 can utilize independent Rx tuning. In some examples, the amount of time for performing equalizer tuning is the same for Tx636-Rx 646 and / or Tx644-Rx 634.

[0047] According to various examples, link training controller 638 can perform link training and selectively request the transmitter to use PAM-4 and precoding as described herein.

[0048] Communication between devices can occur using any protocol. For example, an Ethernet frame can be sent from NIC 630 to device 640. For example, an Ethernet frame can be sent from device 640 to NIC 630. An Ethernet frame can include one or more of the following: preamble, start frame delimiter (SFD), destination MAC address, source MAC address, Ethernet type field, length field, frame check sequence (e.g., cyclic redundancy check (CRC)), and payload.

[0049] Figure 6C FIG. 1 depicts an example system for communicatively coupling a network device to another network device. For example, devices 650 and 670 may include network devices such as one or more of a network interface, switch, router, server, host computing platform, interconnect, fabric, rack, or any computing or communication device. For example, device 670 may be connected to an interface having a plurality of electrical links (e.g., a backplane or copper cables). The system provides a plurality of channels of transmit-receive pairs that can be used to transmit or receive electrical signals between devices 650 and 670. The channels may transmit and / or receive signals. The transmitter of a channel may use an equalizer implemented in an analog circuit to generate an electrical signal for transmission. The equalizer may have one or more current sources for creating the signal, and thus the weights of the current sources may be adjusted to change the signal characteristics. The equalizer settings may be modified to change the weights of the current sources. For example, a digital-to-analog converter (DAC) may be used to create the signal in the digital domain and output the result in analog format.

[0050] According to various examples, transceiver 680 may perform link training and selectively request the transmitter to use PAM-4 and precoding, as described herein. Transceiver 552 may perform operations similar to those of transceiver 680 with device 670 to perform link training and selectively request the transmitter to use PAM-4 and precoding, as described herein.

[0051] Various examples may use one or more of microcontrollers 684-0 through 684-N of device 670 to initiate and manage link training of the transmitter and / or receiver equalizer settings with any of microcontrollers 656-0 through 656-N of device 650.

[0052] Transceiver 680 may be used for transmitting and receiving electrical signals between devices 670 and 650. Transceiver 680 may provide a plurality of transmit and receive channels for electrical signal communication between devices 670 and 650. For example, channels 682-0 through 682-N may provide transmit and receive circuit modules for coupling to the receive and transmit circuit modules of channels 654-0 through 654-N of device 650. Channels 682-0 through 682-N may provide serializer / deserializer (SerDes) formatting of the signals. In some examples, transceiver 680 may be part of a PMD or PHY.

[0053] Device 670 can be communicatively coupled to device 650 via interconnect 660. Interconnect 660 can be an electrical signal conductor that couples the pins or holes of channels 682-0 to 682-N of pluggable device 670 to the holes or pins of channels 654-0 to 654-N of device 650. Device 650 can transmit or receive signals in electrical format to or from device 670.

[0054] Device 650 can include transceiver 652 for communicating with device 670. Transceiver 652 can include channels 654-0 to 654-N, where any one of channels 654-0 to 654-N includes receive and transmit circuit modules. In some examples, transceiver 652 can be part of a PMD or PHY. Any microcontrollers 656-0 to 656-N can be used to manage the operation of their channels.

[0055] In some examples, a single microcontroller can manage the equalizer settings of one or more channels. The one or more parameters can cause the receiver or transmitter device in any one of channels 654-0 to 654-N to adjust its equalizer settings for a particular tap, whether increasing or decreasing the coefficient value of the equalizer tap. In some examples, the setting of a tap can be adjusted independently of the adjustment of the setting of another tap.

[0056] In some examples, device 650 can request a change in the equalizer setting of any tap of the transmitter equalizer circuit of device 670. Similarly, device 670 can request a change in the equalizer setting of any tap of the transmitter equalizer circuit of device 650. Thus, device 670 and device 650 can adjust the transmitter equalizer settings used by the partner device. In addition, either device 670 or device 650 can adjust the receiver equalizer settings to compensate for channel distortion.

[0057] For example, to initiate an equalizer setting change, any microcontrollers 684-0 to 684-N can determine the signal quality of the received signal, determine which transmitter side tap of device 650 is to be changed, and whether to increment or decrement the setting of the tap. For example, the eye opening of the received signal can be measured. The microcontroller can estimate inter-symbol interference (ISI) and select the setting based on the ISI reaching a minimum value. The microcontroller can search for available transmitter tap settings and select the setting that results in the largest open eye. The transmitter equalizer settings can start changing periodically at link startup or after link startup and can run periodically. Similar operations can be performed for microcontrollers 656-0 to 656-N to adjust the transmit equalizer settings of device 670.

[0058] Device 670 and / or device 650 may perform packet processing, such as one or more of media access control, any protocol layer processing, security, routing, destination lookup, etc.

[0059] Figure 7 A system that can perform link training is depicted. Host 700 may utilize network interface device 720 to communicate with host 760 via network interface device 770 using link 750. An optical and / or electrical signal propagation medium may provide communication for link 750. Various examples of host 700 and host 760 are described with respect to FIG. 4, and various examples of network interface device 720 and network interface device 770 are described with respect to FIGS. 5 and / or 6. The examples described herein may be used in 5G base stations or cellular communication networks.

[0060] Host 700 may use one or more processors to execute port configuration software 706. A communication device manufacturer may provide port configuration software 706 to manage the operation of serializer-deserializer (SerDes) 732 that communicates using one or more of links 750. Port configuration 706 may implement the use of one or more ports and establish link 750 between network interface device 720 and network interface device 770. Port configuration 706 may manage the use of ports and links by controlling the API and driver 708 stack of link media access controller (MAC) ( Figure 7 not shown in the figure) and physical layer interface (PHY) 730.

[0061] During the training of link 750 using driver and API 708, port configuration software 706 may configure the operation of link monitoring circuit module 740 in PHY 730 of network interface device 720 to perform monitoring of one or more of links 750. In some examples, link monitoring circuit module 740 may be implemented as a process executed by a processor or microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or other programmable hardware device. Link monitoring circuit module 740 may monitor the eye height of the analog signal received from the transmission medium (e.g., cable or optical fiber) by the SerDes among SerDes 732 or the digital conversion of the signal. Link monitoring circuit module 740 may perform link training and selectively request the transmitter to use PAM-4 and precoding, as described herein.

[0062] Link monitoring can be port mode agnostic and can be used for Ethernet (e.g., IEEE 802.3-2018), Common Public Radio Interface (CPRI) (e.g., CPRI Specification v7.0 (2015)), Peripheral Component Interconnect Express (PCIe) (e.g., PCI-SIG PCI Express (2015)), or another serial input / output (I / O) protocol.

[0063] Note that link monitoring can be utilized on one or both sides of a link. For example, PHY 780 can utilize link monitoring 782 that operates in a manner similar to link monitoring 740.

[0064] Figure 8 An example network interface is depicted. Various resources in the network interface can perform link training and selectively request that the transmitter use PAM-4 and precoding, as described herein. Transceiver 802 can be capable of receiving and transmitting packets that conform to an applicable protocol such as Ethernet as described in IEEE 802.3, although other protocols can also be used. Transceiver 802 can receive packets from the network via a network medium (not depicted) and transmit packets to the network. Transceiver 802 can include PHY circuit module 814 and Media Access Control (MAC) circuit module 816. PHY circuit module 814 can include encoding and decoding circuit modules (not shown) to encode and decode data packets according to an applicable physical layer specification or standard.

[0065] In some examples, as described herein, PHY 814 can select a PRBS polynomial and / or seed for generating training signals. In some examples, PHY 814 can include a PMD to select a PRBS polynomial and / or seed for training multiple channels. According to the examples described herein, various resources in the network interface can perform link establishment, link training, or link retraining.

[0066] MAC circuit module 816 can be configured to assemble data to be transmitted into packets that include a destination address and a source address along with network control information and an error detection hash value. Processor 804 can be any combination of a processor, core, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that allows programming of network interface 800. For example, processor 804 can provide identification of resources for performing a workload and generation of a bitstream for execution on the selected resources. For example, a “smart network interface” can use processor 804 to provide packet processing capabilities in the network interface.

[0067] The packet distributor 824 can use the time slot allocation or RSS described herein to provide the distribution of received packets for processing by multiple CPUs or cores. When the packet distributor 824 uses RSS, the packet distributor 824 can calculate a hash or make another determination based on the content of the received packet to determine which CPU or core is to process the packet.

[0068] The interrupt coalescer 822 can perform interrupt moderation, whereby the network interface interrupt coalescer 822 waits for multiple packets to arrive or for a time-out to expire before generating an interrupt for the host system to process the received packet(s). Receive Segment Coalescing (RSC) can be performed by the network interface 800, whereby portions of the input packet are combined into segments of the packet. The network interface 800 provides this combined packet to the application.

[0069] The Direct Memory Access (DMA) engine 852 can copy the packet header, packet payload, and / or descriptor directly from the host memory to the network interface or vice versa, rather than copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer.

[0070] The memory 810 can be any type of volatile or non-volatile memory device and can store any queues or instructions for programming the network interface 800. The transmit queue 806 can include data for transmission by the network interface or references to the data. The receive queue 808 can include data received by the network interface from the network or references to the data. The descriptor queue 820 can include descriptors that reference data or packets in the transmit queue 806 or the receive queue 808. The bus interface 812 can provide an interface to a host device (not depicted). For example, the bus interface 812 can be compatible with a PCI, PCI Express, PCI-x, Serial ATA, and / or USB compatible interface (although other interconnect standards can be used).

[0071] In some examples, the network interfaces and other examples described herein can be used in combination with base stations (e.g., 3G, 4G, 5G, etc.), macro base stations (e.g., 5G networks), pico base stations (e.g., IEEE 802.11 compatible access points), nano base stations (e.g., for point-to-multipoint (PtMP) applications), on-premises data centers, off-premises data centers, edge network elements, fog network elements, and / or hybrid data centers (e.g., data centers that use virtualization, cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

[0072] Figure 9 depicts a system. Components of system 900 (e.g., processor 910, network interface 950, etc.) perform link training and selectively request that the transmitter use PAM-4 and precoding as described herein. System 900 includes a processor 910 that provides processing, operation management, and instruction execution for system 900. Processor 910 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware for providing processing for system 900, or a combination of processors. Processor 910 controls the overall operation of system 900 and may be or include one or more programmable general or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of such devices.

[0073] In one example, system 900 includes an interface 912 coupled to processor 910, which may represent a higher-speed interface or high-throughput interface for system components that require a higher-bandwidth connection, such as memory subsystem 920 or graphics interface component 940 or accelerator 942. Interface 912 represents interface circuitry, which may be a standalone component or integrated onto the processor die.

[0074] The accelerator 942 can be a fixed-function or programmable offload engine that the processor 910 can access or use. For example, the accelerators among the accelerators 942 can provide compression (DC) capabilities, cryptographic services such as public-key encryption (PKE), cipher, hash / authentication capabilities, decryption, or other capabilities or services. In some examples, additionally or alternatively, the accelerators among the accelerators 942 provide the in-situ selection controller capabilities as described herein. In some cases, the accelerator 942 can be integrated into the CPU socket (e.g., into the connector of a motherboard or circuit board that includes the CPU and provides an electrical interface to the CPU). For example, the accelerator 942 can include a single-core or multi-core processor, a graphics processing unit, a logical execution unit, a single-level or multi-level cache, functional units that can be used to execute programs or threads independently, an application-specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and programmable processing elements such as a field-programmable gate array (FPGA) or a programmable logic device (PLD). The accelerator 942 can provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or the graphics processing units can be made available for use by artificial intelligence (AI) or machine learning (ML) models. For example, an AI model can use or include one or more of the following: reinforcement learning schemes, Q-learning schemes, deep Q-learning, or asynchronous advantage actor-critic algorithms (A3C), combined neural networks, recursive combined neural networks, or other AI or ML models. Multiple neural networks, processor cores, or graphics processing units can be made available for use by AI or ML models.

[0075] Memory subsystem 920 represents the main memory of system 900 and provides storage for code to be executed by processor 910 or data values to be used in execution routines. Memory subsystem 920 may include one or more memory devices 930, such as read-only memory (ROM), flash memory, one or more random access memories (RAM) (such as static random access memory (SRAM), dynamic random access memory (DRAM), or other memory devices), or a combination of such devices. Among other things, memory 930 also stores and hosts an operating system (OS) 932, etc., to provide a software platform for executing instructions in system 900. Additionally, applications 934 may execute from memory 930 on the software platform of OS 932. Applications 934 represent programs having their own operation logic to perform one or more functions. Processes 936 represent agents or routines that provide auxiliary functions to OS 932 or one or more applications 934 or combinations thereof. OS 932, applications 934, and processes 936 provide software logic to provide functionality for system 900. In one example, memory subsystem 920 includes a memory controller 922, which is a memory controller for generating commands and issuing commands to memory 930. It will be understood that memory controller 922 may be a physical part of processor 910 or a physical part of interface 912. For example, memory controller 922 may be an integrated memory controller integrated onto a circuit having processor 910.

[0076] In some examples, OS 932 may be Server or a personal computer, VMware vSphere, openSUSE, RHEL, CentOS, Debian, Ubuntu, or any other operating system. The OS and drivers may execute on CPUs sold or designed by Texas and other companies.

[0077] In some examples, the driver for the OS 932 or the network interface 950 can enable or disable the network interface 950 from performing link training and selectively request the transmitter to use PAM-4 and precoding, as described herein. In some examples, the driver for the OS 932 or the network interface 950 can enable or disable the network interface 950 from indicating support for performing link training and selectively request the transmitter to apply PAM-4 and precoding of the transmitted signal, as described herein. The network interface 950 can indicate to the OS 932 or the driver the ability to perform link training and selectively request the transmitter to use PAM-4 or other modulation schemes and precoding, as described herein. The network interface 950 can receive (e.g., from the OS 932 or the driver) configurations and instructions to perform or not perform link training and selectively request the transmitter to use PAM-4 or other modulation schemes and precoding, as described herein.

[0078] Although not specifically shown, it will be understood that system 900 can include one or more buses or bus systems between the devices, such as a memory bus, a graphics bus, an interface bus, or others. The bus or other signal lines can communicatively or electrically couple the components together, or both communicatively and electrically couple the components. The bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuit modules or combinations. The bus can include, for example, one or more of the following: a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire).

[0079] In one example, system 900 includes an interface 914 that can be coupled to interface 912. In one example, interface 914 represents interface circuitry that can include discrete components and integrated circuit modules. In one example, a plurality of user interface components or peripheral components or both are coupled to interface 914. The network interface 950 provides system 900 with the ability to communicate with remote devices (e.g., servers or other computing devices) via one or more networks. In some examples, the network interface 950 can refer to one or more of the following: a Network Interface Controller (NIC), a Remote Direct Memory Access (RDMA)-enabled NIC, a SmartNIC, a router, a switch, a forwarding element, an Infrastructure Processing Unit (IPU), a Data Processing Unit (DPU), or a network attached facility.

[0080] The network interface 950 may include an Ethernet adapter, a wireless interconnect component, a cellular network interconnect component, a USB (Universal Serial Bus), or other wired- or wireless-standard-based or proprietary interfaces. The network interface 950 may transfer data to devices in the same data center or rack or to remote devices, which may include sending data stored in the memory.

[0081] Some examples of the network interface 950 are part of an infrastructure processing unit (IPU) or a data processing unit (DPU), or are utilized by an IPU or a DPU. xPU may at least refer to an IPU, a DPU, a GPU, a GPGPU, or other processing units (e.g., accelerator devices). The IPU or DPU may include a network interface having one or more programmable pipelines or fixed-function processors to perform operation offloading that could otherwise be performed by a CPU. The IPU or DPU may include one or more memory devices. In some examples, the IPU or DPU may perform virtual switch operations, manage storage transactions (e.g., compression, encryption, virtualization), and manage operations performed on other IPUs, DPUs, servers, or devices.

[0082] Some examples of the network interface 950 may include a programmable packet processing pipeline having one or more consecutive stages with matching action circuit modules. The programmable packet processing pipeline may be programmed using one or more of the following: a protocol-independent packet processor (P4), software for open networking in the cloud (SONiC), a network programming language (NPL), DOCA TM , a data plane development kit (DPDK), OpenDataPlane (ODP), an infrastructure programmer development kit (IPDK), an x86-compatible executable binary, or other executable binaries or others.

[0083] Some examples of the network interface 950 may include a PHY circuit module that may perform link training and selectively request the transmitter to use PAM-4 and precoding, as described herein.

[0084] In one example, the system 900 includes one or more input / output (I / O) interfaces 960. The I / O interfaces 960 may include one or more interface components through which a user interacts with the system 900 (e.g., audio, alphanumeric, tactile / touch, or other connections through the interface). The peripheral interface 970 may include any hardware interface not specifically mentioned above. Peripheral devices generally refer to devices that are dependently connected to the system 900. A dependent connection is a connection where the system 900 provides a software platform or a hardware platform or both on which operations are performed and with which the user interacts.

[0085] In one example, system 900 includes a storage subsystem 980 for storing data in a non-volatile manner. In one example, in certain system implementations, at least some components of storage subsystem 980 may overlap with components of memory subsystem 920. Storage subsystem 980 includes one or more storage devices 984, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical disks or combinations thereof. Storage device 984 preserves code or instructions and data 986 in a persistent state (e.g., the value is retained even if power to system 900 is interrupted). While memory 930 is typically an execution or operating memory for providing instructions to processor 910, storage device 984 may generally be considered a “memory”. Although storage device 984 is non-volatile, memory 930 may include volatile memory (e.g., if power to system 900 is interrupted, the value or state of the data is indeterminate). In one example, storage subsystem 980 includes a controller 982 to interface with storage device 984. In one example, controller 982 is a physical part of interface 914 or processor 910, or may include circuitry or logic in both processor 910 and interface 914.

[0086] Volatile memory is memory whose state (and thus the data stored therein) is indeterminate if power to the device is interrupted. Non-volatile memory (NVM) devices are memory whose state is determinate even if power to the device is interrupted.

[0087] In an example, system 900 may be implemented using an interconnected compute expansion unit (sled) of a processor, memory, storage, network interface, and other components. High-speed interconnects may be used, such as: Ethernet (IEEE 802.3), Remote Direct Memory Access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Quick UDP Internet Connections (QUIC), Converged Ethernet RDMA (RoCE), Peripheral Component Interconnect Express (PCIe), Intel QuickPath Interconnect (QPI), Intel UltraPath Interconnect (UPI), Intel on-chip system fabric (IOSF), Omni-Path, Compute Express Link (CXL), HyperTransport, High-Speed Fabric, NVLink, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Infinity Fabric (IF), Accelerator Cache Coherence Interconnect (CCIX), 3GPP Long-Term Evolution (LTE) (4G), 3GPP 5G, and their variants. Data may be replicated or stored to virtualized storage nodes or accessed using protocols such as fabric-based NVMe (NVMe-oF) or NVMe-based protocols.

[0088] Communication between devices may be performed using a network, interconnect, or circuit module that provides chip-to-chip communication, die-to-die communication, packet-based communication, communication through device interfaces, fabric-based communication, etc. Die-to-die communication may be compliant with an Embedded Multi-Die Interconnect Bridge (EMIB).

[0089] Figure 10Illustrates an example system. In this system, the IPU 1000 uses one or more of the processor 1006, processor 1010, accelerator 1020, memory pool 1030, or servers 1040-0 to 1040-N to manage the performance of one or more processes, where N is an integer greater than or equal to 1. In some examples, the processor 1006 of the IPU 1000 can execute one or more processes, applications, VMs, containers, microservices, etc. that request to execute a workload through one or more of the processor 1010, accelerator 1020, memory pool 1030, and / or servers 1040-0 to 1040-N. The IPU 1000 can communicate with the processor 1010, accelerator 1020, memory pool 1030, and / or servers 1040-0 to 1040-N using the network interface 1002 or one or more device interfaces. The IPU 1000 can use the programmable pipeline 1004 to process packets to be transmitted from or received by the network interface 1002. As described herein, the IPU 1000 can include a PHY circuit module that can perform link training and selectively request the transmitter to use PAM-4 and precoding.

[0090] Examples herein can be implemented in various types of computing and networking devices such as switches, routers, racks, and blade servers (such as those employed in data center and / or server farm environments). Servers used in data centers and server farms include arrayed server configurations such as rack-based servers or blade servers. These servers are interconnected in communication via various network devices (provision), such as partitioning a collection of servers into local area networks (LANs) with appropriate switching and routing facilities between the LANs to form a private intranet. For example, cloud hosting facilities typically employ large data centers with a large number of servers. A blade includes a separate computing platform configured to perform server-type functions, i.e., a "server on a card". Thus, a blade can include components common to a traditional server, including a main printed circuit board (motherboard) that provides internal wiring (e.g., a bus) for coupling appropriate integrated circuits (ICs) and other components mounted on the board.

[0091] In some examples, the network interfaces and other examples described herein can be used in conjunction with: base stations (e.g., 3G, 4G, 5G, etc.), macro base stations (e.g., 5G networks), pico stations (e.g., IEEE 802.11 compliant access points), nano stations (e.g., for point-to-multipoint (PtMP) applications), micro data centers, local data centers, remote data centers, edge network elements, fog network elements, and / or hybrid data centers (e.g., data centers using virtualization, cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

[0092] For example, link establishment, link training, or link retraining can be performed by base stations, local data centers, remote data centers, edge network elements (computing elements physically closer to the base station or network access point than the data center), fog network elements (computing elements physically closer to the base station or network access point than the data center but farther from the edge network), and / or hybrid data centers (e.g., data centers using virtualization, cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments) that support communication using wired or wireless protocols (e.g., 3GPP Long Term Evolution (LTE) (4G) or 3GPP 5G). The network or computing elements can be used in a local area network (LAN), a metropolitan area network (MAN), a network with devices connected using fiber optic links, a campus area network (CAN), or a wide area network (WAN).

[0093] Various examples can be implemented using hardware elements, software elements, or a combination of both. In some examples, the hardware elements can include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chip sets, and so on. In some examples, the software elements can include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or combinations thereof. Determining whether to implement an example using hardware elements and / or software elements can vary according to any number of factors, such as the desired computing rate, power level, heat tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints. The processor can be a hardware state machine, digital control logic, a central processing unit, or one or more combinations of any hardware, firmware, and / or software elements.

[0094] Some examples can be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium can include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium can include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. In some examples, the logic can include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or combinations thereof.

[0095] According to some examples, the computer-readable medium can include a non-transitory storage medium for storing or holding instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform the methods and / or operations according to the described examples. The instructions can include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions can be implemented according to a predefined computer language, manner, or syntax for commanding a machine, computing device, or system to perform a specific function. Any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language can be used to implement the instructions.

[0096] One or more aspects of at least one example can be implemented by representative instructions stored on at least one machine-readable medium, the instructions representing various logics within a processor, which when read by a machine, computing device, or system, cause the machine, computing device, or system to fabricate the logics to perform the techniques described herein. Such representations, referred to as “IP cores,” can be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities to be loaded into the manufacturing machines that actually fabricate the logics or processors.

[0097] The occurrences of the phrase “one example” or “an example” do not necessarily all refer to the same example. Any aspect described herein can be combined with any other aspect or similar aspect described herein, regardless of whether the aspects are described with respect to the same figure or element. The partitioning, omission, or inclusion of the block functions depicted in the figures does not mean that the hardware components, circuits, software, and / or elements for implementing those functions will necessarily be partitioned, omitted, or included in the example.

[0098] Some examples may use the expressions “coupled” and “connected” and their derivatives to describe. These terms are not necessarily intended as synonyms for each other. For example, a description using the terms “connected” and / or “coupled” can indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupled” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0099] The terms “first,” “second,” etc. do not denote any order, quantity, or importance herein, but are used to distinguish one element from another. The terms “a” and “an” herein do not denote a limitation of quantity, but rather denote the presence of at least one of the items being referenced. The term “assert” used herein with respect to a signal denotes the state of the signal in which the signal is active and can be achieved by applying to the signal any logic level of either logic 0 or logic 1. The term “following” or “after” can refer to immediately following some other event or events, or subsequent to some other event or events. According to alternative examples, other sequences of operations can also be performed. Additionally, depending on the particular application, additional operations can be added or removed. Any combination of variations can be used, and those of ordinary skill in the art who benefit from this disclosure will understand many variations, modifications, and alternative examples thereof.

[0100] Unless otherwise specifically stated, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood in the context as typically used to mean that an item, term, etc. can be X, Y, or Z or a combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language generally does not and should not imply that certain examples require the presence of at least one of X, at least one of Y, or at least one of Z individually. Additionally, unless otherwise specifically stated, conjunctive language such as the phrase "at least one of X, Y, and Z" should also be understood to mean X, Y, Z, or a combination thereof, including "X, Y, and / or Z".

[0101] Illustrative examples of the apparatuses, systems, and methods disclosed herein are provided below. Examples of the apparatuses, systems, and methods may include one or more of the examples described below and combinations thereof.

[0102] Example 1 includes one or more examples and includes a device that includes an Ethernet physical layer transceiver (PHY) circuit module for frame communication with a remote link partner. The Ethernet PHY circuit module includes: a physical medium dependent (PMD) circuit module; and a transmitter circuit module and a receiver circuit module for the frame communication, where: the PMD circuit module is to perform link training with a partner transmitter and, based on the magnitude of one or more equalizer coefficient values, selectively request the partner transmitter to apply a modulation scheme and precoding during the link training. The modulation scheme includes 4-level pulse amplitude modulation (PAM-4) or 6-level pulse amplitude modulation (PAM-6), and the request for the partner transmitter to apply the modulation scheme and precoding during the link training includes: transmitting a control signal to the partner transmitter.

[0103] Example 2 includes one or more examples, where the control signal includes a modulation and precoding request.

[0104] Example 3 includes one or more examples, where the equalizer coefficient values include one or more of the following: decision feedback equalizer (DFE) tap coefficient values, main coefficient values, or post-tap coefficient values, feed-forward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

[0105] Example 4 includes one or more examples, where, based on the magnitude of one or more equalizer coefficient values, the PMD circuit module does not request the partner transmitter to use a modulation scheme and precoding.

[0106] Example 5 includes one or more examples and includes a circuit module for applying forward error correction (FEC) to correct errors in a signal received from the partner transmitter.

[0107] Example 6 includes one or more examples and includes circuitry for requesting an equalizer setting adjustment by the partner transmitter based on the link training.

[0108] Example 7 includes one or more examples and includes at least one non-transitory computer-readable medium having instructions stored thereon that, if executed by one or more processors, cause the one or more processors to: execute an operating system (OS) to configure circuitry of a network interface device to: enable execution of link training and, during the link training, selectively request a partner transmitter to use a modulation scheme and precoding based on magnitudes of one or more equalizer coefficient values.

[0109] Example 8 includes one or more examples, wherein the modulation scheme includes 4-level pulse amplitude modulation (PAM-4) or 6-level pulse amplitude modulation (PAM-6).

[0110] Example 9 includes one or more examples, wherein the requesting the partner transmitter to apply the modulation scheme and precoding during the link training is based on transmitting a control signal to the partner transmitter.

[0111] Example 10 includes one or more examples, wherein the control signal includes a modulation and precoding request.

[0112] Example 11 includes one or more examples, wherein the equalizer coefficient values include one or more of the following: decision feedback equalizer (DFE) tap coefficient values, main coefficient values, or post-tap coefficient values, feed-forward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

[0113] Example 12 includes one or more examples, wherein, based on magnitudes of one or more equalizer coefficient values, the PMD circuitry does not request the partner transmitter to use a modulation scheme and precoding.

[0114] Example 13 includes one or more examples, wherein the OS is to selectively cause the circuitry of the network interface device not to use a modulation scheme and precoding during the link training based on magnitudes of one or more equalizer coefficient values.

[0115] Example 14 includes one or more examples and includes a method that includes: a physical medium dependent (PMD) circuit module performing link training with a partner transmitter and selectively requesting the partner transmitter to apply a modulation scheme and precoding based on the magnitude of one or more equalizer coefficient values during the link training, where the modulation scheme includes 4-level pulse amplitude modulation (PAM-4) or 6-level pulse amplitude modulation (PAM-6).

[0116] Example 15 includes one or more examples, where the request for the partner transmitter to apply the modulation scheme and precoding during the link training is based on transmitting a control signal to the partner transmitter.

[0117] Example 16 includes one or more examples, where the control signal includes a modulation and precoding request.

[0118] Example 17 includes one or more examples, where the equalizer coefficient values include one or more of the following: decision feedback equalizer (DFE) tap coefficient values, main coefficient values, or trailing coefficient values, feed-forward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

[0119] Example 18 includes one or more examples and includes: based on the magnitude of one or more equalizer coefficient values, the PMD circuit module does not request the partner transmitter to use a modulation scheme and precoding.

[0120] Example 19 includes one or more examples and includes requesting the partner transmitter to adjust equalizer settings based on the link training.

Claims

1. A device, comprising: An Ethernet physical layer transceiver (PHY) circuit module for frame communication with a remote link partner, the Ethernet PHY circuit module comprising: A physical medium dependent (PMD) circuit module; and A transmitter circuit module and a receiver circuit module for the frame communication, wherein: The PMD circuit module is to perform link training with a partner transmitter and, based on the magnitude of one or more equalizer coefficient values, selectively request the partner transmitter to apply a modulation scheme and precoding during the link training, The modulation scheme includes 4-level pulse amplitude modulation (PAM-4) or 6-level pulse amplitude modulation (PAM-6), and The request for the partner transmitter to apply the modulation scheme and precoding during the link training includes: transmitting a control signal to the partner transmitter.

2. The device according to claim 1, wherein The control signal includes a modulation and precoding request.

3. The device according to claim 1, wherein, The equalizer coefficient values include one or more of the following: decision feedback equalizer (DFE) preamble coefficient values, main coefficient values or postamble coefficient values, feedforward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

4. The device according to claim 1, wherein, Based on the magnitude of one or more equalizer coefficient values, the PMD circuit module does not request the partner transmitter to use a modulation scheme and precoding.

5. The device according to claim 4, comprising a circuit module for applying forward error correction (FEC) to correct errors in a signal received from the partner transmitter.

6. The device according to any one of claims 1-5, comprising a circuit module for requesting an equalizer setting adjustment by the partner transmitter based on the link training.

7. At least one non-transitory computer-readable medium, comprising instructions stored thereon that, if executed by one or more processors, cause the one or more processors to: Execute an operating system (OS) to configure a circuit module of a network interface device such that: Enable the execution of link training and, during the link training, selectively request a partner transmitter to use a modulation scheme and precoding based on the magnitude of one or more equalizer coefficient values.

8. The computer-readable medium according to claim 7, wherein, The modulation scheme includes 4-level pulse amplitude modulation (PAM-4) or 6-level pulse amplitude modulation (PAM-6).

9. The computer-readable medium according to claim 7, wherein, The request for the partner transmitter to apply the modulation scheme and precoding during the link training is based on transmitting a control signal to the partner transmitter.

10. The computer-readable medium according to claim 9, wherein, The control signal includes a modulation and precoding request.

11. The computer-readable medium according to claim 7, wherein, The equalizer coefficient values include one or more of the following: decision feedback equalizer (DFE) preamble coefficient values, main coefficient values or postamble coefficient values, feedforward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

12. The computer-readable medium according to claim 7, wherein, Based on the magnitude of one or more equalizer coefficient values, the PMD circuit module does not request the partner transmitter to use a modulation scheme and precoding.

13. The computer-readable medium according to any one of claims 7-12, wherein, The OS is to selectively cause the circuit module of the network interface device not to use a modulation scheme and precoding during the link training based on the magnitude of one or more equalizer coefficient values.

14. A method, comprising: A Physical Medium Dependent (PMD) circuit module performs link training with a partner transmitter and selectively requests the partner transmitter to apply a modulation scheme and precoding based on the magnitude of one or more equalizer coefficient values during the link training.

15. The method according to claim 14, wherein, The modulation scheme includes 4-level Pulse Amplitude Modulation (PAM-4) or 6-level Pulse Amplitude Modulation (PAM-6).

16. The method according to claim 14, wherein, The request for the partner transmitter to apply the modulation scheme and precoding during the link training is based on transmitting a control signal to the partner transmitter.

17. The method according to claim 16, wherein, The control signal includes a modulation and precoding request.

18. The method according to claim 14, wherein, The equalizer coefficient values include one or more of the following: decision feedback equalizer (DFE) tap coefficient values, main coefficient values or trailing coefficient values, feed-forward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

19. The method according to claim 14, comprising: Requesting the partner transmitter to adjust equalizer settings based on the link training.

20. The method according to any one of claims 14-19, comprising: Based on the magnitude of one or more equalizer coefficient values, the PMD circuit module does not request the partner transmitter to use a modulation scheme and precoding.

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