Driving circuit, driving chip and display device

Abstract

The application discloses a driving circuit, a driving chip and a display device. The driving circuit comprises: a current source comprising a source branch and a plurality of mirror branches, each mirror branch comprising a first driving transistor, at least part of the first driving transistor being gated to provide a driving current to a load in an output stage of the driving circuit, a plurality of gate terminal charging and discharging units, each gate terminal charging and discharging unit being configured to provide a gate terminal charging current or a gate terminal discharging current to the first driving transistor in a corresponding mirror branch; and a biasing unit configured to provide a biasing current with adjustable size to the plurality of gate terminal charging and discharging units to adjust a gate voltage rising / falling slope of the first driving transistor in the plurality of mirror branches. The gate voltage rising / falling slope of the gate terminal of the first driving transistor in each mirror branch is adjusted by the adjustable current source and the gate terminal charging and discharging unit, and then the change rate of the driving current is adjusted, so that electromagnetic interference caused by rapid change of the driving current can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving circuit, a driving chip and a display device. BACKGROUND

[0002] The pixel element used in the LED display device is LED. The LED display device has the following advantages: high brightness, wide viewing angle, rich color and customizable screen shape. Therefore, the LED display device is widely used in various fields such as industry, transportation, commercial advertising, information publishing, sports competition and the like.

[0003] Figure 1 is a schematic structural diagram of the LED display driving circuit in the prior art. The basic working principle is that the voltage VC is compared with Vref2 through the operational amplifier OP2, and the conduction of M0 is controlled according to the comparison result, the voltage VB is compared with Vref1 through the operational amplifier OP1, and VA is controlled according to the comparison result, so as to realize the accurate copying of the Iref current by M2, M3...Mn, and the conduction of the M2, M3...Mn branch is controlled to control the current flowing through the LED lamp, so as to realize the adjustment of the brightness of the LED lamp.

[0004] However, in the driving circuit, after the brightness of the LED lamp is determined, the driving current provided by the driving circuit is certain. That is, the conduction of M2, M3...Mn is fixed. Thus, the rising rate of the driving current is certain. In this way, at the moment of starting the circuit, the driving circuit will generate a transient large current, and the transient large current change will cause electromagnetic radiation and generate electromagnetic waves, thereby causing electromagnetic interference (EMI, Electromagnetic Interference). SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a driving circuit, a driving chip and a display device, which can control the change slope of the driving current, thereby avoiding the electromagnetic interference caused by the rapid change of the current.

[0006] According to an aspect of the present application, a driving circuit is provided, comprising: a current source comprising a source branch and a plurality of mirror branches, each mirror branch comprising a first driving transistor, at least part of the first driving transistor being gated to provide a driving current to a load in an output stage of the driving circuit, a plurality of gate terminal charging and discharging units, each gate terminal charging and discharging unit being configured to provide a gate terminal charging current or a gate terminal discharging current to the first driving transistor in the corresponding mirror branch; and a biasing unit configured to provide an adjustable biasing current to the plurality of gate terminal charging and discharging units to adjust the rising / falling slope of the gate voltage of the first driving transistor in the plurality of mirror branches.

[0007] Optionally, the biasing unit comprises: a first branch for providing a first biasing current, the gate-end charging and discharging unit mirroring the first biasing current to provide the charging current; and a second branch for providing a second biasing current, the gate-end charging and discharging unit mirroring the second biasing current to provide the discharging current.

[0008] Optionally, the first branch comprises a first transistor and a first current source with adjustable current, a first end of the first transistor being connected to a first power supply end, a second end being connected to the gate end and grounded through the first current source; the second branch comprises a second transistor and a second current source with adjustable current, a first end of the second transistor being connected to the gate end and connected to the first power supply end through the second current source, a second end being grounded, wherein the gate end of the first transistor and the gate end of the second transistor are further connected to the gate-end charging and discharging unit.

[0009] Optionally, the source branch comprises a second driving transistor, the driving circuit further comprises: a control unit for providing an on voltage for turning on the second driving transistor and the corresponding first driving transistor in the output stage; and a selection unit adapted to each of the mirror branches for providing the on voltage to the selected mirror branch or providing an off voltage to the unselected mirror branch in the output stage.

[0010] Optionally, the gate end of the first driving transistor is connected to the corresponding selection unit to receive the on voltage or the off voltage, a first end provides a mirror current, and a second end is grounded through a first resistor; the gate end of the second driving transistor is connected to the control unit, a first end provides a source current, and a second end is grounded through a second resistor, wherein the ratio of the first driving transistor in each of the mirror branches and the second driving transistor in the source branch is the same as the ratio of the first resistor in the mirror branch and the second resistor in the source branch.

[0011] Optionally, the control unit comprises: an operational amplifier, a same-phase input end receiving a reference voltage, an opposite-phase input end being connected to the second end of the second driving transistor, and an output end providing the on voltage; and an output module connected between the output end of the operational amplifier and each of the selection units for providing the on voltage to each of the selection units.

[0012] Optionally, the output module comprises: a comparator, having a non-inverting input connected to the gate of the first driving transistor in each of the mirror branches and an inverting input connected to the output of the operational amplifier; a D flip-flop, having a clock input connected to the output of the comparator and a data input receiving a first signal; and a first enable switch connected between the output of the operational amplifier and each of the selection units, the first enable switch being controlled by the output of the D flip-flop to provide the turn-on voltage to the selection unit when the first enable switch is closed.

[0013] Optionally, each of the selection units comprises: a second enable switch connected between the first enable switch and the gate of the first driving transistor in the corresponding mirror branch, the second enable switch being controlled by the corresponding gate signal to provide the turn-on voltage to the gate of the first driving transistor in the corresponding mirror branch when the corresponding mirror branch is gated; and a third enable switch connected between the gate of the first driving transistor in the corresponding mirror branch and ground, the third enable switch being controlled by the corresponding gate signal to provide the turn-off voltage to the gate of the first driving transistor in the corresponding mirror branch when the corresponding mirror branch is not gated.

[0014] Optionally, each of the gate charging and discharging units comprises a first mirror transistor, a fourth enable switch, a fifth enable switch and a second mirror transistor connected in sequence between a first power supply terminal and ground, the first mirror transistor having a gate connected to the first branch to mirror the first bias current in proportion, the second mirror transistor having a gate connected to the second branch to mirror the second bias current in proportion, the fourth enable switch and the fifth enable switch having a node connected to the gate of the corresponding first driving transistor, the fourth enable switch being controlled by a first enable signal to provide the charging current when the corresponding mirror branch is gated; and the fifth enable switch being controlled by a second enable signal to provide the discharging current when the corresponding mirror branch is not gated.

[0015] Optionally, the driving circuit further comprises a reset unit configured to turn off the source branch in a non-output stage.

[0016] Optionally, the reset unit comprises a reset transistor having a first terminal connected to the gate of the second driving transistor, a second terminal connected to ground, and a gate receiving a reset pulse signal through an inverter, the reset pulse signal also being used to reset the D flip-flop.

[0017] Optionally, the load comprises a light emitting element, and the driving circuit further comprises a processing unit configured to provide the corresponding gate signal to each of the mirror branches according to a target brightness of the light emitting element.

[0018] Optionally, the display driving circuit further comprises an enable signal generation unit configured to provide the first enable signal and the second enable signal according to the selection signal, the reset pulse signal and the output signal of the D flip-flop.

[0019] Optionally, the enable signal generation unit comprises an NAND circuit configured to receive the inverted signal of the output signal of the D flip-flop, the selection signal corresponding to each of the mirror branches and the reset pulse signal, and provide the first enable signal corresponding to each of the mirror branches; and an AND circuit configured to receive the selection signal corresponding to each of the mirror branches and the inverted signal of the reset pulse signal, and provide the second enable signal corresponding to each of the mirror branches.

[0020] According to still another aspect of the present application, there is provided a driving chip, comprising the display driving circuit according to any one of the above.

[0021] According to a third aspect of the present application, there is provided a display device, comprising a display panel and the driving chip according to the above.

[0022] According to the display driving circuit, the driving chip and the display device provided by the present application, the adjustable current source and the gate terminal charge / discharge unit are configured to adjust the rising / falling slope of the gate voltage of the first driving transistor in each mirror branch, and further adjust the change rate of the driving current, so that the electromagnetic interference caused by the rapid change of the driving current can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0024] Figure 1 a schematic structural diagram of an LED display driving circuit in the prior art is shown;

[0025] Figure 2 a schematic structural diagram of a display device is shown;

[0026] Figure 3 a schematic structural diagram of a display driving circuit according to an embodiment of the present application is shown;

[0027] Figure 4 a schematic structural diagram of a display driving circuit according to an embodiment of the present application is shown; Figure 3 a schematic structural diagram of a plurality of components in the display driving circuit according to an embodiment of the present application is shown;

[0028] Figure 5 a schematic structural diagram of a plurality of components in the display driving circuit according to an embodiment of the present application is shown; Figure 3 a schematic structural diagram of an enable signal generation unit in the display driving circuit according to an embodiment of the present application is shown;

[0029] Figure 6 a working waveform diagram of the display driving circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] Various embodiments of the present application will be described hereinafter in greater detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements throughout. For clarity, each part of the drawings is not drawn to scale.

[0031] Meanwhile, certain terms have been used throughout this description and claims to refer to particular components. As one skilled in the art will appreciate, manufacturers can refer to a component by different names. This document does not intend to distinguish between components that differ in name but not in function. In the description and in the claims of the application, each of the words "comprise" "comprises" "comprising" "include" "includes" "including" and "contain" "contains" "containing" when used in this document (and its claims) are taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

[0032] It should be understood that, in the following description, "circuitry" can include a single or multiple components, hardware circuitry, programmable circuitry, state machine circuitry, and / or elements that store instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that the two are connected without any intervening elements.

[0033] In addition, it should also be noted that, in this document, the terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0034] Taking the LED as an example of the driven load, Figure 2 is a schematic structural diagram of a display device. Referring to Figure 2 , the display device 10 includes an LED display screen and a driving chip 100. The LED display screen includes a plurality of LED lamp groups D1~Dn. The driving chip 100 includes driving circuits 110 corresponding to the LED lamp groups to provide driving currents to the LED lamp groups. As an example, only the driving circuit 110 providing a driving current Id1 to the lamp group D1 is shown in Figure 2

[0035] ​In order to avoid electromagnetic interference caused by rapid change of driving current, the application discloses a driving circuit. The driving circuit disclosed by the application can be applied in the display device as described above, as the driving circuit 110 corresponding to each LED lamp group. Figure 3 The schematic structural diagram of the driving circuit is shown. Referring to Figure 3 The driving circuit 110 includes a current source, a bias unit 112, a gate terminal charge-discharge unit 113, a control unit, a selection unit 115, a reset unit, a processing unit 116 and an enable signal generation unit 117.

[0036] Figure 4 The schematic structural diagram of Figure 3 the bias unit 112, the gate terminal charge-discharge unit 113, the output module 114 of the control unit and the selection unit 115 is shown; Figure 5 The schematic structural diagram of Figure 3 the enable signal generation unit 117 is shown. It should be noted that the structures of the gate terminal charge-discharge unit 113 and the selection unit 115 connected with different mirror branches should be the same, and in Figure 4 the following, only the gate terminal charge-discharge unit 113 and the selection unit 115 connected with the mirror branch where the first driving transistor MSN1 is located are shown as an example. The following will be described in combination with Figures 3 to 5 the driving circuit of the embodiment of the application.

[0037] The current source is used to provide driving current to the load. The current source can be a proportional current source. Referring to Figure 3 , the current source includes a source branch 111a and a plurality of mirror branches 111b. For the display device, the load can be an LED, and the current source selects the corresponding mirror branch 111b according to the brightness of the LED, so as to adjust the size of the driving current. Specifically, the processing unit 116 is used to provide the selection signals Sel1, Sel2...Seln of each mirror branch 111b according to the received display data Data. The selection signals Sel1, Sel2...Seln select the corresponding mirror branch 111b during the respective active periods, so as to adjust the size of the driving current.

[0038] Each mirror branch 111b includes a first driving transistor and a first resistor, and in Figure 3In each mirror branch 111b, the first drive transistor is MSN1, MSN2,... MSNn, and the control terminal voltage is VG1, VG2,... VGn, respectively. The first resistor is R1, R2,... Rn, respectively. For each first drive transistor in each mirror branch 111b, the first terminal is used to provide the mirror current of the mirror branch 111b, and the second terminal is connected to ground through the first resistor of the mirror branch. The control terminals of the first drive transistors in each mirror branch are connected to the first node Q. For clarity, the specific position of the first node Q is shown in Figure 4 The voltage of the first node Q is VQ.

[0039] The source branch 111a includes a second drive transistor MSN0 and a second resistor R0. The first terminal of the second drive transistor MSN0 is connected to the first terminals of the first drive transistors and is used to provide the source current, the second terminal is connected to ground through the second resistor R0, and the control terminal voltage is VG0.

[0040] It should be noted that the size of the first drive transistor in each mirror branch 111b is proportional to the size of the second drive transistor MSN0. At the same time, the resistance ratio of the first resistor in each mirror branch 111b to the second resistor R0 is the same as the size ratio of the first drive transistor and the second drive transistor MSN0 in the mirror branch 111b. Generally, the size ratio of the second drive transistor MSN0 to the first drive transistors MSN1, MSN2,... MSNn is 1:2:4:... :2 （n-1） , and accordingly, the ratio of the second resistor R0 to the first resistors R1, R2,... Rn is also 1:2:4:... :2 （n-1） . At the same time, the ratio also provides the ratio of the mirror current to the source current of each mirror branch 111b.

[0041] The control unit is used to provide an on voltage to turn on the second drive transistor MSN0 and the first drive transistors in the output stage of the drive circuit 110. Referring to Figure 3 , the control unit includes an operational amplifier A1 and an output module 114.

[0042] The non-inverting input terminal of the operational amplifier A1 receives a reference voltage Vref, the inverting input terminal is connected to the second terminal of the second drive transistor MSN0, and the output terminal is connected to the gate terminal of the second drive transistor MSN0 to provide the on voltage in the output stage.

[0043] The output module 114 is connected between the output terminal of the operational amplifier A1 and each selection unit 115, and is used to provide the on voltage to each selection unit 115. Referring to Figure 4The output module 114 includes a comparator CI, a D flip-flop and a first enable switch SI. The non-inverting input terminal of the comparator CI is connected to the gate terminal of the first driving transistor in all the mirror branches 111b at a first node Q, and the inverting input terminal of the comparator CI is connected to the output terminal of the operational amplifier Al. The clock input terminal CLK of the D flip-flop is connected to the output terminal of the comparator CI, the data input terminal receives the first signal TIEH, and the reset terminal receives a reset pulse signal PWM. When the reset pulse signal PWM is at a first level, for example, a low level, the D flip-flop is reset; when the reset pulse signal PWM is at a second level, for example, a high level, the D flip-flop works normally and samples and outputs the first signal TIEH at the active edge of the clock signal. One end of the first enable switch SI is connected to the output terminal of the operational amplifier Al, and the other end is connected to each selection unit 115. The first enable switch SI is controlled to be closed or opened by the output signal CMP of the D flip-flop. For example, the first enable switch SI is closed when the output signal CMP is at a high level, so that the first signal TIEH is always set to a high level, and thus the first enable switch SI is closed and provides the start-up voltage to each selection unit 115 when the D flip-flop outputs the first signal TIEH.

[0044] The plurality of selection units 115 are respectively adapted to the corresponding mirror branches 111b. The selection unit 115 is configured to provide the start-up voltage to the gate terminal of the first driving transistor in the corresponding mirror branch 111b when the corresponding mirror branch 111b is selected, or to provide the cut-off voltage to the gate terminal of the first driving transistor in the corresponding mirror branch 111b when the corresponding mirror branch 111b is not selected. When each first driving transistor is an NMOS, the cut-off voltage can be a ground voltage. For example, each selection unit 115 includes a second enable switch S2 and a third enable switch S3. The second enable switch S2 is connected between the output module 114 and the corresponding mirror branch 111b, specifically, one end of the second enable switch S2 is connected to the first enable switch SI, and the other end is connected to the gate terminal of the first driving transistor in the corresponding mirror branch 111b. The third enable switch S3 is connected between the corresponding mirror branch 111b and the cut-off voltage, and for the case where the first driving transistor is not an NMOS, specifically, one end of the third enable switch S3 is connected to the gate terminal of the first driving transistor in the corresponding mirror branch 111b, and the other end is grounded.

[0045] Specifically, the selection unit 115 is further described by taking the mirror branch 111b in which the first driving transistor MSN1 is located as an example. Referring to FIG. 2, the selection unit 115 includes a second enable switch S2 and a third enable switch S3. The second enable switch S2 is connected between the output module 114 and the mirror branch 111b, specifically, one end of the second enable switch S2 is connected to the first enable switch SI, and the other end is connected to the gate terminal of the first driving transistor MSN1 in the mirror branch 111b. The third enable switch S3 is connected between the mirror branch 111b and the cut-off voltage, and for the case where the first driving transistor MSN1 is not an NMOS, specifically, one end of the third enable switch S3 is connected to the gate terminal of the first driving transistor MSN1 in the mirror branch 111b, and the other end is grounded. Figure 4The second enable switch S2 has one end connected with the first enable switch S1 and the other end connected with the gate of the first drive transistor MSN1. The third enable switch S3 has one end connected with the gate of the first drive transistor MSN1 and the other end connected with the ground. The second enable switch S2 and the third enable switch S3 are controlled by the selection signal Sel1 of the mirror branch 111b. When the corresponding selection signal Sel1 is at the effective level, the second enable switch S2 is closed to provide the gate of the first drive transistor MSN1 with the on voltage; when the corresponding selection signal Sel1 is at the ineffective level, the third enable switch S3 is closed to provide the gate of the first drive transistor MSN1 with the off voltage. Figure 4 In the embodiment, in order to realize the opposite states of the second enable switch S2 and the third enable switch S3, the third enable switch S3 is controlled by the inverse signal Sel1_B of the selection signal Sel1.

[0046] In order to realize the adjustable rate of the drive current, the driving circuit further comprises a bias unit 112 and a gate charging and discharging unit 113 corresponding to each mirror branch 111b.

[0047] Each gate charging and discharging unit 113 is configured to provide the first drive transistor in the corresponding mirror branch with a gate charging current or a gate discharging current. The bias unit 112 is configured to provide each gate charging and discharging unit 113 with a bias current I0 with adjustable size, so as to adjust the rising / falling slope of the gate voltage of the first drive transistor in each mirror branch 111b.

[0048] The bias unit 112 comprises a first branch and a second branch. The gate charging and discharging unit 113 mirrors the first bias current provided by the first branch in proportion to provide a charging current for the gate of the first drive transistor in the corresponding mirror branch 111b, or mirrors the second bias current provided by the second branch in proportion to provide a discharging current for the gate of the first drive transistor in the corresponding mirror branch 111b.

[0049] Further, the first branch comprises a first transistor MP0 and a first current source IP0 with adjustable current size. The first end of the first transistor MP0 is connected with the first power supply end AVDD, the second end is connected with the gate and grounded through the first current source IP0. The first transistor MP0 is further connected with each gate charging and discharging unit 113.

[0050] The second branch comprises a second transistor MN0 and a second current source IN0 with adjustable current size. The second end of the second transistor MN0 is grounded, the first end and the gate are connected and connected with the first power supply end AVDD through the second current source IN0. The second transistor MN0 is further connected with each gate charging and discharging unit 113.

[0051] Each gate charge-discharge unit 113 includes a first mirror transistor, a fourth enable switch, a fifth enable switch and a second mirror transistor connected in sequence between the first power supply terminal AVDD and the ground. The gate of the first mirror transistor is connected with the first branch of the bias unit 112, specifically the gate of the first transistor MP0. The gate of the second mirror transistor is connected with the second branch of the bias unit 112, specifically the gate of the second transistor MN0. The fourth enable switch in each gate charge-discharge unit 113 is controlled by a corresponding first enable signal to be closed / opened; the fifth enable switch in each gate charge-discharge unit 113 is controlled by a corresponding second enable signal to be closed / opened. As an example, in Figure 3 the gate charge-discharge unit 113 connected with the mirror branch 111b corresponding to the first driving transistor MSN1 receives the first enable signal SP1 and the second enable signal SN1.

[0052] It should be understood that, in order to make the gate charge-discharge speed of the first driving transistors in each mirror branch 111b consistent, the mirror ratio of the first bias current / second bias current of each gate charge-discharge unit 113 is the same as the ratio between the mirror current provided by the corresponding mirror branch and the source current. For example, the above-mentioned current ratio can be achieved by adjusting the size of the first mirror transistor and the second mirror transistor in each gate charge-discharge unit 113. For example, the size ratio of the second driving transistor MN0 and each first driving transistor MSN1, MSN2...MSNn is 1:2:4...:2 （n-1） . Accordingly, in each gate charge-discharge unit 113, the ratio of the first mirror transistor and the first transistor MP0, and the ratio of the second mirror transistor and the second transistor MN0 are all 1:2:4...:2 （n-1） .

[0053] Specifically, taking the gate charge-discharge unit 113 corresponding to the mirror branch 111b where the first driving transistor MSN1 is located as an example, the bias unit 112 and the gate charge-discharge unit 113 are further introduced.

[0054] The gate charge-discharge unit 113 includes a first mirror transistor MP1, a fourth enable switch S4, a fifth enable switch S5 and a second mirror transistor MN1 connected in sequence between the first power supply terminal AVDD and the ground.

[0055] The gate terminal of the first mirror transistor MP1 is connected with the first branch, and the first bias current is mirrored in proportion. The second mirror transistor MN1 is connected with the second branch, and the second bias current is mirrored in proportion. The middle nodes of the fourth enable switch S4 and the fifth enable switch S5 are connected with the gate terminal of the corresponding first drive transistor MSN1, wherein the fourth enable switch S4 is controlled by the first enable signal SP1, and is closed to provide the charging current when the corresponding mirror branch 111b is selected; the fifth enable switch S5 is controlled by the second enable signal SN1, and is closed to provide the discharging current when the corresponding mirror branch 111b is not selected.

[0056] Further, in combination with the above Figure 3 and Figure 5 The first enable signal and the second enable signal received by each gate charging and discharging unit 113 are generated by the enable signal generation unit 117 according to the output signal CMP of the D flip-flop, the gate signal Sel of the corresponding mirror branch, and the reset pulse signal PWM.

[0057] Referring to Figure 5 For example, the enable signal generation unit 117 includes an NAND gate circuit and an AND gate circuit. The NAND gate circuit is used to provide the first enable signal SP of the corresponding mirror branch 111b according to the inverse signal of the D flip-flop output signal CMP, the gate signal Sel of the corresponding mirror branch 111b, and the reset pulse signal PWM. The AND gate circuit is used to provide the second enable signal SN of the corresponding mirror branch 111b according to the inverse signal of the reset pulse signal PWM and the gate signal Sel of the corresponding mirror branch 111b.

[0058] Further, the driving circuit provided by the present application further comprises a reset unit. The reset unit is used to reset the gate voltage of the second drive transistor MSN0 in the non-output stage. The reset unit comprises a reset transistor MNR. The first end of the reset transistor MNR is connected with the gate terminal of the second drive transistor MSN0, the second end is grounded, and the gate terminal receives the reset pulse signal PWM through the inverter INV1.

[0059] Figure 6 is a working waveform schematic diagram of the driving circuit of the embodiment of the present application. Still taking the first mirror branch as an example, wherein PWM is the reset pulse signal, Id1 is the driving current provided by the driving circuit for the LED lamp bead D1, VG1 is the gate voltage of the first drive transistor MSN1, and IR1 is the mirror current provided by the mirror branch where the MSN1 is located. The anode of the LED lamp bead is connected with the power supply end VCC.

[0060] The following mirror branch 111b where the first drive transistor MSN1 is located is taken as an example to introduce the working process of the drive circuit. The low level of each signal is represented by "0" and the high level is represented by "1". The first level of the reset pulse signal PWM is low, the second level is high, the active level of the selection signal Sel is high, the fourth enable switch S4 is low and the fifth enable switch S5 is high as an example.

[0061] When the mirror branch 111b where the first drive transistor MSN1 is located is not selected, Sel1=0, the second enable switch S2 is opened, the third enable switch S3 is closed, and the gate of the first drive transistor MSN1 is grounded through the closed third enable switch S3. At the same time, SP1=1, SN1=0, the fourth enable switch S4 and the fifth enable switch S5 are both opened, and the gate charge unit 113 has no effect on the gate voltage of the first drive transistor MSN1.

[0062] When the mirror branch 111b where the first drive transistor MSN1 is located is selected, Sel1=1, the following cases exist:

[0063] When the reset pulse signal PWM is low, the reset transistor MNR resets the gate of the second drive transistor MSN0, so that the gate voltage VG0 of the second drive transistor MSN0 is the ground voltage. The low reset pulse signal PWM also resets the D flip-flop, so that the output signal CMP of the D flip-flop is 0, and the first enable switch S1 is opened. At this time, SP1=1, SN1=1, the fourth enable switch S4 is opened, the fifth enable switch S5 is closed, and the gate of the first drive transistor MSN1 is grounded.

[0064] When the rising edge of the reset pulse signal PWM arrives, the output signal CMP of the D flip-flop remains 0, at this time SP1=0, SN1=0, the fourth enable switch S4 is closed, the fifth enable switch S5 is opened, and the charging current is provided to the gate of the first drive transistor MSN1 by the first mirror transistor MP1. When the gate voltage VG1 of the first drive transistor MSN1 is slightly higher than the gate voltage VG0 of the second drive transistor MSN0, the comparator C1 outputs 1, the D flip-flop outputs the first signal TIEH=1, the first enable switch S1 is closed, and the control terminals of the first drive transistor MSN1 and the second drive transistor MSN2 are connected in equipotential. At the same time, SP=1, SN1=0, and the gate charge unit 113 stops providing the charging current.

[0065] When the PWM falling edge arrives, the process of PWM=0 is repeated.

[0066] The working principles of other mirror branches are the same and will not be repeated here.

[0067] Since the gate voltage of the first driving transistor in each mirror branch has the same charging and discharging speed, in the embodiments provided in the present application, the rising / falling slope of the gate voltage can be controlled by adjusting the current size of the first current source IP0 and the second current source IN0, and then the change rate of the driving current can be adjusted, so that the electromagnetic interference caused by the rapid change of the driving current can be avoided.

[0068] Further, the present application also provides a driving chip and a display device. The driving chip comprises the driving circuit as above. The display device comprises the chip as above and a display panel. The driving chip and the display device also have the beneficial effects as above, which will not be described herein again.

[0069] In accordance with the embodiments of the present application as above, these embodiments do not describe all the details and do not limit the present application to only the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The protection scope of the present application should be defined by the scope of the claims of the present application.

Claims

1. A drive circuit, wherein, The driving circuit is used for driving an LED display panel, and the driving circuit comprises: a current source comprising a source branch and a plurality of mirror branches, each mirror branch comprising a first drive transistor, in an output stage of the driving circuit, a corresponding first drive transistor is gated according to display data to provide a driving current with adjustable size to a load, a plurality of gate terminal charging and discharging units, each of the gate terminal charging and discharging units being used for providing a gate terminal charging current or a gate terminal discharging current to the first drive transistor in a corresponding mirror branch; and a bias unit used for providing a bias current with adjustable size to the plurality of gate terminal charging and discharging units to adjust a gate voltage rising / falling slope of the first drive transistor in the plurality of mirror branches, so that the driving current linearly changes, wherein the bias unit comprises: a first branch comprising a first current source with adjustable size, the size of the first bias current being adjusted by adjusting the size of the first current source, and the gate terminal charging and discharging units mirror the first bias current in proportion to provide the charging current; and a second branch comprising a second current source with adjustable size, the size of the second bias current being adjusted by adjusting the size of the second current source, and the gate terminal charging and discharging units mirror the second bias current in proportion to provide the discharging current.

2. The driving circuit according to claim 1, wherein the first branch further comprises a first transistor, a first end of the first transistor being connected to a first power supply end, a second end being connected to a gate terminal and being grounded through the first current source; the second branch further comprises a second transistor, a first end of the second transistor being connected to the gate terminal and being connected to the first power supply end through the second current source, and a second end being grounded, wherein the gate terminal of the first transistor and the gate terminal of the second transistor are further connected to the gate terminal charging and discharging units.

3. The drive circuit of claim 2, wherein, the source branch comprises a second drive transistor, the driving circuit further comprises: a control unit used for providing an on voltage for turning on the second drive transistor and a corresponding first drive transistor in the output stage; and a selection unit adapted to each mirror branch, used for providing the on voltage to a selected mirror branch or providing an off voltage to an unselected mirror branch in the output stage.

4. The driving circuit according to claim 3, wherein the gate terminal of the first drive transistor is connected to a corresponding selection unit to receive the on voltage or the off voltage, a first end provides a mirror current, and a second end is grounded through a first resistor; the gate terminal of the second drive transistor is connected to the control unit, a first end provides a source current, and a second end is grounded through a second resistor, wherein the ratio of the first drive transistor in each mirror branch and the second drive transistor in the source branch is the same as the ratio of the first resistor in the mirror branch and the second resistor in the source branch.

5. The drive circuit of claim 4, wherein, the control unit comprises: an operational amplifier, a same-phase input end receiving a reference voltage, an opposite-phase input end being connected to the second end of the second drive transistor, and an output end providing the on voltage; and An output module is connected between the output terminal of the operational amplifier and each of the selection units, for providing the turn-on voltage to each of the selection units.

6. The drive circuit of claim 5, wherein, The output module comprises: a comparator, whose non-inverting input terminal is connected to the gate terminal of the first drive transistor in each of the mirror branches, and whose inverting input terminal is connected to the output terminal of the operational amplifier; a D flip-flop, whose clock input terminal is connected to the output terminal of the comparator, and whose data input terminal receives a first signal; a first enable switch, which is connected between the output terminal of the operational amplifier and each of the selection units, and is controlled by the output signal of the D flip-flop to provide the turn-on voltage to the selection unit when closed.

7. The drive circuit of claim 6, wherein, Each of the selection units comprises: a second enable switch, which is connected between the first enable switch and the gate terminal of the first drive transistor in the corresponding mirror branch, and is controlled by the gate signal of the corresponding mirror branch to be closed and provide the turn-on voltage to the gate terminal of the first drive transistor in the mirror branch when the mirror branch is gated; and a third enable switch, which is connected between the gate terminal of the first drive transistor in the corresponding mirror branch and ground, and is controlled by the corresponding gate signal to be closed and provide the turn-off voltage to the gate terminal of the first drive transistor in the mirror branch when the mirror branch is not gated.

8. The drive circuit of claim 7, wherein, Each of the gate charging and discharging units comprises, in sequence, a first mirror transistor, a fourth enable switch, a fifth enable switch and a second mirror transistor, which are connected between a first power supply terminal and ground, the gate terminal of the first mirror transistor is connected to the first branch to mirror the first bias current in proportion, the gate terminal of the second mirror transistor is connected to the second branch to mirror the second bias current in proportion, the intermediate node of the fourth enable switch and the fifth enable switch is connected to the gate terminal of the corresponding first drive transistor, the fourth enable switch is controlled by a first enable signal to be closed to provide the charging current when the corresponding mirror branch is gated; and the fifth enable switch is controlled by a second enable signal to be closed to provide the discharging current when the corresponding mirror branch is not gated.

9. The drive circuit of claim 8, wherein, The drive circuit further comprises: a reset unit for turning off the source branch in a non-output stage.

10. The drive circuit of claim 9, wherein, The reset unit comprises: a reset transistor, whose first terminal is connected to the gate terminal of the second drive transistor, whose second terminal is grounded, and whose gate terminal receives a reset pulse signal through an inverter, the reset pulse signal is also used to reset the D flip-flop.

11. The drive circuit according to claim 10, wherein the load comprises a light emitting element, the drive circuit further comprises a processing unit for providing the corresponding gate signal to each of the mirror branches according to a target brightness of the light emitting element.

12. The drive circuit of claim 11, wherein, Further comprising: an enable signal generation unit for providing the first enable signal and the second enable signal according to the gate signal, the reset pulse signal and the output signal of the D flip-flop.

13. The drive circuit of claim 12, wherein, The enable signal generation unit comprises: A NOR gate circuit receives the inverted signal of the D flip-flop output signal, the strobe signal corresponding to each of the mirror branches, and a reset pulse signal, and provides the first enable signal corresponding to each of the mirror branches; and A NOR gate circuit receives the inverted signal of the D flip-flop output signal, the strobe signal corresponding to each of the mirror branches, and a reset pulse signal, and provides the first enable signal corresponding to each of the mirror branches; and 14. A driver chip, wherein, The driving circuit according to any one of claims 1-13. The driving circuit according to any one of claims 1-13.

15. A display device, wherein, The display panel according to claim 14. The display panel according to claim 14. The driving chip according to claim 14. ​

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