Gate drive circuit, gate drive circuit detection method and display panel

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a gate driving circuit detection method and a display panel, and the gate driving circuit comprises a plurality of clock signal lines and N cascaded driving circuit modules. Each driving circuit module comprises a circuit unit, and the circuit unit at least comprises a control node and an output transistor; each driving circuit module further comprises a node outgoing line, and the first end of the node outgoing line is electrically connected with the control node; the node outgoing line is configured to transmit an external test voltage to the control node in a test stage so as to control the output transistor to be in a turn-off state; according to the invention, the time sequence voltage of the control node is independently controlled, and the short circuit abnormity of the source and drain electrodes of the output transistor can be detected in the test stage, so that the detection comprehensiveness and accuracy of a GDL product in the test stage are improved, abnormal products are prevented from flowing into a back-end process, and the yield and cost control of back-end products are improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a gate driving circuit detection method, and a display panel. Background Art

[0002] Currently, in the ATT (Array Test Technology) stage of GDL (Gate Driver on Array), the defect detection of GDL mainly follows the principle of "promptly repairing the repairable defects and scrapping the non-repairable ones in a timely manner". This principle can improve the backend yield and reduce production costs.

[0003] However, for the current GDL circuit design, in the ATT stage, it is impossible to effectively detect the source-drain short circuit abnormality of the output transistors inside the GDL, resulting in GDL products with potential defects flowing into the backend manufacturing process, which affects the backend yield and cost control of the products.

[0004] Therefore, how to detect the source-drain short circuit abnormality of the output transistors inside the GDL is an urgent problem to be solved currently. Summary of the Invention

[0005] The present application provides a gate driving circuit, a gate driving circuit detection method, and a display panel, which solve the problem of detecting the source-drain short circuit abnormality of the output transistors inside the GDL, thereby improving the detection accuracy of the gate driving circuit in the test stage.

[0006] In a first aspect, the present application provides a gate driving circuit, which includes: a plurality of clock signal lines and N cascaded driving circuit modules; each driving circuit module includes a circuit unit, and the circuit unit at least includes a control node and an output transistor. The control end of the output transistor is electrically connected to the control node, the first end of the output transistor is electrically connected to the corresponding clock signal line, and the second end of the output transistor is electrically connected to the corresponding scan line; the output transistor is configured to output a gate driving signal to the corresponding scan line according to the clock signal on the clock signal line under the action of the working voltage on the control node; each driving circuit module further includes a node lead-out line, and the first end of the node lead-out line is electrically connected to the control node; the node lead-out line is configured to transmit an external test voltage to the control node during the test stage to control the output transistor to be in an off state.

[0007] Optionally, the second end of the node lead-out line is defined as a first test connection end, and the first test connection end is configured to be electrically connected to a device that outputs the external test voltage during the test stage.

[0008] Optionally, the gate drive circuit also includes: a first detection line, one end of the first detection line is defined as a second test connection terminal, and the second test connection terminal is configured to be electrically connected to a device that outputs a control voltage during a test phase; a second detection line, one end of the second detection line is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to a device that outputs the external test voltage during a test phase; each drive circuit module also includes a first control transistor, the control end of the first control transistor is electrically connected to the first detection line, the first end of the first control transistor is electrically connected to the second end of the node lead line, and the second end of the first control transistor is electrically connected to the second detection line.

[0009] Optionally, the gate drive circuit further includes: a first detection line, one end of the first detection line is defined as a second test connection end, and the second test connection end is configured to be electrically connected to a device for outputting a control voltage during a test phase; each drive circuit module further includes: a first control transistor, the control end of the first control transistor is electrically connected to the first detection line, and the first end of the first control transistor is electrically connected to the second end of the node lead-out line; a second control transistor, the control end of the second control transistor is electrically connected to the first detection line, and the first end of the second control transistor is connected to the second end of the first control transistor; a third detection line, the first end of the third detection line is connected to the second end of the second control transistor of the drive circuit module at this level, and the second end of the third detection line is connected to the last detection line. The second end of the third detection line is connected to the second end of the second control transistor of the first-stage driving circuit module, or the second end of the third detection line is connected to the second end of the second control transistor of the next-stage driving circuit module; wherein, when the second end of the third detection line is connected to the second end of the second control transistor of the previous-stage driving circuit module, the second end of the third detection line of the first-stage driving circuit module is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to the device that outputs the external test voltage during the test phase; when the second end of the third detection line is connected to the second end of the second control transistor of the next-stage driving circuit module, the second end of the third detection line of the N-th stage driving circuit module is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to the device that outputs the external test voltage during the test phase.

[0010] Optionally, the gate drive circuit further includes: a pull-down control line, the pull-down control line being configured to be electrically connected to a device that outputs the control voltage during a test phase; and one end of the first detection line being electrically connected to the pull-down control line.

[0011] Optionally, the multiple clock signal lines extend along the cascading direction of N driving circuit modules, the node lead-out line is arranged perpendicular to the multiple clock signal lines, and the first detection line and the second detection line are respectively arranged parallel to the clock signal lines.

[0012] In a second aspect, the present application provides a method for detecting a gate driving circuit, which is applied to the gate driving circuit. In the test stage, the detection method includes: using a node lead-out line to output an external test voltage to a control node, so that the output transistor is in an off state; using a clock signal line to output a driving voltage to the first end of the output transistor; detecting the relationship between the output voltage at the second end of the output transistor and the driving voltage to determine the short-circuit state of the output transistor.

[0013] Optionally, when the gate driving circuit includes a first detection line and a second detection line, the step of using the node lead-out line to output an external test voltage to the control node includes: using the first detection line to receive a control voltage to turn on a first control transistor; using the second detection line to receive the external test voltage, so that the node lead-out line outputs the external test voltage to the control node.

[0014] Optionally, when the gate driving circuit includes a first detection line and a third detection line, the step of using the node lead-out line to output an external test voltage to the control node includes: using the first detection line to receive a control voltage to turn on the first control transistor and a second control transistor; using the third detection line to receive the external test voltage, so that the node lead-out line outputs the external test voltage to the control node.

[0015] In a third aspect, the present application provides a display panel, including a display area and a non-display area. The display area includes multiple scan lines; the non-display area includes a gate driving circuit, and the driving output end of the circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0016] The technical solution provided by the present application has at least the following beneficial effects: In the present application, the control node lead-out line encapsulated inside the circuit unit is led out of the circuit unit through the node lead-out line, and then a corresponding external test voltage is input to the node lead-out line through an external detection device, so that the timing voltage of the control node can be controlled separately. The source-drain short-circuit abnormality of the output transistor can be detected in the test stage, thereby improving the comprehensiveness and accuracy of the detection of the GDL product in the test stage, avoiding abnormal products from flowing into the backend process, and improving the yield and cost control of the backend products. Description of the Drawings

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 The structural schematic diagram of the first gate driving circuit provided by the embodiment of the present application is shown.

[0019] Figure 2 The circuit schematic diagram of a circuit unit provided by the embodiment of the present application is shown.

[0020] Figure 3 The arrangement schematic diagram of a plurality of display panels provided by the embodiment of the present application is shown.

[0021] Figure 4 The front schematic diagram of a display panel provided by the embodiment of the present application is shown.

[0022] Figure 5 The timing schematic diagram when a circuit unit provided by the embodiment of the present application is normally detected is shown.

[0023] Figure 6 The design schematic diagram of an output transistor provided by the embodiment of the present application is shown.

[0024] Figure 7 The timing schematic diagram when a short-circuit abnormality is detected provided by the embodiment of the present application is shown.

[0025] Figure 8 The design schematic diagram of a gate driving circuit provided by the embodiment of the present application is shown.

[0026] Figure 9 The structural schematic diagram of the second gate driving circuit provided by the embodiment of the present application is shown.

[0027] Figure 10 The design schematic diagram of another gate driving circuit provided by the embodiment of the present application is shown.

[0028] Figure 11 The structural schematic diagram of the third gate driving circuit provided by the embodiment of the present application is shown.

[0029] Figure 12 The arrangement schematic diagram of another plurality of display panels provided by the embodiment of the present application is shown.

[0030] Figure 13 The front schematic diagram of another display panel provided by the embodiment of the present application is shown.

[0031] Figure 14 The following is a schematic structural diagram of the fourth gate driving circuit provided by an embodiment of the present application.

[0032] Figure 15 The following is a schematic structural diagram of the fifth gate driving circuit provided by an embodiment of the present application.

[0033] Figure 16 The following is a schematic flow diagram of a method for detecting a gate driving circuit provided by an embodiment of the present application.

[0034] Explanation of reference numerals: 100, gate driving circuit; 200, scan line; 310, input signal terminal in the gate driving circuit; 320, connection terminal of the external detection device; 330, via hole. 110, clock signal line; 120, driving circuit module; 121, circuit unit; 1211, precharging unit; 1212, pull-down control unit; 1213, reset unit; 122, node lead-out line; 123, third detection line; 130, first detection line; 140, second detection line. Q, control node; C, storage capacitor; T0, output transistor; T1, first control transistor; T2, second control transistor; Pad1, first test connection terminal; Pad2, second test connection terminal; Pad3, third test connection terminal; LC, pull-down control line; VGL, cathode signal line; STV, reset signal line. Detailed implementation manners

[0035] Now, example embodiments will be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0036] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0037] The present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application and should not be construed as a limitation to the present application.

[0038] In a first aspect, the present application provides a gate driving circuit, which specifically includes the following embodiments: Figure 1 The following shows a schematic structural diagram of a first gate driving circuit provided by an embodiment of the present application; as Figure 1 shown, the gate driving circuit 100 includes multiple clock signal lines 110, and different timing clock signals are output on each clock signal line 110. In Figure 1 it includes 4 clock signal lines, corresponding to CK1, CK2, CK3, and CK4 respectively, and the timings output on each clock signal line are different.

[0039] The gate driving circuit 100 of this embodiment includes N cascaded driving circuit modules 120, and each driving circuit module 120 further includes a circuit unit 121. The circuit unit 121 at least includes a control node Q and an output transistor T0. The control end of the output transistor T0 is electrically connected to the control node Q, the first end of the output transistor T0 is electrically connected to the corresponding clock signal line 110, and the second end of the output transistor T0 is electrically connected to the corresponding scan line 200; the output transistor T0 is used to output a gate driving signal to the corresponding scan line 200 according to the clock signal on the clock signal line 110 under the action of the working voltage on the control node Q.

[0040] It should be noted that the control node Q is commonly known as the Q point and is used to control the opening and closing of the output transistor T0; when the output transistor T0 is an N-type MOS transistor, the output transistor T0 is turned on when the voltage on the control node Q is high, and the clock signal on the clock signal line 110 is output as a gate driving signal to the scan line 200 in the panel, thereby turning on the transistor in the panel that controls pixel charging; conversely, the output transistor T0 is turned off when the voltage on the control node Q is low, and the output of the gate driving signal stops; in addition, when the output transistor T0 is a P-type MOS transistor, its working principle is opposite to that of the N-type MOS transistor, which will not be elaborated here. The working voltage in this embodiment refers to the voltage that can turn on the output transistor during the normal scanning stage.

[0041] It is worth noting that in the circuit unit 121, it not only includes the control node Q and the output transistor T0, but also includes such as Figure 2The pre-charge unit 1211, pull-down control unit 1212, storage capacitor C, reset unit 1213, etc. as shown; for the nth-stage circuit unit, the pre-charge unit 1211 is used to pre-charge its control node Q through the gate driving signal output by the (n - 4)th-stage circuit unit, so as to turn on the output transistor T0 in advance before the nth-stage clock signal arrives; the pull-down control unit 1212 is used to pull down and maintain the voltages on the control node Q and the second end of the output transistor T0 through the pull-down control signal output on the pull-down control line LC, that is, noise reduction processing; the reset unit 1213 is used to reset the voltage on the control node Q through the reset signal on the reset signal line STV; the storage capacitor C is used to store the voltage on the control node Q. Figure 2 Only as an example of the specific circuit structure of the circuit unit 121, as long as the circuit unit 121 includes the control node Q and the output transistor T0, it is applicable to this application.

[0042] In addition, from Figure 2 the circuit structure, it can be seen that the gate driving circuit 100 not only includes multiple clock signal lines 110, but also at least includes a pull-down control line LC, a reset signal line STV, and a cathode signal line VGL.

[0043] Figure 3 The figure shows a schematic arrangement diagram of multiple display panels provided by an embodiment of this application; as Figure 3 shown, 4 display panels with the same size are simultaneously fabricated on a glass panel, and each display panel is Figure 4 the double-end drive as shown, Figure 3 In the figure, the reference numeral 310 represents the input signal terminal in the gate driving circuit 100, such as the clock signal line 110, the pull-down control line LC, the reset signal line STV, and the cathode signal line VGL, etc., and the reference numeral 320 represents the connection terminal of the external detection device. The connection terminal of the external detection device is electrically connected to the input signal terminal of the gate driving circuit 100. A test voltage can be sent to the display gate driving circuit 100 through the external detection device, so as to detect the abnormal conditions of the display panel in real time, achieving timely repair for those that can be repaired and timely scrapping for those that cannot be repaired.

[0044] Here, taking the Figure 2 GDL circuit structure as an example, the current detection method for the gate driving circuit 100 at the ATT stage is as follows: (1) Set all the input signals of the circuit unit 121 to high potential, then the potential of the control node Q in the circuit unit 121 is also high, and all the gate driving signals output by the circuit unit 121 are high potential, and all the pixel rows in the plane are simultaneously turned on.

[0045] (2) Maintain the normal timing of all input signals in the circuit unit 121, and turn on all pixel rows in the plane one by one. The waveform of point Q is as Figure 5 shown; among them, in Figure 5 , STV represents the waveform on the reset signal line STV, which is also the frame start signal; G1 represents the output waveform of the first-stage circuit unit 121, G2 represents the output waveform of the second-stage circuit unit 121, Q1 represents the waveform of point Q of the first-stage circuit unit 121, and Q2 represents the waveform of point Q of the second-stage circuit unit 121.

[0046] (3) Set all input signals of the circuit unit 121 to low potential, then no gate drive signal is output, and all pixel rows in the plane are turned off.

[0047] However, the above three detection methods cannot detect whether there is a short circuit abnormality between the source and drain of the output transistor T0.

[0048] As Figure 6 shown, 6a represents a schematic diagram of the normal output transistor T0, and 6b represents a schematic diagram of the abnormality of the short circuit between the source and drain of the output transistor T0; it can be seen from 6b that regardless of the voltage of the gate of the output transistor T0, the source and drain are both conducting; in order to detect whether there is a short circuit abnormality between the source and drain of the output transistor T0, set the gate voltage of the output transistor T0 to the turn-off voltage and detect whether the drain voltage changes with the change of the source voltage; that is, when the output transistor T0 is in the off state, detect whether there is a situation where a pixel row in the plane is turned on to detect the short circuit abnormality between the source and drain.

[0049] The inventor of the present application has found through research that by separately controlling the timing of the control node Q in the circuit unit 121, the short circuit abnormality between the source and drain of the output transistor T0 can be detected during the test phase. Specifically: As Figure 1 shown, each drive circuit module 120 further includes a node lead 122, and the first end of the node lead 122 is electrically connected to the control node Q; the node lead 122 is configured to transmit an external test voltage to the control node Q during the test phase to control the output transistor T0 to be in the off state.

[0050] In this embodiment, when the second end of the node lead 122 is used as the first test connection terminal Pad1, the first test connection terminal Pad1 is configured to be electrically connected to a device that outputs an external test voltage during the test phase; among them, the device that outputs an external test voltage can be an external detection device directly connected to the first test connection terminal Pad1.

[0051] It should be noted that in this embodiment, the control node Q inside the circuit unit 121 is led out to the outside of the circuit unit through the node lead wire 122, and then the timing of the control node Q is separately controlled through the node lead wire 122, so that the source-drain short circuit abnormality of the output transistor T0 can be detected in the test stage. The specific detection process is as follows: (1) In the ATT stage, the second end of each node lead wire 122 is used as the first test connection terminal Pad1, and the external detection device is directly electrically connected to the first test connection terminal Pad1. The external test voltage output by the external detection device is a low level to the first test connection terminal Pad1, and then the low level is output to the control node Q through the node lead wire 122, thereby turning off the output transistor T0.

[0052] (2) At the same time, control the clock signal line 110 corresponding to the circuit unit 121 to output a driving voltage; if it is detected that the pixel rows in the plane are lit, it means that there is a short circuit abnormality between the source and drain of the output transistor T0 in the circuit unit 121; if it is detected that the pixel rows in the plane are not lit, it means that there is no short circuit abnormality between the source and drain of the output transistor T0 in the circuit unit 121; the specific timing is as Figure 7 shown Figure 7 where CK represents the waveform on the clock signal line 110, Q represents the waveform on the control node Q, and the short circuit output represents the output waveform when there is a short circuit abnormality between the source and drain of the output transistor T0.

[0053] In addition, it should be noted that the above detection process only elaborates on whether there is a short circuit between the source and drain of the output transistor T0. Other abnormality detections of the circuit unit 121, and abnormality detections of the in-plane scan line 200 and data lines can be carried out normally according to related technologies, which will not be elaborated here. In addition, when checking whether the pixel rows in the plane are lit, data signals need to be input to all column data lines at the same time.

[0054] In addition, in this embodiment, the level type of the external test voltage is determined according to the type of the output transistor T0. If the output transistor T0 is an N-type MOS transistor, the external test voltage is a low level. If the output transistor T0 is a P-type MOS transistor, the external test voltage is a high level; similarly, the level type of the driving voltage is determined according to the type of the control transistor that controls the opening and closing of the scan line 200 in the panel. If the control transistor in the panel is an N-type MOS transistor, the driving voltage is a high level. If the control transistor is a P-type MOS transistor, the driving voltage is a low level.

[0055] It should be noted that when detecting the source-drain short circuit condition of the output transistor T0 through the node lead wire 122 in the test stage, one or more circuit units 121 can be detected simultaneously, and adaptive compatibility is carried out according to the connection pins of the external detection device.

[0056] In addition, the wiring method of the node lead 122 in this embodiment can be led out along the longitudinal arrangement of the circuit unit 121 (i.e., vertically arranged or approximately vertically arranged), or can be led out perpendicular to the longitudinal arrangement of the circuit unit 121 (i.e., horizontally arranged or approximately horizontally arranged). Since the vertical setting of the node lead 122 will increase the length of the lead and the complexity of the cross-wire, it is preferably arranged horizontally, as Figure 8 shown in the design schematic diagram. In addition to the control node Q and the output transistor T0, the circuit unit 121 also includes other reset transistors, pre-charge transistors, and pull-down control transistors, which will not be elaborated here.

[0057] A plurality of clock signal lines 110, pull-down control lines LC, cathode signal lines VGL, reset signal lines STV, etc. are vertically arranged on the left side of the circuit unit 121. The node leads 122 corresponding to each circuit unit 121 are respectively arranged in a different layer and cross with the signal lines such as the clock signal lines 110, pull-down control lines LC, cathode signal lines VGL, and reset signal lines STV. That is to say, although the node lead 122 intersects with the clock signal line 110, they are not connected. In Figure 8 the plurality of clock signal lines 110, pull-down control lines LC, cathode signal lines VGL, reset signal lines STV, and the gate electrodes of the transistors are designed on the same metal layer M1, and the node leads 122 and the source-drain electrodes of the transistors are designed on another metal layer M2. If the conduction between the metal layer M1 and the metal layer M2 is to be realized, it can be electrically connected through Figure 8 the through hole 330 in

[0058] Furthermore, in order to reduce the coupling effect between the node lead 122 and other metal lines, this embodiment can avoid it by reducing the wiring width of the node lead 122. In addition, since the node lead 122 is only used when the output transistor T0 is separately detected in the test stage, and the input is also a low potential, it hardly affects the normal operation of other lines in the display panel.

[0059] It can be seen from this that in this application, the control node Q encapsulated inside the circuit unit 121 is led out of the circuit unit through the node lead 122, and then the corresponding voltage is input to the node lead 122 through an external detection device, so as to realize the separate control of the timing voltage of the control node Q. The source-drain short-circuit abnormality of the output transistor T0 can be detected in the test stage, thereby improving the detection comprehensiveness and accuracy of the GDL product in the test stage, avoiding abnormal products from flowing into the backend process, and improving the yield and cost control of the backend product.

[0060] In the process of the invention and creation, the inventors of the present application also found that there are too many first test connection pads Pad1 in the above embodiments, and the number that can be detected simultaneously by the external detection device is limited, resulting in a problem of low detection efficiency.

[0061] To solve the above problem of low detection efficiency, the present application provides another gate drive circuit 100, which specifically includes the following embodiments: Figure 9 The following shows a schematic structural diagram of the second gate drive circuit 100 provided by the embodiment of the present application; as Figure 9 shown, on the basis of Figure 1 , the gate drive circuit 100 further includes a first detection line 130 and a second detection line 140; wherein, one end of the first detection line 130 is defined as a second test connection pad Pad2, and the second test connection pad Pad2 is configured to be electrically connected to the device outputting the control voltage during the test phase; one end of the second detection line 140 is defined as a third test connection pad Pad3, and the third test connection pad Pad2 is configured to be electrically connected to the device outputting the external test voltage during the test phase.

[0062] In addition, each drive circuit module 120 further includes a first control transistor T1. The control end of the first control transistor T1 is electrically connected to the first detection line 130, the first end of the first control transistor T1 is electrically connected to the second end of the node lead 122, and the second end of the first control transistor T1 is electrically connected to the second detection line 140.

[0063] It should be noted that in this embodiment, the voltage on the control node Q is controlled separately, and the specific steps for detecting the source-drain detection result of the output transistor T0 during the test phase are as follows: (1) During the test phase, the external detection device outputs a control voltage to the second test connection pad Pad2, and turns on the first control transistor T1 through the first detection line 130, so that the second end of the node lead 122 is electrically connected to the second detection line 140; that is to say, the control voltage is the turn-on signal of the first control transistor T1. When the first control transistor T1 is turned on, each node lead 122 is electrically connected to the second detection line 140. Since one end of the node lead 122 is connected to the control node Q and the other end of the node lead 122 is connected to the second detection line 140, it is equivalent that the control node Q of each circuit unit 121 is connected to the second detection line 140.

[0064] (2) During the test phase, the external detection device outputs an external test voltage to the third test connection pad Pad3, and outputs the external test voltage to the control node Q through the second detection line 140 and the node lead 122 to turn off the output transistor T0; the output transistors T0 in all circuit units 121 can be simultaneously turned off through the external test voltage on the second detection line 140.

[0065] (3) Meanwhile, the external detection device controls to output a driving voltage that can turn on the scanning line 200 on each clock signal line 110; when it is detected that there is a lit pixel row in the display panel, it means that the second end of the output transistor T0 in the corresponding row also outputs a driving voltage, that is, the source-drain detection result of the output transistor T0 is abnormal; a pixel row that is not lit in the display panel means that there is no signal output at the second end of the corresponding output transistor T0, that is, the source-drain detection result of the output transistor T0 is normal.

[0066] (4) In the non-test stage, no signal is output on the first detection line 130 and the second detection line 140, and all the first control transistors T1 are in the off state, thus avoiding the short-circuit problem between the control nodes Q.

[0067] It can be seen from this that in this embodiment, the source-drain of all output transistors T0 can be simultaneously detected only through two detection lines, which greatly improves the detection efficiency. From Figure 1 and Figure 9 comparison, it can be seen that Figure 1 among the N first test connection pads Pad1, Figure 2 only 1 second test connection pad Pad2 and 1 third test connection pad Pad3 (equivalent to 2 test connection pads) are required in

[0068] In this embodiment, Figure 9 the design schematic diagram of the gate driving circuit shown is as Figure 10 shown, Figure 10 among them, the first control transistor T1 is only taken as an example. The gate of the first control transistor T1 and the first detection line 130 belong to the same metal layer, and the source and drain of the first control transistor T1 and the second detection line 140 belong to another metal layer.

[0069] As Figure 10 shown, in this embodiment, multiple clock signal lines 110 extend along the cascading direction of N driving circuit modules, the node lead 122 is perpendicular or approximately perpendicular to the multiple clock signal lines 110, and the first detection line 130 and the second detection line 140 are respectively parallel or approximately parallel to the clock signal lines 110.

[0070] To solve the problem of low detection efficiency above, the present application also provides another gate driving circuit, which specifically includes the following embodiments: Figure 11 The structure schematic diagram of the third gate driving circuit provided by the embodiment of the present application is shown in Figure 11As shown, on the basis of Figure 1 , the gate driving circuit 100 further includes: a first detection line 130, one end of the first detection line 130 is defined as a second test connection terminal Pad2, and the second test connection terminal Pad2 is configured to be electrically connected to a device for outputting a control voltage during a test phase.

[0071] In addition, each drive circuit module 120 further includes a first control transistor T1, a second control transistor T2, and a third detection line 123; the control terminal of the first control transistor T1 is electrically connected to the first detection line 130, and the first end of the first control transistor T1 is electrically connected to the second end of the node lead-out line 122; the control terminal of the second control transistor T2 is electrically connected to the first detection line 130, and the first end of the second control transistor T2 is connected to the second end of the first control transistor T1; the first end of the third detection line 123 is connected to the second end of the second control transistor T2 of the current-stage drive circuit module, and the second end of the third detection line 123 is connected to the second end of the second control transistor T2 of the previous-stage drive circuit module, or the second end of the third detection line 123 is connected to the second end of the second control transistor T2 of the next-stage drive module.

[0072] In this embodiment, when the second end of the third detection line 123 is connected to the second end of the second control transistor T2 of the previous-stage drive circuit module, the second end of the third detection line 123 of the first-stage drive circuit module is defined as a third test connection terminal Pad3, and the third test connection terminal Pad3 is configured to be electrically connected to a device for outputting an external test voltage during a test phase.

[0073] When the second end of the third detection line 123 is connected to the second end of the second control transistor T2 of the next-stage drive circuit module, the second end of the third detection line 123 of the Nth-stage drive circuit module is defined as a third test connection terminal Pad3, and the third test connection terminal Pad3 is configured to be electrically connected to a device for outputting an external test voltage during a test phase.

[0074] It should be noted that this embodiment separately controls the voltage on the control node Q, and the steps for detecting the source-drain detection result of the output transistor T0 during the test phase specifically include the following: (1) During the test phase, the external detection device outputs a control voltage to the second test connection terminal Pad2, and simultaneously turns on all the first control transistors T1 and the second control transistors T2 through the first detection line 130, so that the second ends of the node leads 122 are electrically connected to the corresponding third detection lines 123 respectively, and there is also an electrical connection between all the third detection lines 123; that is to say, the control voltage is the turn-on voltage of the first control transistors T1 and the second control transistors T2. When the first control transistors T1 are turned on, each node lead 122 is electrically connected to the third detection line 123. Since one end of the node lead 122 is connected to the control node Q and the other end of the node lead 122 is connected to the third detection line 123, it is equivalent to that the control node Q of each circuit unit 121 is connected to the third detection line 123; and because the turned-on second control transistors T2 connect all the third detection lines 123, it makes the control node Q of each circuit unit 121 equivalent to be connected to the third test connection terminal Pad3.

[0075] (2) During the test phase, the external detection device outputs an external test voltage to the third test connection terminal Pad3, and outputs the external test voltage to the control node Q through the third detection line 123 and the node lead 122, and turns off the output transistor T0; that is to say, the external test voltage on the third detection line 123 can turn off all the output transistors T0 in all the circuit units 121 simultaneously.

[0076] (3) At the same time, the external detection device controls to output a driving voltage that can turn on the scanning line 200 on each clock signal line 110; when it is detected that there is a lit pixel row in the display panel, it means that the second end of the output transistor T0 in the corresponding row also outputs a driving voltage, that is, the source-drain detection result of the output transistor T0 is abnormal; a pixel row in the display panel that is not lit means that there is no signal output at the second end of the corresponding output transistor T0, that is, the source-drain detection result of the output transistor T0 is normal.

[0077] (4) During the non-test phase, there is no signal output on the first detection line 130 and the second detection line 140, and all the first control transistors T1 and the second control transistors T2 are in the off state, thus avoiding the short-circuit problem between the control nodes Q.

[0078] In summary, this embodiment can achieve the purpose of simultaneously detecting the source-drain of all the output transistors T0, greatly improving the detection efficiency; in addition, from Figure 1 and Figure 11 's comparison, it can be seen that Figure 1 among the N first test connection terminals Pad1, Figure 2Only one second test connection terminal Pad2 and one third test connection terminal Pad3 (equivalent to two test connection terminals) are required, which greatly reduces the requirements for test connection terminals in this embodiment. While improving the detection efficiency, it also reduces the requirements for external detection devices.

[0079] From Figure 9 and Figure 11 Comparing, it can be seen that the two solutions are parallel solutions with the same technical concept. The differences between the technical solutions are as follows: Figure 9 The second detection line 140 of Figure 11 is originally a complete wire, Figure 9 is to connect multiple segments of the third detection line in series into a complete wire through N second control transistors T2; the differences in technical effects are as follows: Figure 11 In , the second detection line 140 is connected to the control nodes Q in all circuit units through the first control transistor T1 at the same time. Although the transistors controlled by the first detection line 130 are turned on and off, due to the difference in the working timing of the GDL between different circuit units, the time of input voltage on the control nodes Q in different circuit units is also different. As a result, it may affect the upper and lower adjacent-level GDLs due to the change of the voltage at point Q, causing fluctuations in the potential of point Q and affecting the normal operation of the GDL during display; therefore, by Figure 11 adding the second control transistor T2 between multiple segments of the third detection line, the influence of voltage on the GDL circuit can be further blocked.

[0080] Referring to Figure 12 shown, compared with Figure 3 , two lines are added to the display panel, corresponding to Figure 9 the first detection line 130 and the second detection line 140 in Figure 11 respectively, and can also correspond to Figure 11 the first detection line 130 and the third detection line 123 in Figure 12 ; among them, Figure 12 the corresponding third detection line 123 in is only the third detection line 123 in the first-level drive circuit module 120 or the Nth-level drive circuit module 120; referring to Figure 13 shown, compared with Figure 4 , two lines are added to both sides of the display panel, corresponding to Figure 9 the first detection line 130 and the second detection line 140 in Figure 13 respectively; among them, Figure 13 the first control transistor T1 and the second control transistor T2 are not shown in

[0081] In another embodiment, the gate drive circuit 100 further includes: a pull-down control line LC, and the pull-down control line LC is configured to be electrically connected to a device that outputs a control voltage during the test stage; one end of the first detection line 130 is electrically connected to the pull-down control line LC.

[0082] It should be noted that, in order to further reduce the number of test signals output by the external detection device, the one ends of the first detection lines in Figure 9 and Figure 11 can be respectively electrically connected to the original pull-down control line in the gate driving circuit, so that during the test phase, a control voltage is output to the first detection line 130 through the pull-down control line LC, as shown in Figure 14 and Figure 15 ; Usually, there are 1 or 2 pull-down control lines LC in the gate driving circuit. On this basis, in this embodiment, it is not necessary to add a second test connection end, and only one third test connection end is required, which further reduces the functional requirements for the external detection device, and there is no overlap of redundant signals and GDL lines to affect the normal operation performance of the GDL.

[0083] Second, the present application provides a method for detecting a gate driving circuit, which specifically includes the following embodiments: Figure 16 The figure shows a schematic flowchart of a method for detecting a gate driving circuit provided by an embodiment of the present application; this detection method is applied to the gate driving circuit shown in the above embodiment, and specifically includes the following steps during the test phase: Step S100: Output an external test voltage to the control node by using a node lead wire, so that the output transistor is in an off state.

[0084] Step S200: Output a driving voltage to the first end of the output transistor by using a clock signal line.

[0085] Step S300: Detect the relationship between the output voltage at the second end of the output transistor and the driving voltage to determine the short-circuit state of the output transistor.

[0086] Further, when the gate driving circuit includes a first detection line and a second detection line, outputting an external test voltage to the control node by using a node lead wire includes: receiving a control voltage by using the first detection line to make the first control transistor in an open state; receiving an external test voltage by using the second detection line, and making the node lead wire output the external test voltage to the control node.

[0087] Further, when the gate driving circuit includes a first detection line and a third detection line, outputting an external test voltage to the control node by using a node lead wire includes: receiving a control voltage by using the first detection line to make the first control transistor and the second control transistor in an open state; receiving an external test voltage by using the third detection line, and making the node lead wire output the external test voltage to the control node.

[0088] It should be noted that the specific principle of this method for detecting a gate driving circuit is the same as that of the above embodiment, and will not be elaborated here.

[0089] In a third aspect, the present application provides a display panel, including a display area and a non-display area. The display area includes a plurality of scan lines; the non-display area includes the gate driving circuit described in the above embodiments, and a driving output end of a circuit unit in the gate driving circuit is electrically connected to at least one scan line.

[0090] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0091] In the description of this specification, the description with reference to terms such as "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as a limitation to the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the description of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A gate driving circuit, characterized in that, The gate drive circuit comprises: Multiple clock signal lines and N cascaded drive circuit modules; Each driving circuit module includes a circuit unit, the circuit unit at least includes a control node and an output transistor, the control end of the output transistor is electrically connected to the control node, the first end of the output transistor is electrically connected to the corresponding clock signal line, and the second end of the output transistor is electrically connected to the corresponding scan line; the output transistor is configured to output a gate drive signal to the corresponding scan line according to the clock signal on the clock signal line under the action of the working voltage on the control node; Each driving circuit module also includes a node lead line, a first end of which is electrically connected to the control node; the node lead line is configured to transmit an external test voltage to the control node during a test phase to control the output transistor to be in an off state.

2. The gate driving circuit according to claim 1, wherein The second end of the node lead is defined as a first test connection end, and the first test connection end is configured to be electrically connected to a device that outputs the external test voltage during a test phase.

3. The gate driving circuit according to claim 1, wherein The gate drive circuit further includes: a first detection line, one end of which is defined as a second test connection end, and the second test connection end is configured to be electrically connected to a device that outputs a control voltage during a test phase; a second detection line, one end of which is defined as a third test connection terminal, and the third test connection terminal is configured to be electrically connected to a device that outputs the external test voltage during a test phase; Each driving circuit module also includes a first control transistor, a control end of the first control transistor is electrically connected to the first detection line, a first end of the first control transistor is electrically connected to the second end of the node lead line, and a second end of the first control transistor is electrically connected to the second detection line.

4. The gate driving circuit according to claim 1, wherein The gate drive circuit further includes: a first detection line, one end of the first detection line is defined as a second test connection end, and the second test connection end is configured to be electrically connected to a device that outputs a control voltage during a test phase; Each drive circuit module also includes: a first control transistor, wherein a control end of the first control transistor is electrically connected to the first detection line, and a first end of the first control transistor is electrically connected to a second end of the node lead line; a second control transistor, wherein a control end of the second control transistor is electrically connected to the first detection line, and a first end of the second control transistor is connected to a second end of the first control transistor; a third detection line, wherein a first end of the third detection line is connected to a second end of a second control transistor of a current-stage driving circuit module, a second end of the third detection line is connected to a second end of a second control transistor of a previous-stage driving circuit module, or a second end of the third detection line is connected to a second end of a second control transistor of a next-stage driving module; Wherein, when the second end of the third detection line is connected to the second end of the second control transistor of the upper-level driving circuit module, the second end of the third detection line of the first-level driving circuit module is defined as the third test connection end, and the third test connection end is configured to be electrically connected to the device for outputting the external test voltage during the test phase; When the second end of the third detection line is connected to the second end of the second control transistor of the lower-level driving circuit module, the second end of the third detection line of the Nth-level driving circuit module is defined as the third test connection end, and the third test connection end is configured to be electrically connected to the device for outputting the external test voltage during the test phase.

5. The gate driving circuit according to claim 3 or 4, wherein The gate driving circuit further includes: a pull-down control line configured to be electrically connected to the device for outputting the control voltage during the test phase; One end of the first detection line is electrically connected to the pull-down control line.

6. The gate driving circuit according to claim 3, wherein The plurality of clock signal lines extend along the cascading direction of the N driving circuit modules, the node lead-out line is perpendicular to the plurality of clock signal lines, and the first detection line and the second detection line are respectively parallel to the clock signal lines.

7. A method for detecting a gate driving circuit, characterized in that, Applied to the gate driving circuit according to any one of claims 1-6, during the test phase, the detection method includes: Using the node lead-out line to output an external test voltage to the control node to turn off the output transistor; Using the clock signal line to output a driving voltage to the first end of the output transistor; Detecting the relationship between the output voltage at the second end of the output transistor and the driving voltage to determine the short-circuit state of the output transistor.

8. The gate drive circuit detection method according to claim 7, wherein When the gate driving circuit includes a first detection line and a second detection line, the step of using the node lead-out line to output an external test voltage to the control node includes: Receiving the control voltage by using the first detection line to turn on the first control transistor; Receiving the external test voltage by using the second detection line to cause the node lead-out line to output the external test voltage to the control node.

9. The gate drive circuit detection method according to claim 7, wherein When the gate driving circuit includes a first detection line and a third detection line, the step of using the node lead-out line to output an external test voltage to the control node includes: Receiving the control voltage by using the first detection line to turn on the first control transistor and the second control transistor; Receiving the external test voltage by using the third detection line to cause the node lead-out line to output the external test voltage to the control node.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines; characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1 to 6, and the driving output end of the circuit unit in the gate driving circuit is electrically connected to at least one scanning line.

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