Pixel scanning drive circuit, display panel and display device

Abstract

This application relates to a pixel scanning driving circuit, a display panel, and a display device. The circuit includes a pixel unit array, a first preset number of scan lines, and a scanning driving module. Each row of pixel units corresponds to two target scan lines, and the first group of pixel units in the row is driven by the first target scan line, while the second group of pixel units in the row is driven by the second target scan line. The scanning driving module is used to: in response to starting a scan of the current frame image, output a scanning driving signal to the first scan line in the first preset number of scan lines; for the nth scan line and the (n+1)th scan line, first output a scanning driving signal to the (n+1)th scan line, and then output a scanning driving signal to the nth scan line. This application embodiment can improve the inconsistent coupling during scan line voltage changes caused by the different distances between the pixel electrodes and the scan lines, thereby improving the uniformity of the panel display brightness.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a pixel scanning driving circuit, a display panel, and a display device. Background Technology

[0002] Current LCD (Liquid Crystal Display) displays are evolving towards higher resolution, higher image quality, and larger sizes. TFT-LCD (Thin Film Transistor LCD) drives the display using a line-by-line scanning method, meaning that when the scan signal for one line is high, the corresponding TFT in that line is turned on, and data in the column direction can be written to the pixel. To reduce power consumption and cost, a dual-gate driving method can be used, reducing the resources required by the data driver IC. This means that pixels in the same row are driven by two scan signals at different times, and one output of the data driver IC is connected to two data lines.

[0003] However, with the increase in scan lines, the number of parasitic capacitances generated between different scan lines and pixel electrodes also increases, and the distance between the scan lines and pixel electrodes results in different values ​​of parasitic capacitance. Therefore, dual-gate driven liquid crystal panels will produce bright and dark stripes, affecting image display quality. Summary of the Invention

[0004] In view of this, in order to solve some or all of the above-mentioned technical problems, embodiments of this application provide a pixel scanning driving circuit, a display panel, and a display device.

[0005] In a first aspect, embodiments of this application provide a pixel scan driving circuit, the circuit comprising: a pixel unit array, a first preset number of scan lines, and a scan driving module; the scan driving module is connected to the first preset number of scan lines; for each row of pixel units in the pixel unit array, the row of pixel units corresponds to two target scan lines, and the first group of pixel units in the row of pixel units is driven by the first target scan line of the two target scan lines, and the second group of pixel units in the row of pixel units is driven by the second target scan line of the two target scan lines; the scan driving module is configured to: in response to starting a scan of the current frame image, output a scan driving signal to the first scan line of the first preset number of scan lines; for the nth scan line and the (n+1)th scan line, first output a scan driving signal to the (n+1)th scan line, and then output a scan driving signal to the nth scan line, wherein n is an even number greater than 1.

[0006] In one possible implementation, the rising edge of the scan signal on the nth scan line is triggered during the high level period of the scan signal on the (n+1)th scan line; the falling edge of the scan signal on the (n+1)th scan line is triggered during the high level period of the scan signal on the nth scan line.

[0007] In one possible implementation, the scan driver module includes an output line switching unit for connecting the nth output line of the scan driver module to the (n+1)th scan line.

[0008] In one possible implementation, the two target scan lines are located on the same side of the corresponding row of pixel units, and the index of the target scan line closer to the corresponding row of pixel units is less than the index of the target scan line farther from the corresponding row of pixel units.

[0009] In one possible implementation, the circuit further includes a compensation scan line, which, along with the first scan line, is located on both sides of the first row of pixel units in the pixel unit array. The distance between the compensation scan line and the second scan line in the first preset number of scan lines is greater than the distance between the first scan line and the second scan line. The compensation scan line is connected to a scan driving module, which is further configured to: in response to starting a scan of the current frame image, first output a scan driving signal to the first scan line in the first preset number of scan lines, and then output a scan driving signal to the compensation scan line.

[0010] In one possible implementation, the scan driver module includes an output line switching unit, which is used to connect the first output line of the scan driver module to the compensation scan line, the zeroth output line of the scan driver module to the first scan line, and the nth output line of the scan driver module to the (n+1)th scan line.

[0011] In one possible implementation, the two target scan lines are located on either side of a corresponding row of pixel units.

[0012] In one possible implementation, the circuit further includes a second preset number of data lines; each of the second preset number of data lines corresponds to a column of pixel units and is used to transmit display data to the corresponding column of pixel units; each of the second preset number of data lines is connected to at least one corresponding target data line.

[0013] Secondly, embodiments of this application provide a display panel, which includes: a controller, a data driving module, and the aforementioned pixel scanning driving circuit, wherein the controller is connected to the data driving module and the scanning driving module in the pixel scanning driving circuit.

[0014] Thirdly, embodiments of this application provide a display device, including: a display panel, a panel frame, a power module, and a data receiving module as described in the second aspect above; the display panel is mounted on the panel frame, the power supply terminal of the display panel is connected to the power module, and the signal receiving terminal of the display panel is connected to the data receiving module.

[0015] The pixel scanning driving circuit, display panel, and display device provided in this application adjust the scanning order of each row of the pixel unit array when displaying an image. Specifically, when scanning of the current frame image begins, a scanning driving signal is output to the first scan line. For the nth and (n+1)th scan lines, a scanning driving signal is output to the (n+1)th scan line first, followed by the nth scan line, where n is an even number greater than 1. This increases the distance between the scan line and the pixel unit driven by the scan line during the driving state when the level of a scan line changes. This reduces the parasitic capacitance between the scan line and the pixel unit driven by the scan line during the driving state, thereby lowering the voltage coupled from each scan line to the pixel unit. This improves the inconsistent coupling caused by varying distances between the pixel electrode and the scan line during voltage changes, thus enhancing the uniformity of the panel's display brightness. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1 This is a schematic diagram of the pixel array architecture in the related technology of this application embodiment;

[0020] Figure 2 This is a schematic diagram illustrating the distance difference between scan lines and pixel units in the related technologies of this application embodiment;

[0021] Figure 3 This is a timing diagram of the scan drive signal in the related technology of the embodiments of this application;

[0022] Figure 4 This is a schematic diagram of the structure of a pixel scanning driving circuit provided in an embodiment of this application;

[0023] Figure 5 A timing diagram of a scan drive signal provided in an embodiment of this application;

[0024] Figure 6 The circuit structure diagram of the scanning driving module provided in the embodiments of this application is shown.

[0025] Figure 7 This is a schematic diagram of another pixel scanning driving circuit provided in an embodiment of this application;

[0026] Figure 8 A timing diagram of another scan drive signal provided in an embodiment of this application;

[0027] Figure 9 A circuit diagram of another scanning driving module provided in an embodiment of this application;

[0028] Figure 10 A schematic diagram of another pixel scanning driving circuit provided in the embodiments of this application;

[0029] Figure 11 A schematic diagram of another pixel scanning driving circuit provided in the embodiments of this application;

[0030] Figure 12 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0031] Figure 13 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0032] Figure label:

[0033] 400 - Pixel scan driving circuit; 401 - Pixel unit array; 402 - First preset number of scan lines; 403 - Scan driving module; 4031 - Output line switching unit; 1200 - Display panel; 1201 - Controller; 1202 - Data driving module; 1300 - Display device; 1301 - Panel frame; 1302 - Power supply module; 1303 - Data receiving module. Detailed Implementation

[0034] Various exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this application.

[0035] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of this application are only used to distinguish different steps, devices or modules, and do not represent any specific technical meaning, nor do they indicate the logical order between them.

[0036] It should also be understood that in this embodiment, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0037] It should also be understood that any component, data or structure mentioned in the embodiments of this application can generally be understood as one or more unless explicitly defined or given contrary guidance in the context.

[0038] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects have an "or" relationship.

[0039] It should also be understood that the description of the various embodiments in this application emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0040] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0041] Techniques, circuits, and devices known to a person skilled in the art may not be discussed in detail, but where appropriate, such techniques, circuits, and devices should be considered part of the specification.

[0042] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0043] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. To facilitate understanding of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] like Figure 1As shown, this is a schematic diagram of the H-type architecture in related technologies. Here, Dn represents the data line distribution, L_n represents the scan line distribution, and G_n represents the received scan drive signal. Figure 1 It can be seen that there are two scan lines between two adjacent rows of pixel units, and the two scan lines are at different distances from the pixel units in the same row. For example Figure 2 As shown, this illustrates two different connection methods within the panel. It can be seen that the distance from scan line L_1 to one end of the TFT pixel electrode is d1, and the distance from scan line L_2 to one end of the TFT pixel electrode is d2. Clearly, d2 > d1. This distance will cause a parasitic capacitance C between the scan line and the pixel electrode. gs Different sizes, i.e., C gs1 >C gs2 Different parasitic capacitances will cause a feedthrough voltage ΔV when the scan line is turned off. p =C gs / (C gs +C lc +C st The difference is that ΔV p1 >ΔV p2 This causes the positive polarity controlled by G_1 to be darker and the negative polarity controlled to be brighter; the opposite is true for the polarity controlled by G_2. Therefore, it is possible that... Figure 1 The case where two columns of pixels are bright and two columns of pixels are dark.

[0045] like Figure 3 As shown, this is the typical scan timing for each scan line. (From...) Figure 3 and Figure 1 As can be seen, in the above architecture, the sub-pixel controlled by L_3 is too close to both the L_3 and L_2 scan lines. During the high-level period of L_3, the falling edge of L_2 increases the voltage fed into the sub-pixel controlled by L_3, and the falling edge of L_3 itself also increases the voltage. Therefore, the sub-pixel controlled by L_3 is significantly affected by both L_2 and L_3. However, for the sub-pixel controlled by L_4, since L_2 is off during its driving period, only L_3 and L_4 themselves significantly affect the input voltage. Furthermore, L_4 is farther from the sub-pixel than L_2, resulting in a lower input voltage. This leads to uneven brightness between the sub-pixels controlled by L_3 and L_4.

[0046] To solve the above technical problems, such as Figure 4As shown, this application embodiment provides a pixel scanning driving circuit 400, which is typically used in display panels. The circuit 400 specifically includes: a pixel unit array 401, a first preset number of scan lines 402, and a scanning driving module 403. The scanning driving module 403 is connected to the first preset number of scan lines 402.

[0047] The aforementioned scan drive module 403 can also be referred to as GOA (Gate on Array), which includes multiple scan signal output lines, each connected to a scan line. For example... Figure 4 As shown, the scan signal output lines included in the scan drive module 403 are represented by G_1-G_M, and the first preset number of scan lines 402 are represented by L_1-L_M.

[0048] For each row of pixel units in the pixel unit array 401, the row of pixel units corresponds to two target scan lines, and the first group of pixel units in the row of pixel units is driven by the first target scan line of the two target scan lines, and the second group of pixel units in the row of pixel units is driven by the second target scan line of the two target scan lines.

[0049] like Figure 4 As shown, for the first row of pixel units, scan lines L_1 and L_2 are the corresponding target scan lines. Some pixel units are connected to scan line L_1 via TFTs, and other pixel units are connected to scan line L_2 via TFTs. The scan signals received by L_1 and L_2 respectively drive pixel units at different positions in the same row.

[0050] The scan drive module 403 is used to: in response to starting a scan of the current frame image, output a scan drive signal to the first scan line of the first preset number of scan lines 402; for the nth scan line and the (n+1)th scan line, first output a scan drive signal to the (n+1)th scan line, and then output a scan drive signal to the nth scan line. Here, n is an even number greater than 1.

[0051] That is, for all scan lines except the first scan line, the order in which even-numbered scan lines and odd-numbered scan lines receive the scan drive signals is swapped. Typically, the scan drive module 403, under the control of the timing controller, outputs scan drive signals from terminals G_1-G_M according to the timing sequence. The output sequence of the scan drive module 403 is usually G_1, G_2, ..., G_M. By adjusting the connection order with the scan lines, the timing sequence of the scan drive signals received on each scan line is as follows... Figure 5 As shown, the order of the received scan drive signals, in the order of L_1, L_2, ..., L_M, is G_1, G_3, G_2, G_5, G_4, ..., G_M-1, G_M.

[0052] The principle by which this application embodiment can improve the brightness uniformity of the displayed image is as follows:

[0053] Taking L3 and L4 control sub-pixels as an example, if conventional methods are used... Figure 3 The driving timing shown shows that since L_2 and L_3 are both adjacent to the sub-pixels corresponding to D1 to D6, the feed voltage of L_2 to these sub-pixels is ΔV. p2 =C Ls2 / (C Ls2 +C lc +C st (-VLH+VLL), the feed voltage of L_3 to these sub-pixels is ΔV p3 =C Ls3 / (C Ls3 +C lc +C st The total effect is ΔV (-VLH+VLL). p2 +ΔV p3 .

[0054] For the sub-pixels controlled by L_4, according to Figure 3 The driving timing shown indicates that only the falling edges on L_3 and L_4 will affect their feed voltage. Since L_2 and L_3 are equidistant from the sub-pixels controlled by L_4, the effect of L_3 on the feed voltage of the sub-pixels controlled by L_4 is also ΔV. p2 =C Ls2 / (C Ls2 +C lc +C st (-VLH+VLL), then the effect of L_4 on its feed voltage is ΔV p4 =C Ls4 / (C Ls4 +C lc +C st (-VLH+VLL), the total effect ΔV p2 +ΔV p4 .

[0055] It can be seen that the difference in the feed voltage experienced by the sub-pixels controlled by L_3 and L_4 is ΔV. p3 -ΔV p4 And because C Ls3 and C Ls4 The difference in capacitance due to the distance between them, therefore, ΔV p3 >ΔV p4 This leads to uneven brightness of the pixels corresponding to the two scan lines.

[0056] In this embodiment, the scan lines other than the first scan line receive the scan drive signal by swapping the odd-numbered and even-numbered positions. Figure 4 and Figure 5 As shown, for the sub-pixel controlled by L_3, L_3 drives the corresponding sub-pixel before L_2. The falling edge of the scan drive signal received by L_3 is located during the high level period of L_2, and the distance between L_3 and the sub-pixel controlled by L_2 is relatively large. As a result, the parasitic capacitance generated by L_3 to the sub-pixel controlled by L_2 is small, thereby reducing the voltage fed into the sub-pixel controlled by L_2 and improving the uniformity of the display screen.

[0057] The pixel scanning driving circuit provided in this application adjusts the scanning order of each row of the pixel unit array when displaying an image. Specifically, when scanning of the current frame image starts, a scanning driving signal is output to the first scan line. For the nth and (n+1)th scan lines, a scanning driving signal is output to the (n+1)th scan line first, and then to the nth scan line, where n is an even number greater than 1. This increases the distance between the scan line and the pixel unit driven by the scan line during the driving state when the level of a certain scan line changes. This reduces the parasitic capacitance between the scan line and the pixel unit driven by the scan line during the driving state, thereby lowering the voltage coupled from each scan line to the pixel unit. This improves the inconsistent coupling caused by varying distances between the pixel electrode and the scan line during scan line voltage changes, thus enhancing the uniformity of panel display brightness.

[0058] In some optional implementations of this embodiment, such as Figure 5 The timing diagram shown indicates that the rising edge of the scan signal on the nth scan line is triggered during the high level period of the scan signal on the (n+1)th scan line; the falling edge of the scan signal on the (n+1)th scan line is triggered during the high level period of the scan signal on the nth scan line.

[0059] As described above, the bright and dark stripes are caused by the following: during the high-level period of the scan drive signal on scan line a, if another scan line b generates a falling edge, it will cause a voltage to be fed into the pixel unit controlled by scan line a. Figure 1 Taking L_3 and L_4 as examples, ΔV p3 >ΔV p4 If a method can be found to reduce the downward coupling tendency of the voltage generated by the rising and falling edges of L_3, then the feed voltage of the pixel units controlled by L_3 and L_4 can be made closer to equal. Downward coupling is a problem caused by the scanning line being closed; if the upward coupling effect of the voltage when the scanning line is open can be fed into the pixel capacitance, then the above problem can be solved.

[0060] therefore, Figure 4 In the circuit shown, the rising edge of L_2 must be triggered when L_3 is high, and the rising edge of L_2 cannot occur when L_4 is high. For example... Figure 5 As shown, the order of the signals received by L_2 and L_3 is reversed, so that the rising edge of the signal on L_2 occurs during the high-level phase of the signal on L_3. For the sub-pixel controlled by L_3, the effect of L_2 when it is turned on is to make ΔV... p2′ Raising it upwards, the effect of closing L_3 on it is to make ΔV p3 Decrease, i.e., ΔV p3 = (-VGH+VGL)*C gs3 / (C gs3 +C lc +C st If the overall impact is ΔV, then the total impact is ΔV. p3′ =ΔV p3 +ΔV p2′ = (-VGH+VGL)*C gs3 / (C gs3 +C lc +C st )+ΔV p2′ Because |ΔV p3 |>|ΔV p2′ |, then we can know that after adding them, ΔV p3′ The overall absolute value decreased.

[0061] For the sub-pixel controlled by L_4, during its high-level period, L_2 is already off and there is no rising or falling edge; only L_5 has a rising edge. Since L_5 is physically far from L_4, its rising or falling edge has virtually no effect on L_4.

[0062] Therefore, the feed voltage of the sub-pixel controlled by L_4 is ΔV p4 =C gs4 / (C gs4 +C lc +C st (-VGH+VGL). Originally ΔV p3 and ΔV p4 Both methods pull down the pixel voltage, and |ΔV p3 |>|ΔV p4 |, here because of ΔV p3′ It was lifted slightly, therefore, ΔV p3′ and ΔV p4 The closer the two sides are, the better the uniformity of brightness.

[0063] In this embodiment, by triggering the rising edge of the scan signal on the nth scan line during the high-level period of the scan signal on the (n+1)th scan line, the absolute value of the feed voltage from the (n+1)th scan line to the pixel unit it controls can be reduced. This effectively reduces the difference in feed voltage between different columns of pixels by adjusting the timing of the scan lines and the positional relationship of the rising and falling edges, thereby improving the uniformity of the panel display brightness.

[0064] In some optional implementations of this embodiment, such as Figure 6 As shown, the scan driving module 403 includes an output line switching unit 4031, which connects the nth output line of the scan driving module 403 to the (n+1)th scan line. That is, the output line switching unit cross-connects the scan lines other than the first scan line with the output lines of the scan driving module 403.

[0065] The aforementioned output line switching unit can be a separate, detachable connector, or it can be integrated internally or externally into the scan drive module 403. This embodiment, by setting up the output line switching unit, enables flexible adjustment of the timing of the scan drive signals received by each scan line, which helps to expand the application scenarios of this circuit.

[0066] In some optional implementations of this embodiment, such as Figure 4 In the circuit shown, the two target scan lines are located on the same side of the corresponding row of pixel units, and the index of the target scan line closer to the corresponding row of pixel units is less than the index of the target scan line farther from the corresponding row of pixel units.

[0067] Specifically, such as Figure 4 As shown, for the first row of pixel units, scan lines L_1 and L_2 are both located on the same side of the first row of pixel units, and L_1 is closer to the first row of pixel units than L2.

[0068] The circuit architecture provided in this embodiment, when controlling the two scan lines of the same row of pixel units to be on the same side, can make full use of the adjusted timing and reduce the probability of bright and dark stripes appearing on the display screen.

[0069] In some optional implementations of this embodiment, such as Figure 7 As shown, the circuit also includes a compensation scan line L_0, a compensation scan line, and a first scan line L_1, located on either side of the first row of pixel units in the pixel unit array 401. The distance between the compensation scan line L_0 and the second scan line L_2 in the first preset number of scan lines 402 is greater than the distance between the first scan line L_1 and the second scan line L_2. That is... Figure 7As shown, L_0 is located above the first row of pixel units, and L_1 is located below the first row of pixel units.

[0070] The compensation scan line L_0 is connected to the scan drive module 403. The scan drive module 403 is also used to: in response to starting a scan of the current frame image, first output a scan drive signal to the first scan line in the first preset number of scan lines 402, and then output a scan drive signal to the compensation scan line.

[0071] like Figure 8 The diagram shows the timing of the scan drive signals received by the compensation scan line L_0 and the first preset number of scan lines 402. It can be seen that the scan drive module 403 can output a scan drive signal to L_1 via output line G_0, and output a scan drive signal to L_0 via output line G_1. The scanning order of scan lines L_0 and L_1 is reversed. The compensation scan line L_0 is not connected to any pixel unit; the signal level change on it is only to compensate for the feed voltage from L_1 to the pixel unit it controls.

[0072] Figure 8 As shown in the timing diagram, the rising edge of the scan drive signal on L_0 occurs during the high level period of the signal on L_1, and the falling edge occurs during the high level period of the signal on L_3. Since L_0 is far from the sub-pixel controlled by L_3, it has no effect on the sub-pixel controlled by L_3. Therefore, the scan drive signal on L_0 can reduce the feed voltage from L1 to the pixel unit it controls.

[0073] This embodiment, by setting a compensation scan line, enables all pixel units controlled by the scan line to generate a compensation feed voltage, thereby reducing the difference in feed voltage among all pixel units on the panel and improving the overall display uniformity of the panel.

[0074] In some optional implementations of this embodiment, based on Figure 7 The circuit architecture shown is as follows: Figure 9 As shown, the scan driving module 403 includes an output line switching unit 4031. The output line switching unit 4031 is used to connect the first output line G_1 of the scan driving module 403 to the compensation scan line L_0, connect the 0th output line G_0 of the scan driving module 403 to the first scan line L_1, and connect the nth output line of the scan driving module 403 to the (n+1)th scan line.

[0075] This embodiment, by setting up an output line switching unit, enables flexible adjustment of the timing of the scan drive signals received by all scan lines, including the compensation scan lines, which helps to expand the application scenarios of this circuit.

[0076] In some optional implementations of this embodiment, such as Figure 10 As shown, this illustrates another schematic diagram of the circuit architecture provided in this application. For each row of pixel units, there are two target scan lines, each located on either side of the corresponding row of pixel units.

[0077] Figure 10 The architecture shown can also swap the driving timing of the nth scan line L_n and the (n+1)th scan line L_n+1, that is, first output the scan driving signal to the (n+1)th scan line L_n+1, and then output the scan driving signal to the nth scan line L_n. Here, n is an even number greater than 1.

[0078] In this embodiment, with Figure 5 The timing diagram shown outputs a scan drive signal. The falling edge of L_1 occurs during the high level period of L_3. Since L_1 is relatively far from the sub-pixel controlled by L_3, the influence of signal level changes on L_1 on the feed voltage of the sub-pixel controlled by L_3 can be reduced. The rising edge of L_2 occurs during the high level period of L_3, which can affect ΔV. p3 This generates an upward voltage, reducing ΔV. p3 The absolute value of the input voltage. Similarly, the difference between the absolute values ​​of the input voltages of each column of pixel units will decrease, thereby improving the uniformity of the panel display brightness.

[0079] In some optional implementations of this embodiment, such as Figure 11 As shown, the circuit also includes a second preset number of data lines (including D1-DK).

[0080] Each data line in the second preset number of data lines corresponds to a column of pixel units and is used to transmit display data to the corresponding column of pixel units. Each data line in the second preset number of data lines is connected to at least one corresponding target data line.

[0081] like Figure 11 The circuit architecture shown is an H-type architecture, meaning that a row of pixels is driven by two scan lines, and the same output terminal (including S1-SJ) of the data driver IC is connected to two data lines, outputting different data signals to the two data lines at different times.

[0082] This embodiment implements the pixel scanning drive circuit on an H-type architecture panel, thereby solving the problem of bright and dark stripes on the H-type architecture panel.

[0083] Figure 12 This is a schematic diagram of the structure of a display panel 1200 provided in an embodiment of this application, as shown below. Figure 12As shown, the display panel 1200 specifically includes: a controller 1201, a data driving module 1202, and the aforementioned pixel scan driving circuit 400. The timing controller is connected to the data driving module and the scan driving module in the pixel scan driving circuit. The controller can configure the scan driving module and the data driving module, and control the timing of the output signals.

[0084] The display panel provided in this application embodiment, by applying the above-described pixel scanning driving circuit, can improve the inconsistent coupling during scan line voltage changes caused by the different distances between the pixel electrodes and the scan lines, thereby improving the uniformity of the panel display brightness.

[0085] Figure 13 This is a schematic diagram of the structure of a display device 1300 provided in an embodiment of this application, as shown below. Figure 13 As shown, the display device 1300 includes:

[0086] Display panel 1200, panel frame 1301, power module 1302 and data receiving module 1303;

[0087] The display panel 1200 can be Figure 12 The display panel 1200 is shown. The display panel 1200 is mounted on the panel frame 1301.

[0088] The power supply terminal of the display panel 1200 is connected to the power module 1302, and the signal receiving terminal of the display panel 1200 is connected to the data receiving module 1303.

[0089] The power module 1302 can provide the power required for the operation of the display panel 1200, and the data receiving module 1303 can receive the input data. The display panel 1200 drives the corresponding pixels to display the corresponding colors according to the received data.

[0090] In addition, the display device Figure 13 In addition to the components shown, it may also include a memory for storing data and programs, a processor for running applications, a data transfer bus, and various data interfaces (such as network interfaces and user interfaces).

[0091] The display device provided in this application embodiment, by applying the above-described display panel, can improve the inconsistent coupling during scan line voltage changes caused by the different distances between the pixel electrodes and the scan lines on the panel, thereby improving the uniformity of the panel display brightness.

[0092] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different circuits to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] The steps of the circuits or algorithms described in connection with the embodiments disclosed herein can be implemented in hardware, software modules executed by a processor, or a combination of both. The software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0094] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also mean including the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0095] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A pixel scanning drive circuit, characterized by comprising: The circuit includes: a pixel unit array, a first preset number of scan lines, and a scan driving module; The scanning drive module is connected to the first preset number of scan lines; For each row of pixel units in the pixel unit array, the row of pixel units corresponds to two target scan lines, and the first group of pixel units in the row of pixel units is driven by the first target scan line of the two target scan lines, and the second group of pixel units in the row of pixel units is driven by the second target scan line of the two target scan lines. The scanning drive module is configured to: in response to starting a scan of the current frame image, output a scan drive signal to the first scan line among the first preset number of scan lines; for the nth scan line and the (n+1)th scan line, first output a scan drive signal to the (n+1)th scan line, and then output a scan drive signal to the nth scan line, where n is an even number greater than 1.

2. The circuit according to claim 1, characterized in that, The rising edge of the scan signal on the nth scan line is triggered during the high level period of the scan signal on the (n+1)th scan line; the falling edge of the scan signal on the (n+1)th scan line is triggered during the high level period of the scan signal on the nth scan line.

3. The circuit according to claim 1, characterized in that, The scan driving module includes an output line switching unit, which is used to connect the nth output line of the scan driving module to the (n+1)th scan line.

4. The circuit according to claim 1, characterized in that, The two target scan lines are located on the same side of the corresponding row of pixel units, and the index of the target scan line closer to the corresponding row of pixel units is less than the index of the target scan line farther from the corresponding row of pixel units.

5. The circuit according to claim 4, characterized in that, The circuit also includes a compensation scan line, which and the first scan line are located on both sides of the first row of pixel units in the pixel unit array, and the distance between the compensation scan line and the second scan line in the first preset number of scan lines is greater than the distance between the first scan line and the second scan line. The compensation scan line is connected to the scan driving module, and the scan driving module is further configured to: in response to starting a scan of the current frame image, first output a scan driving signal to the first scan line among the first preset number of scan lines, and then output a scan driving signal to the compensation scan line.

6. The circuit according to claim 5, characterized in that, The scan driving module includes an output line switching unit, which is used to connect the first output line of the scan driving module to the compensation scan line, connect the 0th output line of the scan driving module to the first scan line, and connect the nth output line of the scan driving module to the (n+1)th scan line.

7. The circuit according to claim 1, characterized in that, The two target scan lines are located on either side of the corresponding row of pixel units.

8. The circuit according to claim 1, characterized in that, The circuit also includes a second preset number of data lines; Each data line in the second preset number of data lines corresponds to a column of pixel units and is used to transmit display data to the corresponding column of pixel units; Each of the second preset number of data lines is connected to at least one corresponding target data line.

9. A display panel, characterized in that, include: The controller, the data driving module, and the pixel scanning driving circuit according to any one of claims 1-8, wherein the controller is connected to the data driving module and the scanning driving module in the pixel scanning driving circuit.

10. A display device, characterized in that, include: The display panel, panel frame, power module, and data receiving module as described in claim 9; The display panel is mounted on the panel frame, the power supply terminal of the display panel is connected to the power module, and the signal receiving terminal of the display panel is connected to the data receiving module.

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