Noise reduction circuit and gate drive circuit

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit, and the noise reduction circuit comprises a noise reduction control unit which is used for reducing the noise of a gate under the action of a noise reduction control signal outputted by a noise reduction control end and a voltage on a driving control node, a noise reduction signal is output at the non-scanning time of the scanning stage of the current-stage gate driving module; the noise reduction execution unit is used for carrying out noise reduction processing on the voltage on the driving control node, the driving output end and the stage transmission output end according to the noise reduction signal; the threshold value correction unit is used for enabling a transistor in the noise reduction execution unit to be in a reverse bias state in the blanking stage; according to the noise reduction circuit, the transistor in the noise reduction execution unit is in the reverse bias state in the blanking stage through the threshold correction unit, so that the forward bias state of the transistor in the noise reduction execution unit during noise reduction is counteracted, the problem that the threshold voltage of the noise reduction transistor drifts is solved, and the noise reduction stability of the noise reduction circuit is improved.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of display driving, and particularly relates to a noise reduction circuit and a gate driving circuit. Background Art

[0002] TFT-LCD (Thin-Film Transistor Liquid Crystal Display) realizes image display by controlling the light transmittance of pixels in the display area. Specifically: under the action of an applied voltage, the liquid crystal molecules inside a single pixel are deflected, thereby changing the light transmittance and presenting colors; the display area is composed of pixels arranged in an array, and dynamic display is achieved by switching the pixel states frame by frame.

[0003] GOA (Gate Driver on Array) is a key circuit for TFT-LCD to achieve progressive scanning. However, the noise reduction circuit for noise reduction processing of each key node is the core module for the reliable operation of GOA. However, the noise reduction transistors in the noise reduction circuit are in a forward gate-source voltage (Vgs) bias state for a long time during operation, which easily causes the threshold voltage (Vth) of the noise reduction transistors to drift, resulting in unstable noise reduction and abnormal GOA output signals, affecting the display effect of the display panel.

[0004] Therefore, how to improve the unstable noise reduction caused by the threshold voltage drift of the noise reduction transistors is the problem to be solved currently in the baseband. Summary of the Invention

[0005] Embodiments of the present application provide a noise reduction circuit and a gate driving circuit. The transistors in the noise reduction execution unit are in a reverse bias state during the blanking stage through a threshold correction unit, so as to offset the forward bias state of the transistors in the noise reduction execution unit during noise reduction, improve the problem of the threshold voltage drift of the noise reduction transistors, and improve the noise reduction stability of the noise reduction circuit.

[0006] In a first aspect, an embodiment of the present application provides a noise reduction circuit, which is applied to a gate driving circuit. The gate driving circuit includes N cascaded gate driving modules. The nth gate driving module includes at least a driving control node, a driving output end, a stage transmission output end, and a noise reduction circuit. The noise reduction circuit includes: a noise reduction control unit, a first control end of the noise reduction control unit is connected to a noise reduction control end, and a second control end of the noise reduction control unit is connected to the driving control node, and is configured to output a noise reduction signal during a non-scanning time of a scanning stage of the current-stage gate driving module under the action of a noise reduction control signal output by the noise reduction control end and a voltage on the driving control node; a noise reduction execution unit, a control end of the noise reduction execution unit is connected to an output end of the noise reduction control unit, and an output end of the noise reduction execution unit is respectively connected to the driving control node, the driving output end, and the stage transmission output end, and is configured to perform noise reduction processing on voltages on the driving control node, the driving output end, and the stage transmission output end according to the noise reduction signal; a threshold correction unit, the threshold correction unit is connected to the noise reduction execution unit, and is configured to make a transistor in the noise reduction execution unit in a reverse bias state during a blanking stage.

[0007] Optionally, the noise reduction control unit includes: a first transistor, a control end of the first transistor is connected to the noise reduction control end, and a first end of the first transistor is connected to the control end of the first transistor; a second transistor, a control end of the second transistor is connected to a second end of the first transistor, and a first end of the second transistor is connected to the first end of the first transistor; a third transistor, a control end of the third transistor is connected to the driving control node, a first end of the third transistor is connected to the second end of the first transistor, and a second end of the third transistor is connected to a first low-level end; a fourth transistor, a control end of the fourth transistor is connected to the control end of the third transistor, a first end of the fourth transistor is connected to a second end of the second transistor, and a second end of the fourth transistor is connected to the first low-level end.

[0008] Optionally, the noise reduction execution unit includes: a fifth transistor, a control end of the fifth transistor is connected to an output end of the noise reduction control unit, a first end of the fifth transistor is connected to the driving output end, and a second end of the fifth transistor is connected to a second low-level end; a sixth transistor, a control end of the sixth transistor is connected to the control end of the fifth transistor, a first end of the sixth transistor is connected to the driving control node, and a second end of the sixth transistor is connected to the first low-level end; a seventh transistor, a control end of the seventh transistor is connected to the control end of the fifth transistor, a first end of the seventh transistor is connected to the stage transmission output end, and a second end of the seventh transistor is connected to the second low-level end.

[0009] Optionally, the threshold correction unit includes: an eighth transistor, a control end of the eighth transistor is connected to a control end of the fifth transistor, and a first end of the eighth transistor is connected to the control end of the eighth transistor; a ninth transistor, a control end of the ninth transistor is connected to a second end of the fifth transistor, a first end of the ninth transistor is connected to a second end of the eighth transistor, and a second end of the ninth transistor is connected to a first low level terminal.

[0010] Optionally, the threshold correction unit further includes: a tenth transistor, a control end of the tenth transistor is connected to a second end of the first transistor, a first end of the tenth transistor is connected to the control end of the tenth transistor, and a second end of the tenth transistor is connected to a first end of the ninth transistor.

[0011] Optionally, the threshold correction unit includes: an eighth transistor, a control end of the eighth transistor is connected to a second end of the fifth transistor, and a first end of the eighth transistor is connected to the control end of the fifth transistor; a ninth transistor, a control end of the ninth transistor is connected to a first end of the eighth transistor, a first end of the ninth transistor is connected to a second end of the eighth transistor, and a second end of the ninth transistor is connected to a first low level terminal.

[0012] Optionally, in the scanning stage, the first low level terminal and the second low level terminal output a low level; in the blanking stage, the first low level terminal and the second low level terminal first output a low level and then output a high level.

[0013] Optionally, the threshold correction unit includes: an eighth transistor, a control end of the eighth transistor is connected to a control end of the fifth transistor, and a first end of the eighth transistor is connected to the control end of the eighth transistor; a ninth transistor, a control end of the ninth transistor is connected to a correction power supply terminal, a first end of the ninth transistor is connected to a second end of the eighth transistor, and a second end of the ninth transistor is connected to the first low level terminal.

[0014] Optionally, in the scanning stage, the first low level terminal, the second low level terminal, and the correction power supply terminal output a low level; in the blanking stage, the first low level terminal and the second low level terminal first output a low level and then output a high level, and the correction power supply terminal outputs a high level.

[0015] In a second aspect, an embodiment of the present application provides a gate driving circuit, including N cascaded gate driving modules, and the nth gate driving module includes: a pull-up unit, the pull-up unit is respectively connected to a driving output terminal of the (n - i)th gate driving module and a stage transmission output terminal of the (n - i)th gate driving module; A pull-down unit, where the pull-down unit is connected to the stage transmission output end of the (n + j)-th stage gate driving module, and the pull-down unit is further connected to the pull-up unit through a driving control node; an output unit, where the output unit is respectively connected to a clock signal terminal and the driving control node; a noise reduction circuit, where the noise reduction circuit is respectively connected to the driving control node, the driving output end, and the stage transmission output end of the current stage gate driving module.

[0016] The technical solution provided by the embodiments of the present application has at least the following beneficial effects: In the present application, through the noise reduction signal output by the noise reduction control unit, the noise reduction execution unit performs noise reduction processing on the voltages on the driving control node, the driving output end, and the stage transmission output end during the non-scanning time of the scanning stage of the current stage; through the threshold correction unit, the transistors in the noise reduction execution unit are in a reverse bias state during the blanking stage to offset the forward bias state of the transistors in the noise reduction execution unit during noise reduction, improving the problem of drift in the threshold voltage of the noise reduction transistors and enhancing the noise reduction stability of the noise reduction circuit. Description of the Drawings

[0017] The drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with the present disclosure and used together with the description to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 Shown is a schematic structural diagram of a gate driving module provided by an embodiment of the present application.

[0019] Figure 2 Shown is a schematic circuit diagram of a noise reduction circuit in the related art.

[0020] Figure 3 Shown is a schematic structural diagram of a noise reduction circuit provided by an embodiment of the present application.

[0021] Figure 4 Shown is a schematic circuit diagram of the first noise reduction circuit provided by an embodiment of the present application.

[0022] Figure 5 Shown is a schematic diagram of the first driving timing provided by an embodiment of the present application.

[0023] Figure 6 Shown is a schematic circuit diagram of the second noise reduction circuit provided by an embodiment of the present application.

[0024] Figure 7 Shown is a schematic circuit diagram of the third noise reduction circuit provided by an embodiment of the present application.

[0025] Figure 8 The circuit schematic diagram of the fourth noise reduction circuit provided by the embodiment of the present application is shown as follows.

[0026] Figure 9 The schematic diagram of the second driving timing provided by the embodiment of the present application is shown as follows.

[0027] Explanation of the reference numerals: 100, noise reduction circuit; 110, noise reduction control unit; 120, noise reduction execution unit; 130, threshold correction unit; T1, the first transistor; T2, the second transistor; T3, the third transistor; T4, the fourth transistor; T5, the fifth transistor; T6, the sixth transistor; T7, the seventh transistor; T8, the eighth transistor; T9, the ninth transistor; T10, the tenth transistor; Qn, driving control node; Pn, noise reduction control node; Fn, stage transmission output terminal; Gn, driving output terminal; LC, noise reduction control terminal; VC, correction power supply terminal; VSS1, the first low level terminal; VSS2, the second low level terminal. Detailed implementation manners

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art.

[0029] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present application.

[0030] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted here that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below by referring to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation to the present application.

[0031] It has been found by the inventors of the present application that the gate driving circuit includes N cascaded gate driving modules, such as Figure 1As shown in the figure, the nth - stage gate driving module mainly includes a pull - up unit, a pull - down unit, an output unit, a reset unit, and a noise reduction circuit, etc. The pull - up unit and the pull - down unit generate the voltage at point Q. The pull - up unit and the pull - down unit need to obtain multiple stage - transfer signals from the upper and lower gate driving modules. The voltage at point Q is the turn - on voltage of the output unit, which enables the output unit to output a gate driving signal to provide a turn - on voltage for the display area. The reset unit is used to avoid the influence between frames, and the noise reduction circuit performs noise reduction processing on the signals at each key node. Among them, Qn represents the driving control node of the nth - stage gate driving module, Gn represents the driving output terminal of the nth - stage gate driving module, Fn represents the stage - transfer output terminal of the nth - stage gate driving module, CKn represents the clock signal terminal of the nth - stage gate driving module, Reset represents the reset signal terminal, LC represents the noise reduction control terminal, Gn - 3 represents the driving output terminal of the (n - 3)th - stage gate driving module, Fn - 3 represents the stage - transfer output terminal of the (n - 3)th - stage gate driving module, and Fn + 4 represents the stage - transfer output terminal of the (n + 4)th - stage gate driving module.

[0032] The normal output of the gate driving module is a necessary condition to ensure the normal display of the picture. Therefore, the noise suppression effect of the noise reduction circuit on the signal is particularly important. Figure 2 The following is a circuit schematic diagram of the noise reduction circuit in the related art. The first transistor T1 and the second transistor T2 are control transistors, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all noise reduction transistors. When the driving control node (i.e., point Q) in the nth - stage gate driving module is at a low level, the noise reduction control terminal LC continuously outputs a high level. At this time, the first transistor T1 is turned on, and the second transistor T2 is turned off, making the noise reduction control node Pn at a high level, and respectively turning on the third transistor T3, the fourth transistor T4, and the fifth transistor T5, so as to continuously pull down the signals on the driving output terminal Gn, the driving control node Qn, and the stage - transfer output terminal Fn, achieving noise reduction processing on each important node in the gate driving module. Since the driving output terminal, the driving control node, and the stage - transfer output terminal in each stage of the gate driving module are not noise - reduced only during the scanning time of the current stage, and the other time is the noise reduction processing time period. Therefore, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 in the noise reduction circuit need to be in a forward gate - source voltage bias state for a long time, which easily causes the problem of threshold voltage (Vth) drift of the noise reduction transistors, and further leads to abnormal output signals of the GOA circuit, affecting the display effect of the display panel.

[0033] In order to improve the problem of threshold voltage drift of the noise reduction transistors, this application provides a noise reduction circuit, which specifically includes the following embodiments: Figure 3 The following is a structural schematic diagram of a noise reduction circuit provided by an embodiment of this application. The noise reduction circuit 100 of this embodiment is applied to a gate driving circuit, and the gate driving circuit includes N cascaded gate driving modules. AsFigure 1 As shown, each level of the gate driving module includes at least a driving control node Qn, a driving output terminal Gn, a stage transmission output terminal Fn, and a noise reduction circuit 100.

[0034] As Figure 3 shown, the noise reduction circuit 100 includes: a noise reduction control unit 110. The first control end of the noise reduction control unit 110 is connected to the noise reduction control end LC, and the second control end of the noise reduction control unit 110 is connected to the driving control node Qn, and is used to output a noise reduction signal during the non-scanning time of the scanning stage of the current level of the gate driving module under the action of the noise reduction control signal output by the noise reduction control end LC and the voltage on the driving control node Qn.

[0035] It should be noted that in the driving technology of the display panel, the scanning stage and the blanking stage are key points in the timing control. The two jointly ensure the correct update of pixel data and the stability of the display. The scanning stage is the stage where the gate driving circuit activates pixels row by row and writes data. For example, in a display with progressive scanning, the gate driving signal will sequentially select each row of pixels from top to bottom, and write the voltage signal into the pixel unit of that row through the data line. The blanking stage is the "interval period" between scans. At this time, the driving circuit stops writing data, which is used to switch rows or frames to prevent signal overlap from causing display disorders.

[0036] In this embodiment, under the combined action of the noise reduction control signal output by the noise reduction control end LC and the voltage on the driving control node Qn, the noise reduction control unit 110 in the nth level of the gate driving module outputs a noise reduction signal during the non-scanning time period of the scanning stage of the nth level of the gate driving module, and does not output a noise reduction control signal during the scanning time period of the nth level of the gate driving module.

[0037] In this embodiment, the noise reduction circuit 100 further includes a noise reduction execution unit 120. The control end of the noise reduction execution unit 120 is connected to the output end of the noise reduction control unit 110, and the output end of the noise reduction execution unit 120 is respectively connected to the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn, and is used to perform noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn according to the noise reduction signal.

[0038] It should be noted that in this embodiment, noise reduction processing is performed on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn according to the noise reduction signal. That is to say, the noise reduction execution unit 120 continuously pulls down the signals on the driving output terminal Gn, the driving control node Qn, and the stage transmission output terminal Fn to avoid display anomalies such as pixel mischarging caused by leakage current or other transistor abnormalities in the circuit causing the voltages on the driving output terminal Gn, the driving control node Qn, or / and the stage transmission output terminal Fn to be at a high level.

[0039] In this embodiment, the noise reduction circuit 100 further includes a threshold correction unit 130. The threshold correction unit 130 is connected to the noise reduction execution unit 120 and is configured to make the transistors in the noise reduction execution unit 120 in a reverse bias state during the blanking stage.

[0040] It should be noted that according to the working principle of the gate driving module, as long as the noise reduction control unit 110 outputs a noise reduction signal, the noise reduction execution unit 120 will perform noise reduction processing on the corresponding important nodes. Also, since the driving output terminal Gn, the driving control node Qn, and the stage transmission output terminal Fn in each stage of the gate driving module are not subjected to noise reduction only during the scanning time of the current stage, and the other times are all noise reduction processing time periods. Therefore, the transistors in the noise reduction execution unit 120 need to be in a working state for a long time (i.e., a forward gate-source voltage bias state), which easily causes the problem of drift of the threshold voltage (Vth) of the noise reduction transistors, and further leads to abnormal output signals of the gate driving circuit, affecting the display effect of the display panel. However, in this embodiment, the threshold correction unit 130 makes the transistors in the noise reduction execution unit 120 in a reverse bias state during the blanking stage to offset the forward bias state of the transistors in the noise reduction execution unit 120 during the non-scanning time periods of the scanning stage, and avoid the problem of drift of the threshold voltage of the noise reduction transistors.

[0041] It can be seen from this that through the noise reduction signal output by the noise reduction control unit 110 of the present application, the noise reduction execution unit 120 performs noise reduction processing on the voltages on the driving control node Qn, the driving output terminal Gn, and the stage transmission output terminal Fn during the non-scanning time of the scanning stage of the current stage. Through the threshold correction unit 130, the transistors in the noise reduction execution unit 120 are in a reverse bias state during the blanking stage to offset the forward bias state of the transistors in the noise reduction execution unit 120 during noise reduction, improving the problem of drift of the threshold voltage of the noise reduction transistors and enhancing the noise reduction stability of the noise reduction circuit 100.

[0042] Figure 4 The following shows a circuit schematic diagram of the first noise reduction circuit provided by an embodiment of the present application, as Figure 4As shown in the figure, the noise reduction control unit 110 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. Among them, the control terminal of the first transistor T1 is connected to the noise reduction control terminal LC, and the first terminal of the first transistor T1 is connected to the control terminal of the first transistor T1; the control terminal of the second transistor T2 is connected to the second terminal of the first transistor T1, and the first terminal of the second transistor T2 is connected to the first terminal of the first transistor T1; the control terminal of the third transistor T3 is connected to the drive control node Qn, the first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, and the second terminal of the third transistor T3 is connected to the first low-level terminal VSS1; the control terminal of the fourth transistor T4 is connected to the control terminal of the third transistor T3, the first terminal of the fourth transistor T4 is connected to the second terminal of the second transistor T2, and the second terminal of the fourth transistor T4 is connected to the first low-level terminal VSS1.

[0043] Optionally, in the scanning stage, the first low-level terminal VSS1 and the second low-level terminal VSS2 output low levels; in the blanking stage, the first low-level terminal VSS1 and the second low-level terminal VSS2 first output low levels and then output high levels.

[0044] It should be noted that the main purpose of the noise reduction control unit 110 in this embodiment is to invert the voltage on the drive control node Qn, that is: when the voltage on the drive control node Qn is high, the noise reduction control unit 110 outputs a low level, and when the voltage on the drive control node Qn is low, the noise reduction control unit 110 outputs a high level; hereby combined with Figure 5 the timing diagram, the specific working principle of the noise reduction control unit 110 is elaborated: (1) When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type MOS transistors, the noise reduction control terminal LC outputs a high level continuously during the scanning stage, and the first transistor T1 is continuously turned on; as Figure 5 shown, the scanning stage is divided into time periods t1, t2, and t3, and the blanking stage is divided into time periods t4, t5, and t6.

[0045] (2) During the scanning time (t2) of the current-stage gate drive module, the voltage on the drive control node Qn is high, and the third transistor T3 and the fourth transistor T4 are turned on simultaneously, so that the voltages on the node An and the noise reduction control node Pn are both the first low level output by the first low-level terminal VSS1, thereby turning off the second transistor T2, and the noise reduction control unit 110 outputs the first low level; as Figure 5 shown, during the scanning stage, the first low-level terminal VSS1 outputs the first low level, and the voltage on the noise reduction control node Pn is also the first low level.

[0046] (3) During the non-scanning time (t1 and t3) of the scanning stage of the current-stage gate driving module, the voltage on the driving control node Qn is at a low level, and at the same time, the third transistor T3 and the fourth transistor T4 are turned off, so that the voltage on the node An is at a high level, thereby turning on the second transistor T2, and the noise reduction control unit 110 outputs a high level, that is, a noise reduction signal; as Figure 5 shown, during the time periods t1 and t3 of the scanning stage, the noise reduction signal on the noise reduction control node Pn is at a high level.

[0047] Additionally, it should be noted that the above description of the working principle is based on the example that the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all N-type MOS transistors. When the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are P-type transistors, the working principle is the same but the driving timing is opposite, so it will not be elaborated here.

[0048] As Figure 4 shown, the noise reduction execution unit 120 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; wherein, the control end of the fifth transistor T5 is connected to the output end of the noise reduction control unit 110, the first end of the fifth transistor T5 is connected to the driving output end Gn, and the second end of the fifth transistor T5 is connected to the second low-level end VSS2; the control end of the sixth transistor T6 is connected to the control end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the driving control node Qn, and the second end of the sixth transistor T6 is connected to the first low-level end VSS1; the control end of the seventh transistor T7 is connected to the control end of the fifth transistor T5, the first end of the seventh transistor T7 is connected to the stage transmission output end Fn, and the second end of the seventh transistor T7 is connected to the second low-level end VSS2.

[0049] It should be noted that here, taking the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 as N-type MOS transistors as an example, the working principle of the noise reduction execution unit 120 is described in detail: (1) When the noise reduction control unit 110 outputs a noise reduction signal, that is, the voltage on the noise reduction control node Pn is at a high level, at the same time, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned on, so that the voltage on the driving output end Gn is pulled down to the second low level through the turned-on fifth transistor T5, the voltage on the driving control node Qn is pulled down to the first low level through the turned-on sixth transistor T6, and the voltage on the stage transmission output end Fn is pulled down to the first low level through the turned-on seventh transistor T7; as Figure 5As shown, during the scanning phase, the clock signal terminal CK outputs a clock signal, and the first low-level terminal VSS1 and the second low-level terminal VSS2 respectively output a first low level and a second low level; in addition, the voltage values of the first low level and the second low level can be the same or different; optionally, by respectively adjusting the voltage values of the first low level and the second low level, the leakage current of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be reduced, and the stability of the voltage on the noise reduction control node Pn can be improved.

[0050] (2) When the noise reduction control unit 110 does not output a noise reduction signal, that is, the voltage on the noise reduction control node Pn is at a low level, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are simultaneously turned off, and the noise reduction process of the voltages on the drive control node Qn, the drive output terminal Gn, and the stage transmission output terminal Fn is stopped.

[0051] As Figure 4 shown, the threshold correction unit 130 includes an eighth transistor T8 and a ninth transistor T9. The control terminal of the eighth transistor T8 is connected to the control terminal of the fifth transistor T5, and the first terminal of the eighth transistor T8 is connected to the control terminal of the eighth transistor T8; the control terminal of the ninth transistor T9 is connected to the second terminal of the fifth transistor T5, the first terminal of the ninth transistor T9 is connected to the second terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9 is connected to the first low-level terminal VSS1.

[0052] It should be noted that during the blanking phase, if the noise reduction control node Pn is at a low level and the first low-level terminal VSS1 and the second low-level terminal VSS2 are at a high level, the transistors in the noise reduction execution unit 120 can be made to be in a reverse bias state, achieving the purpose of reverse correction of the threshold voltage; here, taking the eighth transistor T8 and the ninth transistor T9 as N-type MOS transistors as an example, combined with Figure 5 the timing diagram to make a detailed description of the specific working principle of the threshold correction unit 130: (1) During the t4 period of the blanking phase, the noise reduction control terminal LC is pulled down from a high level to a low level, causing the noise reduction control unit 110 to stop outputting current to the noise reduction control terminal LC; (2) During the t5 period of the blanking phase, the second low-level terminal VSS2 is controlled to output a high level, and the first low-level terminal VSS1 remains at a low potential. At this time, the noise reduction control terminal LC is also at a high potential, so the eighth transistor T8 and the ninth transistor T9 are both turned on, causing the high potential on the noise reduction control terminal LC to be released to the first low-level terminal VSS1 by the turned-on eighth transistor T8 and ninth transistor T9, thereby causing the voltage of the noise reduction control node Pn to turn to a low level; (3) During the t6 period of the blanking stage, control the first low-level terminal VSS1 and the second low-level terminal VSS2 to both output high levels. At this time, the second terminals of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all at high levels, and the control terminals of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all at low levels, realizing that the transistors in the noise reduction execution unit 120 (abbreviated as noise reduction transistors) are in a reverse bias state, and this reverse bias state is maintained until the start of the next frame.

[0053] It can be seen from this that from the timing of each signal in the scanning stage and the blanking stage, it shows that in this embodiment, without affecting the original control logic, the threshold voltage of the noise reduction transistor is reversely corrected during the blanking stage; optionally, to further improve the correction effect of the threshold voltage, the time ratio of the blanking stage can be increased without affecting the display effect.

[0054] Figure 6 The following shows the circuit schematic diagram of the second noise reduction circuit provided by the embodiment of the present application; Figure 6 The shown noise reduction circuit 100 is the same as the Figure 4 circuit structures of the noise reduction control unit 110 and the noise reduction execution unit 120 therein, and the only difference lies in the connection manner of two transistors in the threshold correction unit 130; as Figure 6 shown, the threshold correction unit 130 includes an eighth transistor T8 and a ninth transistor T9; the control terminal of the eighth transistor T8 is connected to the second terminal of the fifth transistor T5, and the first terminal of the eighth transistor T8 is connected to the control terminal of the fifth transistor T5; the control terminal of the ninth transistor T9 is connected to the first terminal of the eighth transistor T8, the first terminal of the ninth transistor T9 is connected to the second terminal of the eighth transistor T8, and the second terminal of the ninth transistor T9 is connected to the first low-level terminal VSS1.

[0055] It should be noted that Figure 6 and Figure 4 have the same control logic, both based on the Figure 5 timing diagram. The working principle of the threshold correction unit 130 in this embodiment is as follows: (1) During the t4 period of the blanking stage, the noise reduction control terminal LC is pulled down from a high level to a low level, causing the noise reduction control unit 110 to stop outputting current to the noise reduction control node Pn; (2) During the t5 period of the blanking stage, control the second low-level terminal VSS2 to output a high level, and keep the first low-level terminal VSS1 at a low potential. At this time, the noise reduction control node Pn is also at a high potential. Therefore, both the eighth transistor T8 and the ninth transistor T9 are turned on, so that the high potential on the noise reduction control node Pn is released to the first low-level terminal VSS1 by the turned-on eighth transistor T8 and ninth transistor T9, thereby turning the voltage of the noise reduction control node Pn into a low level; (3) During the t6 period of the blanking stage, control both the first low-level terminal VSS1 and the second low-level terminal VSS2 to output high levels. At this time, the second ends of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all at high levels, and the control ends of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all at low levels, realizing that the transistors in the noise reduction execution unit 120 (referred to as noise reduction transistors) are in a reverse bias state, and this reverse bias state is maintained until the start of the next frame.

[0056] Figure 7 The figure shows a circuit schematic diagram of a third noise reduction circuit provided by an embodiment of the present application; Figure 7 The shown noise reduction circuit 100 is Figure 4 On the basis of the shown noise reduction circuit 100, a tenth transistor T10 is added; the specific structure is as Figure 7 shown. The threshold correction unit 130 includes an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; the control end of the eighth transistor T8 is connected to the control end of the fifth transistor T5, and the first end of the eighth transistor T8 is connected to the control end of the eighth transistor T8; the control end of the ninth transistor T9 is connected to the second end of the fifth transistor T5, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is connected to the first low-level terminal VSS1; the control end of the tenth transistor T10 is connected to the second end of the first transistor T1, the first end of the tenth transistor T10 is connected to the control end of the tenth transistor T10, and the second end of the tenth transistor T10 is connected to the first end of the ninth transistor T9.

[0057] It should be noted that Figure 7 and Figure 4 have the same control logic, and both are based on the timing diagram of Figure 5 ; during Figure 5During time periods t1 and t3, the potential logics of node An and noise reduction control node Pn in the noise reduction control unit 110 are the same, that is, both are high levels; at this time, the tenth transistor T10 is turned on by the high potential on node An, thereby raising the potential of node Kn, and further reducing the drain-source voltage of the eighth transistor T8, so as to achieve the purpose of reducing the leakage current on the noise reduction control node Pn, so that the noise reduction control node Pn is not affected by the leakage of the eighth transistor T8 and the ninth transistor T9 during the scanning stage.

[0058] Figure 8 The figure shows a circuit schematic diagram of a fourth noise reduction circuit provided by an embodiment of the present application; Figure 8 The shown noise reduction circuit 100 and Figure 4 The circuit structures of the noise reduction control unit 110 and the noise reduction execution unit 120 in are the same, and the difference is only in the control mode of the ninth transistor T9 in the threshold correction unit 130; as Figure 8 shown, the threshold correction unit 130 includes an eighth transistor T8 and a ninth transistor T9; the control end of the eighth transistor T8 is connected to the control end of the fifth transistor T5, and the first end of the eighth transistor T8 is connected to the control end of the eighth transistor T8; the control end of the ninth transistor T9 is connected to the correction power supply terminal VC, the first end of the ninth transistor T9 is connected to the second end of the eighth transistor T8, and the second end of the ninth transistor T9 is connected to the first low level terminal VSS1.

[0059] Optionally, during the scanning stage, the first low level terminal VSS1, the second low level terminal VSS2 and the correction power supply terminal VC output low levels; during the blanking stage, the first low level terminal VSS1 and the second low level terminal VSS2 first output low levels and then output high levels, and the correction power supply terminal VC outputs high levels.

[0060] It should be noted that in this embodiment, Figure 4 On the basis of, a correction power supply terminal VC is added to replace the second low level terminal VSS2 connected to the control end of the ninth transistor T9; the main purpose is that when the control correction power supply terminal VC is at a low level, its voltage can be less than or equal to the first low level output by the first low level terminal VSS1, so that the gate-source voltage of the ninth transistor T9 is less than or equal to 0, and further the leakage of the ninth transistor T9 can be reduced; Figure 8 The control logic of is as Figure 9 shown: (1) During the scanning stage (t1, t2, t3), control the clock signal terminal CK to output a clock signal, control the first low level terminal VSS1, the second low level terminal VSS2 and the correction power supply terminal VC to output the first low level, the second low level and the third low level respectively, and the third low level is less than or equal to the first low level, so as to ensure the turn-off effect of the ninth transistor T9 during time periods t1 and t3 and avoid leakage current on the noise reduction control node Pn.

[0061] (2) During the t4 period of the blanking stage, control the first low-level terminal VSS1 and the second low-level terminal VSS2 to maintain a low potential, while the corrected power supply terminal VC outputs a high level, so that the voltage on the noise reduction control node Pn is pulled down to the first low level through the turned-on eighth transistor T8 and ninth transistor T9.

[0062] (3) During the t5 period of the blanking stage, control both the first low-level terminal VSS1 and the second level terminal to output a high level, so that the fifth transistor T5, sixth transistor T6, and seventh transistor T7 in the noise reduction execution unit 120 are in a reverse bias state, realizing the reverse correction of the threshold voltage of the noise reduction transistor.

[0063] In summary, the noise reduction circuit provided by the present application, without affecting the control logic of the noise reduction control unit and the noise reduction execution unit, realizes the purpose of reverse biasing the noise reduction transistor in the blanking stage through the threshold correction units of multiple embodiments, so as to delay or offset the threshold voltage drift caused by the forward biasing in the scanning stage, and avoid the abnormal driving of the gate driving circuit due to the decrease in the noise reduction ability.

[0064] In an embodiment, the present application provides a gate driving circuit, which includes N cascaded gate driving modules. The nth gate driving module includes: a pull-up unit, a pull-down unit, an output unit, and a noise reduction circuit. The pull-up unit is respectively connected to the driving output terminal of the (n - i)th gate driving module and the stage transmission output terminal of the (n - i)th gate driving module; the pull-down unit is connected to the stage transmission output terminal of the (n + j)th gate driving module, and the pull-down unit is also connected to the pull-up unit through a driving control node; the output unit is respectively connected to the clock signal terminal and the driving control node; the noise reduction circuit is respectively connected to the driving control node, the driving output terminal, and the stage transmission output terminal of the current-stage gate driving module.

[0065] It should be noted that the specific structure of the gate driving module provided in this embodiment is as Figure 1 shown. The working principle of the gate driving module was described above by taking i = 3 and j = 4 as examples, and will not be elaborated here.

[0066] In addition, the terms "first", "second", "third", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0067] In the description of this specification, the descriptions referring to the terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0068] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and the specification of the present application shall fall within the scope covered by the patent of the present application.

Claims

1. A noise reduction circuit, characterized in that, Applied to a gate driving circuit, the gate driving circuit includes N cascaded gate driving modules. The nth - stage gate driving module includes at least a driving control node, a driving output terminal, a stage transmission output terminal, and a noise reduction circuit. The noise reduction circuit includes: A noise reduction control unit. The first control end of the noise reduction control unit is connected to a noise reduction control terminal, and the second control end of the noise reduction control unit is connected to the driving control node. It is used to output a noise reduction signal during the non - scanning time of the scanning stage of the current - stage gate driving module under the action of the noise reduction control signal output from the noise reduction control terminal and the voltage on the driving control node. A noise reduction execution unit. The control end of the noise reduction execution unit is connected to the output end of the noise reduction control unit, and the output end of the noise reduction execution unit is respectively connected to the driving control node, the driving output terminal, and the stage transmission output terminal. It is used to perform noise reduction processing on the voltages on the driving control node, the driving output terminal, and the stage transmission output terminal according to the noise reduction signal. A threshold correction unit. The threshold correction unit is connected to the noise reduction execution unit and is used to make the transistors in the noise reduction execution unit in a reverse - biased state during the blanking stage.

2. The noise reduction circuit according to claim 1, wherein The noise reduction control unit includes: A first transistor. The control end of the first transistor is connected to the noise reduction control terminal, and the first end of the first transistor is connected to the control end of the first transistor. A second transistor. The control end of the second transistor is connected to the second end of the first transistor, and the first end of the second transistor is connected to the first end of the first transistor. A third transistor. The control end of the third transistor is connected to the driving control node, the first end of the third transistor is connected to the second end of the first transistor, and the second end of the third transistor is connected to a first low - level terminal. A fourth transistor. The control end of the fourth transistor is connected to the control end of the third transistor, the first end of the fourth transistor is connected to the second end of the second transistor, and the second end of the fourth transistor is connected to the first low - level terminal.

3. The noise reduction circuit according to claim 2, wherein The noise reduction execution unit includes: A fifth transistor. The control end of the fifth transistor is connected to the output end of the noise reduction control unit, the first end of the fifth transistor is connected to the driving output terminal, and the second end of the fifth transistor is connected to a second low - level terminal. A sixth transistor. The control end of the sixth transistor is connected to the control end of the fifth transistor, the first end of the sixth transistor is connected to the driving control node, and the second end of the sixth transistor is connected to the first low - level terminal. A seventh transistor. The control end of the seventh transistor is connected to the control end of the fifth transistor, the first end of the seventh transistor is connected to the stage transmission output terminal, and the second end of the seventh transistor is connected to the second low - level terminal.

4. The noise reduction circuit according to claim 3, wherein The threshold correction unit includes: An eighth transistor. The control end of the eighth transistor is connected to the control end of the fifth transistor, and the first end of the eighth transistor is connected to the control end of the eighth transistor. A ninth transistor, a control end of the ninth transistor is connected to a second end of the fifth transistor, a first end of the ninth transistor is connected to a second end of the eighth transistor, and a second end of the ninth transistor is connected to a first low-level end.

5. The noise reduction circuit according to claim 4, wherein The threshold correction unit further includes: A tenth transistor, a control end of the tenth transistor is connected to a second end of the first transistor, a first end of the tenth transistor is connected to the control end of the tenth transistor, and a second end of the tenth transistor is connected to the first end of the ninth transistor.

6. The noise reduction circuit according to claim 3, wherein The threshold correction unit includes: An eighth transistor, a control end of the eighth transistor is connected to a second end of the fifth transistor, and a first end of the eighth transistor is connected to a control end of the fifth transistor; A ninth transistor, a control end of the ninth transistor is connected to a first end of the eighth transistor, a first end of the ninth transistor is connected to a second end of the eighth transistor, and a second end of the ninth transistor is connected to a first low-level end.

7. The noise reduction circuit according to any one of claims 4-6, wherein In a scanning stage, the first low-level end and the second low-level end output low levels; In a blanking stage, the first low-level end and the second low-level end first output low levels and then output high levels.

8. The noise reduction circuit according to claim 3, wherein The threshold correction unit includes: An eighth transistor, a control end of the eighth transistor is connected to a control end of the fifth transistor, and a first end of the eighth transistor is connected to the control end of the eighth transistor; A ninth transistor, a control end of the ninth transistor is connected to a correction power supply end, a first end of the ninth transistor is connected to a second end of the eighth transistor, and a second end of the ninth transistor is connected to the first low-level end.

9. The noise reduction circuit according to claim 8, wherein In a scanning stage, the first low-level end, the second low-level end, and the correction power supply end output low levels; In a blanking stage, the first low-level end and the second low-level end first output low levels and then output high levels, and the correction power supply end outputs a high level.

10. A gate driving circuit includes N cascaded gate driving modules, characterized in that, The nth-stage gate driving module includes: A pull-up unit, the pull-up unit is respectively connected to a driving output end of the (n-i)th-stage gate driving module and a stage transmission output end of the (n-i)th-stage gate driving module; A pull-down unit, the pull-down unit is connected to a stage transmission output end of the (n+j)th-stage gate driving module, and the pull-down unit is further connected to the pull-up unit through a driving control node; An output unit, the output unit is respectively connected to a clock signal end and the driving control node; The noise reduction circuit according to any one of claims 1-9, the noise reduction circuit is respectively connected to a driving control node, a driving output end, and a stage transmission output end of the current-stage gate driving module.

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