Target detection methods, devices, electronic equipment, and media based on FPGA chips

By leveraging the heterogeneous computing architecture of FPGA chips and improved network structure, and utilizing the collaborative work of the processor system and programmable logic, the problem of high power consumption in target detection networks was solved, achieving low-power target detection.

CN120375158BActive Publication Date: 2026-05-26LANZHOU UNIV
View PDF 2 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
LANZHOU UNIV
Filing Date
2025-03-26
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

Existing object detection networks consume a lot of computational resources and consume a lot of power during convolution calculations, making them difficult to deploy effectively on power-constrained devices.

Method used

Using a heterogeneous computing architecture based on FPGA chips, the processor system obtains the network layer information of the target network model and sends convolution operation instructions to the programmable logic part. The programmable logic part performs convolution operations, and combined with improved network structures such as depthwise separable convolution and average pooling layers, target detection is achieved.

Benefits of technology

It achieves low-power target detection, reduces the consumption of computing resources, and is suitable for power-constrained devices.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN120375158B_ABST
    Figure CN120375158B_ABST
Patent Text Reader

Abstract

This application discloses a target detection method, apparatus, electronic device, and medium based on an FPGA chip. The method includes: a processor system sending corresponding convolution operation instructions to a programmable logic unit (PLU) based on the network layer information of the target network model; the PLU obtaining an initial feature map corresponding to the image to be detected based on the convolution operation instructions; performing convolution operations on the initial feature map using the network layers to obtain a convolution-processed target feature map; and the processor system determining the target detection box in the image to be detected based on the target feature map. This application achieves a low-power target detector by utilizing the cooperation between the programmable logic unit and the processor system unit within the FPGA chip, leveraging the low-power characteristics of the programmable logic unit and the flexibility of the processor system unit in data configuration.
Need to check novelty before this filing date? Find Prior Art