System and method for Feiteng CPU to simulate X86 to clear BIOS configuration

Abstract

The invention discloses a system and a method for simulating X86 to clear BIOS (Basic Input / Output System) configuration by a Feiteng CPU (Central Processing Unit), and the system for simulating X86 to clear BIOS configuration by the Feiteng CPU. Comprising a GD32 single-chip microcomputer, a clear button, a first analog switch MA1, a first analog switch MB1, a first analog switch MC1, a second analog switch MA2, a second analog switch MB2, a second analog switch MC3, a first BIOS chip, a second BIOS chip, a third BIOS chip, an RTC chip, a Feiteng CPU, a first load switch, a button cell and a second load switch, and the Feiteng CPU is connected with the RTC chip through an IIC bus. The RTC chip is connected with one end of the first load switch, the other end of the first load switch is used for being connected with a P3V3STBY voltage end, the negative electrode of the button battery is grounded, and the positive electrode of the button battery is connected with the RTC chip through the second load switch; time information in the RTC chip can be cleared without dismounting a button cell, BIOS configuration information can be cleared by simulating X86 one key, the cost is low, and operation is convenient; the whole method is simple, fast and low in cost.

Description

Technical Field

[0001] The present invention relates to the technical field of a system for a Feiteng CPU to simulate X86 to clear BIOS configuration, and in particular to a system and method for a Feiteng CPU to simulate X86 to clear BIOS configuration. Background Art

[0002] As Figure 1 shown, in an X86 device, BIOS configuration information is stored in the CMOS circuit inside the CPU of the X86 device. If you want to clear the BIOS configuration, you only need to remove the battery and short the clear bios pin to ground to clear all BIOS configuration information.

[0003] In ARM devices such as Feiteng, the time information in the BIOS configuration information is stored in the RTC chip and can be cleared by removing the battery, but other BIOS configuration information located in the BIOS chip cannot be cleared.

[0004] Currently, the common method for a Feiteng device to clear the BIOS configuration is as follows:

[0005] 1. Remove the battery to clear the RTC time. At that time, in order to prevent the system time from being accidentally cleared due to vibration, the existing button battery is usually glued. If you want to remove the button battery, you need to remove the glue, and re-installation also requires gluing, which is laborious and troublesome.

[0006] 2. Remove the BIOS chip and burn a new BIOS on a dedicated programmer. However, the BIOS chip needs to be burned on a dedicated programmer, and the dedicated programmer is generally expensive and not available to everyone.

[0007] Therefore, in this patent application of the present invention, the applicant has carefully studied a system and method for a Feiteng CPU to simulate X86 to clear the BIOS configuration to solve the above problems. Summary of the Invention

[0008] Aiming at the deficiencies of the above-mentioned prior art, the main purpose of the present invention is to provide a system and method for a Feiteng CPU to simulate X86 to clear the BIOS configuration, which can realize clearing the time information inside the RTC chip without removing the button battery, and also realize simulating X86 to clear the BIOS configuration information with low cost and convenient operation; the whole method is simple, fast and low-cost.

[0009] To achieve the above purpose, the present invention adopts the following technical solutions:

[0010] A system for a Feiteng CPU to simulate X86 to clear BIOS configuration, including a GD32 single-chip microcomputer, a clear button, a first analog switch MA1, a first analog switch MB1, a first analog switch MC1, a second analog switch MA2, a second analog switch MB2, a second analog switch MC3, a first BIOS chip, a second BIOS chip, a third BIOS chip, an RTC chip, a Feiteng CPU, a first load switch, a button battery, and a second load switch;

[0011] The clear button is connected to the GD32 single-chip microcomputer, and the GD32 single-chip microcomputer controls the connection of the first load switch, the second load switch, the first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 through control signals to control the opening and closing states of the corresponding load switch and the corresponding analog switch after the clear button is pressed;

[0012] The GD32 single-chip microcomputer is connected to one end of the first analog switch MA1 through the first SPI bus, the other end of the first analog switch MA1 is connected to the first BIOS chip, and the first BIOS chip is connected to one end of the second analog switch MA2; the first BIOS chip, the second BIOS chip, and the third BIOS chip all store the BIOS content of the initial configuration; the GD32 single-chip microcomputer is connected to one end of the second analog switch MB1 through the second SPI bus, the other end of the second analog switch MB1 is connected to the second BIOS chip, and the second BIOS chip is connected to one end of the second analog switch MB2;

[0013] The GD32 single-chip microcomputer is connected to one end of the third analog switch MC1 through the third SPI bus, the other end of the third analog switch MC1 is connected to the third BIOS chip, and the third BIOS chip is connected to one end of the second analog switch MC3; the other ends of the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are jointly connected to the Feiteng CPU through the QSPI bus;

[0014] The Feiteng CPU is connected to the RTC chip through the IIC bus, the RTC chip is connected to one end of the first load switch, the other end of the first load switch is used to connect to the P3V3_STBY voltage terminal, the negative electrode of the button battery is grounded, and the positive electrode of the button battery is connected to the RTC chip through the second load switch.

[0015] As a preferred solution, the first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are all analog switches with a signal bandwidth greater than 200KHZ.

[0016] As a preferred solution, it further includes a first status display lamp for displaying the current connection status of the GD32 single-chip microcomputer to the first BIOS chip, a second status display lamp for displaying the current connection status of the GD32 single-chip microcomputer to the second BIOS chip, and a third status display lamp for displaying the current connection status of the GD32 single-chip microcomputer to the third BIOS chip;

[0017] The first status display lamp, the second status display lamp, and the third status display lamp are respectively connected to the GD32 single-chip microcomputer.

[0018] As a preferred solution, it further includes a fourth status display lamp for indicating that the BIOS configuration has been successfully cleared, and the fourth status display lamp is connected to the GD32 single-chip microcomputer.

[0019] A method for a Feiteng CPU to simulate X86 to clear the BIOS configuration, which is based on the system for the Feiteng CPU to simulate X86 to clear the BIOS configuration; includes the following steps:

[0020] Power on the system, and by default, the first load switch and the second load switch are in the closed state;

[0021] Step S1, control all analog switches other than a second analog switch connected to the corresponding one BIOS chip currently used by the Feiteng CPU to the off state, where the BIOS chip currently used by the Feiteng CPU is defined as the current BIOS chip;

[0022] Step S2, long press the clear button to control both the first load switch and the second load switch to the off state and maintain for a preset time;

[0023] Step S3, control a second analog switch connected to the current BIOS chip to the off state;

[0024] Step S4, control any one of the other two second analog switches to the on state to switch the Feiteng CPU to use any one of the other two non-current BIOS chips. At the same time, control the two first analog switches that were in the off state in Step S1 and not connected to the current BIOS chip to the on state, and the GD32 single-chip microcomputer updates the initially configured BIOS content in the other non-current BIOS chip to the current BIOS chip through the corresponding SPI bus;

[0025] Step S5, control both the first load switch and the second load switch to the on state, that is, complete one BIOS configuration clearing.

[0026] As a preferred solution, the Feiteng CPU X86-simulating BIOS configuration clearing system further includes a first status display lamp for displaying the current connection of the GD32 single-chip microcomputer to the first BIOS chip, a second status display lamp for displaying the current connection of the GD32 single-chip microcomputer to the second BIOS chip, and a third status display lamp for displaying the current connection of the GD32 single-chip microcomputer to the third BIOS chip;

[0027] The first status display lamp, the second status display lamp, and the third status display lamp are respectively connected to the GD32 single-chip microcomputer;

[0028] In step S4, after the Feiteng CPU switches to use any one of the other two non-current BIOS chips, the corresponding status display lamp is lit to display the corresponding BIOS chip currently connected by the GD32 single-chip microcomputer.

[0029] As a preferred solution, the Feiteng CPU X86-simulating BIOS configuration clearing system further includes a fourth status display lamp for indicating that the BIOS configuration has been successfully cleared, and the fourth status display lamp is connected to the GD32 single-chip microcomputer;

[0030] In step S5, after a BIOS configuration clearing is completed, the fourth status display lamp is lit.

[0031] Compared with the prior art, the present invention has obvious advantages and beneficial effects. Specifically, it mainly realizes the clearing of the time information inside the RTC chip without removing the button battery by connecting the GD32 single-chip microcomputer to the first load switch and the second load switch respectively. Moreover, through the cooperation of multiple analog switches and multiple BIOS chips, it realizes the simulation of one-key clearing of BIOS configuration information by X86, with low cost and convenient operation; the whole method is simple, fast, and has low cost;

[0032] Secondly, through the cooperation of multiple status display lamps, the user can intuitively understand the current status, which brings convenience to the use.

[0033] To more clearly elaborate the structural features, technical means, and the specific purposes and functions achieved by the present invention, the present invention will be further described in detail below with reference to the drawings and specific embodiments. Description of the Drawings

[0034] Figure 1 is a general control principle block diagram of the prior art.

[0035] Figure 2 is a general control principle block diagram of an embodiment of the present invention.

[0036] Explanation of the Reference Numerals in the Drawings:

[0037] 10. GD32 single-chip microcomputer

[0038] 11. Clear button

[0039] 20. Feiteng CPU

[0040] 31. First BIOS chip 32. Second BIOS chip

[0041] 33. Third BIOS chip

[0042] 41. First status indicator light 42. Second status indicator light

[0043] 43. Third status indicator light 44. Fourth status indicator light

[0044] 50. RTC chip

[0045] 51. First load switch 52. Second load switch

[0046] 53. Button battery

[0047] 61. Chip

[0048] 62. Chip. Detailed implementation method

[0049] The present invention will be further described below in conjunction with the accompanying drawings and the detailed implementation method.

[0050] As Figure 2 shown, a system for simulating X86 to clear the BIOS configuration of a Feiteng CPU includes a GD32 single-chip microcomputer 10, a clear button 11, a first analog switch MA1, a first analog switch MB1, a first analog switch MC1, a second analog switch MA2, a second analog switch MB2, a second analog switch MC3, a first BIOS chip 31, a second BIOS chip 32, a third BIOS chip 33, an RTC chip 50, a Feiteng CPU 20, a first load switch 51, a button battery 53, a second load switch 52, a first status indicator light 41 for displaying that the GD32 single-chip microcomputer 10 is currently connected to the first BIOS chip 31, a second status indicator light 42 for displaying that the GD32 single-chip microcomputer 10 is currently connected to the second BIOS chip 32, a third status indicator light 43 for displaying that the GD32 single-chip microcomputer 10 is currently connected to the third BIOS chip 33, and a fourth status indicator light 44 for displaying that the BIOS configuration has been successfully cleared;

[0051] The first status indicator light 41, the second status indicator light 42, the third status indicator light 43, and the fourth status indicator light 44 are respectively connected to the GD32 single-chip microcomputer 10.

[0052] The clear button 11 is connected to the GD32 single-chip microcomputer 10, and the GD32 single-chip microcomputer controls the connection of the first load switch 51, the second load switch 52, the first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 through a control signal to control the opening and closing states of the corresponding load switch and the corresponding analog switch after the clear button 11 is pressed. Preferably, both the first load switch 51 and the second load switch 52 use load switches of model JW7115, and the model of the GD32 single-chip microcomputer 10 is GD32F103.

[0053] Preferably, the first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are all analog switches with a signal bandwidth greater than 200KHZ. In this embodiment, the first analog switch MA1, the first analog switch MB1, and the first analog switch MC1 are integrated on a chip 61, and the model of the chip 61 is TMUXS7614D. In this embodiment, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are integrated on another chip, and the model of the other chip is also TMUXS7614D. Here, the other chip is defined as chip 62, that is, the model of chip 62 is also TMUXS7614D.

[0054] The GD32 single-chip microcomputer is connected to one end of the first analog switch MA1 through the first SPI bus, the other end of the first analog switch MA1 is connected to the first BIOS chip 31, and the first BIOS chip 31 is connected to one end of the second analog switch MA2; the first BIOS chip 31, the second BIOS chip 32, and the third BIOS chip 33 all store the BIOS content of the initial configuration; the GD32 single-chip microcomputer is connected to one end of the second analog switch MB1 through the second SPI bus, the other end of the second analog switch MB1 is connected to the second BIOS chip 32, and the second BIOS chip 32 is connected to one end of the second analog switch MB2;

[0055] The GD32 single-chip microcomputer is connected to one end of the third analog switch MC1 through the third SPI bus, the other end of the third analog switch MC1 is connected to the third BIOS chip 33, and the third BIOS chip 33 is connected to one end of the second analog switch MC3; the other ends of the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are jointly connected to the Feiteng CPU 20 through the QSPI bus;

[0056] The Feiteng CPU 20 is connected to the RTC chip 50 via the IIC bus. One end of the RTC chip 50 is connected to one end of the first load switch 51, and the other end of the first load switch 51 is used to connect to the P3V3_STBY voltage terminal. The negative electrode of the button battery 53 is grounded, and the positive electrode of the button battery 53 is connected to the RTC chip 50 via the second load switch 52.

[0057] A method for the Feiteng CPU to simulate X86 to clear the BIOS configuration, which is based on the system for the Feiteng CPU to simulate X86 to clear the BIOS configuration; includes the following steps:

[0058] Power on the system, and by default, the first load switch 51 and the second load switch 52 are in the closed state;

[0059] Step S1, control all analog switches other than a second analog switch connected to the corresponding one BIOS chip currently used by the Feiteng CPU 20 to the off state. Among them, the BIOS chip currently used by the Feiteng CPU 20 is defined as the current BIOS chip;

[0060] Step S2, long press the clear button 11, control both the first load switch 51 and the second load switch 52 to the off state, and maintain the preset time; in this embodiment, the preset time is 1 to 2 seconds.

[0061] Step S3, control a second analog switch connected to the current BIOS chip to the off state;

[0062] Step S4, control any one of the other two second analog switches to the on state to switch the Feiteng CPU 20 to use any one of the other two non-current BIOS chips. At the same time, control the two first analog switches that were in the off state in step S1 and not connected to the current BIOS chip to the on state. The GD32 single-chip microcomputer updates the initially configured BIOS content in another BIOS chip among the other two non-current BIOS chips to the current BIOS chip via the corresponding SPI bus. In this embodiment, in step S4, after the Feiteng CPU 20 switches to use any one of the other two non-current BIOS chips, the corresponding status indicator light is lit to indicate the corresponding BIOS chip currently connected by the GD32 single-chip microcomputer 10.

[0063] Step S5, control both the first load switch 51 and the second load switch 52 to the on state, that is, complete one time of clearing the BIOS configuration. In this embodiment, in step S5, after completing one time of clearing the BIOS configuration, the fourth status indicator light 44 is lit.

[0064] Next, taking the BIOS chip currently used by the Feiteng CPU 20 after the system is powered on as the first BIOS chip 31 (i.e., the current BIOS chip is the first BIOS chip 31) as an example, the method for the Feiteng CPU to simulate X86 to clear the BIOS configuration in this embodiment will be roughly described as follows:

[0065] Power on the system, and by default, the first load switch 51 and the second load switch 52 are in the closed state;

[0066] Step S1, control all the analog switches other than the second analog switch MA2 connected to the first BIOS chip 31 (i.e., the first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MB2, and the second analog switch MC3) to the off state;

[0067] Step S2, long press the clear button 11, control both the first load switch 51 and the second load switch 52 to the off state, and keep it for 1 to 2 seconds;

[0068] Step S3, control the second analog switch MA2 to the off state;

[0069] Step S4, control the second analog switch MB2 to the closed state to switch the Feiteng CPU 20 to use the second BIOS chip 32. At the same time, control the first analog switch MB1 and the first analog switch MC1 to the closed state. The GD32 single-chip microcomputer updates the initially configured BIOS content in the third BIOS chip 33 to the first BIOS chip 31 through the third SPI bus and the first SPI bus. Meanwhile, both the third status display light 43 and the first status display light 41 are lit.

[0070] Step S5, control both the first load switch 51 and the second load switch 52 to the closed state, that is, complete one clear of the BIOS configuration. Meanwhile, the fourth status display light 44 is lit.

[0071] In summary, the design key point of the present invention is that it mainly realizes clearing the time information inside the RTC chip without removing the button battery by connecting the first load switch and the second load switch respectively through the GD32 single-chip microcomputer. Moreover, through the cooperation of multiple analog switches and multiple BIOS chips, it realizes simulating X86 to clear the BIOS configuration information with low cost and convenient operation; the whole method is simple, fast, and has low cost;

[0072] Secondly, through the cooperation of multiple status display lights, the user can intuitively understand the current status, which brings convenience to the use.

[0073] The above are only the preferred embodiments of the present invention, and do not impose any limitation on the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A system for simulating the X86 BIOS configuration clearing of Feiteng CPU, characterized in that: It includes a GD32 microcontroller, a clear button, a first analog switch MA1, a first analog switch MB1, a first analog switch MC1, a second analog switch MA2, a second analog switch MB2, a second analog switch MC3, a first BIOS chip, a second BIOS chip, a third BIOS chip, an RTC chip, a Feiteng CPU, a first load switch, a button battery, and a second load switch; The clear button is connected to the GD32 microcontroller, and the GD32 microcontroller controls the connection of the first load switch, the second load switch, the first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 through control signals to control the opening and closing states of the corresponding load switch and the corresponding analog switch after the clear button is pressed; The GD32 microcontroller is connected to one end of the first analog switch MA1 through the first SPI bus, the other end of the first analog switch MA1 is connected to the first BIOS chip, and the first BIOS chip is connected to one end of the second analog switch MA2; the first BIOS chip, the second BIOS chip, and the third BIOS chip all store the BIOS content of the initial configuration; the GD32 microcontroller is connected to one end of the second analog switch MB1 through the second SPI bus, the other end of the second analog switch MB1 is connected to the second BIOS chip, and the second BIOS chip is connected to one end of the second analog switch MB2; The GD32 microcontroller is connected to one end of the third analog switch MC1 through the third SPI bus, the other end of the third analog switch MC1 is connected to the third BIOS chip, and the third BIOS chip is connected to one end of the second analog switch MC3; the other ends of the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are jointly connected to the Feiteng CPU through the QSPI bus; The Feiteng CPU is connected to the RTC chip through the IIC bus, the RTC chip is connected to one end of the first load switch, the other end of the first load switch is used to connect to the P3V3_STBY voltage terminal, the negative electrode of the button battery is grounded, and the positive electrode of the button battery is connected to the RTC chip through the second load switch.

2. The system for simulating X86 to clear BIOS configuration by the Feiteng CPU according to claim 1, wherein: The first analog switch MA1, the first analog switch MB1, the first analog switch MC1, the second analog switch MA2, the second analog switch MB2, and the second analog switch MC3 are all analog switches with a signal bandwidth greater than 200KHZ.

3. The Feiteng CPU-based system for simulating X86 to clear the BIOS configuration according to claim 1, wherein: It also includes a first status indicator light for displaying the current connection of the GD32 microcontroller to the first BIOS chip, a second status indicator light for displaying the current connection of the GD32 microcontroller to the second BIOS chip, and a third status indicator light for displaying the current connection of the GD32 microcontroller to the third BIOS chip; The first status indicator light, the second status indicator light, and the third status indicator light are respectively connected to the GD32 microcontroller.

4. The Feiteng CPU simulation X86 BIOS configuration clearing system according to claim 1, wherein: It also includes a fourth status indicator light for displaying that the BIOS configuration has been successfully cleared, and the fourth status indicator light is connected to the GD32 microcontroller.

5. A method for Feiteng CPU to simulate X86 to clear BIOS configuration, characterized in that: The system for simulating the X86 to clear the BIOS configuration based on any one of claims 1 to 4; includes the following steps: Power on the system, and by default, the first load switch and the second load switch are in the closed state; Step S1, control all analog switches other than a second analog switch connected to a corresponding BIOS chip currently used by the Feiteng CPU to be in the off state, where the BIOS chip currently used by the Feiteng CPU is defined as the current BIOS chip; Step S2, long press the clear button, control both the first load switch and the second load switch to be in the off state, and maintain for a preset time; Step S3, control a second analog switch connected to the current BIOS chip to be in the off state; Step S4, control any one of the other two second analog switches to be in the closed state to switch the Feiteng CPU to use any one of the other two non-current BIOS chips, and at the same time, control two first analog switches that were in the off state in Step S1 and not connected to the current BIOS chip to be in the closed state, and the GD32 single-chip microcomputer updates the initially configured BIOS content in the other BIOS chip among the other two non-current BIOS chips to the current BIOS chip through the corresponding SPI bus; Step S5, control both the first load switch and the second load switch to be in the closed state, that is, complete one BIOS configuration clearing.

6. The method for the Feiteng CPU to simulate the X86 to clear the BIOS configuration according to claim 1, wherein: The system for simulating the X86 to clear the BIOS configuration by the Feiteng CPU further includes a first status display light for displaying the first BIOS chip currently connected to the GD32 single-chip microcomputer, a second status display light for displaying the second BIOS chip currently connected to the GD32 single-chip microcomputer, and a third status display light for displaying the third BIOS chip currently connected to the GD32 single-chip microcomputer; The first status display light, the second status display light, and the third status display light are respectively connected to the GD32 single-chip microcomputer; In Step S4, after the Feiteng CPU switches to use any one of the other two non-current BIOS chips, the corresponding status display light is lit to display the corresponding BIOS chip currently connected to the GD32 single-chip microcomputer.

7. The method for emulating an X86 to clear the BIOS configuration by the Feiteng CPU according to claim 1, characterized in that: The system for simulating the X86 to clear the BIOS configuration by the Feiteng CPU further includes a fourth status display light for displaying that the BIOS configuration has been successfully cleared, and the fourth status display light is connected to the GD32 single-chip microcomputer; In Step S5, after completing one BIOS configuration clearing, the fourth status display light is lit.

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