Display panel and display device

Abstract

The application provides a display panel and a display device, wherein the display panel comprises an array substrate, the array substrate comprises a display area and a non-display area, the display area comprises data lines and scan lines arranged in different layers and pixel units connected with the data lines and the scan lines, a first jump signal of a row scan signal is coupled on the data lines to generate a first coupling voltage, the non-display area is provided with a connecting line connected with the data lines and an anti-coupling line, a second jump signal of a clock pulse signal on the anti-coupling line is coupled on the connecting line to generate a second coupling voltage, the first coupling voltage and the second coupling voltage are offset to each other, so that the voltage of the data signal is not changed in the charging time, and the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display devices, and particularly relates to a display panel and a display device. BACKGROUND

[0002] The display panel is generally composed of a color film substrate, a liquid crystal layer and an array substrate, wherein the array substrate is provided with a display area and a non-display area, the display area is provided with corresponding data lines, scan lines and a pixel array, the pixel array is composed of pixel units arranged in an array, the pixel units correspond to the data lines and the scan lines, the scan lines are used for inputting row scan signals line by line, the data lines are used for inputting data signals, and the pixel units display corresponding to the received row scan signals and data signals.

[0003] Due to the existence of overlapping between the scan lines and the data lines in the array substrate, there is a coupling effect, as shown in the following formula: Figure 1 TP is a data output control signal, TP is the rising edge of the data signal input to the source drive circuit, the falling edge is used for controlling the source drive circuit to output the latched data signal to the data line of the display panel, when the row scan signal on the scan line jumps, the data signal on the data line will be coupled, causing the data signal to jump, if the data signal jump time t1 occurs in the charging time, it will cause the storage voltage of the pixel unit to change or the charging to be insufficient, and finally affect the display effect of the display panel. SUMMARY

[0004] The purpose of the present application is to provide a display panel, which aims to solve the problem that the traditional display panel has the row scan signal jump coupling causing the data signal to jump, affecting the display effect of the display panel.

[0005] The first aspect of the embodiment of the present application provides a display panel, comprising an array substrate, the array substrate comprising:

[0006] a display area, the display area comprising a plurality of data lines and a plurality of scan lines arranged in different layers, and pixel units connected to the data lines and the scan lines, a plurality of scan lines are used for inputting row scan signals line by line, a plurality of data lines are used for inputting data signals respectively, and a first jump signal of the row scan signal generates a first coupling voltage on the data line;

[0007] a non-display area, the non-display area comprising a plurality of connection lines connecting a source drive circuit and a plurality of data lines, the connection lines being arranged in the same layer as the data lines and being used for transmitting the data signals to the data lines;

[0008] The non-display area further comprises an anti-coupling line arranged in a layer different from the connection line, the anti-coupling line is arranged in parallel with the scan line, the anti-coupling line is used for inputting a clock pulse signal, each second jump signal of the clock pulse signal is phase-aligned with the first jump signal of a row scan signal, the second jump signal generates a second coupling voltage on the connection line, the first coupling voltage and the second coupling voltage offset each other, and the first jump signal and the second jump signal are corresponding ones of rising edge signals and falling edge signals.

[0009] Optionally, the display area is symmetrically divided into a first display area and a second display area along a second direction, the first display area has a first refresh rate, the second display area has a second refresh rate, each scan line comprises a first sub-scan line and a second sub-scan line, a plurality of first sub-scan lines are located in the first display area and are used for inputting first row scan signals row by row, and a plurality of second sub-scan lines are located in the second display area and are used for inputting second row scan signals row by row.

[0010] The anti-coupling line comprises a first anti-coupling line and a second anti-coupling line, the first anti-coupling line is arranged in parallel with the first sub-scan line, and the second anti-coupling line is arranged in parallel with the second sub-scan line.

[0011] The clock pulse signal comprises a first clock pulse signal and a second clock pulse signal, the first anti-coupling line is used for inputting the first clock pulse signal, and the second anti-coupling line is used for inputting the second clock pulse signal.

[0012] Each second jump signal of the first clock pulse signal is phase-aligned with the first jump signal of the first row scan signal, and each second jump signal of the second clock pulse signal is phase-aligned with the first jump signal of the second row scan signal.

[0013] Optionally, along a first direction, the width of a corresponding scan line is equal to the width of a corresponding anti-coupling line arranged in parallel, and the first direction is the arrangement direction of the corresponding scan line.

[0014] Optionally, the anti-coupling line is arranged in the same layer as the scan line.

[0015] The voltage of a high level of the clock pulse signal is a negative value of the voltage of a row off signal of the row scan signal, and the voltage of a low level of the clock pulse signal is a negative value of the voltage of a row on signal of the row scan signal.

[0016] Optionally, the anti-coupling line is arranged in a layer different from the scan line and is located in an upper layer or a lower layer of the data line at the same time.

[0017] The layer distance between the anti-coupling line and the connecting line is less than the layer distance between the scanning line and the data line, the voltage of the low level of the clock pulse signal is less than the voltage of the row opening signal of the row scanning signal, and the voltage of the high level of the clock pulse signal is less than the voltage of the row opening signal of the row scanning signal.

[0018] Alternatively, the layer distance between the anti-coupling line and the connecting line is greater than the layer distance between the scanning line and the data line, the voltage of the low level of the clock pulse signal is greater than the voltage of the row opening signal of the row scanning signal, and the voltage of the high level of the clock pulse signal is greater than the voltage of the row opening signal of the row scanning signal.

[0019] Optionally, the anti-coupling line is arranged in a layer different from the scanning line and symmetrically located at the upper layer and the lower layer of the data line.

[0020] The voltage of the high level of the clock pulse signal is equal to the voltage of the row opening signal of the row scanning signal, and the voltage of the low level of the clock pulse signal is equal to the voltage of the row closing signal of the row scanning signal.

[0021] Optionally, the anti-coupling line is arranged in a layer different from the scanning line and respectively located at the upper layer and the lower layer of the data line.

[0022] The layer distance between the scanning line and the data line is greater than the layer distance between the anti-coupling line and the connecting line.

[0023] The voltage of the high level of the clock pulse signal is less than the voltage of the row opening signal of the row scanning signal, and the voltage of the low level of the clock pulse signal is less than the voltage of the row closing signal of the row scanning signal.

[0024] Alternatively, the layer distance between the scanning line and the data line is less than the layer distance between the anti-coupling line and the connecting line.

[0025] The voltage of the high level of the clock pulse signal is greater than the voltage of the row opening signal of the row scanning signal, and the voltage of the low level of the clock pulse signal is greater than the voltage of the row closing signal of the row scanning signal.

[0026] A second aspect of the embodiment of the present application provides a display device, comprising a driving circuit of a display panel and the display panel as described above, the scanning line, the connecting line and the anti-coupling line of the display panel are connected with the driving circuit of the display panel, and the driving circuit of the display panel is used for outputting a row scanning signal, a data signal and a clock pulse signal to the scanning line, the data line and the anti-coupling line respectively.

[0027] Optionally, the driving circuit of the display panel comprises:

[0028] The source driving circuit is connected with the plurality of connection lines and is used for outputting a plurality of data signals according to a first control signal.

[0029] The gate driving circuit is connected with the plurality of scan lines and is used for outputting a plurality of row scan signals according to a second control signal.

[0030] The pulse output circuit is connected with the anti-coupling line and is used for outputting the clock pulse signal according to a third control signal.

[0031] The timing controller is connected with the source driving circuit, the gate driving circuit and the pulse output circuit respectively and is used for outputting the first control signal, the second control signal and the third control signal respectively.

[0032] Optionally, the pulse output circuit comprises a differential trace, a comparator, a first electronic switch tube and a second electronic switch tube.

[0033] The input end of the differential trace is used for inputting a differential signal, the differential trace is connected with the positive input end and the inverting input end of the comparator respectively, the output end of the comparator is connected with the control end of the first electronic switch tube and the control end of the second electronic switch tube respectively, the first end of the first electronic switch tube is used for inputting a first voltage signal, the first end of the second electronic switch tube is used for inputting a second voltage signal, the second end of the first electronic switch tube and the second end of the second electronic switch tube are connected to constitute the output end of the pulse output circuit, and the first voltage signal and the second voltage signal are alternately outputted to constitute the clock pulse signal.

[0034] Compared with the prior art, the display panel comprises an array substrate, the array substrate comprises a display area and a non-display area, the display area comprises data lines and scan lines arranged in different layers and pixel units connected with the data lines and the scan lines in correspondence, a first jump signal of a row scan signal is coupled to generate a first coupling voltage on the data lines, the non-display area is provided with a connection line connected with the data lines and an anti-coupling line, a second jump signal of a clock pulse signal on the anti-coupling line is coupled to generate a second coupling voltage on the connection line, and the first coupling voltage and the second coupling voltage offset each other, so that the voltage of the data signal does not change in the charging time, and the display effect of the display panel is improved. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 It is a schematic diagram of signal coupling between the scan lines and the data lines in the traditional array substrate.

[0036] Figure 2 It is a structural schematic diagram of the array substrate provided by the embodiment one of the application.

[0037] Figure 3The signal coupling schematic diagram of the scan line, the data line and the anti-coupling line in the array substrate provided by the embodiment one of the present application is shown in the figure;

[0038] Figure 4 The waveform schematic diagram of the scan line and the anti-coupling line in the array substrate provided by the embodiment one of the present application is shown in the figure;

[0039] Figure 5 The structure schematic diagram of the array substrate provided by the embodiment two of the present application is shown in the figure;

[0040] Figure 6 The structure schematic diagram of the array substrate provided by the embodiment three of the present application is shown in the figure;

[0041] Figure 7 The structure schematic diagram of the array substrate provided by the embodiment four of the present application is shown in the figure;

[0042] Figure 8 The structure schematic diagram of the array substrate provided by the embodiment five of the present application is shown in the figure;

[0043] Figure 9 The structure schematic diagram of the array substrate provided by the embodiment six of the present application is shown in the figure;

[0044] Figure 10 The waveform schematic diagram of the scan line and the anti-coupling line in the array substrate provided by the embodiment six of the present application is shown in the figure;

[0045] Figure 11 The first structure schematic diagram of the display device provided by the embodiment seven of the present application is shown in the figure;

[0046] Figure 12 The second structure schematic diagram of the display device provided by the embodiment seven of the present application is shown in the figure;

[0047] Figure 13 The circuit schematic diagram of the pulse output circuit provided by the embodiment seven of the present application is shown in the figure;

[0048] Figure 14 The waveform schematic diagram of the differential signal and the clock pulse signal provided by the embodiment seven of the present application is shown in the figure.

[0049] In the figure, the various reference signs are as follows:

[0050] 100, array substrate; 200, driving circuit of display panel; 210, gate driving circuit; 220, source driving circuit; 230, pulse output circuit; 240, time sequence controller; 110, display area; 120, non-display area; 111, data line; 112, scan line; 121, connecting line; 122, anti-coupling line; 1121, first sub-scan line; 1122, second sub-scan line; 1221, first anti-coupling line; 1222, second anti-coupling line; 231, differential trace;

[0051] U1, comparator; U2, first operational amplifier; U3, second operational amplifier; M1, first electronic switch; M2, second electronic switch; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor;

[0052] TP, data transmission control signal; VGH, horizontal row enable signal; VGL, horizontal row disable signal; CLK, clock pulse signal;

[0053] t1, the transition time of the data signal; H1, the interlayer distance between the scan line and the data line; H2, the interlayer distance between the anti-coupling line and the connecting line. Detailed Implementation

[0054] To make the technical problems, solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0055] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0056] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0057] Example 1

[0058] A first aspect of the present invention provides a display panel including an array substrate 100. The display panel further includes a color filter substrate and a liquid crystal layer. The color filter substrate and the array substrate 100 are disposed opposite to each other. The liquid crystal layer is located between the color filter substrate and the array substrate 100. The color filter substrate includes an upper polarizer, a color filter, a common electrode layer and an upper alignment layer. The array substrate 100 includes a lower alignment layer, a driving layer and a lower polarizer. The driving layer is a thin-film transistor driving layer, which is used to drive the liquid crystal molecules of the liquid crystal layer in conjunction with the common electrode layer.

[0059] Among them, such asFigure 2 As shown, in this embodiment, the array substrate 100 includes:

[0060] Display area 110 includes multiple columns of data lines 111 and multiple rows of scan lines 112 arranged in different layers, as well as pixel units connected to the data lines 111 and scan lines 112 respectively. The multiple rows of scan lines 112 are used to input row scan signals line by line, and the multiple columns of data lines 111 are used to input data signals respectively. The first transition signal of the row scan signal generates a first coupling voltage on the data lines 111.

[0061] The non-display area 120 includes multiple connecting lines 121 that connect the source drive circuit 220 and multiple rows of data lines 111. The connecting lines 121 are arranged on the same layer as the data lines 111 and are used to transmit data signals to the data lines 111.

[0062] The non-display area 120 also includes an anti-coupling line 122 disposed on a different layer from the connecting line 121. The anti-coupling line 122 is disposed parallel to the scan line 112. The anti-coupling line 122 is used to input a clock pulse signal CLK. Each second transition signal of the clock pulse signal CLK is phase-aligned with the first transition signal of a row of scan signals. The second transition signal generates a second coupling voltage on the connecting line 121. The first coupling voltage and the second coupling voltage cancel each other out. The first transition signal and the second transition signal are one of the rising edge signal and the falling edge signal.

[0063] In this embodiment, the display area 110 includes a data line 111, a scan line 112, and a pixel array. The pixel array consists of pixel units arranged in an array. Each pixel unit is connected to a scan line 112 and a data line 111. When a line scan signal is received, the pixel unit is turned on and charged by receiving a data signal. The pixel unit forms a driving voltage with the common electrode layer on the color filter substrate to drive the liquid crystal deflection and displays the corresponding image information in conjunction with the color filter on the color filter substrate.

[0064] When multiple horizontal scanning signals are input line by line, the rising or falling edge of the horizontal scanning signal will be coupled on the data line 111, causing the data signal to rise or fall during the charging time. The voltage change of the data signal is the first coupling voltage, which will change the magnitude of the driving voltage, ultimately causing the display panel to fail to display the normal grayscale voltage and resulting in display abnormality.

[0065] To address this issue, in this embodiment, an anti-coupling line 122 is provided in the non-display area 120 on the array substrate 100. The non-display area 120 is also provided with multiple connecting lines 121, which are connected to multiple data lines 111 one by one. The multiple connecting lines 121 are also connected to the signal terminals of the source drive circuit 220. The source drive circuit 220 is used to output multiple data signals, and the connecting lines 121 are used to transmit the received data signals to the data lines 111.

[0066] The anti-coupling line 122 can be connected to the driving circuit 200 of the display panel, for example, to the timing controller 240 or to one of the signal terminals of the source driving circuit 220, and the specific connection method is not limited.

[0067] The anti-coupling line 122 is set parallel to the scan line 112, and can be set on the same layer as the scan line 112 or set differently. The anti-coupling line 122 partially overlaps with multiple data lines 111, such as... Figure 3 As shown, the anti-coupling line 122 receives the clock pulse signal CLK output by the driving circuit. The clock pulse signal CLK is composed of alternating high and low levels. The i-th second transition signal of the clock pulse signal CLK is phase-aligned with the first transition signal of the i+1th row scanning signal input by the i+1th scan line 112. The second transition signal of the clock pulse signal CLK generates a second coupling voltage on the connecting line 121. Since the data line 111 is connected to the connecting line 121, it is equivalent to the second transition signal generating a second coupling voltage on the data line 111. The absolute values ​​of the second coupling voltage and the first coupling voltage are equal, one is a positive voltage and the other is a negative voltage. The first coupling voltage and the second coupling voltage cancel each other out, thereby ensuring that there is no voltage change in the data signal during the charging time and improving the display effect of the display panel.

[0068] For example Figure 3As shown, assuming the anti-coupling line 122 and the scan line 112 are set on the same layer, the rising edge signal on the scan line 112 causes the data signal to change. The second change signal is the falling edge signal, that is, the falling edge signal of the clock pulse signal CLK is sequentially phase-aligned with each row scan signal. When the rising edge signal of the second row scan signal begins to change, the clock pulse signal CLK synchronously changes to a falling edge signal. The rising edge signal and the falling edge signal generate an upward first coupling voltage and a downward second coupling voltage on the data line 111, respectively. The first coupling voltage and the second coupling voltage cancel each other out. Similarly, when the rising edge signal of the third row scan signal begins to change, the clock pulse signal CLK synchronously changes to a falling edge signal. The rising edge signal and the falling edge signal generate an upward first coupling voltage and a downward second coupling voltage on the data line 111, respectively. The first coupling voltage and the second coupling voltage cancel each other out. Finally, the voltage change of the data signal caused by the first change signal of each row scan signal is compensated, ensuring that there is no voltage change of the data signal during the charging time and improving the display effect of the display panel.

[0069] Or such as Figure 4 As shown, in an optional embodiment, the first transition signal of the row scan signal is a falling edge signal. The falling edge signal generates a downward first coupling voltage on the data signal. Assuming that the anti-coupling line 122 is set on the same layer as the scan line 112, the rising edge signal of the clock pulse signal CLK is phase-aligned with the falling edge signal of the row scan signal. The rising edge signal of the clock pulse signal CLK generates an upward second coupling voltage on the connection line 121. The first coupling voltage and the second coupling voltage cancel each other out, thereby compensating for the voltage change in the data signal caused by the first transition signal of each row scan signal, ensuring that there is no voltage change in the data signal during the charging time, and improving the display effect of the display panel.

[0070] The voltage level of the high-level clock pulse signal CLK can be specifically set according to the voltage level of the row scan signal, the distance between data line 111 and scan line 112, and the interlayer distance between data line 111 and connecting line 121.

[0071] The type of the second transition signal of the clock pulse signal CLK can be specifically set according to the type of the first transition signal and the interlayer position of the anti-coupling line 122 of the scan line 112. For example, when the anti-coupling line 122 and the scan line 112 are arranged on different layers and symmetrically located on both sides of the data line 111, and when the rising edge signal of the row scan signal causes the data signal to transition, the rising edge signal of the clock pulse signal CLK can be phase-aligned with the rising edge signal of the row scan signal, and the voltage of the high-level signal of the clock pulse signal CLK can be equal to the voltage of the row enable signal VGH, and the voltage of the low-level signal of the clock pulse signal CLK can be equal to the row disable signal VGL. The row enable signal VGH and the row disable signal VGL constitute the row scan signal, and the voltage of the row enable signal VGH is greater than the voltage of the row disable signal VGL.

[0072] In one optional embodiment, to facilitate adjustment of the clock pulse signal CLK voltage, the widths of the corresponding scan line 112 and the corresponding parallel anti-coupling line 122 are equal along a first direction. The first direction refers to the arrangement direction of the corresponding scan line 112. The connecting line 121 is an extension of the data line 111, and both have the same dimensions. For example... Figure 6 As shown, in order to achieve the overlap area between the anti-coupling line 122 and each connecting line 121 and the overlap area between the scan line 112 and the data line 111, the widths of the scan line 112 and the anti-coupling line 122 are equal. Therefore, when the corresponding level signal of the clock pulse signal CLK and the corresponding level signal of the scan line 112 are equal, the second coupling voltage generated by the clock pulse signal CLK coupled on the connecting line 121 will have the same value but opposite polarity as the first coupling voltage generated by the scan line 112 coupled on the connecting line 121, thereby achieving coupling voltage cancellation and improving the display effect.

[0073] The beneficial effects of the present invention embodiments compared with the prior art are as follows: The above-mentioned display panel includes an array substrate 100, which includes a display area 110 and a non-display area 120. The display area 110 includes data lines 111 and scan lines 112 disposed in different layers, as well as pixel units correspondingly connected to the data lines 111 and scan lines 112. The first transition signal of the row scan signal is coupled on the data line 111 to generate a first coupling voltage. The non-display area 120 is provided with a connecting line 121 and an anti-coupling line 122 connecting the data line 111. The second transition signal of the clock pulse signal CLK on the anti-coupling line 122 is coupled on the connecting line 121 to generate a second coupling voltage. The first coupling voltage and the second coupling voltage cancel each other out, thereby ensuring that the data signal has no voltage change during the charging time and improving the display effect of the display panel.

[0074] Example 2

[0075] In another alternative embodiment, such as Figure 5As shown, the display area 110 is symmetrically divided into a first display area 1101 and a second display area 1102 along the second direction. The first display area 1101 has a first refresh rate, and the second display area 1102 has a second refresh rate. Each scan line 112 includes separate first sub-scan lines 1121 and second sub-scan lines 1122. Multiple first sub-scan lines 1121 are located in the first display area 1101 and are used to input the first row scan signal line by line. Multiple second sub-scan lines 1122 are located in the second display area 1102 and are used to input the second row scan signal line by line.

[0076] The anti-coupling line 122 includes a first anti-coupling line 1221 and a second anti-coupling line 1222. The first anti-coupling line 1221 is arranged parallel to the first sub-scan line 1121, and the second anti-coupling line 1222 is arranged parallel to the second sub-scan line 1122.

[0077] The clock pulse signal CLK includes a first clock pulse signal and a second clock pulse signal. The first anti-coupling line 1221 is used to input the first clock pulse signal, and the second anti-coupling line 1222 is used to input the second clock pulse signal.

[0078] Each second transition signal of the first clock pulse signal is phase-aligned with the first transition signal of a first row scan signal, and each second transition signal of the second clock pulse signal is phase-aligned with the first transition signal of a second row scan signal.

[0079] In this embodiment, the display area 110 can be partitioned, and different display areas 110 can have different refresh rates. The non-display area 120 includes a first non-display area 120 corresponding to the first display area 1101 and a second non-display area 120 corresponding to the second display area 1102. The first non-display area 120 is provided with multiple connecting lines 121 and a first anti-coupling line 1221, and the second non-display area 120 is provided with multiple connecting lines 121 and a second anti-coupling line 1222.

[0080] Each second transition signal of the first clock pulse signal is phase-aligned with the first transition signal of the first row scan signal. The first row scan signal input to the first display area 1101 and the data line 111 can generate a first coupling voltage. The first clock pulse signal on the first anti-coupling line 1221 of the first non-display area 120 and the connecting line 121 can generate a second coupling voltage. The first coupling voltage and the second coupling voltage are equal in magnitude and opposite in polarity, and the voltages cancel each other out.

[0081] Similarly, each second transition signal of the second clock pulse signal is phase-aligned with the first transition signal of the second row scan signal. The second row scan signal input to the second display area 1102 and the data line 111 can generate a first coupling voltage. The second clock pulse signal on the second anti-coupling line 1222 of the second non-display area 120 and the connecting line 121 can generate a second coupling voltage. The first coupling voltage and the second coupling voltage are equal in magnitude and opposite in polarity, and the voltages cancel each other out.

[0082] The frequency of the first clock pulse signal is set to correspond to the refresh rate of the first display area 1101, and the frequency of the second clock pulse signal is set to correspond to the refresh rate of the second display area 1102.

[0083] In an optional embodiment, to facilitate adjustment of the voltage of the clock pulse signal CLK, along the first direction, the width of the first sub-scan line 1121 is equal to the width of the corresponding parallel first anti-coupling line 1221, and the width of the corresponding second sub-scan line 1122 is equal to the width of the corresponding parallel second anti-coupling line 1222. Therefore, when the corresponding level signal of the clock pulse signal CLK and the corresponding level signal of the scan line 112 are equal, the second coupling voltage generated by the clock pulse signal CLK coupled on the connecting line 121 will be equal in value but opposite in polarity to the first coupling voltage generated by the scan line 112 coupled on the connecting line 121, thereby achieving coupling voltage cancellation and improving the display effect.

[0084] Example 3

[0085] like Figure 6 As shown, in an optional embodiment, the anti-coupling line 122 and the scan line 112 are arranged on the same layer;

[0086] The high level voltage of the clock pulse signal CLK is the negative value of the row turn-off signal VGL of the row scan signal, and the low level voltage of the clock pulse signal CLK is the negative value of the row turn-on signal VGH of the row scan signal.

[0087] In this embodiment, as Figure 3 As shown, assuming that the rising edge of the horizontal scanning signal causes a data signal transition, since the widths of the anti-coupling line 122 and the scan line 112 are equal, and the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is equal to the interlayer distance H1 between the scan line 112 and the data line 111, the low-level signal of the clock pulse signal CLK is the negative voltage of the horizontal enable signal VGH. The first coupling voltage generated by the rising edge of the horizontal scanning signal and the second coupling voltage generated by the falling edge of the clock pulse signal CLK cancel each other out, thus improving the display effect.

[0088] Or, such as Figure 4As shown, when the falling edge of the horizontal scanning signal causes a data signal transition, since the widths of the anti-coupling line 122 and the scan line 112 are equal, and the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is equal to the interlayer distance H1 between the scan line 112 and the data line 111, the high-level voltage of the clock pulse signal CLK is the negative value of the horizontal off signal VGL of the horizontal scanning signal. The first coupling voltage generated by the falling edge of the horizontal scanning signal and the second coupling voltage generated by the rising edge of the clock pulse signal CLK cancel each other out, thus improving the display effect.

[0089] Example 4

[0090] In an alternative embodiment, such as Figure 7 As shown, the anti-coupling line 122 and the scan line 112 are disposed on different layers and are located on the upper or lower layer of the data line 111.

[0091] The interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is less than the interlayer distance H1 between the scan line 112 and the data line 111. The negative voltage of the low level of the clock pulse signal CLK is less than the voltage of the row enable signal VGH of the row scan signal. The negative voltage of the high level of the clock pulse signal CLK is less than the voltage of the row enable signal VGH of the row scan signal.

[0092] Alternatively, the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is greater than the interlayer distance H1 between the scan line 112 and the data line 111, the negative voltage of the low level of the clock pulse signal CLK is greater than the voltage of the row enable signal VGH of the row scan signal, and the negative voltage of the high level of the clock pulse signal CLK is greater than the voltage of the row enable signal VGH of the row scan signal.

[0093] For example Figure 7 For example, assuming that both the anti-coupling line 122 and the scan line 112 are located below the data line 111, when the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is less than the interlayer distance H1 between the scan line 112 and the data line 111, such as... Figure 3 As shown, assuming that the rising edge of the horizontal scanning signal causes a data signal transition, since the width of the anti-coupling line 122 is equal to that of the scanning line 112, the absolute value of the low-level signal of the clock pulse signal CLK needs to be less than the negative voltage value of the horizontal enable signal VGH. The absolute values ​​of the first coupling voltage generated by the rising edge of the horizontal scanning signal and the second coupling voltage generated by the falling edge of the clock pulse signal CLK are equal, but their polarities are opposite. The voltages cancel each other out, improving the display effect.

[0094] Alternatively, when the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is greater than the interlayer distance H1 between the scan line 112 and the data line 111, such as Figure 4As shown, when the falling edge of the horizontal scanning signal causes a data signal transition, since the width of the anti-coupling line 122 is equal to that of the scanning line 112, the high-level voltage of the clock pulse signal CLK needs to be greater than the negative voltage of the horizontal turn-off signal VGL of the horizontal scanning signal. The absolute values ​​of the first coupling voltage generated by the falling edge of the horizontal scanning signal and the second coupling voltage generated by the falling edge of the clock pulse signal CLK are equal, but their polarities are opposite. The voltages cancel each other out, improving the display effect.

[0095] Example 5

[0096] In an alternative embodiment, such as Figure 8 As shown, the anti-coupling line 122 and the scan line 112 are arranged in different layers and are symmetrically located on the upper and lower layers of the data line 111.

[0097] The voltage of the high level of the clock pulse signal CLK is equal to the voltage of the row enable signal VGH of the row scan signal, and the voltage of the low level of the clock pulse signal CLK is equal to the voltage of the row disable signal VGL of the row scan signal.

[0098] When the anti-coupling line 122 and the scan line 112 are located on the data line 111 and the upper and lower layers respectively, for example, when the anti-coupling line 122 is located on the upper layer of the data line 111 and the scan line 112 is located on the lower layer of the data line 111, then the rising edge signal of the clock pulse signal CLK and the rising edge signal of the row scan signal need to be phase-aligned, or the falling edge signal of the clock pulse signal CLK and the falling edge signal of the scan signal need to be phase-aligned.

[0099] When the anti-coupling line 122 and the scan line 112 are arranged on different layers and symmetrically located above and below the data line 111, the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is equal to the interlayer distance H1 between the scan line 112 and the data line 111. Assuming that the rising edge of the row scan signal causes a data signal transition, such as... Figure 10 As shown, the rising edge of the clock pulse signal CLK and the rising edge of the horizontal scanning signal need to be phase-aligned, and the high-level signal of the clock pulse signal CLK should be equal to the voltage of the horizontal enable signal VGH. The absolute values ​​of the first coupling voltage generated by the rising edge of the horizontal scanning signal and the second coupling voltage generated by the rising edge of the clock pulse signal CLK should be equal, but their polarities should be opposite, so that the voltages cancel each other out and improve the display effect.

[0100] Alternatively, assuming that the falling edge of the horizontal scanning signal causes a data signal transition, the falling edge of the clock pulse signal CLK and the falling edge of the horizontal scanning signal need to be phase-aligned, and the low level of the clock pulse signal CLK should be equal to the voltage of the horizontal turn-off signal VGL. The absolute values ​​of the first coupling voltage generated by the falling edge of the horizontal scanning signal and the second coupling voltage generated by the falling edge of the clock pulse signal CLK should be equal, but their polarities should be opposite, thus canceling each other out and improving the display effect.

[0101] Example 6

[0102] In an alternative embodiment, such as Figure 9 As shown, the anti-coupling line 122 and the scan line 112 are disposed on different layers and are located on the upper and lower layers of the data line 111, respectively.

[0103] The interlayer distance H1 between scan line 112 and data line 111 is greater than the interlayer distance H2 between anti-coupling line 122 and connecting line 121;

[0104] The voltage of the high level of the clock pulse signal CLK is less than the voltage of the row enable signal VGH of the row scan signal, and the voltage of the low level of the clock pulse signal CLK is less than the voltage of the row disable signal VGL of the row scan signal.

[0105] Alternatively, the interlayer distance H1 between scan line 112 and data line 111 is less than the interlayer distance H2 between anti-coupling line 122 and connection line 121;

[0106] The voltage of the high level of the clock pulse signal CLK is greater than the voltage of the row enable signal VGH of the row scan signal, and the voltage of the low level of the clock pulse signal CLK is greater than the voltage of the row disable signal VGL of the row scan signal.

[0107] In this embodiment, when the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is less than the interlayer distance H1 between the scan line 112 and the data line 111, such as Figure 10 As shown, assuming that the rising edge of the row scanning signal causes a data signal transition, since the width of the anti-coupling line 122 is equal to that of the scan line 112, the high-level signal of the clock pulse signal CLK needs to be less than the voltage of the row enable signal VGH. The absolute values ​​of the first coupling voltage generated by the rising edge of the row scanning signal and the second coupling voltage generated by the rising edge of the clock pulse signal CLK are equal, but their polarities are opposite. The voltages cancel each other out, improving the display effect.

[0108] Alternatively, when the interlayer distance H2 between the anti-coupling line 122 and the connecting line 121 is greater than the interlayer distance H1 between the scan line 112 and the data line 111, such as Figure 10As shown, when the falling edge of the horizontal scanning signal causes a data signal transition, since the width of the anti-coupling line 122 is equal to that of the scanning line 112, the voltage of the low-level signal of the clock pulse signal CLK needs to be greater than the voltage of the horizontal turn-off signal VGL of the horizontal scanning signal. The absolute values ​​of the first coupling voltage generated by the falling edge of the horizontal scanning signal and the second coupling voltage generated by the falling edge of the clock pulse signal CLK are equal, but their polarities are opposite. The voltages cancel each other out, improving the display effect.

[0109] Example 7

[0110] A second aspect of the present invention provides a display device, such as... Figure 11 As shown, the display device includes a driving circuit 200 for the display panel and a display panel. The specific structure of the display panel is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The scan line 112, connecting line 121, and anti-coupling line 122 of the display panel are connected to the driving circuit 200 of the display panel. The driving circuit 200 of the display panel is used to output a row scan signal, a data signal, and a clock pulse signal CLK to the scan line 112, the data line 111, and the anti-coupling line 122, respectively.

[0111] In this embodiment, the driving circuit 200 of the display panel is used to output multiple horizontal scanning signals and multiple data signals to turn on the pixel units line by line. The pixel units are connected to a scan line 112 and a data line 111 respectively. When the horizontal scanning signal is received, the pixel units are turned on and charged when the data signal is received. The pixel units also form a driving voltage with the common electrode layer on the color filter substrate to drive the liquid crystal deflection and display the corresponding image information in conjunction with the color filter on the color filter substrate.

[0112] The driving circuit 200 of the display panel also outputs a correspondingly changing clock pulse signal CLK according to the horizontal scanning signal. The first coupling voltage generated by the first transition signal of the horizontal scanning signal and the second coupling voltage generated by the second transition signal of the clock pulse signal CLK cancel each other out, thereby improving the display effect.

[0113] Depending on the signal output type, in one alternative embodiment, such as Figure 12 As shown, the driving circuit 200 for the display panel includes:

[0114] The source drive circuit 220 is connected to multiple connection lines 121 and is used to output multiple data signals according to the first control signal;

[0115] The gate drive circuit 210 is connected to the multi-line scan line 112 and is used to output multiple line scan signals line by line according to the second control signal.

[0116] The pulse output circuit 230, connected to the anti-coupling line 122, is used to output a clock pulse signal CLK according to the third control signal.

[0117] The timing controller 240 is connected to the source drive circuit 220, the gate drive circuit 210 and the pulse output circuit 230 respectively, and is used to output the first control signal, the second control signal and the third control signal respectively.

[0118] In this embodiment, the timing controller 240 acts as the master controller, outputting a first control signal, a second control signal, and a third control signal respectively. This controls the source drive circuit 220 to output multiple data signals to multiple connection lines 121, controls the gate drive circuit 210 to output multiple horizontal scan signals to multiple scan lines 112, and controls the pulse output circuit 230 to output a clock pulse signal CLK to the anti-coupling line 122. Ultimately, the first coupling voltage generated by the first transition signal of the horizontal scan signal and the second coupling voltage generated by the second transition signal of the clock pulse signal CLK cancel each other out, thereby improving the display effect.

[0119] The pulse output circuit 230 can employ a clock generator, signal amplifier, or similar structure. To prevent electromagnetic interference, in an optional embodiment, such as... Figure 13 As shown, the pulse output circuit 230 includes a differential line 231, a comparator U1, a first electronic switch M1, and a second electronic switch M2.

[0120] The input terminal of differential line 231 is used to input differential signals. Differential line 231 is connected to the non-inverting input terminal and the inverting input terminal of comparator U1, respectively. The output terminal of comparator U1 is connected to the control terminal of the first electronic switch M1 and the control terminal of the second electronic switch M2, respectively. The first terminal of the first electronic switch M1 is used to input the first voltage signal, and the first terminal of the second electronic switch M2 is used to input the second voltage signal. The second terminals of the first electronic switch M1 and the second terminals of the second electronic switch M2 are connected to form the output terminal of the pulse output circuit 230. The first voltage signal and the second voltage signal are output alternately to form the corresponding clock pulse signal CLK.

[0121] In this embodiment, the pulse output circuit 230 uses differential traces 231. The symmetry of the differential traces 231 is utilized to cancel electromagnetic radiation and improve electromagnetic interference and conduction. The timing controller 240 is used to output differential signals, such as... Figure 14As shown, the differential signal is an alternating positive voltage and a negative voltage, such as 1V and -1V. The alternating differential signal is output to comparator U1. A first resistor R1 is connected between the non-inverting input terminal and the inverting input terminal of comparator U1. Comparator U1 compares the voltage difference between the non-inverting input terminal and the inverting input terminal and outputs a comparison signal with alternating high and low levels. The comparison signal then alternately controls the first electronic switch M1 and the second electronic switch M2 to turn on and outputs a clock pulse signal CLK composed of the first voltage signal and the second voltage signal.

[0122] The first and second voltage signals can be output using appropriate amplifiers or signal sources, for example... Figure 13 As shown, the first voltage signal is output by the first inverting amplifier, which consists of the first operational amplifier U2, the second resistor R2, and the third resistor R3. The second voltage signal is output by the second inverting amplifier, which consists of the fourth resistor R4, the fifth resistor R5, and the second operational amplifier U3. For example, the first voltage signal is the negative value of the horizontal enable signal VGH, -VGH, and the second voltage signal is the negative value of the horizontal disable signal VGL, -VGL. The horizontal enable signal VGH is input to the inverting input terminal of the first operational amplifier U2, and the horizontal disable signal VGL is input to the inverting input terminal of the second operational amplifier U3. The signals are amplified by the inverting amplifier with an amplification factor of -1 to achieve the output of -VGH and -VGL.

[0123] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A display panel, comprising an array substrate, characterized in that, The array substrate includes: The display area includes multiple columns of data lines and multiple rows of scan lines arranged in different layers, as well as pixel units connected to the data lines and the scan lines. The multiple rows of scan lines are used to input row scan signals line by line, and the multiple columns of data lines are used to input data signals respectively. The first transition signal of the row scan signal generates a first coupling voltage on the data lines. The non-display area includes multiple connecting lines that connect the source drive circuit and the multiple rows of data lines. The connecting lines are arranged on the same layer as the data lines and are used to transmit the data signals to the data lines. The non-display area also includes an anti-coupling line disposed on a different layer from the connection line. The anti-coupling line is disposed parallel to the scan line and is used to input a clock pulse signal. Each second transition signal of the clock pulse signal is phase-aligned with the first transition signal of the row scan signal. The second transition signal generates a second coupling voltage on the connection line. The first coupling voltage and the second coupling voltage cancel each other out. The first transition signal and the second transition signal are corresponding to one of the rising edge signal and the falling edge signal.

2. The display panel as described in claim 1, characterized in that, The display area is symmetrically divided into a first display area and a second display area along the second direction. The first display area has a first refresh rate, and the second display area has a second refresh rate. Each scan line includes a separate first sub-scan line and a second sub-scan line. Multiple first sub-scan lines are located in the first display area and are used to input the first line scan signal line by line. Multiple second sub-scan lines are located in the second display area and are used to input the second line scan signal line by line. The anti-coupling line includes a first anti-coupling line and a second anti-coupling line. The first anti-coupling line is arranged parallel to the first sub-scan line, and the second anti-coupling line is arranged parallel to the second sub-scan line. The clock pulse signal includes a first clock pulse signal and a second clock pulse signal. The first anti-coupling line is used to input the first clock pulse signal, and the second anti-coupling line is used to input the second clock pulse signal. Each second transition signal of the first clock pulse signal is phase-aligned with the first transition signal of the first row scan signal, and each second transition signal of the second clock pulse signal is phase-aligned with the first transition signal of the second row scan signal.

3. The display panel as described in claim 1 or 2, characterized in that, Along the first direction, the width of the corresponding scan line is equal to that of the corresponding parallel anti-coupling line, and the first direction is the arrangement direction of the corresponding scan line.

4. The display panel as described in claim 3, characterized in that, The anti-coupling line is disposed on the same layer as the scan line; The high-level voltage of the clock pulse signal is the negative of the voltage of the row-off signal of the row scan signal, and the low-level voltage of the clock pulse signal is the negative of the voltage of the row-on signal of the row scan signal.

5. The display panel as described in claim 3, characterized in that, The anti-coupling line is disposed on a different layer from the scan line and is located on either the upper or lower layer of the data line; The interlayer distance between the anti-coupling line and the connecting line is less than the interlayer distance between the scan line and the data line; the negative voltage value of the low level of the clock pulse signal is less than the voltage of the row enable signal of the row scan signal; and the negative voltage value of the high level of the clock pulse signal is less than the voltage of the row enable signal of the row scan signal. Alternatively, the interlayer distance between the anti-coupling line and the connecting line is greater than the interlayer distance between the scan line and the data line, the negative voltage value of the low level of the clock pulse signal is greater than the voltage of the row enable signal of the row scan signal, and the negative voltage value of the high level of the clock pulse signal is greater than the voltage of the row enable signal of the row scan signal.

6. The display panel as described in claim 3, characterized in that, The anti-coupling line is disposed on a different layer from the scan line and is symmetrically located on the upper and lower layers of the data line; The voltage of the high level of the clock pulse signal is equal to the voltage of the row enable signal of the row scan signal, and the voltage of the low level of the clock pulse signal is equal to the voltage of the row disable signal of the row scan signal.

7. The display panel as described in claim 3, characterized in that, The anti-coupling line is disposed on a different layer from the scan line and is located on the upper and lower layers of the data line, respectively. The interlayer distance between the scan line and the data line is greater than the interlayer distance between the anti-coupling line and the connecting line; The voltage of the high level of the clock pulse signal is less than the voltage of the row enable signal of the row scan signal, and the voltage of the low level of the clock pulse signal is less than the voltage of the row disable signal of the row scan signal. Alternatively, the interlayer distance between the scan line and the data line is smaller than the interlayer distance between the anti-coupling line and the connecting line; The high-level voltage of the clock pulse signal is greater than the voltage of the row enable signal of the row scan signal, and the low-level voltage of the clock pulse signal is greater than the voltage of the row disable signal of the row scan signal.

8. A display device, characterized in that, The display panel includes a driving circuit for the display panel and a display panel as described in any one of claims 1 to 7, wherein the scan lines, connecting lines, and anti-coupling lines of the display panel are connected to the driving circuit of the display panel, and the driving circuit of the display panel is used to output a row scan signal, a data signal, and a clock pulse signal to the scan lines, the data lines, and the anti-coupling lines, respectively.

9. The display device as claimed in claim 8, characterized in that, The driving circuit of the display panel includes: The source drive circuit is connected to multiple of the aforementioned connection lines and is used to output multiple data signals according to the first control signal; A gate driving circuit, connected to multiple rows of the scan lines, is used to output multiple rows of scan signals line by line according to a second control signal; A pulse output circuit, connected to the anti-coupling line, is used to output the clock pulse signal according to the third control signal; The timing controller is connected to the source drive circuit, the gate drive circuit and the pulse output circuit respectively, and is used to output the first control signal, the second control signal and the third control signal respectively.

10. The display device as claimed in claim 9, characterized in that, The pulse output circuit includes differential wiring, a comparator, a first electronic switch, and a second electronic switch. The input terminals of the differential traces are used to input differential signals. The differential traces are connected to the non-inverting input terminal and the inverting input terminal of the comparator, respectively. The output terminals of the comparator are connected to the control terminals of the first electronic switch and the second electronic switch, respectively. The first terminal of the first electronic switch is used to input a first voltage signal, and the first terminal of the second electronic switch is used to input a second voltage signal. The second terminals of the first and second electronic switches are connected to form the output terminal of the pulse output circuit. The first voltage signal and the second voltage signal are output alternately to form the corresponding clock pulse signal.

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