Full-parallel arbitrary multiplying power variable sampling system

Abstract

The invention provides a full-parallel arbitrary multiplying power variable sampling system, and belongs to the technical field of signal processing. The system comprises an up-sampling system and a down-sampling system, the up-sampling system is used for a transmitter and comprises an up-sampling filter and an up-sampling interpolator, and the down-sampling system is used for a receiver and comprises a down-sampling filter, an extractor and a down-sampling interpolator; the up-sampling system can process four paths of input signals in parallel, and four paths of output signals are obtained after the four paths of input signals are processed in parallel; the down-sampling system is formed by cascading a plurality of down-sampling filters and an extractor, an extraction module is responsible for down-sampling of integer 2n times, and a decimal interpolator is connected behind the extractor to realize down-sampling processing of any decimal times. According to the invention, the limitation of traditional integer or simple fractional multiple sampling is broken through, arbitrary-multiplying-power precise resampling of the GHz-level signal is realized, the processing speed and the interpolation precision are obviously improved, the error is low, the anti-aliasing capability is strong, and the method is suitable for the high-requirement fields such as private network communication.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal processing, and particularly relates to a fully parallel arbitrary-ratio variable sampling system. Background Art

[0002] According to the conclusions drawn from the analysis of the development status and market scale of the Chinese communication industry in 2022, private network communication equipment occupies a dominant position, which will follow stricter frequencies and signals and serve specific enterprise customers. With the development of 5G technology, the types and demands of customers are increasing day by day. In important sectors such as energy, finance, government, and national security, private network communication undertakes important missions such as emergency rescue and smart cities. Since the specific transmission frequency bands of different industries are different, the requirements for the change of signal sampling rate are not all integer multiples, but more are fractional multiples. Most traditional structures serve integer and simple fractional multiple resampling, and the research on arbitrary multiple resampling is very urgent.

[0003] In the instant processing of signals, whether stable transmission and reliable identification can be achieved depends on filters. For traditional variable sampling rate filters, the serial input method can no longer meet the high-speed requirements of data flow, so the parallelization transformation of the original serial architecture is imminent. Summary of the Invention

[0004] The purpose of the present invention is to provide a fully parallel arbitrary-ratio variable sampling system to solve the technical problems of small change multiples, limited serial processing hardware, and only integer multiple processing existing in the variable sampling technology in the prior art.

[0005] To solve the above technical problems, the specific technical solution of the present invention is as follows:

[0006] A fully parallel arbitrary-ratio variable sampling system, the system includes an upsampling system and a downsampling system. The upsampling system for the transmitter includes an upsampling filter and an upsampling interpolator, and the downsampling system for the receiver includes a downsampling filter, a decimator, and a downsampling interpolator;

[0007] The upsampling system can process 4 input signals in parallel, and the 4 input signals are processed in parallel to obtain 4 output signals;

[0008] The downsampling system is composed of a plurality of cascaded downsampling filters and decimators. The decimation module is responsible for downsampling by an integer multiple of 2^n, and a fractional interpolator is connected after the decimator to achieve arbitrary fractional downsampling processing.

[0009] Further, the upsampling interpolator adopts a Farrow structure suitable for polynomial interpolation; the upsampling interpolator includes a parallelization module, a data cache module, a numerically controlled oscillator, and a multiply-accumulate unit module.

[0010] Further, in the upsampling system, four consecutive sampling points in the input data stream are four input signals, denoted as x(4n), x(4n + 1), x(4n + 2), and x(4n + 3) respectively. After passing through four parallelization modules, the four input signals are stored in the corresponding data buffer modules respectively. The upsampling filter generates four independent interpolation control words through a numerically controlled oscillator. Each control word provides its own interpolation interval μ, which determines the interpolation position of each input signal. The data buffer modules non-linearly fetch data from the FIFO according to their respective interpolation control words to ensure that the data corresponds one-to-one with the current interpolation reference point. Subsequently, the multiply-accumulate unit module calculates the interpolation coefficient in real time according to the interpolation interval μ to complete the multiply-accumulate operation of polynomial interpolation, and outputs the interpolated signals y(4n), y(4n + 1), y(4n + 2), and y(4n + 3) after parallel processing, that is, the four output signals.

[0011] Further, the downsampling filter uses a half-band filter.

[0012] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention breaks through the limitations of traditional integer or simple fractional multiple variable sampling, realizes arbitrary multiple accurate resampling of GHz-level signals, significantly improves the processing speed and interpolation accuracy, has low error and strong anti-aliasing ability, and is applicable to high-demand fields such as private network communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0014] Figure 1 It is a schematic structural diagram of the full-parallel arbitrary multiple variable sampling system of the present invention.

[0015] Figure 2 It is a schematic structural diagram of the upsampling system of the present invention.

[0016] Figure 3 It is a schematic structural diagram of the downsampling system of the present invention.

[0017] Figure 4Waveform comparison diagram of different sampling rate change multiples in the upsampling part of the present invention; among them, (a) time-domain waveform diagram of upsampling from 62KHz to 2GHz; (b) frequency-domain waveform diagram of upsampling from 62KHz to 2GHz; (c) time-domain waveform diagram of upsampling from 2.15MHz to 2GHz; (d) frequency-domain waveform diagram of upsampling from 2.15MHz to 2GHz; (e) time-domain waveform diagram of upsampling from 360MHz to 2GHz; (f) frequency-domain waveform diagram of upsampling from 360MHz to 2GHz; (g) time-domain waveform diagram of upsampling from 1.33GHz to 2GHz; (h) frequency-domain waveform diagram of upsampling from 1.33GHz to 2GHz.

[0018] Figure 5 Time-frequency domain waveform comparison of multi-frequency signals in the downsampling part of the present invention from the original sampling rate of 2GHz to 210MHz; (a) time domain after the first-stage decimation; (b) time domain after the second and third stages of decimation; (c) frequency domain after the first-stage decimation; (d) frequency domain after the second and third stages of decimation; (e) time domain after the last-stage decimation; (f) frequency domain after the last-stage decimation; (g) time domain comparison between the original signal and the output signal after downsampling; (h) frequency domain comparison between the original signal and the output signal after downsampling. Specific implementation mode

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0020] The present invention proposes a fully parallel arbitrary-ratio variable sampling system, as Figures 1-3 shown, the system includes an upsampling system and a downsampling system. The upsampling system for the transmitter includes an upsampling filter and an upsampling interpolator, and the downsampling system for the receiver includes a downsampling filter, a decimator, and a downsampling interpolator.

[0021] The upsampling filter is used to perform anti-aliasing filtering on the input signal to suppress the high-frequency image components that may be introduced during the upsampling interpolation process, ensuring the spectral purity and reconstruction accuracy of the interpolated signal.

[0022] The present invention compares the impulse responses and amplitude-frequency characteristics of various interpolation functions, observes the fitting degree of the amplitude response, phase response, and spectral characteristics of the interpolation function to the ideal function, and finally selects the Lagrange interpolation function as the interpolation function of the upsampling interpolator; uses the Lagrange algorithm to deduce the influence of high-order (7th order) interpolation on the interpolation effect.

[0023] The upsampling interpolator adopts the Farrow structure applicable to polynomial interpolation. As Figure 2 shown, the upsampling interpolator includes a parallelization module, a data cache module, a numerically controlled oscillator, and a multiply-accumulate unit module. The upsampling system can process 4 input signals in parallel, and 4 output signals are obtained after parallel processing of the 4 input signals.

[0024] After comparing the fast FIR algorithm and the fast convolution algorithm, the present invention finds that the waveforms after processing by the two algorithms are consistent with the theoretical waveform under the serial structure, and the parallel decomposition is correct. The number of filter taps in the implementation structure of the fast convolution algorithm is less. Therefore, the parallelization module of the present invention adopts the fast convolution algorithm.

[0025] The data cache module adopts the fifo structure of dual-port RAM. By controlling the change of the address value, the corresponding filtered data can be fetched. The address of the output data does not increment automatically, but changes according to the change of the interpolation reference point.

[0026] The multiply-accumulate unit module is responsible for outputting the address control word and the interpolation interval of the FIFO structure of the data cache module. In order to improve the operation speed and ensure the operation accuracy, the multiply-accumulate unit module uses the pipeline technology to convert multiplication into shift addition, performs bit truncation processing on the output result, speeds up the operation speed, ensures the output accuracy, saves resources on the premise of ensuring the precision; finally, the output error of the test system is about 1%.

[0027] Specifically, when implemented, 4 consecutive sampling points in the input data stream are 4 input signals, which are respectively denoted as x(4n), x(4n + 1), x(4n + 2), x(4n + 3). After passing through 4 parallelization modules, the 4 input signals are respectively stored in the corresponding data cache modules (FIFOs). Since the interpolation ratio is not fixed, according to the requirements of any interpolation ratio, the upsampling filter generates 4 independent interpolation control words (NCO1 to NCO4) through a numerically controlled oscillator (NCO). Each control word provides its own interpolation interval μ, which determines the interpolation position of each input signal.

[0028] The data cache module non-linearly fetches data from the FIFO according to their respective interpolation control words to ensure that the data corresponds one by one to the current interpolation reference point. Subsequently, the multiply-accumulate unit module calculates the interpolation coefficient in real time according to the interpolation interval μ, completes the multiply-accumulate operation of polynomial interpolation, and outputs the interpolated signals y(4n), y(4n + 1), y(4n + 2), y(4n + 3) after parallel processing, that is, 4 output signals, realizing high-efficiency and accurate upsampling at any ratio.

[0029] Due to the spectral aliasing phenomenon that occurs during the extraction process of the extractor, the downsampling filter of the present invention uses a half-band filter, which has the advantages of parameter symmetry and half of the coefficients being zero, greatly reducing the computational complexity. The half-band filter is an anti-aliasing low-pass filter placed before the extractor. After filtering out the frequency components that may cause aliasing in the original signal, it is then connected to the extractor for integer decimation operation.

[0030] Since the extractor can only perform integer decimation, to achieve arbitrary downsampling ratios, it is composed of multiple downsampling filters cascaded with the extractor. The decimation module is responsible for integer decimation by a factor of 2^n. Calculate the total decimation ratio required according to the ratio of the target sampling rate to the input sampling rate, and dynamically select the decimation path that best matches this ratio for activation by the control logic, while the remaining paths do not participate in this sampling process. After the signal completes integer decimation through the half-band filter and the extractor, it will be sent to the downsampling interpolator. The downsampling interpolator is a fractional interpolator used to achieve fine adjustment of non-integer sampling ratios to ensure that the final output signal meets the target sampling rate requirements.

[0031] Connect a fractional interpolator after the extractor to achieve arbitrary fractional downsampling processing. To meet the requirements of hardware interface and resource limitations, a dedicated bit-width truncation module is used to truncate the interpolated output data, retaining appropriate numbers of integer and fractional parts to ensure the best balance between output accuracy and hardware resource utilization efficiency.

[0032] Next, the sampling system of the present invention will be verified by simulation.

[0033] The implementation process of the upsampling system is as follows: Starting from the generation of the input signal, after completing the sampling rate conversion, it is compared with the generated input signal to determine whether the sampling rate conversion is successful. First, 1) Set an appropriate number of sampling points, and generate an input signal with a certain sampling rate through a software simulation platform. 2) Then, use the ratio of the target sampling rate to the original sampling rate to obtain the interpolation estimation points μ_k and convert them into fixed-point numbers. 3) Calculate the interpolated values corresponding to each interpolation point through the coefficients of the designed structure, and simulate the output of fixed-point numbers using the hardware platform. 4) Based on the fixed-point numbers processed and output by the software simulation platform, convert them into floating-point numbers, and draw the time-domain and frequency-domain waveforms of the input signal and the signal after changing the sampling rate. 5) Compare the waveform of the transformed signal with the original signal to determine whether the sampling rate change is successful.

[0034] Example 1: Original sampling rate fs: 62 kHz, original number of sampling points: 200

[0035] Target sampling rate fi: 2 GHz, number of points after resampling: 6451612

[0036] Frequencies of the input signal are 1 kHz respectively, oversampling ratio: 62

[0037] Example 2: Original sampling rate fs: 2.15 MHz, original number of sampling points: 200

[0038] Target sampling rate fi: 2 GHz, number of points after resampling: 186046

[0039] Input signal frequencies are 76 kHz respectively, oversampling multiple: 28

[0040] Example 3: Original sampling rate fs: 360 MHz, original number of sampling points: 200

[0041] Target sampling rate fi: 2 GHz, number of points after resampling: 1112

[0042] Input signal frequencies are 9.8 MHz respectively, oversampling multiple: 36

[0043] Example 4: Original sampling rate fs: 1.33 GHz, original number of sampling points: 2000

[0044] Target sampling rate fi: 2 GHz, number of points after resampling: 3007

[0045] Input signal frequencies are 56 MHz respectively, oversampling multiple: 24

[0046] From Figure 4 It is found from (a) to (b) in that, for upsampling from 62 KHz, because the sampling change multiple is too high, that is, the output clock is much faster than the input clock, the interpolation will suddenly become 0 due to insufficient input data. After sending the output data to the software simulation platform, it is necessary to perform zero-removing processing on the data to obtain the correct output result. As Figure 4 In (c) to (h) in, as the sampling conversion multiple gradually decreases, for the fractional part wk fixed-point number of the change multiple, the data gradually increases, accumulating a certain error. When interpolating from 1.33 GHz to 2 GHz, the time-domain waveform will have an error after several cycles, but it has basically no influence in the frequency domain and no clutter is generated; the accuracy of the interpolation is analyzed below.

[0047] The input and output sampling rates and the number of sampling points within one period are counted, the number of actual interpolation points and the theoretically obtained number are calculated, and the errors all fluctuate around 1%, and the larger the sampling rate change multiple, the smaller the error. Within the allowable error range, the design of this system is verified to be correct through simulation and can meet the requirement of upsampling to the GHz level.

[0048] The implementation process of the downsampling part is as follows:

[0049] First, 1) Set appropriate number of sampling points to generate an input signal with a certain sampling rate. 2) Implement the decimation result of 2^n integer times through n groups of decimation modules (half-band filter + decimator). 3) Feed it into the interpolation system to calculate the interpolation result. 4) Draw the time-domain and frequency-domain waveforms of the original signal and the signal after changing the sampling rate, and analyze the time-domain waveform and frequency-spectrum waveform to evaluate the resampling effect.

[0050] Superimpose signals with multiple different center frequencies to test the anti-aliasing effect of the system. The downsampling system should be able to filter out the noise in the clock domain of the last-stage decimator.

[0051] Example 5: Original sampling rate fs: 2 GHz, number of sampling points: 163,840;

[0052] Target sampling rate fi: 0.21 GHz, number of points after resampling: 17,218;

[0053] Input signal frequencies: 90 kHz, 1.6 MHz, 10 MHz, 75 MHz, 90 MHz, 110 MHz, 150 MHz. Figure 5 The time-domain waveform diagrams of the first stage and the second stage are shown. It can be seen that the number of sampling points is reduced from the initial 163,840 to 81,920 after the first-stage decimation; and it becomes 40,960 points after the second-stage decimation; there is no obvious change in the frequency-domain waveform, and there are still 7 signals with different frequencies; but after passing through the last-stage decimator, that is Figure 5 (a) in is the time-domain waveform diagram of the signal after the first-stage decimation. The number of sampling points is reduced from the initial 163,840 to 81,920, and the number of sampling points is halved. The overall shape of the time-domain waveform remains unchanged. Figure 5 (b) is the time-domain waveform diagram of the signal after further passing through the second-stage decimation. The number of sampling points is further reduced by half to 40,960 points, and the time-domain waveform still retains the characteristics of the original signal. Figure 5 (c) in is the frequency-domain waveform diagram after the first-stage decimation. At this time, there is no obvious change in the frequency spectrum, and the 7 frequency components (90 kHz, 1.6 MHz, 10 MHz, 75 MHz, 90 MHz, 110 MHz, 150 MHz) in the original input signal are all completely retained, indicating that there is no obvious frequency-spectrum aliasing phenomenon during the first-stage decimation process. Figure 5In (d), the frequency-domain changes of the signal in the second and third decimation stages are shown. Among them, the upper figure (blue spectrum) is the signal spectrum after the second-stage decimation. It can be seen that all seven frequency components (90 kHz, 1.6 MHz, 10 MHz, 75 MHz, 90 MHz, 110 MHz, 150 MHz) are still retained, indicating that high-frequency filtering has not been performed at this stage. The lower figure (red spectrum) is the signal spectrum after the third-stage decimation. Only the signals of 90 kHz, 1.6 MHz, and 10 MHz in the low-frequency part are retained, and the remaining high-frequency components have been effectively filtered, verifying the good performance of the anti-aliasing filter in the third-stage decimation of this system. Figure 5 In (e) and (f), it can be seen that the number of points is reduced by half to 10,240 points, and the signals of frequencies such as 75 MHz, 90 MHz, 110 MHz, and 150 MHz are filtered out, leaving only three frequencies: 90 kHz, 1.6 MHz, and 10 MHz. Figure 5 In (g), it is the time-domain waveform diagram of the original input signal and the output signal of the downsampling system. At a sampling rate of 2 GHz, the number of sampling points of the input signal is 163,840 points; when downsampled to a sampling rate of 210 MHz, the number of sampling points of the output signal is 17,218 points. The change in the number of sampling points is 9.516 times (163,840 / 17,218), which is basically the same as the change in the sampling rate of 9.523 times (2 GHz / 210 MHz). And observing Figure 5 In (h), it can be seen that the anti-aliasing effect of the system is good. The four signals that would cause aliasing in the original signal are all filtered out before interpolation, without introducing noise to the output signal after interpolation and without generating clutter.

[0054] After testing the anti-aliasing effect of the system on multiple frequency signals, the effect of sampling rate conversion at different levels will be tested below. Since the anti-aliasing effect of the system has been tested level by level, the following simulation only shows the time-domain and frequency-domain waveform diagrams of the input and the final output signal after the system downsampling, without showing the detailed intermediate decimation filtering process.

[0055] Example 6: Original sampling rate fs: 2 GHz, number of sampling points: 2000;

[0056] Target sampling rate fi: 1.5 GHz, number of points after resampling: 1500;

[0057] Input signal frequencies: 1 MHz, 600 MHz

[0058] Example 7: Original sampling rate fs: 2 GHz, number of sampling points: 16,111,100;

[0059] Target sampling rate fi: 13.2 MHz, number of points after resampling: 106,333;

[0060] Input signal frequencies: 0.81 kHz, 6.5 kHz

[0061] Example 8: Original sampling rate fs: 2 GHz, number of sampling points: 13107200;

[0062] Target sampling rate fi: 91 kHz, number of points after resampling: 593;

[0063] Input signal frequencies: 960 Hz, 7.9 kHz

[0064] As the multiple of the sampling rate change increases, a large number of sampling points of the original signal are required. During the calculation process, due to insufficient points, certain errors will occur, but the errors are all maintained at about 0.5%, which has little impact on the waveform accuracy, and no clutter at other frequencies will be generated in the frequency domain. The system design is correct and available, and the test passes.

[0065] It can be understood that the present invention is described by some embodiments. Those skilled in the art know that without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and embodiments. In addition, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the scope protected by the present invention.

Claims

1. A fully parallel arbitrary magnification variable sampling system, characterized in that The system includes an upsampling system and a downsampling system. The upsampling system for the transmitter includes an upsampling filter and an upsampling interpolator, and the downsampling system for the receiver includes a downsampling filter, a decimator, and a downsampling interpolator; The upsampling system can process 4 input signals in parallel. After parallel processing of the 4 input signals, 4 output signals are obtained; The downsampling system is composed of a cascade of multiple downsampling filters and decimators. The decimation module is responsible for downsampling by an integer multiple of 2^n. A fractional interpolator is connected after the decimator to achieve downsampling processing with any fractional multiple.

2. The all-parallel arbitrary magnification variable sampling system according to claim 1, wherein The upsampling interpolator adopts a Farrow structure suitable for polynomial interpolation; the upsampling interpolator includes a parallelization module, a data cache module, a numerically controlled oscillator, and a multiply-accumulate unit module.

3. The fully parallel arbitrary magnification variable sampling system according to claim 2, characterized in that, In the upsampling system, 4 consecutive sampling points in the input data stream are 4 input signals, denoted as x(4n), x(4n + 1), x(4n + 2), and x(4n + 3) respectively; after passing through 4 parallelization modules, the 4 input signals are stored in the corresponding data cache modules respectively. The upsampling filter generates 4 independent interpolation control words through the numerically controlled oscillator. Each control word provides its own interpolation interval μ, which determines the interpolation position of each input signal; the data cache module non-linearly retrieves data from the FIFO according to its respective interpolation control word to ensure that the data corresponds one-to-one with the current interpolation reference point. Subsequently, the multiply-accumulate unit module calculates the interpolation coefficients in real time according to the interpolation interval μ to complete the multiply-accumulate operation of polynomial interpolation, and outputs the interpolated signals y(4n), y(4n + 1), y(4n + 2), and y(4n + 3) after parallel processing, that is, 4 output signals.

4. The fully parallel arbitrary magnification variable sampling system according to claim 1, characterized in that, The downsampling filter uses a half-band filter.

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