FPGA-based queue-driven array radar signal processing implementation method
By employing a queue-driven data buffering method in the FPGA, the data buffer is divided into multiple parts, and data is read and processed in a specific order. This solves the problem of inflexible parameter switching in FPGA array radar signal processing, and improves program flexibility and debugging efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CNGC INST NO 206 OF CHINA ARMS IND GRP
- Filing Date
- 2025-04-10
- Publication Date
- 2026-07-24
AI Technical Summary
FPGAs have problems in array radar signal processing, such as inflexible parameter switching, poor program portability, and low program modification efficiency. In particular, the timing arrangement is complicated when switching modes quickly, which increases the difficulty of design and debugging.
A queue-driven data caching approach is adopted, which divides the data cache area into a data cache area, a parameter cache area, and a data status area. Parameters are read by determining the status of the data status area, and data is read and processed in the order of transmission pulse period, accumulation period, etc., to achieve isolation between modules and fast switching of parameter timing.
It achieves independence between modules, reduces timing coupling, simplifies parameter switching and program portability, and improves program flexibility and debugging efficiency.
Smart Images
Figure CN120405578B_ABST
Abstract
Description
Technical Field
[0001] The embodiments of this application relate to the field of array radar signal processing technology, and in particular to an FPGA-based queue-driven array radar signal processing implementation method. Background Technology
[0002] With the widespread application of digital array radar, the demands on radar signal processing data throughput and processing capabilities are increasing. Array radars often consist of hundreds, thousands, or even tens of thousands of independent receiving elements, and all array data needs to be aggregated to achieve beamforming. Moreover, the most significant advantage of digital array radar is its multi-beam capability; therefore, technicians often need to form multi-beam coverage of the airspace of interest, all of which greatly increases the data processing pressure. The rise of broadband array radar has further placed higher demands on signal processing capabilities.
[0003] FPGAs are characterized by their high data throughput and processing power. For example, Xilinx's Virtex-7-690T has 84 high-speed transceiver ports, each with a processing rate of up to 11.3Gbps. This development board also has 3600 multipliers, enabling simultaneous multiplication operations. Therefore, FPGAs have become an indispensable processor in array radar signal processing. Unlike the serial processing based on traditional CPU processors, FPGAs perform parallel pipelined processing under a fixed clock cycle. In FPGAs, all processing is time-based, and calculations must be accurate to one clock cycle. This means that program modifications can be very significant when parameters change, sometimes requiring redesign. When parameters switch and calculations change, considerable effort is often spent adjusting timing, increasing workload and design and debugging difficulty. Furthermore, during rapid mode switching, if the time cycle changes significantly, modules like frequency domain pulse compression and MTD (Mean Transmission Device) use ping-pong buffering, making timing arrangements and data buffering extremely complex. In other words, although FPGAs can effectively achieve high-speed data output and complete large-scale data computation, FPGA programs have disadvantages such as inflexible parameter switching, poor program portability, and low program modification efficiency. The flexibility of FPGAs urgently needs to be improved. Summary of the Invention
[0004] In view of this, the embodiments of this application propose an FPGA-based queue-driven array radar signal processing implementation method. It adopts a queue-driven data caching design, which isolates the processing timing coupling between modules, ensures the independence of module operation, and facilitates the switching of mode parameters, as well as the porting, writing and debugging of the program.
[0005] To achieve the above objectives, embodiments of this application propose a FPGA-based queue-driven array radar signal processing implementation method. The method includes the following steps: dividing the queue data buffer into three parts: a data buffer area, a parameter buffer area, and a data status area; during a read operation, determining the read parameters based on the status of the data status area, and then reading the data according to the parameters; cyclically storing the DDC (Digital Down Converter) data according to the transmission pulse cycle in the queue, reading it according to the corresponding parameters based on the storage order, and performing DBF (Digital BeamForming) calculations; cyclically storing the DBF-processed data according to the transmission pulse cycle in the queue, reading it according to the corresponding parameters based on the storage order, and performing PC (Pulse Compression) calculations; cyclically storing the PC-processed data according to the accumulation cycle in the queue, reading it according to the corresponding parameters based on the storage order, and performing MTD (Moving Target Detection) calculations.
[0006] To achieve the above objectives, embodiments of this application also propose an FPGA-based queue-driven array radar signal processing system. The system includes: a cache partitioning module, a DBF (Data Deployment Function) operation module, a PC (Programmable Array) operation module, and an MTD (Mean Transmission Targeting) operation module. The cache partitioning module divides the queue data cache into three parts: a data cache area, a parameter cache area, and a data status area. During read operations, it determines the parameters based on the status of the data status area and then reads the data according to the parameters. The DBF operation module stores the data after DDC (Data Deployment Control) in a queue according to the transmission pulse cycle, reads the data according to the storage order and performs DBF operations based on the corresponding parameters. The PC operation module stores the data after DBF operations in a queue according to the transmission pulse cycle, reads the data according to the storage order and performs PC operations based on the corresponding parameters. The MTD operation module stores the data after PC operations in a queue according to the accumulation cycle, reads the data according to the storage order and performs MTD operations based on the corresponding parameters.
[0007] To achieve the above objectives, embodiments of this application also propose an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform an FPGA-based queue-driven array radar signal processing implementation method as described above.
[0008] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the FPGA-based queue-driven array radar signal processing method described above.
[0009] This application proposes an FPGA-based queue-driven array radar signal processing method. Data after Direct Current Generation (DDC) is stored cyclically in a queue according to the transmission pulse cycle. Data is then read according to the storage order and corresponding parameters, and DBF (Deep Data Flow) calculations are performed. Data after DBF calculations is stored cyclically in a queue according to the transmission pulse cycle. Data is then read according to the storage order and corresponding parameters, and PC (Programmatic Computation) calculations are performed. Data after PC calculations is stored cyclically in a queue according to the accumulation cycle. Data is read according to the storage order and corresponding parameters, and MTD (Mean Time Difference) calculations are performed. In other words, this application performs queue-based data caching after DDC, DBF calculations, and PC calculations. This achieves module isolation and rapid parameter timing switching, avoids the use of global timing, reduces timing coupling between modules, and ensures the independence of module operations. To implement queue-based data caching, this application divides the queue data cache into three parts: a data cache area, a parameter cache area, and a data state area. During read operations, the parameters are read based on the state of the data state area, and then the data is read according to the parameters. This design facilitates parameter switching, as well as program portability, writing, and debugging.
[0010] Optionally, there are N data buffers and N parameter buffers, and the data buffers and parameter buffers correspond one-to-one; where N is an integer greater than 1.
[0011] Optionally, the data buffer is used to store relevant data during signal processing. Write and read addresses enable write and read operations according to required rules. The parameter buffer stores relevant processing parameters corresponding to the data. It is written synchronously with the data; during data read operations, the parameters are read first, and then the quantity of data to be read and the relevant read rules are determined based on the parameters. The data status area represents the data status of each data buffer, which is either "not written" or "written and waiting." After the data in the data buffer corresponding to the current loop address is read, it is determined whether the data status of the data buffer corresponding to the next loop address is "written and waiting." If so, data is read; otherwise, the process continues to wait until the data status becomes "written and waiting" before reading the data. This data writing and data storage operation is scientific and reasonable, preventing data pollution.
[0012] Optionally, the step of storing the DDC-post data in a queue according to the transmission pulse cycle, and reading and performing DBF operations according to the storage order and corresponding parameters includes: storing the DDC-post data of each pulse sequentially into N data buffers in the order of distance first and then channel; then, reading the data according to the storage order based on a preset data rate; determining the time of data reading based on the data read and the data rate; and performing DBF operations on the read data. The determined time of data reading ensures that the rate of DBF operations after output remains unchanged, without altering the structure of the DBF operations.
[0013] Optionally, the data after DBF calculation is stored in a queue according to the transmission pulse period. The data is read and PC calculation is performed according to the corresponding parameters based on the order of storage. This includes: storing the data after DBF calculation of each pulse into N data buffers in a cyclic manner, first the range and then the beam. Then, reading out the data of each beam in a manner, first the beam and then the range, and performing PC calculation on the read data.
[0014] Optionally, the data after PC calculation is stored in a queue according to the accumulation period. The data is read and MTD calculation is performed according to the storage order and corresponding parameters. This includes: storing the data after PC calculation of each pulse into N data buffers in a loop according to the order of beam, then range, then pulse. Then, the data is read in the order of range, then pulse, then beam, and the read data is subjected to MTD calculation.
[0015] Optionally, after storing the data after PC calculation in a queue according to the accumulation period, and reading the data according to the storage order and performing MTD calculation according to the corresponding parameters, the method further includes: performing constant false alarm detection based on the data after MTD calculation. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a flowchart of an FPGA-based queue-driven array radar signal processing implementation method provided in one embodiment of this application;
[0018] Figure 2 This is a schematic diagram of a queue data buffer area provided in one embodiment of this application;
[0019] Figure 3 This is a schematic diagram of data flow during data processing provided in one embodiment of this application;
[0020] Figure 4 This is a schematic diagram illustrating the caching of data after DBF operation provided in one embodiment of this application;
[0021] Figure 5 This is a schematic diagram illustrating the caching of data after PC processing, provided in one embodiment of this application;
[0022] Figure 6 This is a schematic diagram of a FPGA-based queue-driven array radar signal processing implementation system provided in another embodiment of this application;
[0023] Figure 7 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation
[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to enable readers to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.
[0025] To address the lack of flexibility in FPGAs, one embodiment of this application proposes an FPGA-based queue-driven array radar signal processing implementation method. The implementation details of this FPGA-based queue-driven array radar signal processing implementation method are described below. The following details are provided for ease of understanding and are not essential for implementing this solution.
[0026] The specific flow of the FPGA-based queue-driven array radar signal processing implementation method proposed in this embodiment can be described as follows: Figure 1 As shown, it includes:
[0027] Step 101: Divide the queue data cache into three parts: data cache area, parameter cache area, and data status area. When performing a read operation, read the parameters by determining the status of the data status area, and then read the data according to the parameters.
[0028] In its implementation, this application employs a queue-based circular storage method for data storage. To avoid using global timing parameters and reduce timing coupling between modules, the queue data buffer in the FPGA is pre-divided into three parts: a data buffer, a parameter buffer, and a data status area. During read operations, parameters are read based on the status of the data status area, and then data is read according to the parameters. This approach to data writing and storage operations is more scientific and rational, preventing data contamination.
[0029] In one example, there are N data buffers and N parameter buffers, and there is a one-to-one correspondence between the data buffers and the parameter buffers, where N is an integer greater than 1.
[0030] In one example, the partitioning of the queue data buffer is as follows: Figure 2 As shown, the data cache area and parameter cache area with the same label correspond to each other.
[0031] In one example, N data buffers are used to store relevant data during signal processing. Write and read addresses enable write and read operations according to the required rules.
[0032] In one example, N parameter buffers are used to store the relevant processing parameters corresponding to the data. The parameters are written synchronously with the data. When performing a data reading operation, the parameters are read first, and then the number of data to be read and the relevant reading rules are determined based on the parameters.
[0033] In one example, the data status area is used to represent the data status of each data buffer. The data status is either not written or write-complete waiting. After the data in the data buffer corresponding to the current loop address is read, it is determined whether the data status of the data buffer corresponding to the next loop address is write-complete waiting. If it is, the data is read. If not, it continues to wait until its data status becomes write-complete waiting before reading the data.
[0034] Step 102: Store the data after DDC in a queue according to the transmission pulse period, and read it according to the corresponding parameters and perform DBF calculation according to the storage order.
[0035] In the specific implementation, the FPGA acquires the data after DDC in real time, and then stores the acquired data after DDC in a queue according to the transmission pulse period. According to the storage order, it reads the data according to the corresponding parameters and performs DBF operation to obtain the data after DBF operation.
[0036] In one example, the data flow during data processing is as follows: Figure 3 As shown.
[0037] In one example, after the FPGA acquires the data after DDC, it needs to sequentially store the data after DDC for each pulse into N data buffers in the order of distance first and then channel. Then, based on the preset data rate, the data is read according to the storage order. The time of reading the data is determined according to the condition of the read data and the data rate. DBF operation is performed on the read data. The determined time of reading the data ensures that the rate of DBF operation after output remains unchanged. This design does not require changing the structure of DBF operation.
[0038] It should be noted that the preset data rate can be set by those skilled in the art according to actual needs, and this application does not impose any specific limitations on it.
[0039] Step 103: Store the data after DBF calculation in a queue according to the transmission pulse period, and read it according to the corresponding parameters and perform PC calculation according to the storage order.
[0040] In the specific implementation, after the FPGA completes the DBF operation and obtains the data after the DBF operation, it needs to store the data after the DBF operation in a queue according to the transmission pulse period. Then, it needs to read the data according to the corresponding parameters based on the storage order and perform PC operation to obtain the data after PC operation.
[0041] In one example, the FPGA needs to store the data after DBF calculation for each pulse into N data buffers in a loop, first the range and then the beam. Then, it needs to read out the data of each beam in a loop, first the beam and then the range, and perform PC calculations on the read data.
[0042] In one example, the process of caching the data after DBF operation is as follows: Figure 4 As shown.
[0043] Step 104: Store the data after PC calculation in a queue according to the accumulation period, and read the data according to the corresponding parameters and perform MTD calculation according to the storage order.
[0044] In the specific implementation, after the FPGA completes the PC operation and obtains the data after the PC operation, it needs to store the data after the PC operation in a queue according to the accumulation period. According to the storage order, the data is read and MTD operation is performed according to the corresponding parameters to obtain the data after the MTD operation, that is, the MTD detection result.
[0045] In one example, the FPGA needs to store the data after PC calculation for each pulse in N data buffers in a sequential manner, first beam, then range, then pulse. Then, the data is read in the same manner, first range, then pulse, then beam, and the read data is processed by MTD calculation.
[0046] In one example, the process of caching the data after PC processing is as follows: Figure 5 As shown.
[0047] In one example, such as Figure 3 As shown, after the FPGA performs MTD operation on the read data and obtains the data after the MTD operation, it is also necessary to perform constant false alarm detection based on the data after the MTD operation, so as to determine whether the target signal exists.
[0048] This embodiment proposes an FPGA-based queue-driven array radar signal processing method. Data after Direct Current Generation (DDC) is stored cyclically in a queue according to the transmission pulse cycle. Data is then read and processed using DBF (Data Flow Analysis) based on the storage order and corresponding parameters. Data after DBF is stored cyclically in a queue according to the transmission pulse cycle. Data after PC (Programmable Execution) is read and processed using the storage order and corresponding parameters. Data after PC is stored cyclically in a queue according to the accumulation cycle. Data is read and processed using MTD (Mean Time Difference) based on the storage order and corresponding parameters. In other words, this embodiment performs queue-based data caching after DDC, DBF, and PC operations. This achieves isolation between modules and rapid switching of parameter timing, avoids the use of global timing, reduces timing coupling between modules, and ensures the independence of module operations. To implement queue-based data caching, this application divides the queue data cache into three parts: a data cache area, a parameter cache area, and a data state area. During read operations, the parameters are read based on the state of the data state area, and then the data is read according to the parameters. This design facilitates parameter switching, program portability, writing, and debugging.
[0049] The steps in the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this application.
[0050] Accordingly, another embodiment of this application proposes an FPGA-based queue-driven array radar signal processing implementation system. The details of this FPGA-based queue-driven array radar signal processing implementation system are described below. The following implementation details are provided for ease of understanding only and are not essential for implementing this example. Figure 6 This is a schematic diagram of the structure of a queue-driven array radar signal processing system based on FPGA proposed in this embodiment, including: a cache partitioning module 201, a DBF operation module 202, a PC operation module 203, and an MTD operation module 204.
[0051] The cache partitioning module 201 is used to divide the queue data cache into three parts: a data cache area, a parameter cache area, and a data status area. It is also used to read parameters by determining the status of the data status area during a read operation, and then read data based on the parameters.
[0052] DBF calculation module 202 is used to store the data after DDC in a queue according to the transmission pulse period, and read it according to the corresponding parameters according to the storage order and perform DBF calculation.
[0053] The PC calculation module 203 is used to store the data after DBF calculation in a queue according to the transmission pulse period, and read it according to the corresponding parameters and perform PC calculation according to the storage order.
[0054] The MTD calculation module 204 is used to store the data after PC calculation in a queue according to the accumulation period, and read the data according to the storage order and corresponding parameters to perform MTD calculation.
[0055] It is not difficult to see that this embodiment is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above method embodiment. The relevant technical details and technical effects mentioned in the above method embodiment are still effective in this embodiment. In order to reduce repetition, they will not be repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above method embodiment.
[0056] It is worth mentioning that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.
[0057] Another embodiment of this application proposes an electronic device, the specific structure of which can be as follows: Figure 7As shown, it includes: at least one processor 301; and a memory 302 communicatively connected to the at least one processor 301; wherein the memory 302 stores instructions executable by the at least one processor 301, the instructions being executed by the at least one processor 301 to enable the at least one processor 301 to execute an FPGA-based queue-driven array radar signal processing implementation method as described in the above method embodiments.
[0058] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.
[0059] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.
[0060] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.
Claims
1. A method for implementing queue-driven array radar signal processing based on FPGA, characterized in that, include: The queue data cache is divided into three parts: data cache area, parameter cache area, and data status area. When performing a read operation, the parameters are read by determining the status of the data status area, and then the data is read according to the parameters. The data after DDC is stored in a queue according to the transmission pulse period. The data is then read according to the corresponding parameters and DBF calculation is performed based on the order of storage. The data after DBF calculation is stored in a queue according to the transmission pulse period. The data is then read according to the corresponding parameters and PC calculation is performed based on the order of storage. The data after PC calculation is stored in a queue according to the accumulation period. The data is read and MTD calculation is performed according to the storage order and corresponding parameters.
2. The FPGA-based queue-driven array radar signal processing implementation method as described in claim 1, characterized in that, There are N data buffers and N parameter buffers, and there is a one-to-one correspondence between the data buffers and the parameter buffers; where N is an integer greater than 1.
3. The FPGA-based queue-driven array radar signal processing implementation method as described in claim 2, characterized in that, The data buffer is used to store relevant data during signal processing. By using write and read addresses, data can be written and read according to the required rules. The parameter buffer is used to store the relevant processing parameters corresponding to the data. It is written synchronously with the data. When performing data reading operations, the parameters are read first, and then the amount of data to be read and the relevant reading rules are determined based on the parameters. The data status area is used to represent the data status of each data buffer. The data status is either not written or write-complete and waiting. After the data in the data buffer corresponding to the current loop address is read, it is determined whether the data status of the data buffer corresponding to the next loop address is write-complete and waiting. If it is, the data is read. If not, the waiting continues until the data status becomes write-complete and waiting, and then the data is read.
4. The FPGA-based queue-driven array radar signal processing implementation method as described in claim 3, characterized in that, The data after DDC is stored in a queue in a circular manner according to the transmit pulse period. It is then read according to the storage order and the corresponding parameters are used to perform DBF calculations, including: The data after DDC for each pulse is sequentially stored into N data buffers in the order of distance first, then channel. Then, based on the preset data rate, the data is read according to the storage order. The time of reading the data is determined according to the condition of the read data and the data rate. DBF operation is performed on the read data. The determined time of reading the data ensures that the rate of DBF operation after output remains unchanged, and the structure of DBF operation does not need to be changed.
5. The FPGA-based queue-driven array radar signal processing implementation method as described in claim 3, characterized in that, The data after DBF calculation is stored in a queue according to the transmit pulse period. It is then read according to the stored order and the corresponding parameters are used for PC calculation, including: The data after DBF calculation for each pulse is stored sequentially in N data buffers in the order of range first, then beam. Then, the data of each beam is read out sequentially in the order of beam first, then range, and PC calculation is performed on the read data.
6. The FPGA-based queue-driven array radar signal processing implementation method as described in claim 3, characterized in that, The data after PC calculation is stored in a queue according to the accumulation period. Data is then read and processed using MTD calculations based on the storage order and corresponding parameters, including: The data after PC calculation for each pulse is stored in N data buffers in a cyclical manner, first beam, then range, then pulse. Then, the data is read in the same manner, first range, then pulse, then beam, and MTD calculation is performed on the read data.
7. A method for implementing queue-driven array radar signal processing based on FPGA as described in any one of claims 1 to 6, characterized in that, After storing the data processed by the PC in a queue according to the accumulation period, and reading the data according to the storage order and performing MTD calculations based on the corresponding parameters, the method further includes: Constant false alarm rate (CFAR) detection is performed based on the data obtained from MTD calculations.
8. A FPGA-based queue-driven array radar signal processing implementation system, characterized in that, include: The cache partitioning module is used to divide the queue data cache into three parts: a data cache area, a parameter cache area, and a data status area. It is also used to read parameters by determining the status of the data status area during a read operation, and then read the data based on the parameters. The DBF operation module is used to store the data after DDC in a queue according to the transmission pulse period, and read it according to the storage order and corresponding parameters to perform DBF operation. The PC calculation module is used to store the data after DBF calculation in a queue according to the transmission pulse period, and read it according to the corresponding parameters and perform PC calculation according to the storage order. The MTD calculation module is used to store the data after PC calculation in a queue according to the accumulation period, and read the data according to the storage order and corresponding parameters to perform MTD calculation.
9. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform an FPGA-based queue-driven array radar signal processing implementation method as described in any one of claims 1 to 7.