Flow table management method and device, computer device, storage medium and program product

Abstract

The application relates to the technical field of communication, and discloses a flow table management method and device, computer equipment, a storage medium and a program product. The method is applied to a network chip and comprises the following steps: scanning each activation state bit in an activation bitmap; the activation state bit is in one-to-one correspondence with a table entry of a flow table pre-stored in the network chip; the flow table is used for storing processing data of a data packet received by the network chip; each activation state bit in the activation bitmap is updated according to a preset condition, so that hardware logic of the network chip fills the processing data of the data packet into the flow table according to the updated activation bitmap; and the preset condition is used for indicating whether data in the table entry corresponding to the activation state bit is activated. The above scheme has the advantages of low resource occupation and high efficiency when the flow table management function is implemented.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to flow table management methods, devices, computer equipment, storage media, and program products. Background Technology

[0002] To meet ever-increasing throughput demands, network chips often employ a pipeline-structured flow table engine to edit and forward data packets. The flow table engine uses a hash algorithm to look up entry addresses and stores them in the corresponding SRAM (Static Random-Access Memory). The stored entry data includes a key (indicating the entry address) and action data (AD). However, once an entry address is occupied, it is often impossible to add a new entry to the same address, wasting storage resources.

[0003] In related technologies, the hit rate of entries is statistically analyzed through hardware logic, and the aging time of entries is statistically analyzed through software. The aging time of hit entries is refreshed, and the hardware logic deletes entries that have reached their aging time. However, as the number of entries increases, the computational load required by the software and hardware logic also increases, reducing the efficiency of flow table management and potentially causing system crashes. Increasing computing resources also requires high costs. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a flow table management method, apparatus, computer equipment, storage medium and program product to solve the problems of high resource consumption and low efficiency when performing flow table management.

[0005] In a first aspect, the present invention provides a flow table management method applied to a network chip, the method comprising:

[0006] Scan each activation state bit in the activation bitmap; each activation state bit corresponds one-to-one with an entry in the flow table pre-stored in the network chip; the flow table is used to store the processing data of the data packets received by the network chip;

[0007] The activation bitmap is updated according to preset conditions so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table according to the updated activation bitmap; the preset conditions are used to indicate whether the data in the corresponding table entry of the activation bit is activated.

[0008] In one optional implementation, updating each activation state bit in the activation bitmap according to preset conditions includes:

[0009] When the target activation state bit meets the preset conditions, the target activation state bit is updated to the first state; otherwise, the target activation state bit is updated to the second state; the target activation state bit is any one of the activation state bits.

[0010] In one optional implementation, the network chip's hardware logic fills the flow table with the processed data of the data packet based on the updated activation bitmap, including:

[0011] The hardware logic of the network chip acquires the data packet processing data;

[0012] When the target activation state bit is in the first state, the hardware logic of the network chip fills the processed data of the data packet into the entry in the flow table corresponding to the target activation state bit; when the target activation state bit is in the second state, the original entry is retained.

[0013] In an optional implementation, the flow table further includes a priority identifier, which indicates the priority of the corresponding processed data; the method further includes:

[0014] When the target activation state bit is in the first state, the hardware logic of the network chip compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data.

[0015] When the priority of new processing data is not less than the priority of the original processing data, the hardware logic of the network chip fills the new processing data into the entry in the flow table corresponding to the target activation state bit.

[0016] In one optional implementation, the processed data includes matching data and action data; the method further includes:

[0017] When the target activation state bit is in the second state, the hardware logic of the network chip compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data.

[0018] When the priority of the new processing data is not lower than the priority of the original processing data, the hardware logic of the network chip compares the matching data in the new processing data with the matching data in the original processing data.

[0019] When the matching data in the new processing data is the same as the matching data in the original processing data, the hardware logic of the network chip fills the action data in the new processing data into the entry in the flow table corresponding to the target activation state bit.

[0020] In one optional implementation, the method further includes:

[0021] Receive a table deletion command; the table deletion command includes the table deletion matching data and the table deletion priority.

[0022] Read the target activation status bit;

[0023] When the target activation state bit is in the first state, the hardware logic of the network chip compares the table deletion matching data in the table deletion instruction with the matching data corresponding to the target activation state bit, and compares the table deletion priority in the table deletion instruction with the priority corresponding to the target activation state bit.

[0024] When the table deletion matching data in the table deletion instruction is the same as the matching data corresponding to the target activation state bit, and the table deletion priority in the table deletion instruction is not less than the priority corresponding to the target activation state bit, the hardware logic of the network chip deletes the data in the table entry corresponding to the target activation state bit.

[0025] Secondly, the present invention provides a flow table management device applied to a network chip, the device comprising:

[0026] The scanning module is used to scan each activation state bit in the activation bitmap; the activation state bit corresponds one-to-one with the entries in the flow table pre-stored in the network chip; the flow table is used to store the processing data of the data packets received by the network chip.

[0027] The update module is used to update each activation status bit in the activation bitmap according to preset conditions, so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table according to the updated activation bitmap; the preset conditions are used to indicate whether the data in the corresponding table entry of the activation status bit is activated.

[0028] Thirdly, the present invention provides a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the flow table management method of the first aspect or any corresponding embodiment described above.

[0029] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute the flow table management method of the first aspect or any corresponding embodiment thereof.

[0030] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute the flow table management method of the first aspect or any corresponding embodiment thereof.

[0031] The technical solution provided by this invention may include the following beneficial effects:

[0032] The flow table management method provided by this invention is applied to a network chip. During flow table management, the activation status bits in the activation bitmap are first scanned. Each activation status bit corresponds one-to-one with an entry in the flow table pre-stored in the network chip. The flow table stores the processing data of the data packets received by the network chip. Then, the activation status bits in the activation bitmap are updated according to preset conditions, so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table based on the updated activation bitmap. The preset conditions indicate whether the data in the entry corresponding to the activation status bit is active. This solution, by setting an activation bitmap to indicate the activation status of each entry in the flow table, updating the activation status bits in the activation bitmap via software, and processing the corresponding entries based on the activation status bits via hardware logic, achieves flexible flow table management with minimal logic resource consumption and high efficiency. Attached Figure Description

[0033] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This diagram illustrates the storage of table entry data in related technologies.

[0035] Figure 2 This is a flowchart illustrating the flow table management method according to an embodiment of the present invention;

[0036] Figure 3 This is a flowchart illustrating another flow table management method according to an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram illustrating the correspondence between flow tables and activation bitmaps according to an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram illustrating the correspondence between a flow table with added priority identifiers and an activation bitmap according to an embodiment of the present invention.

[0039] Figure 6 This is a structural block diagram of a flow table management device according to an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] To meet the ever-increasing throughput demands, network chips often employ a pipeline-structured flow table engine to edit and forward data packets. The flow table engine uses a hash algorithm to look up entry addresses and stores them in the corresponding SRAM (Static Random-Access Memory). The stored entry data includes a key (indicating the entry address) and action data (AD). Figure 1 A schematic diagram of storing table entry data in related technologies is shown. However, once a table entry address is occupied, it is often impossible to add a new table entry to the same address, wasting storage resources.

[0043] In related technologies, the hardware logic lacks a direct entry refresh mechanism; the refresh of entries is entirely handled by software. The software records all entry information and performs aging time (cnt) statistics. It maintains a cnt count for each entry, initialized to N, and decrements cnt periodically. If the hardware logic reports a hit indication, the software interrupt handler restores the cnt of the corresponding entry to N. When cnt decrements to 0, the software chooses to remove the corresponding entry or re-enter a new entry. The hardware logic assists the software in statistically analyzing the hit status of entries.

[0044] However, as the number of entries increases, the amount of computation required by the software and hardware logic also increases, which reduces the efficiency of flow table management and may even cause system crashes. Increasing computing resources requires higher costs.

[0045] According to an embodiment of the present invention, a flow table management method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0046] This embodiment provides a flow table management method applied to a network chip. Figure 2 This is a flowchart of a flow table management method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0047] Step S201: Scan each active state bit in the active bitmap.

[0048] This flow table management method can be applied to scenarios such as network traffic management, caching systems, databases, security and traffic analysis, edge computing, and distributed storage. The network chip is used to edit and forward data packets in the application scenario. Steps S201 to S202 are executed by a software program running in the processor (e.g., CPU, embedded processor) of the network chip. For example, the network chip can be a programmable switching chip or a smart network interface card (NIC).

[0049] The flow table is pre-stored in the network chip to store the processing data of the data packets received by the network chip. Specifically, the flow table includes multiple entries, which can be empty or store the processing data of the data packets. Each entry stores the processing data of one data packet.

[0050] The activation bitmap includes multiple activation status bits, each corresponding one-to-one with an entry in the flow table pre-stored in the network chip. These bits indicate the activation status of the corresponding entry, i.e., whether the data in the entry is activated by service traffic (a hit match). For example, the activation bitmap uses a bitmap format.

[0051] When performing flow table management, the network chip's software first scans each active state bit in the active bitmap. Specifically, the scanning period can be set, and each scanning period scans each active state bit in the active bitmap in sequence.

[0052] Step S202: Update each activation status bit in the activation bitmap according to preset conditions, so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table according to the updated activation bitmap.

[0053] Next, the network chip's software updates each activation status bit in the activation bitmap. Specifically, it updates each activation status bit in the activation bitmap according to preset conditions. These preset conditions are used to indicate whether the data in the corresponding entry of the activation status bit is active. For example, when the activation status bit meets the preset conditions, the activation status bit is updated to inactive.

[0054] Furthermore, the network chip's hardware logic fills the processed data into the flow table based on the updated activation bitmap. Specifically, the hardware logic can determine whether the data packet received by the network chip can be filled into the flow table based on the indication of each activation status bit in the activation bitmap. For example, if the activation status bit indicates that it is not activated, the original data packet in the flow table will be overwritten by the received data packet; if the activation status bit indicates that it is activated, no overwriting will be performed.

[0055] The flow table management method provided in this embodiment is applied to a network chip. During flow table management, the activation status bits in the activation bitmap are first scanned. Each activation status bit corresponds one-to-one with an entry in the flow table pre-stored in the network chip. The flow table stores the processing data of the data packets received by the network chip. Then, the activation status bits in the activation bitmap are updated according to preset conditions, so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table based on the updated activation bitmap. The preset conditions indicate whether the data in the entry corresponding to the activation status bit is active. This solution, by setting an activation bitmap to indicate the activation status of each entry in the flow table, updating the activation status bits in the activation bitmap via software, and processing the corresponding entries based on the activation status bits via hardware logic, achieves flexible flow table management with minimal logic resource consumption, resulting in high efficiency in flow table management.

[0056] This embodiment provides a flow table management method applied to a network chip. Figure 3 This is a flowchart of a flow table management method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps:

[0057] Step S301: Scan each active state bit in the active bitmap.

[0058] For example, Figure 4 This is a schematic diagram illustrating the correspondence between a flow table and an activation bitmap according to an embodiment of the present invention. The flow table stores processing data of data packets received by the network chip. The processing data includes matching data (key) and action data (ad). The matching data uniquely identifies a data packet or entry and can be a combination of characteristic fields of the data packet, such as a 5-tuple (source / destination IP, port, protocol). The action data indicates the processing action associated with the matching data (e.g., forwarding, dropping, modifying fields). It should be noted that one processing data corresponds to one entry, meaning that the associated matching data and action data belong to the same entry. The active bitmap corresponds one-to-one with the entries of the flow table pre-stored in the network chip.

[0059] Step S302: Update each activation state bit in the activation bitmap according to preset conditions.

[0060] This preset condition is used to indicate whether the data in the corresponding entry of the activation status bit is active.

[0061] Specifically, when a target activation status bit meets a preset condition, the target activation status bit is updated to a first state, which indicates that the activation status bit is not active, and the data in the corresponding entry can be directly overwritten; otherwise, the target activation status bit is updated to a second state, which indicates that the activation status bit is active, and the data in the corresponding entry cannot be overwritten. Here, the target activation status bit can be any one of the various activation status bits. This process is repeated for each activation status bit in the activation bitmap.

[0062] In step S303, the hardware logic of the network chip fills the processing data of the data packet into the flow table according to the updated activation bitmap.

[0063] Specifically, step S303 includes:

[0064] Step S3031: The hardware logic of the network chip acquires the data packet processing data.

[0065] When a table needs to be added, the software sends processing data for the data packet to be edited. The hardware logic obtains this processing data, reads the matching data within it, calculates the hash value corresponding to the matching data to determine the table entry address, obtains the table entry to be stored, and then retrieves the target activation status bit corresponding to the table entry. If a conflict occurs during hash value calculation and the logic cannot obtain the table entry address, the table addition will fail.

[0066] Step S3032: When the target activation state bit is in the first state, the hardware logic of the network chip fills the processed data of the data packet into the entry in the flow table corresponding to the target activation state bit.

[0067] When the target activation status bit is in the first state, it means that the target activation status bit is not activated, that is, it is not used by business traffic (no match hit), and the content can be regarded as invalid and can be directly overwritten and added. Therefore, the hardware logic directly fills the processing data of the data packet into the table entry corresponding to the target activation status bit.

[0068] Step S3033: When the target activation state bit is in the second state, retain the original table entry.

[0069] When the target activation status bit is in the second state, it means that the target activation status bit has been activated, that is, it has been used by business traffic (there is a match). Therefore, the corresponding table entry cannot be directly overwritten. Thus, the hardware logic retains the original table entry and does not overwrite it.

[0070] Optionally, the flow table also includes a priority identifier, which indicates the priority of the corresponding processed data. For example, Figure 5This is a schematic diagram illustrating the correspondence between a flow table and an activation bitmap with added priority identifiers according to an embodiment of the present invention. Priority identifiers (tp) are added to the entries in the flow table, and each priority identifier corresponds one-to-one with the processed data. After adding the priority identifier, when the target activation state bit is in the first state, the hardware logic of the network chip compares the priority of the new processed data corresponding to the target activation state bit with the priority of the original processed data. If the priority of the new processed data is not less than the priority of the original processed data, the hardware logic of the network chip fills the new processed data into the entry in the flow table corresponding to the target activation state bit. In other words, when the target activation state bit is not activated but a priority identifier exists, the entry is overwritten only if the priority of the new processed data is not less than the priority of the original processed data, preventing low-priority processed data from accidentally overwriting the reserved positions of high-priority entries.

[0071] Optionally, when the target activation state bit is in the second state, the network chip's hardware logic compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data. If the priority of the new processing data is not less than the priority of the original processing data, the network chip's hardware logic compares the matching data in the new processing data with the matching data in the original processing data. If the matching data in the new processing data is the same as the matching data in the original processing data, the network chip's hardware logic fills the action data in the new processing data into the entry in the flow table corresponding to the target activation state bit. In other words, when the target activation state bit is activated, a double verification mechanism must be satisfied, i.e., the priority of the new processing data is not less than the priority of the original processing data and the new and old matching data are the same, before the entry corresponding to the target activation state bit can be overwritten, thus achieving strict protection of active data in the flow table.

[0072] Optionally, to clear long-unused entries and free up resources, atomic deletion operations can be implemented to clear entry contents, reclaim storage space, and achieve the aging process for entries. Specifically, the software issues a deletion command, which is received by the hardware logic. This command includes deletion matching data and deletion priority. Then, the hardware logic performs atomic deletion operations on each active state bit in the active bitmap sequentially. Taking the target active state bit as an example, when the target active state bit is in the first state, the network chip's hardware logic compares the deletion matching data in the deletion command with the matching data corresponding to the target active state bit, and compares the deletion priority in the deletion command with the priority corresponding to the target active state bit. When the deletion matching data in the deletion command is the same as the matching data corresponding to the target active state bit, and the deletion priority in the deletion command is not less than the priority corresponding to the target active state bit, the network chip's hardware logic deletes the data in the entry corresponding to the target active state bit; for example, 0 can be entered.

[0073] The flow table management method provided in this embodiment sets an activation bitmap to indicate the activation state of each entry in the flow table, distinguishes the target activation state bit corresponding to each entry into a first state and a second state, updates each activation state bit in the activation bitmap through software, and processes the corresponding entries based on the activation state bit through hardware logic. When the target activation state bit is in the first state, the hardware logic can directly overwrite the newly added corresponding entry, ensuring effective utilization of storage resources. When the target activation state bit is in the second state, the hardware logic retains the original entry, ensuring data security. Thus, flexible management of the flow table is achieved with minimal logical resource consumption, resulting in high efficiency and good security.

[0074] Furthermore, this embodiment adds a priority identifier to the entries in the flow table. Combined with the target activation status bit, when the target activation status bit is in the first state and a priority identifier exists, the entry is overwritten only if the priority of the new processed data is not less than the priority of the original processed data. This prevents low-priority processed data from accidentally overwriting the reserved positions of high-priority entries. When the target activation status bit is in the second state and a priority identifier exists, the entry corresponding to the target activation status bit can only be overwritten if the priority of the new processed data is not less than the priority of the original processed data and the new and old matching data addresses are the same. This achieves strict protection of active data in the flow table, thereby further ensuring data security during the flow table management process.

[0075] Furthermore, this embodiment also sets up an atomic deletion operation. When the table deletion matching data in the received table deletion instruction is the same as the matching data corresponding to the target activation state bit, and the table deletion priority in the table deletion instruction is not less than the priority corresponding to the target activation state bit, the hardware logic deletes the data in the table entry corresponding to the target activation state bit. This realizes the aging operation of the table entry, reclaims storage space, reduces the impact of long-term unused table entries on the flow table management process, and improves management efficiency.

[0076] This embodiment also provides a flow table management device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0077] This embodiment provides a flow table management device, such as Figure 6 As shown, it includes:

[0078] The scanning module 601 is used to scan each activation status bit in the activation bitmap; each activation status bit corresponds one-to-one with an entry in the flow table pre-stored in the network chip; the flow table is used to store the processing data of the data packets received by the network chip.

[0079] The update module 602 is used to update each activation status bit in the activation bitmap according to preset conditions, so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table according to the updated activation bitmap; the preset conditions are used to indicate whether the data in the corresponding table entry of the activation status bit is activated.

[0080] In an alternative implementation, the update module is further configured to:

[0081] When the target activation state bit meets the preset conditions, the target activation state bit is updated to the first state; otherwise, the target activation state bit is updated to the second state; the target activation state bit is any one of the activation state bits.

[0082] In one optional implementation, the network chip's hardware logic fills the flow table with the processed data of the data packet based on the updated activation bitmap, including:

[0083] The hardware logic of this network chip acquires the data packet processing data;

[0084] When the target activation status bit is in the first state, the hardware logic of the network chip fills the processed data of the data packet into the entry in the flow table corresponding to the target activation status bit; when the target activation status bit is in the second state, the original entry is retained.

[0085] In one optional implementation, the flow table further includes a priority identifier, which indicates the priority of the corresponding processed data; the hardware logic of the network chip is also used for:

[0086] When the target activation state bit is in the first state, the hardware logic of the network chip compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data.

[0087] When the priority of new processing data is not less than the priority of the original processing data, the hardware logic of the network chip fills the new processing data into the entry in the flow table corresponding to the target activation state bit.

[0088] In one optional implementation, the processed data includes matching data and action data; the hardware logic of the network chip is also used for:

[0089] When the target activation state bit is in the second state, the hardware logic of the network chip compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data.

[0090] When the priority of new processed data is not lower than the priority of the original processed data, the hardware logic of the network chip compares the matching data in the new processed data with the matching data in the original processed data.

[0091] When the matching data in the new processing data is the same as the matching data in the original processing data, the hardware logic of the network chip fills the action data in the new processing data into the entry in the flow table corresponding to the target activation state bit.

[0092] In one alternative implementation, the hardware logic of the network chip is further used for:

[0093] Receive a table deletion command; the table deletion command includes the table matching data to be deleted and the table deletion priority.

[0094] Read the target activation status bit;

[0095] When the target activation state bit is in the first state, the hardware logic of the network chip compares the table deletion matching data in the table deletion instruction with the matching data corresponding to the target activation state bit, and compares the table deletion priority in the table deletion instruction with the priority corresponding to the target activation state bit.

[0096] When the data to be deleted in the table deletion instruction is the same as the data to be deleted corresponding to the target activation state bit, and the priority of the table deletion instruction is not less than the priority corresponding to the target activation state bit, the hardware logic of the network chip deletes the data in the table entry corresponding to the target activation state bit.

[0097] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0098] In this embodiment, the flow table management device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0099] This invention also provides a computer device having the above-described features. Figure 6 The flow table management device shown.

[0100] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 7As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0101] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0102] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0103] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0104] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0105] The computer device also includes an input device 30 and an output device 40. The processor 10, memory 20, input device 30, and output device 40 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0106] Input device 30 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the computer device, such as a touchscreen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 40 may include display devices, auxiliary lighting devices (e.g., LEDs), and haptic feedback devices (e.g., vibration motors). The aforementioned display devices include, but are not limited to, liquid crystal displays, light-emitting diodes, displays, and plasma displays. In some alternative embodiments, the display device may be a touchscreen.

[0107] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0108] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0109] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and all such modifications and variations fall within the protection scope of the present invention.

Claims

1. A flow table management method, characterized in that, Applied to network chips, the method includes: Scan each activation state bit in the activation bitmap; each activation state bit corresponds one-to-one with an entry in the flow table pre-stored in the network chip; the flow table is used to store the processing data of the data packets received by the network chip; The activation bitmap is updated according to preset conditions so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table according to the updated activation bitmap; the preset conditions are used to indicate whether the data in the corresponding table entry of the activation bit is activated. The step of updating each activation state bit in the activation bitmap according to preset conditions includes: When the target activation state bit meets the preset conditions, the target activation state bit is updated to the first state; otherwise, the target activation state bit is updated to the second state; the target activation state bit is any one of the activation state bits. The hardware logic of the network chip fills the processed data of the data packet into the flow table according to the updated activation bitmap, including: The hardware logic of the network chip acquires the data packet processing data; When the target activation state bit is in the first state, the hardware logic of the network chip fills the processed data of the data packet into the entry in the flow table corresponding to the target activation state bit; when the target activation state bit is in the second state, the original entry is retained. The flow table further includes a priority identifier, which indicates the priority of the corresponding processed data; the method further includes: When the target activation state bit is in the first state, the hardware logic of the network chip compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data. When the priority of new processing data is not less than the priority of the original processing data, the hardware logic of the network chip fills the new processing data into the entry in the flow table corresponding to the target activation state bit.

2. The method according to claim 1, characterized in that, The processed data includes matching data and action data; the method further includes: When the target activation state bit is in the second state, the hardware logic of the network chip compares the priority of the new processing data corresponding to the target activation state bit with the priority of the original processing data. When the priority of the new processing data is not lower than the priority of the original processing data, the hardware logic of the network chip compares the matching data in the new processing data with the matching data in the original processing data. When the matching data in the new processing data is the same as the matching data in the original processing data, the hardware logic of the network chip fills the action data in the new processing data into the entry in the flow table corresponding to the target activation state bit.

3. The method according to claim 2, characterized in that, The method further includes: Receive a table deletion command; the table deletion command includes the table deletion matching data and the table deletion priority. Read the target activation status bit; When the target activation state bit is in the first state, the hardware logic of the network chip compares the table deletion matching data in the table deletion instruction with the matching data corresponding to the target activation state bit, and compares the table deletion priority in the table deletion instruction with the priority corresponding to the target activation state bit. When the table deletion matching data in the table deletion instruction is the same as the matching data corresponding to the target activation state bit, and the table deletion priority in the table deletion instruction is not less than the priority corresponding to the target activation state bit, the hardware logic of the network chip deletes the data in the table entry corresponding to the target activation state bit.

4. A flow meter management device, characterized in that, The device, applied to network chips, includes: The scanning module is used to scan each activation state bit in the activation bitmap; the activation state bit corresponds one-to-one with the entries in the flow table pre-stored in the network chip; the flow table is used to store the processing data of the data packets received by the network chip, wherein the processing data includes matching data and action data, and the processing data corresponds one-to-one with the entries. The update module is used to update each activation status bit in the activation bitmap according to preset conditions, so that the hardware logic of the network chip can fill the processing data of the data packet into the flow table according to the updated activation bitmap; the preset conditions are used to indicate whether the data in the corresponding table entry of the activation status bit is activated. The update module is further configured to update the target activation state bit to a first state when the target activation state bit meets the preset conditions; otherwise, update the target activation state bit to a second state; the target activation state bit is any one of the activation state bits. The update module is further configured to: when the target activation state bit is in the first state, the hardware logic of the network chip fills the processed data of the data packet into the entry in the flow table corresponding to the target activation state bit; when the target activation state bit is in the second state, retain the original entry; when the target activation state bit is in the first state, the hardware logic of the network chip compares the priority of the new processed data corresponding to the target activation state bit with the priority of the original processed data; when the priority of the new processed data is not less than the priority of the original processed data, the hardware logic of the network chip fills the new processed data into the entry in the flow table corresponding to the target activation state bit.

5. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the flow table management method according to any one of claims 1 to 3 by executing the computer instructions.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the flow table management method according to any one of claims 1 to 3.

7. A computer program product, characterized in that, It includes computer instructions for causing a computer to perform the flow table management method according to any one of claims 1 to 3.

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