Image display method, electronic device, chip system, storage medium, and program product

Abstract

Embodiments of the present application provide an image display method, an electronic device, a chip system, a storage medium and a program product, relate to the technical field of terminals, and can reduce display abnormalities in a partial refresh process. The method comprises: when a first interface is displayed, an Xth MIPI data packet is obtained, a target region in the Xth MIPI data packet comprises n predefined data packets and Sth frame image data, and the target region is used to set a data packet carrying image data; based on the n predefined data packets, the first interface is switched to a second interface corresponding to the Sth frame image data; wherein the second interface has the same display content as the first interface in a first partial region, and the second interface has different display content from the first interface in a second partial region, the Sth frame image data is image data of the display content of the second partial region, and the n predefined data packets are used to indicate the first partial region.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to image display methods, electronic devices, chip systems, storage media, and program products. Background Technology

[0002] To reduce power consumption in electronic devices, during content updates, only the changed areas can be updated instead of refreshing the entire display. For example, if the content in a first area of ​​the display panel changes while the content in a second area remains unchanged, the electronic device can update only the content in the first area. During this process, the device's processor needs to transmit image data and commands to the display driver IC (DDIC). These commands can be used to indicate which first area needs to be refreshed.

[0003] However, this method may cause electronic devices to display abnormalities. Summary of the Invention

[0004] This application provides an image display method, an electronic device, a chip system, a storage medium, and a program product. During the partial refresh process of the electronic device, the processor can indicate the area that does not need to be refreshed to the DDIC through a predefined data packet (such as an empty packet) set in the active row. This can reduce display abnormalities caused by the untimely acquisition of the command to indicate the area that does not need to be refreshed, and improve the user experience.

[0005] In a first aspect, embodiments of this application propose an image display method applied to an electronic device. When the electronic device displays a first interface, it acquires the Xth MIPI data packet. The target area in the Xth Mobile Industry Processor Interface (MIPI) data packet includes n predefined data packets and Sth frame image data. The target area is used to set the data packet carrying image data, where n, X, and S are positive integers. Based on the n predefined data packets and the Sth frame image data, the electronic device switches the first interface to a second interface. The second interface displays the same content in the first part of the area as the first interface, and the second interface displays different content in the second part of the area as the first interface. The Sth frame image data is the image data of the content displayed in the second part of the second interface, and the n predefined data packets are used to indicate the first part of the area.

[0006] It should be understood that MIPI data packets can also be called MIPI DSI data packets or MIPI video data packets. X and S can be the same or different. The Xth MIPI data packet is related to the following... Figure 7The format of the MIPI DSI data packets shown is similar, and the target area can be understood as the active row or active area in the following text. n predefined data packets can be one or more predefined data packets. For example, if the image data of the S-th frame is the image data of the M+1-th frame in the following text, then the first interface can be... Figure 4 The interface in (a) is the second interface. Figure 4 The interface (b) in the image. The second part of the area is, for example, the area occupied by the pixels in rows y1 to y2 of the display panel. The first part of the area is, for example, the area outside the second part of the area, such as the area occupied by the pixels in rows 1 to y1-1 of the display panel; and the area occupied by the pixels in rows y2+1 to the last row of the display panel.

[0007] The image display method of this application can indicate areas that do not need to be refreshed (rows that do not need to be refreshed) through a predefined data packet set in the target area of ​​the MIPI data packet. In this way, DDIC does not need to obtain commands from the processor to indicate the rectangular areas that need to be refreshed, which can reduce display anomalies caused by failure to obtain commands indicating the rectangular areas that need to be refreshed in a timely manner, and improve the user experience.

[0008] In one possible implementation, the S-frame image data includes image data corresponding to at least one row of pixels, and the target region includes image data corresponding to each row of pixels in at least one row of pixels and a first type data packet; the target region also includes a first type data packet corresponding to each of the n predefined data packets.

[0009] The image data of the Sth frame, including image data corresponding to at least one row of pixels, can also be understood as: the target area in the Xth MIPI data packet includes image data corresponding to at least one row of pixels. At least one row of pixels can be understood as each row of pixels in the display panel. The image data corresponding to each row of pixels can be RGB data. The image data corresponding to at least one row of pixels can be... Figure 7 The RGB data corresponding to each pixel in rows y1 to y2, set in the active row. The first type of data packet can be one or more data packets. The first type of data packet can be a data packet defined by a protocol (e.g., the MIPI communication protocol).

[0010] This makes the data packet format of the rows that do not need to be refreshed similar to that of the rows that need to be refreshed, which makes it easier for DDIC to identify the data packets of the rows that do not need to be refreshed. Thus, based on the identified predefined data packets and the first type of data packets, it can determine the rows (non-refresh areas) that do not need to be refreshed.

[0011] In one possible implementation, the first type of data packet includes one or more of the following: Horizontal Synchronization Start (HSS) data packet, Horizontal Trailing Edge (HBP) data packet, or Horizontal Leading Edge (HFP) data packet.

[0012] That is, the image data and the first type of data packet corresponding to each row of pixels in at least one row can be: Figure 7 The active row is configured with RGB data, HSS data packets, HBP data packets, and HFP data packets corresponding to each pixel in rows y1 to y2. The first type of data packet corresponding to each of the n predefined data packets can be: Figure 7 The predefined data packets, HSS data packets, HBP data packets, and HFP data packets set in the active row, from row 1 to row y1-1; or the predefined data packets, HSS data packets, HBP data packets, and HFP data packets set from row y2+1 to the last row.

[0013] This makes it easier for DDIC to determine the rows that do not need to be refreshed, and to determine the start time of each row in the rows that need to be refreshed.

[0014] In one possible implementation, the first part of the region includes n consecutive regions, each of the n consecutive regions being a region corresponding to at least one row of consecutive pixels, and n predefined data packets corresponding one-to-one with the n consecutive regions.

[0015] Where n is an integer of 1 or greater than 1. When n is 1, it means that the continuous area formed from one row to another in the display panel is an area where the displayed content does not change, that is, a non-refreshing area. n continuous areas can also be two continuous areas, for example, rows 1 to y1-1 in the following text, which is a continuous area; and rows y2+1 to the last row, which is also a continuous area. Each continuous area corresponds to a predefined data packet, and each predefined data packet is used to indicate the corresponding continuous area. For example, if the n continuous areas are rows 1 to y1-1 and rows y2+1 to the last row in the following text, then the n predefined data packets can be... Figure 7 The predefined data packets corresponding to rows 1 to y1-1 and rows y2+1 to the last row are in the data packet format.

[0016] In this way, DDIC can determine the non-refresh area based on each predefined data packet, and thus not refresh at the (row) position indicated by each predefined data packet.

[0017] In one possible implementation, the first predefined data packet among n predefined data packets is used to indicate the first continuous region in n continuous regions. The first continuous region is the region corresponding to the pixels in rows l1 to l2 of the display screen. The first predefined data packet carries information for indicating rows l1 to l2, where l1 and l2 are positive integers.

[0018] For example, l1 can be 1, l2 can be y1, then the first predefined data packet can be Figure 7 The predefined data packets corresponding to rows 1 to y1-1 in the display panel, where the first continuous area is the region occupied by pixels in row 1 to y1-1 in the display panel; or, l1 can be y2+1, and l2 can be the row number of the last row, then the first predefined data packet can be... Figure 7 The predefined data packets corresponding to the y2+1th row to the last row are defined as follows: the first continuous area is the area occupied by the pixels in the y2+1th row to the last row in the display panel.

[0019] In this way, DDIC can determine which rows do not need to be refreshed based on each predefined data packet.

[0020] In one possible implementation, the information used to indicate lines l1 to l2 is the word count WC in the header of the first predefined data packet.

[0021] This allows DDIC to determine which rows do not need to be refreshed by parsing predefined data packets.

[0022] In one possible implementation, the electronic device includes a processor, a display driver integrated circuit (DDIC), and a display panel; acquiring the Xth MIPI data packet includes: the DDIC receiving the Xth MIPI data packet from the processor and parsing the Xth MIPI data packet; the DDIC determining that the target area in the Xth MIPI data packet includes n predefined data packets; switching the first interface to the second interface corresponding to the Sth frame image data includes: the DDIC instructing the display panel to refresh the second part of the area based on the n predefined data packets and the Sth frame image data; based on the refresh of the second part of the area, the display panel displays the second interface, and the second part of the second interface displays the Sth frame image data.

[0023] The first interface is, for example, Figure 4 The interface in (a) is, for example, the second interface is Figure 4 The interface (b) is shown above. The implementation method is similar to S1007 to S1013 in method 1000. Then the Xth MIPI data packet can be MIPI DSI data packet 2; the n predefined data packets are 2 predefined data packets. The second part of the region is row y1 to row y2.

[0024] In this way, the processor can indicate the rows that DDIC does not need to be refreshed through predefined data packets, which can reduce display anomalies caused by DDIC not receiving commands from the processor (commands indicating the rectangular areas that need to be refreshed) in a timely manner.

[0025] In one possible implementation, the DDIC emits a tearing effect TE signal based on the lowest refresh rate supported by the display panel; the method further includes: when displaying the second interface, the processor detects the TE signal and transmits the (X+1)th MIPI data packet to the DDIC based on the TE signal, wherein the target area of ​​the (X+1)th MIPI data packet includes the (S+1)th frame image data, and the (S+1)th frame image data includes the image data corresponding to each row of pixels in the display panel; based on the (S+1)th frame image data, the DDIC instructs the display panel to refresh each row of pixels; based on the refresh of each row of pixels, the display panel displays a third interface corresponding to the (X+1)th frame image data, and the content displayed on the third interface is the same as that displayed on a portion of the second interface.

[0026] The second interface, for example, can Figure 4 The interface (d) in the text, but it differs from the one described below in that... Figure 4 If the interface (d) is displayed using a partial refresh method, then the first interface does not have to be... Figure 4 The interface (c) in the middle. The third interface can be Figure 11 The interface shown. The (X+1)th MIPI data packet can be MIPI DSI data packet 3 in S1018. The (S+1)th frame image data can be the (M+4)th frame image data. Refreshing each row of pixels means refreshing all rows. The above implementation is similar to the implementation of S1014 to S1021 in method 1000.

[0027] In this way, the processor of the electronic device can transmit complete image data to the DDIC based on the detected TE signal, enabling the display screen to refresh at the lowest refresh rate.

[0028] In one possible implementation, the target area is the active row.

[0029] The active line can also be called the active region. For frames that require partial refresh, the active line can include both non-refreshing and refreshed regions.

[0030] In one possible implementation, the n predefined data packets are n empty packets.

[0031] In this way, an empty packet is a type of data packet defined by the existing protocol, which allows electronic devices to indicate areas that do not need to be refreshed using existing data packets, without the need to define new types of data packets.

[0032] Secondly, embodiments of this application provide an image display device, which may be an electronic device, or a chip or chip system within an electronic device. The image display device may include a display unit and a processing unit. When the image display device is an electronic device, the display unit may be a display screen. The display unit is used to perform display steps to enable the electronic device to implement an image display method described in the first aspect or any possible implementation of the first aspect. When the image display device is an electronic device, the processing unit may be a processor. The image display device may further include a storage unit, which may be a memory. The storage unit is used to store instructions, and the processing unit executes the instructions stored in the storage unit to enable the electronic device to implement an image display method described in the first aspect or any possible implementation of the first aspect. When the image display device is a chip or chip system within an electronic device, the processing unit may be a processor. The processing unit executes the instructions stored in the storage unit to enable the electronic device to implement an image display method described in the first aspect or any possible implementation of the first aspect. The storage unit can be a storage unit inside the chip (e.g., a register, cache, etc.) or a storage unit located outside the chip within the electronic device (e.g., a read-only memory, random access memory, etc.).

[0033] For example, a display unit is used to display a first interface or a second interface.

[0034] Thirdly, embodiments of this application provide an electronic device including a processor and a memory, the memory for storing code instructions, and the processor for running the code instructions to perform the methods described in the first aspect or any possible implementation of the first aspect.

[0035] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program or instructions that, when executed on a computer, cause the computer to perform the methods described in the first aspect or any possible implementation thereof.

[0036] Fifthly, embodiments of this application provide a computer program product including a computer program, which, when run on a computer, causes the computer to perform the methods described in the first aspect or any possible implementation of the first aspect.

[0037] Sixthly, this application provides a chip or chip system including at least one processor and a communication interface. The communication interface and the at least one processor are interconnected via a circuit. The at least one processor is used to run computer programs or instructions to perform the methods described in the first aspect or any possible implementation of the first aspect. The communication interface in the chip can be an input / output interface, pins, or circuits, etc.

[0038] In one possible implementation, the chip or chip system described above in this application further includes at least one memory storing instructions. The memory can be an internal storage unit of the chip, such as a register or cache, or it can be a storage unit of the chip itself (e.g., read-only memory, random access memory, etc.).

[0039] It should be understood that the second to sixth aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a partial refresh process;

[0041] Figure 2 This is a schematic diagram illustrating the process of two display methods;

[0042] Figure 3 This is a timing diagram of a display system;

[0043] Figure 4 A schematic diagram of an image display process;

[0044] Figure 5 This is a schematic diagram of a MIPI DSI data packet format;

[0045] Figure 6 This is a timing diagram of another display system provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram illustrating another MIPI DSI data packet format provided in an embodiment of this application;

[0047] Figure 8 A schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application;

[0048] Figure 9 A schematic diagram illustrating the software and hardware interaction process of the electronic device provided in the embodiments of this application;

[0049] Figure 10 A flowchart illustrating an image display method provided in an embodiment of this application;

[0050] Figure 11 A schematic diagram of a display interface provided in an embodiment of this application;

[0051] Figure 12 This application provides a schematic diagram illustrating the process by which DDIC determines areas that do not require refreshing.

[0052] Figure 13 A schematic block diagram of an image display device provided in an embodiment of this application. Detailed Implementation

[0053] To facilitate a clear description of the technical solutions in the embodiments of this application, some terms and technologies involved in the embodiments of this application will be briefly introduced below:

[0054] 1. Display driver integrated circuit (DDIC)

[0055] It is a key component in the display system, responsible for controlling the pixels of the display panel. DDICs are typically integrated inside the display panel and directly connected to the display's pixel array. Its main functions include:

[0056] Signal conversion: In the future, digital signals from autonomous processors or graphics processing units (GPUs) will be converted into signals that the display screen can understand.

[0057] Timing control: Manages the scanning timing of the display screen to ensure that the image is displayed correctly.

[0058] Voltage control: Adjusts the voltage required to drive the display screen to ensure the stability and consistency of the display effect.

[0059] 2. Graphics RAM (GRAM)

[0060] It is a memory used to store display data. It is typically built into the DDIC or tightly coupled to it. The main functions of GRAM include:

[0061] Data storage: Stores image data transferred from the main processor or GPU.

[0062] Data buffer: It plays a buffering role in the process of display data transmission, ensuring that data can be transmitted to the display screen smoothly.

[0063] Fast access: Provides fast read and write speeds to meet the needs of real-time display.

[0064] 3. Line controller

[0065] It is a key component in the display system, responsible for managing and controlling the data transmission of rows on the display screen. Its main functions include:

[0066] Line data transmission: Controls the transmission of each line of pixel data, ensuring that the data is transmitted to the display screen in sequence.

[0067] Timing control: Manages the row scanning timing of the display screen to ensure that each row of data is transmitted to the display screen at the correct time.

[0068] Signal conditioning: Conditioning and buffering the line data signal to suit the characteristics of the display screen.

[0069] 4. AND Gate

[0070] It is one of the basic components in digital logic circuits. It implements the logical AND operation, and the output is high (1) only when all input signals are high (1); otherwise, the output is low (0). In display systems, ANDGate can be used for the generation of control signals and logical judgments.

[0071] 5. Line Cache (IC Line Cache)

[0072] A line buffer is a memory used to temporarily store rows of data, typically used in image processing and display systems. Its main function is to buffer data to enable smooth data transfer between different processing stages. Line buffers can help reduce data transfer latency and improve the efficiency of display systems.

[0073] 6. Clock

[0074] A clock signal is a signal used for synchronization in digital circuits. It is typically a periodically changing square wave used to coordinate the operation of various parts of the circuit. In display systems, clock signals are used to synchronize data transmission and processing, ensuring that components operate according to a predetermined timing sequence.

[0075] The clock signal changes periodically at a fixed frequency, and the line controller uses this clock signal to synchronize data transmission.

[0076] Each clock cycle, the Line controller checks whether the next line of data needs to be transmitted. The inputs of the AND Gate can be connected to the Clock signal and the Enable signal. The output of the AND Gate is high only when both the Clock and Enable signals are high. The Line controller receives the output signal of the AND Gate and transmits the next line of data when the output signal is high.

[0077] 7. Mobile Industry Processor Interface (MIPI): This can refer to protocols used to define various interfaces within a terminal device. These interfaces may include, but are not limited to, one or two of the following: Camera Serial Interface (CSI), Display Serial Interface (DSI), Digital Radio Frequency Interface (DigRF), or Scalable Low-Power Inter-Microcontroller Bus (SLIMbus), etc.

[0078] 8. Partial refresh technology

[0079] Partial refresh is an optimization technology for displays designed to reduce power consumption and improve refresh efficiency. It saves resources and extends battery life by updating only the areas of the screen that have changed, rather than refreshing the entire screen. Partial refresh technology is widely used in devices such as e-book readers, smartwatches, and smartphones.

[0080] 9. Command mode (CMD mode)

[0081] CMD mode is a mode that controls the display's updates and operation by sending commands. Instead of continuously refreshing the screen, CMD mode updates the displayed content through intermittent image data transmission and commands.

[0082] 10. Video mode

[0083] This is a mode that displays content by continuously refreshing the screen. In this mode, image data is constantly transferred from the frame buffer to the display side to keep the screen content updated. Video mode is typically used for applications that require high refresh rates and low latency, such as video playback, games, and animations.

[0084] 11. Frame buffer

[0085] The frame buffer is a memory area that stores the image data currently displayed on the screen. It typically consists of pixel data generated by the graphics processing unit (GPU) or the central processing unit (CPU). The frame buffer is usually located in the memory inside the system on-chip (SOC), or it may be located in a separate video memory (such as GDDR5 or GDDR6) and managed by a separate GPU.

[0086] 12. Vertical Front Porch (VFP)

[0087] It is part of the display refresh cycle, preceding the vertical sync signal (VSYNC). During this period, the display does not show any valid image data and can be used to transmit and process display commands from the SOC.

[0088] It should be understood that display commands, also known simply as commands, can be used to control various operations on the display screen, such as updating partial screen content (e.g., information used in partial refresh to indicate the rectangular area that needs to be refreshed), adjusting display parameters, etc. For the sake of brevity, this will not be elaborated upon further below.

[0089] 13. Empty packet

[0090] In the MIPI DSI protocol, an empty packet is a special type of data packet, typically used for the following purposes:

[0091] Timing padding: During data transmission, empty packets are used to fill idle time periods to maintain the timing and synchronization of data transmission; Bandwidth management: By inserting empty packets, the bandwidth of data transmission can be controlled to avoid excessive occupation of the transmission channel; Power consumption optimization: Inserting empty packets in areas where the display content does not need to be refreshed can reduce unnecessary data transmission, thereby reducing power consumption.

[0092] 14. Refresh Rate: Also known as screen refresh rate. It is a hardware performance parameter of the display screen of an electronic device, referring to the number of times the display screen can refresh per second, and the unit can be Hertz (Hz), etc. For example, the refresh rate of a terminal device can be a Hz, which means that the graphics card outputs a signals to the display screen a times per second, where a is a positive integer.

[0093] It can be understood that the display panel of an electronic device is filled with physical pixels. For example, if each row of the display panel contains A pixels and each column contains B pixels, then the resolution of the display panel is A×B. Displaying A pixels in one row is called a row scan, and displaying B rows of pixels is called a field scan. The display can scan one field of physical pixels in response to a vertical synchronization (Vsync) signal. Scanning one field of physical pixels allows the display to show one frame of image data. The display completes scanning one field of physical pixels within one Vsync signal cycle, meaning the display can show one frame of image data within one Vsync signal cycle. One Vsync signal cycle can also be called the field synchronization period.

[0094] 15. The tearing effect (TE) signal, also known as the Fmark signal, is a synchronization signal that can be understood as a pulse signal. The TE signal is generated and emitted by a specific module in the display driver integrated circuit (DDIC). This module is often referred to as the timing controller (TCON) module.

[0095] 16. Command receiver processor (RX) and core controller.

[0096] The command receive processor and core controller are two key components in the DDIC, playing crucial roles in data reception, processing, and control. The following is a detailed explanation of these two components:

[0097] The command receiver processor (RX) is the command processor at the receiving end, primarily responsible for receiving and processing commands and data packets sent from the System-on-Chips (SoC). Its specific functions are as follows:

[0098] Command reception: The command receiving processor receives commands and data packets transmitted through the MIPI DSI interface; Command parsing: Parses the received commands to determine the command type and parameters; Data processing: According to the command type, the received data is processed accordingly, such as writing to registers, reading from registers, updating display content, etc.

[0099] The core controller is responsible for managing and coordinating the various subsystems and modules within the display system. Its specific functions include: System Management: Managing the overall operation of the display system, including initialization, configuration, and control; Timing Control: Controlling the timing of the display system, including line timing and frame timing, ensuring image data is transmitted and displayed in the correct timing sequence; Resource Scheduling: Scheduling and allocating resources within the display system, such as memory and processing units, to ensure the efficient operation of each subsystem; Status Monitoring: Monitoring the status of the display system, detecting and handling anomalies, and ensuring system stability and reliability.

[0100] 17. Video timing control module, also known as timing control (TCON) module.

[0101] It is a key component in DDIC, responsible for generating and managing the timing signals required by the display screen. The main functions of the TCON module include: timing signal generation: generating timing signals such as horizontal sync signal (HSYNC), vertical sync signal (VSYNC), and data enable signal (DE).

[0102] 18. Gate-on-array integrated circuit, also known as array gate driver.

[0103] GOA (Gate Actuation) is a gate driving technology used in display panels, particularly in thin-film transistor liquid crystal displays (TFT-LCDs) and active-matrix organic light-emitting diode (AMOLED) displays. GOA technology integrates the gate driving circuitry onto the glass substrate of the display panel, thereby reducing the need for external driver ICs and lowering costs and complexity.

[0104] 19. Other terms

[0105] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with substantially the same function and purpose. For example, "first chip" and "second chip" are used only to distinguish different chips and do not limit their order of execution. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply that they are different.

[0106] It should be noted that, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0107] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, a--c, bc, or abc, where a, b, and c can be single or multiple.

[0108] 20. Electronic equipment

[0109] The electronic devices in this application embodiment may include handheld devices with facial recognition function, vehicle-mounted devices, etc. For example, some electronic devices include: mobile phones, tablets, PDAs, laptops, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in 5G networks, or future evolution of public land mobile communication networks. Terminal devices in a network (PLMN), etc., are not limited to this in the embodiments of this application.

[0110] By way of example and not limitation, in this embodiment, the electronic device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0111] Furthermore, in this embodiment of the application, the electronic device can also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network of human-machine interconnection and object-to-object interconnection.

[0112] The electronic devices in the embodiments of this application may also be referred to as: terminal equipment, user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device, etc.

[0113] In this embodiment, the electronic device or various network devices include a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on top of the operating system layer. The hardware layer includes hardware such as a central processing unit (CPU), a memory management unit (MMU), and memory (also called main memory). The operating system can be any one or more computer operating systems that implement business processing through processes, such as Linux, Unix, Android, iOS, or Windows. The application layer includes applications such as browsers, address books, word processing software, and instant messaging software.

[0114] The terminal device display interface includes processes for acquiring image data and displaying the image data through a display screen. For example, the terminal device may include a processor, a display driver IC (DDIC), and a display panel. The display driver IC (DDIC) and display panel can be understood, for example, as a display screen.

[0115] Image data can typically be synthesized by a processor in a terminal device. A processor can also be called a system-on-a-chip (SOC) or a front-end SOC. SOCs can include, but are not limited to, application processors (APs), graphics processing units (GPUs), and general-purpose processors. For example, an SOC can synthesize image data using a GPU; the DDIC can acquire the image data synthesized by the processor and display it through a display panel.

[0116] To reduce the power consumption of terminal devices, current terminal devices can refresh the displayed content using partial refresh technology.

[0117] For example, suppose the interface of the terminal device displaying the image data of frame A is as follows: Figure 1 The interface shown in (a) is as follows. The interface of the terminal device displaying the image data of frame A+1 is shown in... Figure 1 The interface shown in (b) is shown. A can be a positive integer.

[0118] Compared to interface (a), the updated area in interface (b) includes the pixels occupied by the heart-shaped element 101. Assume the terminal device display includes... The number of pixels is 29 rows and 15 columns. Therefore, the heart shape 101 occupies pixels from rows 8 to 16 and from columns 2 to 14.

[0119] During the process of SOC synthesizing the A+1th frame image data, it can combine the Ath frame image data to determine the regions where the A+1th frame image data has changed compared to the Ath frame image data. Furthermore, SOC can synthesize and transmit the image data of the changed regions to DDIC. Therefore, the M+1th frame image data transmitted by SOC to DDIC can be the data corresponding to pixels in rows 8-16 and columns 2-14.

[0120] Furthermore, the SOC can also instruct the DDIC to refresh the rectangular area via command 1. Command 1 can include, for example, x1, x2, y1, and y2. Assuming the top-left corner of the rectangular area to be refreshed is point A, and the bottom-right corner is point B, then in the screen coordinate system, the coordinates of point A are (x1, y1) and the coordinates of point B are (x2, y2). Therefore, the horizontal coordinate range of the rectangular area to be refreshed is x1 to x2, and the vertical coordinate range is y1 to y2. Thus, the rectangular area to be refreshed could be column x1 to column x2 and row y1 to row y2.

[0121] Combination Figure 1For example, if the coordinates of point A are (2, 8) and the coordinates of point B are (14, 16), then the rectangular area that needs to be refreshed is columns 2 to 8 and rows 8 to 16.

[0122] It should be understood that the coordinate system in the display screen of a terminal device can be called the screen coordinate system, which is a coordinate system used to position elements such as graphics or text on the terminal device's display screen. The origin of the screen coordinate system can be, for example, the upper left corner of the screen, the x-axis can be a horizontal axis pointing to the right side of the display screen, and the y-axis can be a vertical axis pointing to the bottom of the display screen. This application does not make specific limitations in this regard.

[0123] Currently, in partial refresh technology, DDIC typically refreshes the entire row of pixels, rather than just a portion of a row. Therefore, terminal devices... Figure 1 During the transition from interface (a) to interface (b), DDIC can refresh the entire row of pixels in rows 8-16. That is, although the pixels that change are in rows 8-16 and columns 2-14, DDIC will still refresh the entire row of pixels in rows 8-16.

[0124] Continue to combine Figure 1 A line buffer can be integrated into the DDIC, which can also be called an IC line buffer. It can temporarily buffer the line data obtained from the SOC, that is, the image data of each line in lines 8-16. The clock signal can be used to trigger the line controller in the DDIC to read the image data of each line in lines 8-16 from the line buffer. The line controller controls the AND gate to generate a control signal, and drives the line pixels of the display panel through the control signal, so that the 8-16 line pixels on the display panel are updated, so that the electronic device display screen switches from display interface (a) to display interface (b).

[0125] As can be seen from the above process, in the process of displaying an image using partial refresh technology, the SOC needs to transmit image data and commands to the DDIC to indicate the rectangular area that needs to be refreshed.

[0126] It should be understood that, for ease of description, the command used to indicate the rectangular area that needs to be refreshed will be referred to as the refresh area command in the following text. This will not be elaborated upon further below.

[0127] Currently, SoCs and displays typically communicate via the MIPI communication protocol. For liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, the MIPI protocol defines two communication modes: command (CMD) mode and video mode. These two modes differ significantly in image data transmission and display refresh mechanisms.

[0128] like Figure 2 As shown, in CMD mode, the SOC can write the synthesized image data and commands into the DDIC's GRAM through interfaces such as DSI defined by the MIPI communication protocol; the DDIC can then refresh the image data in the GRAM onto the display panel based on the commands.

[0129] In this mode, the display screen refreshes intermittently, and the timing of the DDIC brushing image data from the GRAM to the display panel and the timing of the SOC writing image data to the GRAM may not be completely synchronized.

[0130] In video mode, the image data and commands synthesized by the SOC are not written to the GRAM of the DDIC, but are directly brushed onto the display panel by the DDIC for display.

[0131] In this mode, the display refresh is continuous; that is, the DDIC continuously reads image data from the frame buffer and refreshes the read image data to the display panel. To improve display stability and synchronization, the DDIC typically receives and processes commands (CMDs) from the SOC within a specific time period, which is usually the vertical front porch (VFP) period.

[0132] For example, Figure 3 This is a schematic diagram of the timing of a display system. For example... Figure 3 As shown, the SOC can emit a vertical synchronization (Vsync) signal, and the DDIC can receive the Vsync signal emitted by the SOC. In this way, the SOC can transmit image data and commands to the DDIC based on the Vsync signal, and the DDIC can receive image data and commands from the SOC based on the Vsync signal.

[0133] Figure 3The timing diagram shows the sequence from the Nth Vsync cycle to the (N+3rd)th Vsync cycle. A Vsync cycle can also be understood as a refresh cycle or a frame. Within each Vsync cycle, the DDIC can refresh one frame of image data. For example, in the Nth Vsync cycle, the DDIC can acquire and refresh the Mth frame of image data onto the display panel; in the (N+1th)th Vsync cycle, the DDIC can acquire and refresh the (M+1th)th frame of image data onto the display panel; in the (N+2nd)th Vsync cycle, the DDIC can acquire and refresh the (M+2nd)th frame of image data onto the display panel; and in the (N+3rd)th Vsync cycle, the DDIC can acquire and refresh the (M+3rd)th frame of image data onto the display panel.

[0134] also, Figure 3 The diagram illustrates waveforms for various signals, each with a different function. Specifically, VS represents the Vsync signal; SOC MIPI represents the Vsync signal emitted by the SOC; and DDIC MIPI represents the Vsync signal received by the DDIC. These three can be the same.

[0135] DE is a waveform diagram of the data enable (DE) signal. The DE signal is a control signal, and the SOC can, for example, transmit image data to the DDIC based on the DE signal.

[0136] GOA_EN_N can be understood as a waveform diagram of the gate on array enable negative (GOA_EN_N) signal. The GOA_EN_N signal enables or disables the negative portion of the GOA circuit. For example, when the GOA_EN_N signal is high, the negative portion of the GOA circuit is enabled. GOA_EN_P can be understood as a waveform diagram of the gate on array enable positive (GOA_EN_P) signal. The GOA_EN_P signal enables or disables the positive portion of the GOA circuit. For example, when the GOA_EN_P signal is low, the positive portion of the GOA circuit is enabled. For example, when GOA_EN_P is low and GOA_EN_N is high, it indicates that the GOA circuit is enabled, allowing the DDIC to send data to the display panel when GOA_EN_P is low and GOA_EN_N is high.

[0137] It should be understood that the DDIC can enable the GOA circuit based on the DE signal or a refresh region command. For example, considering the timing of the (N+1)th Vsync cycle, since no refresh region command was received from the SOC in the VFP of the Nth Vsync cycle, the GOA_EN_N and GOA_EN_P signals change with the DE signal in the (N+1)th Vsync cycle. That is, when the DE signal switches from low to high, the GOA circuit is enabled, causing one of the GOA_EN_P signals to be high and the other to be low, so that the display performs a full-screen refresh (refreshing from the first row of pixels to the last row of pixels). In the (N+2)th Vsync cycle, since the DDIC received a refresh region command in the VFP of the (N+1)th Vsync cycle, for example, an instruction to refresh rows y1 to y2. Then, DDIC enables the GOA circuit at the time corresponding to row y1, meaning the GOA_EN_P and GOA_EN_N signals are one high and one low, causing the display to refresh from row y1 onwards. After row y2, the GOA circuit is disabled, and the GOA_EN_P and GOA_EN_N signals are no longer one high and one low, preventing the display from refreshing the area after row y2. EM can be understood, for example, as a control signal for the emission time.

[0138] Based on the waveform diagram of the Vsync signal in SOC MIPI, each Vsync cycle, in chronological order, includes: the effective time period of the vertical sync signal (VSA), the vertical back porch (VBP), the active region, and the VFP. VSA, VBP, the active region, and VFP can represent different time periods, with the unit being a line. Therefore, VSA can be called a VSA region or a VSA line; VBP can be called a VBP region or a VBP line; the active region can be called active or active lines; and VFP can be called a VFP region or a VFP line.

[0139] During the VSA and VBP time periods, DDIC may not refresh the display panel or transmit valid image data, such as red, green, and blue (RGB) data; the active row may transmit valid image data; and VFP may be used to transmit commands, such as refresh area commands.

[0140] It is understandable that, for a Vsync cycle, the SOC can indicate different time periods (VSA line, VBP line, active line, and VFP line) to the DDIC through different data packets. For example, within each Vsync cycle, the SOC can indicate a complete frame of display data through MIPI DSI data packets. MIPI DSI data packets can include various different data packets.

[0141] For example, assuming the DDIC refresh rate of the display panel is 120Hz and one Vsync cycle is 8.3ms, the format of the MIPI DSI data packet corresponding to one Vsync cycle can be as follows: Figure 5 As shown in the diagram, the VSA line includes a Vertical Sync Start (VSS) packet, indicating the start of the vertical sync signal. This packet can be used to indicate the end of one frame and the start of the next. The VSA line also includes a Blanking Link Layer (BLLP) packet following the VSS packet. BLLP packets are used to transmit idle time periods; these packets do not contain valid image data and are used to maintain timing continuity. The VSA line also includes a Horizontal Sync Start (HSS) packet, which indicates the start of the horizontal sync signal, signifying the end of one line of image data and the start of the next. Therefore, multiple cyclically repeated BLLP and HSS packets can represent multiple idle time periods.

[0142] VBP lines consist of multiple cyclically repeated HSS packets and BLLPs, representing multiple idle time periods.

[0143] The active row is used to set valid image data, such as RGB data. In cases requiring full-screen refresh, the active row of the MIPI DSI data packet transmitted by the SOC to the DDIC includes image data from row 1 to the last row, allowing the row buffer in the DDIC to cache the image data from row 1 to the last row.

[0144] It is understood that, in this application, rows L1 to L2 can be interpreted as pixels in rows L1 to L2 of the display panel. For the sake of simplicity, this will not be elaborated further in this application.

[0145] In cases requiring partial refresh, the active row of the MIPI DSI data packet transmitted by the SOC to the DDIC includes image data for the refresh area (the row to be refreshed), such as the image data for rows y1 to y2, allowing the row buffer in the DDIC to cache the image data for rows y1 to y2. Taking partial refresh with the refresh area being rows y1 to y2 as an example (e.g., the N+1th Vsync cycle), the data packets included in the active row are as follows: HSS data packets and BLLPs for each row from row 1 to row y1-1, HSS data packets, horizontal back porch (HBP) data packets, RGB data, and horizontal front porch (HFP) data packets for each row from row y1 to y2, and HSS data packets and BLLPs for each row from row y2+1 to the last row. Here, HBP can be understood as the time period during which the DDIC prepares to acquire the next row of image data; HFP can be understood as the time period used for synchronizing and stabilizing the display.

[0146] VFP lines typically include HSS packets and BLLPs that are repeatedly set multiple times in a cycle, as well as the longest prefix match (LPM) and VSS packets located at the end.

[0147] The VFP, as indicated by the black square, is located relatively late in the Vsync cycle. Before the VFP, the SOC has typically already transmitted valid image data to the DDIC.

[0148] For example, before the VFP in the Nth Vsync cycle, the SOC has already transmitted the Mth frame image data to the DDIC in the active line, where M and N can be the same or different; before the VFP in the N+1th Vsync cycle, the SOC has already transmitted the M+1th frame image data to the DDIC in the active line; before the VFP in the N+2th Vsync cycle, the SOC has already transmitted the M+2th frame image data to the DDIC in the active line; before the VFP in the N+3th Vsync cycle, the SOC has already transmitted the M+3rd frame image data to the DDIC in the active line.

[0149] Furthermore, within the VFP, the SOC can transmit commands to the DDIC. For the DDIC to display the next frame of image data according to the SOC's instructions, the SOC needs to obtain the command corresponding to the next frame of image data before the DDIC does so.

[0150] For example, combined Figure 4Suppose an electronic device displays interface (a) in the Nth Vsync cycle and needs to display interface (b) in the (N+1)th Vsync cycle. The System-on-Chief Interface (SOC) can determine the area in interface (b) that has changed compared to interface (a), for example, pixels in rows y1 to y2. Therefore, before transmitting the (M+1)th frame image data corresponding to interface (b) to the DDIC, the SOC needs to indicate the refresh area (i.e., the rectangular area to be refreshed) to the DDIC. Thus, the SOC needs to send the command corresponding to the (N+1)th Vsync cycle to the DDIC via the VFP in the Nth Vsync cycle. This command can include, for example, x1, x2, y1, and y2, so that the DDIC can determine the rectangular area to be refreshed in the (N+1)th Vsync cycle.

[0151] However, combined Figure 3 Because the VFP duration is short, and the SOC may need to send multiple commands to the DDIC within the VFP, such as dimming commands, the SOC may prioritize sending higher-priority commands to the DDIC during the Nth Vsync cycle of the VFP. This means that the SOC might not send a refresh region command to the DDIC during the Nth Vsync cycle of the VFP. Conversely, the refresh region command might be sent to the DDIC during the (N+1)th Vsync cycle of the VFP.

[0152] Thus, continue combining Figure 3 During the (N+1)th Vsync cycle, the GOA_EN_N and GOA_EN_P signals, based on the DE signal, are initially low and high, respectively, at the beginning of the active row. This causes the display to refresh starting from the first row.

[0153] And combined Figure 4 The M+1th frame of image transmitted from SOC to DDIC is not a complete frame of image data; that is, SOC did not transmit the image data from row 1 to row y1-1 corresponding to interface (b) to DDIC. This makes the combination of... Figure 5 The format of the data packets shown indicates that pixels in rows 1 to y1-1 of the active row correspond to HSS data packets and BLLP, causing the line buffer to not cache image data from rows 1 to y1-1 of frame M+1. Since the line buffer may have cached the last row of image data from frame M, rows 1 to y1-1 of the display panel are overwritten with the last row of image data from frame M. This results in the actual image displayed on the display panel... Figure 4 In the interface (f), the area corresponding to the first row to the y1-1th row repeatedly displays the content corresponding to the last row of pixels in the interface (e).

[0154] In addition, combined Figure 5The active area shown contains the RGB data corresponding to rows y1 and y2. The row buffer caches the image data for rows y1 and y2, causing the image data for rows y1 and y2 of the (M+1)th frame to be overlaid on the display panel. This results in the actual image displayed on the display panel being... Figure 4 In the interface (f), rows y1 to y2 display the image data of frame M+1.

[0155] Similarly, combined Figure 5 In the active area shown, the HSS and BLLP corresponding to rows y2+1 to the last row are not transmitted from the SOC to the DDIC from row y2+1 to the last row of the M+1 frame image data. This means the line buffer does not cache row y2+1 to the last row of the M+1 frame image data. Consequently, row y2+1 to the last row of the M+1 frame image data is overwritten on the display panel with the image data from row y2. This results in the actual image displayed on the display panel being... Figure 4 In the interface (f), the area corresponding to the y2+1th row to the last row repeatedly displays the content corresponding to the pixels in the y2th row.

[0156] This makes electronic devices Figure 4 The interface displayed on the terminal device (f) is not displayed correctly (b). That is, when DDIC receives the M+1th frame of image data, it cannot determine the refresh area (the row that needs to be refreshed) corresponding to the M+1th frame of image data, which makes the interface displayed on the terminal device abnormal and affects the user experience.

[0157] However, the image data of the M+2th frame displayed in the N+2th Vsync cycle after the N+1th Vsync cycle may still display abnormalities. Details are as follows.

[0158] Still combined Figure 3 and Figure 4 First, refer to Figure 4 Suppose that the electronic device displays interface (a) in the Nth Vsync cycle, interface (b) in the (N+1)th Vsync cycle, interface (c) in the (N+2)th Vsync cycle, and interface (d) in the (N+3)th Vsync cycle. Then, DDIC can perform partial refreshes in the (N+1)th and (N+2)th Vsync cycles. In the (N+3)th Vsync cycle, since interface (d) has changed almost completely compared to interface (c), a full-screen refresh is possible in the (N+3)th Vsync cycle.

[0159] Since the Nth Vsync cycle displays a full-screen refresh of interface (a), the Mth frame of image data transmitted by the SOC to the DDIC in the Nth Vsync cycle is the complete image data corresponding to interface (a). In the (N+1)th Vsync cycle, a partial refresh occurs, so the (M+1)th frame of image data transmitted by the SOC to the DDIC in the (N+1)th Vsync cycle is the changed portion of the image data, i.e., the image data from row y1 to row y2. Similarly, in the (N+2)th Vsync cycle, a partial refresh occurs, and the refresh area is the same as the refresh area in the (N+1)th Vsync cycle. Therefore, the (M+2)th frame of image data transmitted by the SOC to the DDIC in the (N+2)th Vsync cycle is the changed portion of the image data, i.e., the image data from row y1 to row y2. In the (N+3)th Vsync cycle, a full-screen refresh occurs, so the image data transmitted by the SOC to the DDIC in the (N+3)th Vsync cycle is the complete image data corresponding to interface (d).

[0160] For DDIC, a full-screen refresh occurs in the Nth Vsync cycle, displaying the image data of the Mth frame. Therefore, the actual interface (e) displayed on the screen is the same as interface (a). Combining the description above, because the SOC fails to transmit the refresh area command to the DDIC in the Nth Vsync cycle via the VFP, the DDIC cannot determine the refresh area in the (N+1)th Vsync cycle, resulting in the electronic device displaying interface (f). See the description above for details.

[0161] Because the SOC transmits a refresh region command to the DDIC in the VFP during the (N+1)th Vsync cycle (actually the command corresponding to the (N+1)th Vsync cycle, but the refresh regions of the (N+1)th Vsync cycle and the (N+2)th Vsync cycle are the same), the DDIC performs a partial refresh in the (N+2)th Vsync cycle based on this command, that is, refreshes rows y1 to y2.

[0162] Combination Figure 3 The timing diagram shows that because the DDIC receives the refresh region command at VFP in the (N+1)th Vsync cycle, the GOA circuit is not enabled from row 1 based on the DE signal. Instead, it is enabled from row y1 based on the refresh region command (indicating y1 and y2). That is, the GOA_EN_N and GOA_EN_P signals switch from row y1 to one being high and the other low. This causes the display to refresh from row y1. Furthermore, after row y2, the GOA circuit is no longer enabled (the GOA_EN_N and GOA_EN_P signals are no longer one high and one low), causing the display to stop refreshing from row y2+1 to the last row.

[0163] That is, in the N+2th Vsync cycle, DDIC does not refresh rows 1 to y1-1, so that the displayed content of rows 1 to y1-1 in interface (g) is the same as that in interface (f); and DDIC does not refresh the portion below row y2, so that the displayed content of the portion below row y2 in interface (g) is the same as that in interface (f). Based on the command instructions y1 and y2 from the SOC, DDIC refreshes rows y1 and y2, so that the displayed content of rows y1 and y2 is updated.

[0164] This causes the interface (g) to still display an error.

[0165] In frame N+3, DDIC can perform a full-screen refresh, and the image data of frame M+3 is also all the image data of the interface (d), so that the display screen can display the interface (h) normally.

[0166] In view of this, this application provides an image display method in which, when a frame of image data requires partial refresh, the active line in the MIPI DSI data packet transmitted by the processor to the DDIC may include an empty packet and the image data of that frame; wherein, the empty packet is used to indicate the non-refreshing area, that is, the line that does not need to be refreshed. In this way, the SOC does not need to transmit the refresh area command to the DDIC in the VFP, which helps to reduce the phenomenon of untimely transmission of refresh area command due to the short VFP time, thereby reducing display abnormalities caused by the DDIC's inability to obtain the refresh area command in time.

[0167] For example, with Figure 4 The process is similar. Assume the terminal device displays interface (a) in the Nth Vsync cycle, interface (b) in the (N+1)th Vsync cycle, interface (c) in the (N+2)th Vsync cycle, and interface (d) in the (N+3)th Vsync cycle. The area where interface (b) changes compared to interface (a) is from row y1 to row y2. That is, the refresh area is from row y1 to row y2.

[0168] The waveforms of various signals in the display system can be displayed as follows: Figure 6 As shown.

[0169] During the Nth Vsync cycle, each row of pixels on the display screen is refreshed, enabling the electronic device to display... Figure 4The interface (a) shows that in the active row of the (N+1)th Vsync cycle, an empty packet is set to indicate a non-refreshing area, allowing DDIC to disable the GOA circuit in the non-refreshing area based on the empty packet. Instead, it enables the circuit in the row that needs to be refreshed. That is, in the (N+1)th Vsync cycle, the GOA circuit is enabled starting from the y1st row, so that the GOA_EN_N signal and the GOA_EN_P signal are one high and the other low, causing the display to refresh from the y1st row; and, based on the empty packet set starting from the y2+1st row, the GOA circuit is disabled starting from the y2+1st row, so that the GOA_EN_N signal and the GOA_EN_P signal are no longer one high and the other low.

[0170] The MIPI DSI data packets acquired by DDIC from the SOC during the (N+1)th Vsync cycle, and Figure 5 The difference in the active row of the MIPIDSI data packet shown is that an empty packet is set in the active row during the N+1th Vsync cycle. The empty packet is used to indicate the area that is not refreshed. For example, the gray-filled part in the N+1th Vsync cycle can indicate the position where the empty packet is set.

[0171] For example, combined Figure 7 , Figure 7 This is a schematic diagram of a MIPI DSI data packet provided in an embodiment of this application. Figure 5 The difference lies in the fact that the active line contains the HSS data packets, HBP data, null packets, and HFP data packets corresponding to lines 1 through y1-1. DDIC can determine that lines 1 through y1-1 do not need to be refreshed based on these data packets. For example, the null packet can carry information indicating lines 1 through y1-1, such as a word count (WC) in the null packet header.

[0172] It should be understood that rows 1 to y1-1 can be considered as rows that do not need to be refreshed, or rows of pixels or non-refreshing areas in the display panel that do not need to be refreshed.

[0173] It is understandable that, in order to be similar to the transmission method of RGB data corresponding to each row of pixels in the active row, HSS data packets, HBP data packets, and HFP data packets are also set sequentially in the adjacent positions of the empty packet.

[0174] That is, each row of valid image data (RGB data) is preceded by an HSS packet and HBP data, and each row of valid image data (RGB data) is followed by an HFP packet. In order to make the transmission format of empty packets similar to that of valid image data (RGB data), so that DDIC can determine the rows that do not need to be refreshed based on the empty packets, in the active rows, each empty packet is also preceded by an HSS packet and HBP data, and each empty packet is followed by an HFP packet.

[0175] and Figure 5 Similarly, the active row is set with valid image data (RGB data) for each row from row y1 to row y2, i.e. Figure 4 The image data of frame M+1 shown in the figure causes DDIC to refresh the image data of rows y1 to y2 onto the display panel.

[0176] It should be understood that rows y1 to y2 can be understood as the rows that need to be refreshed, or the row pixels or refresh area in the display panel that need to be refreshed.

[0177] Similarly, the active row also includes HSS packets, HBP data, null packets, and HFP packets corresponding to rows y2+1 to the last row. DDIC can determine that rows y2+1 to the last row do not need to be refreshed based on these data. For example, the null packet might carry information indicating the rows y2+1 to the last row.

[0178] It should be understood that rows from y2+1 to the last row can be considered as rows that do not need to be refreshed, or rows of pixels or non-refreshing areas in the display panel that do not need to be refreshed.

[0179] This allows the display screen of electronic devices to show... Figure 4 The interface (b) in the middle.

[0180] Subsequently, similarly, due to Figure 4 Compared to interface (b), the area that changes in interface (c) (the refresh area) is still rows y1 to y2. Therefore, the format of the MIPI DSI data packets acquired by DDIC from the SOC during the (N+2)th Vsync cycle is also the same. Figure 7Similarly, DDIC can avoid refreshing rows 1 to y1-1 of the display panel based on the HSS data packets, HBP data, null packets, and HFP data packets corresponding to rows 1 to y1-1; it can refresh the valid image data from rows y1 to y2 (i.e., the image data of frame M+2) onto the display panel based on the valid image data from rows y1 to y2; and it can avoid refreshing rows y2+1 to the last row based on the HSS data packets, HBP data, null packets, and HFP data packets corresponding to rows y2+1 to the last row.

[0181] This allows the display screen of electronic devices to show... Figure 4 The interface (c) in the middle. Afterwards, the electronic device can display the screen in a full-screen refresh mode. Figure 4 The interface (d) in the middle.

[0182] Therefore, in the image display method of this application, the SOC does not need to transmit refresh area commands to the DDIC in the VFP. Instead, it indicates the non-refresh area (the row or row pixels that do not need to be refreshed) to the DDIC through an empty packet set in the active row. In this way, the DDIC can determine the non-refresh area and the refresh area (the row or row pixels that need to be refreshed) when parsing the data packets in the active row. This reduces the number of display anomalies caused by the DDIC not receiving the refresh area command in time, thus improving the user experience.

[0183] It should be noted that, Figure 7 This is merely an example, and the embodiments of this application are illustrated using an empty packet indicating rows (non-refresh areas) that do not need to be refreshed. In some possible implementations, the empty packet in the embodiments of this application can also be replaced with other predefined data packets. This predefined data packet can be a predefined type of data packet that can be used to indicate rows (non-refresh areas) that do not need to be refreshed. That is, if the predefined data packet is not an empty packet, the predefined data packet is related to... Figure 7 The empty packets in the image display method serve the same purpose and are implemented in a similar manner, so they will not be described in detail here.

[0184] The following is combined Figures 8 to 12 The technical solutions of this application and how they solve the aforementioned technical problems are described in detail with specific embodiments. The following specific embodiments can be implemented independently or in combination with each other. Identical or similar concepts or processes may not be described again in some embodiments.

[0185] The embodiments shown in this application can be executed by an electronic device, which may be a terminal device, such as a mobile phone, tablet computer, or smart bracelet; it may also be executed by a chip, chip system, or processor that supports the electronic device in implementing the image display method; or it may be a logic module or software that can implement all or part of the functions of the electronic device. The specific form and number of the devices shown are merely examples and should not constitute any limitation on the implementation of the methods provided in this application. The image display method of the embodiments of this application will be described in detail below from the perspective of the interaction between internal modules of an electronic device.

[0186] It should be understood that an electronic device can be the electronic device itself, or a chip, chip system, or processor that supports the electronic device in implementing image display methods, or a logic module or software that can implement all or part of the functions of the electronic device.

[0187] To facilitate understanding this solution, we will first combine... Figure 8 Describe the hardware structure of the electronic device.

[0188] Figure 8 This is a schematic diagram of the structure of the electronic device 800 provided in an embodiment of this application. Figure 8 As shown, the electronic device 800 may include a processor 810, an external memory interface 820, an internal memory 821, a universal serial bus (USB) interface 830, a charging management module 840, a power management module 841, a battery 842, antenna 1, antenna 2, a mobile communication module 850, a wireless communication module 860, an audio module 870, a sensor module 880, a button 890, a motor 891, an indicator 892, a camera 893, a display screen 894, and a subscriber identification module (SIM) card interface 895, etc.

[0189] The audio module 870 may include a speaker, receiver, microphone, and headphone jack. The sensor module 880 may include a pressure sensor, gyroscope sensor, barometric pressure sensor, magnetic sensor, accelerometer, distance sensor, proximity sensor, fingerprint sensor, temperature sensor, touch sensor, ambient light sensor, and bone conduction sensor.

[0190] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 800. In other embodiments of this application, the electronic device 800 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0191] The processor 810 may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). These different processing units may be independent devices or integrated into one or more processors.

[0192] In some examples, processor 810 can be a system-on-chip (SOC) of electronic device 800.

[0193] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.

[0194] The processor 810 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 810 is a cache memory. This memory can store instructions or data that the processor 810 has just used or that are used repeatedly. If the processor 810 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 810, and thus improves the efficiency of the system.

[0195] In some embodiments, processor 810 may include one or more interfaces.

[0196] Electronic device 800 implements display functions through a GPU, a display screen 894, and an application processor. The GPU is a microprocessor for image processing, connecting the display screen 894 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 810 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0197] Display screen 894 is used to display images, videos, etc. Display screen 894 includes a DDIC and a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled LED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 800 may include one or N displays 194, where N is a positive integer greater than 1.

[0198] The DDIC is one of the main control components of the display screen, often referred to as the "brain" of the display panel. Its primary function is to control the brightness and color of the display panel by sending drive signals and data to the panel in the form of electrical signals, enabling letters, pictures, and other image data to be displayed on the screen. In other words, the DDIC can acquire image data and send it to the display panel to display the image.

[0199] For example, the processor 810 can call the GPU to synthesize image data, and the processor 810 can generate MIPI DSI data packets, which include the image data synthesized by calling the GPU; the processor 810 can transmit the MIPI DSI data packets to the DDIC, so that the DDIC can drive the display panel to display the image.

[0200] Internal memory 821 can be used to store computer executable program code, which includes instructions. Internal memory 821 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.), etc. The data storage area may store data created during the use of electronic device 800 (such as audio data, phonebook, etc.). Furthermore, internal memory 821 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. Processor 810 executes various functional applications and data processing of electronic device 800 by running instructions stored in internal memory 821 and / or instructions stored in memory located in the processor.

[0201] The software system of an electronic device can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This embodiment of the invention uses a layered architecture system as an example to illustrate the software structure of an electronic device.

[0202] In some embodiments, the interaction process between the software architecture and hardware architecture of an electronic device can be as follows: Figure 9 As shown. Among them,

[0203] The software system of an electronic device can adopt a layered architecture, which divides the software and hardware into several layers, each with a clear role and division of labor. Layers communicate with each other through software interfaces. In some embodiments, an electronic device may include, for example, an application layer, an application framework layer, an Android runtime and system libraries, a hardware abstraction layer (HAL), a kernel layer, and a hardware layer.

[0204] 1. Application Layer

[0205] An application may include a series of application packages. For example, the application layer may include application packages such as browsers, games, videos, galleries, phones, and music.

[0206] Applications in the application layer can invoke software and hardware to synthesize image data through the instruction stream of rendering instructions.

[0207] 2. Application Framework Layer

[0208] The application framework layer provides application programming interfaces (APIs) and a programming framework for applications in the application layer. The application framework layer includes some predefined functions.

[0209] The application framework layer may include the window manager service (WMS) and the activity manager service (AMS), etc.

[0210] The window manager can be used to manage window programs. For example, it can obtain the screen size, determine whether there is a status bar, lock the screen, capture the screen, and so on.

[0211] The Activity Manager can be used to launch activities and manage their lifecycle. It can also be used to manage application launches; for example, a desktop launcher can use the Activity Manager to launch an application's activity, or other applications can use the Activity Manager to launch their activities.

[0212] 3. System libraries (native) and Android runtime

[0213] It can include multiple functional modules. For example, image compositing service (surface flinger, SF), 3D graphics processing library (e.g., OpenGL ES), etc.

[0214] Among them, the image compositing service is Android's display compositing service, which is responsible for managing the layers of all applications.

[0215] Image compositing services can combine layers from multiple applications into a single final frame. Furthermore, the image compositing service can determine the refresh area (rows and columns) based on this frame and the previous frame, that is, determine the areas where this frame has changed compared to the previous frame. For example, it can determine the coordinates (x1, y1) of point A and the coordinates (x2, y2) of point B in the above example.

[0216] In addition, the image compositing service can also generate display control commands, which can indicate refresh areas, such as (x1, y1) and (x2, y2), and pass the display control commands to the Hardware Abstraction Layer (HAL).

[0217] The 3D graphics processing library can convert rendering instructions from the application into OpenGL commands, and then call the GPU through the GPU driver to execute the OpenGL commands so that the GPU can render the layers and obtain the rendered layers.

[0218] The Android Runtime consists of core libraries and a virtual machine. The Android runtime is responsible for the scheduling and management of the Android system.

[0219] The core library consists of two parts: one part is the functionalities that need to be called by the Java language, and the other part is the Android core library.

[0220] The application layer and application framework layer run in a virtual machine. The virtual machine executes the Java files of the application layer and application framework layer as binary files. The virtual machine is used to perform functions such as object lifecycle management, stack management, thread management, security and exception management, and garbage collection.

[0221] 4. The Hardware Abstraction Layer (HAL) primarily serves to connect the application framework layer and the kernel layer. The HAL can include the display HAL and the hardware composer (HWC), etc. The display HAL provides an interface with the display hardware, abstracting the underlying hardware details so that upper-layer software does not need to concern itself with the specific hardware implementation.

[0222] The HAL can retrieve display control commands from the image compositing service and then transmit these commands to the display driver.

[0223] HWC can obtain image data synthesized by the image compositing service and cache the image data in the frame buffer.

[0224] 5. The kernel layer is the layer between hardware and software. In an exemplary embodiment, the kernel layer includes a display driver and a GPU driver.

[0225] The display driver receives display control commands from the display HAL and calculates the range of rows that need to be refreshed based on these commands. For example, based on the coordinates (x1, y1) of point A and the coordinates (x2, y2) of point B in the display control command, the refresh area is determined to be rows y1 to y2.

[0226] The display driver can also obtain image data synthesized by the image compositing service from the frame buffer. Based on the obtained image data and the determined refresh area (the rows that need to be refreshed), it generates the corresponding MIPI DSI data packet. The MIPI DSI data packet can be a data packet obtained by the display driver encapsulating the image data according to the MIPI communication protocol.

[0227] For example, for the (M+1)th frame image data mentioned above, the display control command can indicate y1 and y2, and the (M+1)th frame image data acquired by the display driver can be as follows: Figure 4As shown. The format of the MIPI DSI data packet generated by the display driver based on the display control commands and the image data of the (M+1)th frame can be as follows: Figure 7 As shown.

[0228] 6. The hardware layer includes DDIC, display panel, and GPU, etc. DDIC acquires MIPI DSI data packets, parses them, and then applies the parsed image data to the display panel to display the image.

[0229] DDIC can determine the rows that do not need to be refreshed, i.e., the areas that do not need to be refreshed, based on the empty packets included in the active rows of the MIPI DSI data packets.

[0230] The GPU can perform rendering and other processing on the layers under the guidance of the GPU driver.

[0231] It should be noted that, Figure 9 The software architecture shown is for illustrative purposes only. Electronic devices may also include more or fewer software modules; for example, the application layer may include social applications, cameras, maps, and other applications. Figure 9 The software architecture shown does not constitute a limitation on the embodiments of this application.

[0232] Below, in conjunction with Figure 9 The software modules and hardware shown are described in detail from the perspective of the interaction between internal modules of an electronic device to illustrate the image display method 1000 provided in the embodiments of this application.

[0233] Figure 10 This is a schematic flowchart of an image display method 1000 provided in an embodiment of this application. Method 1000 illustrates an electronic device display. Figure 4 The process from interface (a) to interface (d) in the text.

[0234] Method 1000 includes the following steps:

[0235] First, the electronic device is based on displays S1001 to S1006. Figure 4 The interface (a) in the text is a full-screen refresh.

[0236] S1001, Image Composition Service composes the image data of the Mth frame.

[0237] It should be understood that the Mth frame image data can be interpreted as a frame synthesized by the image compositing service after overlaying all applications. The display content corresponding to the Mth frame image data can be as follows: Figure 4 The interface shown in (a) is shown in the image.

[0238] Optionally, the Mth frame image data can be transmitted to the HWC so that the HWC can cache the Mth frame image data in the frame buffer.

[0239] HWC can further process the acquired M-th frame image data, or it can choose not to further process the M-th frame image data; this application does not specifically limit this.

[0240] It should be noted that when the image compositing service is compositing the M-th frame image data, it can compare the M-th frame image data with the (M-1)-th frame image data to determine the area where changes have occurred, from the first row to the last row. In other words, the M-th frame image data needs to be displayed by full-screen refresh.

[0241] S1002, The display driver obtains the image data of the Mth frame from the image compositing service.

[0242] Optionally, the display driver can read the Mth frame image data from the frame buffer.

[0243] S1003. Based on the image data of the Mth frame, the display driver generates MIPI DSI data packet 1.

[0244] Among them, MIPI DSI data packet 1 and Figure 7 The difference in the MIPI DSI data packets shown is that each row in the active row is configured with HSS data packets, HBP data packets, RGB data, and HFP data packets.

[0245] In other words, MIPI DSI data packet 1 includes all valid image data corresponding to all rows.

[0246] S1004, The display driver transmits MIPI DSI data packets to the DDIC.

[0247] S1005 and DDIC receive MIPI DSI data packet 1 from the display driver, parse MIPI DSI data packet 1, and can refresh the Mth frame image data to the display panel based on the parsed MIPI DSI data packet 1, that is, refresh all lines.

[0248] S1006, Display panel display Figure 4 The interface (a).

[0249] Subsequently, the electronic device displays based on S1007 to S1013. Figure 4 The interface (b) in the image shows a partial refresh process.

[0250] S1007, Image Composition Service composes the image data of frame M+1.

[0251] It should be understood that the difference between S1007 and S1001 is that the image compositing service can determine the image to be displayed. Figure 4 The interface (b) shows some changes compared to interface (a). Assume the top-left corner coordinates of the changed area are (x1, y1) and the bottom-right corner coordinates are (x2, y2). The image compositing service can then instruct the display driver to use (x1, y1) and (x2, y2). Therefore, the image compositing service generates display control command 1 based on (x1, y1) and (x2, y2).

[0252] S1008, The display driver obtains display control command 1 from the image compositing service and obtains the image data of frame M+1.

[0253] The image data of the (M+1)th frame can be obtained from the frame buffer.

[0254] S1009. The display driver calculates the rows that need to be refreshed, i.e. the refresh area, based on (x1, y1) and (x2, y2) in the display control command.

[0255] That is, the display driver can determine the rows that need to be refreshed based on (x1, y1) and (x2, y2), from row y1 to row y2.

[0256] S1010, based on the image data of rows y1 to y2 and frame M+1 that need to be refreshed (actually including the image data of rows y1 to y2), the display driver generates MIPI DSI data packet 2. MIPI DSI data packet 2 and... Figure 7 The format of the MIPI DSI data packets shown is similar.

[0257] S1011, The display driver transmits MIPI DSI data packet 2 to DDIC.

[0258] S1012, DDIC receives MIPI DSI data packet 2 from the display driver and parses MIPI DSI data packet 2.

[0259] It should be understood that DDIC can determine that rows 1 to y1-1 do not need to be refreshed based on the empty packets corresponding to rows 1 to y1-1 in the active rows of MIPI DSI data packet 2; and DDIC can refresh rows y1 to y2 based on the valid image data in rows y1 to y2; and can determine that rows y2+1 to the last row do not need to be refreshed based on the empty packets corresponding to rows y2+1 to the last row in the active rows of MIPI DSI data packet 2.

[0260] Therefore, the DDIC control panel refreshes rows y1 to y2.

[0261] S1013, Display panel display Figure 4 The interface (b).

[0262] Subsequently, the electronic device can display the image via S1007 and S1013 (partial refresh). Figure 4 The interface (c); and can be displayed via S1001 to S1006 (full-screen refresh). Figure 4 The interface (d).

[0263] In some scenarios, such as when a user watches a video in a small window on an electronic device, the device may refresh only a portion of the display for an extended period, causing other areas to remain unrefreshed. Since current electronic devices often use variable refresh rate displays (e.g., 1Hz-12Hz), meaning the refresh rate can vary depending on the application, the minimum supported refresh rate for this particular display is 1Hz. Therefore, the entire display area (all rows) will refresh at a minimum of 1Hz.

[0264] Therefore, based on the above embodiments, method 1000 further includes: the DDIC sending a TE signal according to the lowest refresh rate supported by the display screen. In this way, the SOC can determine the timing when complete image data needs to be transmitted based on the TE signal. This ensures that the display screen can at least perform full-screen refresh at the lowest supported refresh rate.

[0265] For example, combined Figure 11 Assuming electronic devices are in Figure 4 The interface (d) needs to be displayed Figure 11 The interface shown is compared to... Figure 4 The interface (d). Figure 11 The interface shown also displays notification 1101, which is... Figure 11 The interface shown has changed in some areas. However, because the SOC detects the TE signal emitted by the DDIC, it can determine that the display needs to refresh all rows (full-screen refresh) based on the TE signal, allowing the SOC to transmit data to the DDIC. Figure 11 The image data shown corresponds to the complete image data of the interface shown, not the image data of the area corresponding to transmission notification 1101. See S1014 to S1021 for details.

[0266] S1014. Based on the lowest refresh rate supported by the display, the DDIC emits a TE signal.

[0267] For example, assuming the display supports a minimum refresh rate of 1Hz, all areas in the display panel need to be refreshed at least at 1Hz, so the DDIC can send a TE signal once per second.

[0268] S1015, The display driver detected the TE signal.

[0269] For example, the display driver can listen to the TE signal through the display controller.

[0270] S1016, Image Compositing Service composes the image data of frame M+4. The image data of frame M+4 can be... Figure 11 The image data corresponding to the interface shown.

[0271] S1017. The display driver obtains the image data of frame M+4 from the image compositing service.

[0272] For example, the image data of the M+4th frame synthesized by the image compositing service can be Figure 11 The notification 1101 indicates the image data for the corresponding area. Therefore, in addition to the M+4th frame image data synthesized by the image compositing service, the display driver can also obtain the image data from the frame buffer based on the detected TE signal. Figure 11 The image data of the area excluding notification 1101 in the interface shown is obtained. Figure 11 The complete image data corresponding to the interface shown. That is, the image data of the (M+4)th frame obtained by the display driver is... Figure 11 The complete image data corresponding to the interface shown.

[0273] even though Figure 11 The interface shown is compared to Figure 4 The interface (d) in the image changes in a local area, but the display driver still acquires the complete image data of frame M+4 based on the TE signal.

[0274] S1018, The display driver generates MIPI DSI data packet 3 based on the complete M+4 frame image data. MIPI DSI data packet 3 is similar to MIPI DSI data packet 1, including valid image data corresponding to each row of pixels on the display panel.

[0275] S1019, Display driver transmits MIPI DSI data packets to DDIC 3.

[0276] S1020 and DDIC receive MIPI DSI data packet 3 from the display driver and parse MIPI DSI data packet 3. Based on the parsed MIPI DSI data packet 3, they refresh all rows of image data on the display panel, that is, refresh all rows on the display panel.

[0277] 1021. Display panel display Figure 11 The interface shown.

[0278] Optionally, S1012 can, for example, be via Figure 12 The process shown is implemented. That is, DDIC can be accessed through... Figure 12The process shown determines the areas that need to be refreshed and the areas that do not need to be refreshed.

[0279] DDCI may include a command receiver processor, a core controller, and a video timing controller.

[0280] The SOC (Display Driver) can generate MIPI DSI data packet 2 and transmit it to the DDIC via MIPI DSI. The command receiver processor in the DDIC can receive MIPI DSI data packet 2 from the SOC and parse it.

[0281] The command receiving processor can determine whether there are empty packets in the active line based on the parsed MIPI DSI data packet 2, so that the command receiving processor can indicate to the video timing controller the line that needs to be refreshed (line y1 to line y2).

[0282] Optionally, the command receiving processor can determine the lines that do not need to be refreshed indicated by each empty packet based on the word count (WC) carried in the header of the empty packet. For example, in combination with... Figure 7 In the MIPI DSI data packet 2 shown, the WC carried in the header of the empty packets corresponding to lines 1 to y1-1 can indicate y1-1, so that the command receiving processor can determine that lines 1 to y1-1 do not need to be refreshed; in the empty packets corresponding to lines y2+1 to the last line, the WC carried in the header can indicate the number of lines from line y2+1 to the last line (for example, if the last line is line y3, then the number of lines is y3-y2), so that the command receiving processor can determine that lines y2+1 to the last line do not need to be refreshed.

[0283] On the one hand, the video timing controller can generate DE signals based on the coordination and management of the core controller.

[0284] On the other hand, the video time domain controller generates GOA_EN_P and GOA_EN_N signals based on the command receiving processor's instruction to refresh the lines that need to be refreshed, so as to enable the GOA circuit in lines y1 to y2, thereby refreshing lines y1 to y2.

[0285] Optionally, if the MIPI DSI data packet transmitted by the SOC to the DDIC is MIPI DSI data packet 1, the command receiving processor can determine that a full-screen refresh is required based on the parsed MIPI DSI data packet 1. In this case, the command receiving processor does not instruct the video timing controller which rows need to be refreshed. The video timing controller then instructs the GOA controller to generate GOA_EN_P and GOA_EN_N signals based on the DE signal, thereby enabling the GOA circuitry in all rows, i.e., refreshing all rows. The GOA controller can be understood as the control unit or chip of the GOA circuitry. The GOA controller can be used to generate and manage gate drive signals to ensure the normal operation of the display panel.

[0286] In addition, combined Figure 12 The components in the DDIC shown can generate TE signals through the video timing controller, so that the SOC can determine the minimum refresh rate of the display based on the TE signals.

[0287] The video timing controller (TCON module) can output the generated TE signal through specific pins or interfaces. For example, the video timing controller can pass the TE signal to the display controller or SOC (such as the display driver) for synchronous display refresh.

[0288] It should be noted that, in the embodiments of this application, the MIPI DSI data packet can be a data packet obtained by encapsulating image data based on the MIPI communication protocol, or it can be called a MIPI video data packet, etc., which is a complete frame of display data. This application does not limit the name of this data packet.

[0289] It should be understood that in the above embodiments, the relative size of each step number does not indicate the order in which the steps are executed, but is determined by the internal logic between each step.

[0290] It should be noted that the module names involved in the embodiments of this application can all be defined as other names, as long as they can achieve the function of each module, and no specific restrictions are placed on the module names.

[0291] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0292] The image display method of the present application embodiments has been described above. The apparatus for performing the above method provided in the present application embodiments is described below. Those skilled in the art will understand that the methods and apparatus can be combined and referenced with each other, and the related apparatus provided in the present application embodiments can perform the steps in the above list sorting method.

[0293] Figure 13 This is a schematic block diagram of an image display device 1300 provided in an embodiment of this application. The device 1300 includes a processor 1301, a communication interface 1302, and a memory 1303. The processor 1301, communication interface 1302, and memory 1303 communicate with each other via internal connection paths. The memory 1303 is used to store instructions, and the processor 1301 is used to execute the instructions stored in the memory 1303. The communication interface 1302 can be used to send signals to other devices (e.g., the processor 1301 or a touchscreen of an electronic device) and to receive signals from other devices (e.g., the memory 1303). Exemplarily, the communication interface 1302 reads instructions stored in the memory 1303 and sends the instructions to the processor 1301.

[0294] It should be understood that the device 1300 may specifically be an electronic device as described in the above embodiments, and may be used to perform the various steps and / or processes corresponding to the electronic device in the above method embodiments. Optionally, the memory 1303 may include read-only memory and random access memory, and provide instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store device type information. The processor 1301 may be used to execute instructions stored in the memory, and when the processor 1301 executes instructions stored in the memory, the processor 1301 is used to perform the various steps and / or processes of the above method embodiments.

[0295] It should be understood that, in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0296] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly manifested as execution by a hardware processor, or as a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor executes the instructions in the memory, combining them with its hardware to complete the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0297] The image display method provided in this application can be applied to electronic devices with communication functions. Electronic devices include terminal devices, and the specific device form of the terminal device can be referred to the above-described related information, which will not be repeated here.

[0298] This application provides an electronic device, which includes a processor and a memory; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, causing the electronic device to perform the above-described method.

[0299] This application provides a chip. The chip includes a processor, which is used to call a computer program in memory to execute the technical solutions in the above embodiments. Its implementation principle and technical effects are similar to those in the related embodiments described above, and will not be repeated here.

[0300] This application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, it implements the methods described above. The methods described in the above embodiments can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted over the computer-readable medium. The computer-readable medium can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium accessible by a computer.

[0301] In one possible implementation, a computer-readable medium may include RAM, ROM, compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage or other magnetic storage devices, or any other medium targeted to carry or to store the required program code in the form of instructions or data structures, and accessible by a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include optical discs, laser discs, optical discs, Digital Versatile Discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0302] This application provides a computer program product, which includes a computer program that, when run, causes the computer to perform the above-described method.

[0303] This application describes embodiments of methods, apparatus (systems), and computer program products according to embodiments of this application with reference to flowchart illustrations and / or block diagrams. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable device to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0304] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. An image display method, characterized in that, Applied to electronic devices, the method includes: When the electronic device displays the first interface, it acquires the Xth MIPI data packet. The target area in the Xth Mobile Industry Processor Interface MIPI data packet includes n predefined data packets and the Sth frame image data. The target area is used to set the data packet carrying the image data, where n, X, and S are positive integers. The electronic device switches the first interface to the second interface based on the n predefined data packets and the S-th frame image data; The second interface displays the same content as the first interface in a first part area, but the second interface displays different content than the first interface in a second part area. The S-frame image data is the image data of the content displayed in the second part area of ​​the second interface, and the n predefined data packets are used to indicate the first part area.

2. The method according to claim 1, characterized in that, The S-frame image data includes image data corresponding to at least one row of pixels, and the target region includes image data corresponding to each row of pixels in the at least one row of pixels and a first type of data packet; The target area also includes the first type of data packet corresponding to each of the n predefined data packets.

3. The method according to claim 2, characterized in that, The first type of data packet includes one or more of the following: Horizontal Synchronization Start (HSS) data packet, Horizontal Back Edge (HBP) data packet, or Horizontal Front Edge (HFP) data packet.

4. The method according to any one of claims 1 to 3, characterized in that, The first part of the region includes n consecutive regions, each of the n consecutive regions being a region corresponding to at least one row of consecutive pixels, and the n predefined data packets correspond one-to-one with the n consecutive regions.

5. The method according to claim 4, characterized in that, The first predefined data packet among the n predefined data packets is used to indicate the first continuous region among the n continuous regions. The first continuous region is the region corresponding to the pixels of the l1st row to the l2nd row in the display screen. The first predefined data packet carries information for indicating the l1st row to the l2nd row, where l1 and l2 are positive integers.

6. The method according to claim 5, characterized in that, The information used to indicate lines l1 to l2 is the word count WC in the header of the first predefined data packet.

7. The method according to any one of claims 1 to 3, 5 to 6, characterized in that, The electronic device includes a processor, a display driver integrated circuit (DDIC), and a display panel; The process of obtaining the Xth MIPI data packet includes: The DDIC receives the Xth MIPI data packet from the processor and parses the Xth MIPI data packet; The DDIC determines that the target region in the Xth MIPI data packet includes the n predefined data packets; Switching the first interface to the second interface corresponding to the S-frame image data includes: The DDIC, based on the n predefined data packets and the S-th frame image data, instructs the display panel to refresh the second part of the area; Based on the refresh of the second portion area, the display panel displays the second interface, and the second portion area of ​​the second interface displays the image data of the Sth frame.

8. The method according to claim 7, characterized in that, The DDIC emits a tearing effect TE signal based on the lowest refresh rate supported by the display panel; The method further includes: When the second interface is displayed, the processor detects the TE signal and transmits the (X+1)th MIPI data packet to the DDIC based on the TE signal. The target area in the (X+1)th MIPI data packet includes the (S+1)th frame image data, and the (S+1)th frame image data includes the image data corresponding to each row of pixels in the display panel. The DDIC, based on the image data of the (S+1)th frame, instructs the display panel to refresh each row of pixels; Based on each row of pixels being refreshed, the display panel displays a third interface corresponding to the image data of the (S+1)th frame, and the content displayed on the third interface is the same as that displayed in a portion of the second interface.

9. The method according to any one of claims 1 to 3, 5 to 6, and 8, characterized in that, The target area is the active row.

10. The method according to any one of claims 1 to 3, 5 to 6, and 8, characterized in that, The n predefined data packets are n empty packets.

11. An electronic device, characterized in that, The electronic device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory being used to store computer program code, the computer program code including computer instructions, and the one or more processors invoking the computer instructions to cause the electronic device to perform the method as described in any one of claims 1 to 10.

12. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the one or more processors being used to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method as described in any one of claims 1 to 10.

14. A computer program product, characterized in that, The computer program product includes computer program code that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1 to 10.

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