Surface defect detection method and system for display chip

Abstract

This invention discloses a method and system for detecting surface defects in display chips. The invention relates to the technical field of display chips. Multiple functional regions are determined by matching the surface image and internal structure image of the display chip, and a first surface defect region is marked on the surface image. Multiple abnormal functional regions are determined based on the multiple functional regions, the first surface defect region, and fault signals of the display chip, ensuring the accuracy of these abnormal functional regions. Therefore, multiple surface defect events are determined based on the multiple abnormal functional regions, the display chip database, and the display chip model. A second surface defect region is then determined based on the multiple surface defect events and the surface image of the display chip. The types of surface defects in the display chip are determined based on the second and first surface defect regions, fully considering both regions to ensure the accuracy of the surface defect types.

Description

Technical Field

[0001] This invention relates to the technical field of display chips, and in particular to a method and system for detecting surface defects in display chips. Background Technology

[0002] With the development of technology, display chips have been gradually applied to people's lives and are used as part of electronic devices. Display chips are also often called display processing units (DPUs) or graphics processing units (GPUs), which are microprocessors specifically designed to process image data and perform graphics rendering tasks.

[0003] In the existing technology, the display chip is located inside the electronic device and will experience some failure events during long-term use. This results in some directly observable surface defect areas on the surface of the display chip. However, the type of surface defect of the display chip is determined solely by the directly observable surface defect areas, ignoring some surface defect areas that cannot be directly observed. This leads to low accuracy in identifying the surface defect types of the display chip. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a method and system for detecting surface defects in display chips.

[0005] This invention provides a method for detecting surface defects in a display chip, comprising: acquiring surface images and internal structure images of the display chip when the display chip is in a faulty state; determining multiple functional regions based on the matching of the surface images and internal structure images of the display chip, and marking a first surface defect region in the surface image; determining multiple abnormal functional regions based on the multiple functional regions, the first surface defect region, and fault signals of the display chip; determining multiple surface defect events based on the multiple abnormal functional regions, a database of the display chip, and the model of the display chip, and determining a second surface defect region based on the multiple surface defect events and the surface image of the display chip; the second surface defect region being a surface defect region that cannot be directly observed from the surface image of the display chip; and determining the type of surface defect in the display chip based on the second surface defect region and the first surface defect region.

[0006] This invention provides a surface defect detection system for a display chip, which is applied to the aforementioned surface defect detection method for display chips. The surface defect detection system for the display chip includes:

[0007] The image module is used to acquire surface and internal structure images of the display chip when the display chip is in a faulty state.

[0008] The first surface defect region module is used to determine multiple functional regions based on the matching of the surface image and the internal structure image of the display chip, and to mark the first surface defect region of the surface image.

[0009] An abnormal functional area module is used to determine multiple abnormal functional areas based on multiple functional areas, a first surface defect area, and fault signals from the display chip.

[0010] The second surface defect region module is used to determine multiple surface defect events based on multiple abnormal functional regions, the database of display chips, and the model of display chips, and to determine the second surface defect region based on the multiple surface defect events and the surface image of the display chip; the second surface defect region is a surface defect region that cannot be directly observed from the surface image of the display chip;

[0011] The surface defect type module is used to determine the surface defect type of the display chip based on the second surface defect area and the first surface defect area.

[0012] Compared with the prior art, the beneficial effects of the present invention are:

[0013] In this embodiment of the invention, multiple functional regions are determined by matching the surface image and internal structure image of the display chip, and a first surface defect region of the surface image is marked. Multiple abnormal functional regions are determined based on the multiple functional regions, the first surface defect region, and the fault signal of the display chip, which takes into account the overall consideration of multiple functional regions, the first surface defect region, and the fault signal of the display chip, and ensures the accuracy of multiple abnormal functional regions.

[0014] Therefore, multiple surface defect events are determined based on multiple abnormal functional areas, the display chip database, and the display chip model. A second surface defect area is determined based on the multiple surface defect events and the surface image of the display chip. The second surface defect area is a surface defect area that cannot be directly observed from the surface image of the display chip. The surface defect type of the display chip is determined based on the second surface defect area and the first surface defect area. By fully considering the second surface defect area and the first surface defect area, the accuracy of the surface defect type of the display chip is ensured. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the surface defect detection method for a display chip in an embodiment of the present invention.

[0016] Figure 2 This is a flowchart illustrating step S11 of the surface defect detection method for a display chip in an embodiment of the present invention.

[0017] Figure 3This is a flowchart illustrating step S12 of the surface defect detection method for a display chip in an embodiment of the present invention.

[0018] Figure 4 This is a flowchart illustrating step S13 of the surface defect detection method for a display chip in an embodiment of the present invention.

[0019] Figure 5 This is a flowchart illustrating step S14 of the surface defect detection method for a display chip in an embodiment of the present invention.

[0020] Figure 6 This is a flowchart illustrating step S15 of the surface defect detection method for a display chip in an embodiment of the present invention.

[0021] Figure 7 This is a schematic diagram of the structural composition of the surface defect detection system for a display chip in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0023] Please see Figures 1 to 7 A method for detecting surface defects in a display chip, comprising:

[0024] Step S11: When the display chip is in a faulty state, acquire surface images and internal structure images of the display chip;

[0025] Step S12: Determine multiple functional regions based on the matching of the surface image and internal structure image of the display chip, and mark the first surface defect region of the surface image;

[0026] Step S13: Determine multiple abnormal functional areas based on multiple functional areas, the first surface defect area, and the fault signal of the display chip;

[0027] Step S14: Determine multiple surface defect events based on multiple abnormal functional areas, the database of display chips, and the model of display chips, and determine a second surface defect region based on multiple surface defect events and the surface image of the display chip; the second surface defect region is a surface defect region that cannot be directly observed from the surface image of the display chip;

[0028] Step S15: Determine the type of surface defect in the display chip based on the second surface defect region and the first surface defect region;

[0029] refer to Figure 2 In step S11, when the display chip is in a fault state, the surface image and internal structure image of the display chip are acquired.

[0030] In the specific implementation of this invention, the specific steps are as follows:

[0031] S111: Collect multiple operating parameters of the display chip, and determine multiple fault parameters of the display chip based on the multiple operating parameters and fault signals. Determine the fault status of the display chip based on the multiple fault parameters, the model of the display chip, and the fault status mapping relationship.

[0032] S112: Real-time monitoring of the fault status of the display chip, determining the detection parameters of the visual inspection section based on the fault status of the display chip, the size of the display chip, and the previous detection data of the display chip, and the visual inspection section performs surface inspection on the display chip to output a surface image of the display chip;

[0033] S113: Based on the fault status of the display chip, the thickness of the display chip, and the previous inspection data of the display chip, the X-ray inspection section determines the inspection parameters of the X-ray inspection section. The X-ray inspection section performs internal inspection on the display chip to output an image of the internal structure of the display chip.

[0034] In the embodiments of this application, multiple operating parameters of the display chip are collected, and multiple fault parameters of the display chip are determined based on the multiple operating parameters of the display chip and the fault signal. The fault state of the display chip is determined based on the multiple fault parameters of the display chip, the model of the display chip, and the fault state mapping relationship. This approach takes into account the overall consideration of the multiple fault parameters of the display chip, the model of the display chip, and the fault state mapping relationship, thus ensuring the accuracy of the fault state of the display chip.

[0035] At this point, various sensors and testing equipment are used to collect key parameters of the display chip during operation. These parameters include, but are not limited to, current, voltage, power consumption, temperature, brightness, color uniformity, and response time. The acquisition of these parameters is usually accomplished by a testing system connected to the display chip, which can record and analyze this data in real time. Optionally, a display chip with the model number XYZ123 is being tested. A dedicated testing device is connected to the chip and set to record the current (I), voltage (V), power consumption (P), and temperature (T) during operation. For example, it is found that the chip has a current of 100mA, a voltage of 5V, a power consumption of 0.5W, and a temperature of 60℃ during normal operation.

[0036] The collected operating parameters are compared with preset fault thresholds or standards. If a parameter exceeds the normal range or deviates significantly from the standard value, it is considered a fault parameter. In addition, if the system receives fault signals from the display chip (such as overheat warnings, short-circuit protection triggers, etc.), these should also be considered sources of fault parameters. Optionally, it was found that the current of the XYZ123 display chip suddenly increased to 200mA during operation, far exceeding the normal 100mA; at the same time, the temperature also rose sharply to 85℃, exceeding the safe range; in addition, the system also received an overheat warning signal; therefore, current (I) and temperature (T) were determined to be fault parameters.

[0037] The fault state of the display chip is determined by using fault parameters, display chip model information, and a pre-established fault state mapping relationship. The fault state mapping relationship is a lookup table, decision tree, or machine learning model that maps fault parameters to specific fault states or categories. Optionally, based on the XYZ123 display chip model information and fault parameters (current I and temperature T), the pre-established fault state mapping relationship is consulted. From this fault state mapping relationship, it is known that when the current increases abnormally and the temperature exceeds the safe range, the fault state is "internal short circuit leading to overheating". Therefore, it is determined that the XYZ123 display chip is currently in the fault state of "internal short circuit leading to overheating".

[0038] Through the above steps, the operating parameters of the display chip were successfully collected, the fault parameters were determined, and the fault state of the display chip was determined by using the fault state mapping relationship. In practical applications, this information will be used to guide the subsequent defect detection process, such as adjusting detection parameters, selecting appropriate detection technologies (such as visual inspection or X-ray inspection), and formulating targeted repair or replacement strategies.

[0039] Furthermore, the fault status of the display chip is monitored in real time. Based on the fault status, size, and previous test data of the display chip, the detection parameters of the visual inspection section are determined. The visual inspection section performs surface inspection on the display chip to output a surface image of the display chip. This comprehensive consideration of the fault status, size, and previous test data of the display chip ensures the accuracy of the detection parameters of the visual inspection section.

[0040] At this point, the continuous monitoring system tracks the fault status of the display chip in real time. This typically involves collecting and analyzing various sensor data from the display chip, such as temperature, current, voltage, and any fault signals or warnings. This data is used to assess the health status of the display chip in real time and trigger a response immediately when a fault occurs. Alternatively, this can be achieved through an automated testing system that integrates data acquisition, analysis, and alarm functions. This system can read the operating parameters of the display chip in real time and determine whether a fault exists based on preset thresholds or rules.

[0041] Once the fault state of the display chip is determined, the detection parameters of the visual inspection section need to be determined based on this state, the physical size of the display chip (which affects the field of view and resolution of image acquisition), and previous inspection data (which reveals the common locations and types of defects). These parameters include camera focal length, exposure time, light source settings, image resolution, etc. Optionally, the detection parameters can be dynamically adjusted based on the above factors to ensure optimal image quality and defect detection sensitivity.

[0042] Using adjusted inspection parameters, a vision inspection system (such as a high-resolution camera) will acquire images of the surface of the display chip; the acquired images will be used in subsequent image processing and analysis steps to identify and locate any potential surface defects.

[0043] Specifically, suppose a display chip is being monitored in real time; the chip has a physical size of 50mm x 50mm, and there are already some records of previous test data for this model of chip; an automated test system is used to collect the chip's operating parameters in real time, such as current, voltage, and temperature; the system detects a sudden increase in current and a significant rise in temperature, triggering an overheat warning.

[0044] Based on the overheat warning and chip size (50mm x 50mm), the camera's focal length and exposure time were adjusted to ensure that subtle changes on the chip surface could be captured. Previous inspection data was also referenced, revealing that common defect types for this chip model include cracks, stains, and scratches; therefore, the image processing algorithm was optimized accordingly. Using the adjusted inspection parameters, images of the chip surface were acquired. The acquired images showed a noticeable crack on the chip surface, consistent with previous expectations. Through this process, real-time monitoring, intelligent parameter adjustment, and advanced imaging technology were successfully used to capture and analyze defects on the display chip surface. This information will be used in subsequent defect classification, location, and repair steps.

[0045] Therefore, the detection parameters of the X-ray detection section are determined based on the fault status of the display chip, the thickness of the display chip, and the previous detection data of the display chip. The X-ray detection section performs internal detection on the display chip to output an image of the internal structure of the display chip. This comprehensive consideration of the fault status of the display chip, the thickness of the display chip, and the previous detection data of the display chip ensures the accuracy of the detection parameters of the X-ray detection section.

[0046] At this point, the X-ray detection parameters are determined by comprehensively considering the chip's fault status, physical thickness, and previous detection data. The fault status indicates the problem area or type inside the chip, while the chip's thickness directly affects the X-ray penetration capability and image quality. Previous detection data provides valuable information about defect type, location, and frequency, which helps optimize the detection parameters. Optionally, an intelligent parameter adjustment system is acquired, which can dynamically adjust parameters such as the voltage, current, exposure time, and detector sensitivity of the X-ray source based on input information. These parameter adjustments aim to ensure that X-rays can penetrate the chip to a sufficient depth while producing high-quality images of the internal structure.

[0047] Using adjusted X-ray inspection parameters, the internal structure of the display chip can be inspected non-destructively. X-rays can penetrate the chip material and record the density and thickness differences of different materials inside the chip, thereby generating images of the internal structure. These images will be used in subsequent image processing and analysis steps to identify and locate any potential internal defects. Optionally, X-ray diffraction imaging (DR) is introduced, which can provide high-resolution images of the internal structure while ensuring non-destructive inspection of the chip.

[0048] Specifically, suppose an X-ray inspection is being performed on a display chip; the chip has a physical thickness of 0.5 mm, and there are already some records of previous inspection data for this model of chip; firstly, the chip's fault status was analyzed, and it was found that the system reported an internal short circuit fault; considering the chip's thickness of 0.5 mm, the voltage and current of the X-ray source were adjusted to ensure that the X-rays could penetrate the chip and produce a clear image of its internal structure; furthermore, previous inspection data were referenced, and it was found that common internal defects of this model of chip include metallic impurities, interlayer short circuits, and cracks; therefore, the image processing algorithm was optimized to better identify these defect types.

[0049] Using adjusted X-ray inspection parameters, the internal structure of the chip was inspected. The results showed a significant metallic impurity in one of the chip's internal layers, which was the cause of the internal short circuit. Through this process, fault condition analysis, intelligent parameter adjustment, and advanced X-ray imaging technology were successfully used to capture and analyze internal structural defects in the display chip. This information will be used in subsequent defect classification, location, and repair steps, helping to improve the quality and reliability of the display chip.

[0050] refer to Figure 3 In step S12, multiple functional regions are determined based on the matching of the surface image and the internal structure image of the display chip, and the first surface defect region of the surface image is marked.

[0051] In the specific implementation of this invention, the specific steps are as follows:

[0052] S121: Acquire surface images and internal structure images of the display chip, and determine the stacked structure model of the display chip based on the surface images and internal structure images of the display chip. At this time, the stacked structure model contains multiple functional circuit paths.

[0053] S122: Based on the multi-functional circuit paths and surface images of the stacked structure model, multiple functional regions of the display chip are determined, and the multiple functional regions are presented on the surface of the display chip.

[0054] S123: Based on surface detection of the surface image of the display chip, determine multiple surface abnormal features, and determine the first surface defect region of the surface image according to the location of the multiple surface abnormal features, the type of the multiple surface abnormal features, and the influence range of the multiple surface abnormal features. The first surface defect region of the surface image is the surface defect region directly observed by the surface image of the display chip.

[0055] In the embodiments of this application, surface images and internal structure images of the display chip are acquired, and a stacked structure model of the display chip is determined based on the surface images and internal structure images of the display chip. At this time, the stacked structure model contains multiple functional circuit paths, which takes into account the overall consideration of the surface images and internal structure images of the display chip, and ensures the accuracy of the stacked structure model of the display chip.

[0056] At this point, high-precision imaging equipment (such as a high-resolution camera) is used to capture surface images of the display chip. These surface images should clearly show all the details of the chip surface, including circuit layout, component locations, connection points, etc. The quality of the acquired images is crucial for subsequent analysis and modeling. Optionally, a high-resolution camera or microscope can be used to photograph the display chip. The focal length, exposure time, and light source intensity of the camera or microscope should be adjusted to ensure optimal image clarity and contrast. The acquired image data should be stored for subsequent processing and analysis.

[0057] Non-destructive imaging techniques (such as X-ray imaging or ultrasound imaging) are used to capture images of the internal structure of the display chip. These images should reveal the internal hierarchy, functional circuit paths, and connections between layers. Optionally, an X-ray imaging system or ultrasound imaging device is used to scan the display chip. The parameters of the imaging device (such as the voltage and current of the X-ray source, and the frequency and intensity of the ultrasound) are adjusted according to the chip's thickness and material properties to optimize image quality. The acquired internal structure image data is stored for subsequent processing and analysis.

[0058] Image processing and modeling techniques will be used to analyze the acquired surface and internal structure images to construct a stacked structure model of the display chip. This stacked structure model will include the layout, thickness, and relative positional relationships of each functional layer within the chip, especially detailed information on functional circuit paths. Optionally, image processing algorithms (such as edge detection, image segmentation, and image registration) will be applied to extract key information from the images. 3D modeling software or computer-aided design (CAD) tools will be used to construct the stacked structure model based on the extracted information. The model will then be validated and optimized to ensure its accuracy and completeness.

[0059] Specifically, suppose we are analyzing a display chip. A high-resolution camera captures images of the chip's surface, clearly showing the circuit layout and component locations. An X-ray imaging system scans the chip, obtaining images of its internal structure, revealing the chip's hierarchical structure and functional circuit paths. Image processing algorithms are applied to extract key information from the images, such as circuit edges, component outlines, and functional circuit paths. Using this information, a layered structure model of the chip is constructed in 3D modeling software. In the layered structure model, the layout, thickness, and connections between the various functional layers inside the chip are clearly visible. The model is then validated and optimized to ensure it accurately reflects the chip's actual structure.

[0060] Furthermore, multiple functional circuit paths and surface images based on the stacked structure model are used to determine multiple functional regions of the display chip. These multiple functional regions are presented on the surface of the display chip, which takes into account the overall consideration of multiple functional circuit paths and surface images of the stacked structure model, ensuring the accuracy of multiple functional regions of the display chip.

[0061] At this point, carefully study the stacked structure model, especially its functional circuit paths. These functional circuit paths are key channels for signal transmission inside the chip, connecting different functional components and regions. By analyzing these paths, understand the functional layout and signal flow inside the chip. Optionally, use 3D modeling software or computer-aided design (CAD) tools to view and edit the stacked structure model; trace the functional circuit paths, identify their start points, end points, and connection points; analyze the connection relationships and signal flow between the functional circuit paths to understand the functional layout of the chip.

[0062] The method combines the surface image of the display chip with the functional circuit paths in the stacked structure model to identify functional regions on the chip. These functional regions correspond to the parts of the chip that perform specific functions or process specific signals. They have obvious layout features on the chip surface, such as specific geometric shapes, markings, or color coding. Optionally, image processing algorithms (such as edge detection, image segmentation, etc.) are used to extract key features from the surface image. The extracted features are matched and compared with the functional circuit paths in the stacked structure model. Based on the matching results, different functional regions are marked on the chip surface image.

[0063] It is necessary to verify and confirm whether the previously identified functional areas are accurate. This can be achieved by comparing with known chip design diagrams, verifying with test signals, or referring to documents provided by the chip manufacturer. Optionally, compare with known chip design diagrams or documents provided by the manufacturer to check whether the identified functional areas are consistent with expectations. Test the chip with test signals or test equipment to verify the correctness and functionality of the functional areas. Based on the verification results, make necessary adjustments and optimizations to the identified functional areas.

[0064] Specifically, suppose we are analyzing a display chip. We carefully studied the functional circuit paths in the stacked structure model to understand the internal functional layout and signal flow of the chip. Combining this with a surface image of the display chip, image processing algorithms were used to extract key features from the image, such as circuit edges and component outlines. The extracted features were matched and compared with the functional circuit paths in the stacked structure model to identify different functional areas on the chip, such as the display driving area, signal processing area, and power management area. Different colors or markings were used on the chip surface image to distinguish these functional areas, making their location and layout more intuitive. We compared the chip with known chip design diagrams and tested the chip using test signals to verify the accuracy and functionality of the identified functional areas. Through this process, we successfully identified multiple functional areas on the display chip, providing strong support for subsequent analysis and testing.

[0065] Therefore, multiple surface anomaly features are determined based on surface detection of the surface image of the display chip, and the first surface defect region of the surface image is determined according to the location, type, and influence range of the multiple surface anomaly features. The first surface defect region of the surface image is the surface defect region directly observed by the surface image of the display chip, which takes into account the overall consideration of the location, type, and influence range of the multiple surface anomaly features, thus ensuring the accuracy of the first surface defect region of the surface image.

[0066] At this point, a comprehensive inspection of the surface image of the display chip is performed to identify any abnormal features. This typically involves using advanced image processing algorithms and techniques, such as machine learning, deep learning, or traditional image processing methods, to automatically detect and analyze anomalies in the image. Optionally, image processing software or algorithms are used to process the surface image of the display chip. Image processing techniques such as edge detection, texture analysis, and color recognition are applied to identify abnormal features in the image. Thresholds or rules are set to determine which features are considered abnormal, which is usually based on comparison with a normal chip surface or on features of known defects.

[0067] Each detected anomalous feature is analyzed in detail to determine its location, type, and impact range. Location typically refers to the specific position of the anomalous feature in the chip surface image, while type includes scratches, stains, cracks, missing components, etc. Impact range refers to the potential impact of the anomalous feature on the chip's function or performance. Optionally, measurement tools in image processing software can be used to determine the location and size of the anomalous feature. Based on the shape, color, and texture of the anomalous feature, it is classified into different types. The impact range is assessed by analyzing the comparison between the anomalous feature and the surrounding normal area, as well as their impact on the chip's function.

[0068] Based on the previously determined location, type, and extent of the anomalous features, a first surface defect region is delineated in the surface image. This first surface defect region is the defect portion directly observable on the chip surface image and is crucial for assessing the chip's quality and reliability. Optionally, marking or drawing tools are used in image processing software to delineate the defect region. The defect region is graded or classified according to the severity and extent of the anomalous features for subsequent analysis and processing. The information on the defect region is recorded, and a detailed inspection report is generated, including the location, type, extent of impact, and repair recommendations for the defect.

[0069] Specifically, suppose we are analyzing a display chip; a comprehensive inspection of the chip's surface image is performed, using advanced image processing algorithms and techniques to identify any abnormal features; during the inspection, a noticeable scratch and a stain are found; these two abnormal features are analyzed in detail; the scratch is located in the central area of ​​the chip surface, approximately 2 mm long and 0.1 mm wide; the stain is located at the edge of the chip, with an area of ​​approximately 1 square millimeter; based on their shape, color, and texture, the scratch is classified as physical damage, and the stain is classified as contamination.

[0070] The potential impact of these two anomalous features on chip functionality or performance was assessed. Scratches can damage the conductive or insulating layers on the chip surface, leading to poor signal transmission or short circuits. Stains can cover critical components or connection points on the chip surface, affecting signal reception and transmission. Therefore, the impact range of both anomalous features was assessed as severe. The areas containing these two anomalous features were delineated as the first surface defect areas in image processing software and clearly marked using a marking tool. Information about the defect areas was recorded, and a detailed inspection report was generated, including the location, type, impact range, and repair recommendations of the defects. This report provided strong support for subsequent analysis and processing.

[0071] In one embodiment of this application, an anomaly feature matching table is collected, as shown in Table 1.

[0072] Table 1. Anomaly Feature Matching Table

[0073]

[0074] Anomaly Feature 1 (Scratch): Matches the scratch feature in the anomaly feature matching table. The impact range is assessed as affecting the conductive or insulating layer. Anomaly Feature 2 (Stain): Matches the stain feature in the anomaly feature matching table. The impact range is assessed as covering critical components. Anomaly Feature 3 (Crack): Matches the crack feature in the anomaly feature matching table. The impact range is assessed as damaging the circuit structure.

[0075] To more accurately determine the first surface defect region, a weight is assigned to each anomalous feature, and a score is given based on its influence range. The weight is determined based on factors such as the severity of the anomalous feature and its impact on chip functionality. The score is calculated based on factors such as the location, size, and number of anomalous features. The first surface defect region of the surface image is determined based on the anomalous feature or combination of anomalous features with the highest total score. If the score of a certain anomalous feature is much higher than that of other features, the defect region is delineated with that feature as the center. If the scores of multiple anomalous features are similar, their relative positions and mutual influences are considered to delineate a defect region that includes all relevant features.

[0076] At this point, the first surface defect area is a circular area with radius R centered at (x2, y2) (the stain has the highest score and the greatest impact on chip function); the first surface defect area contains a significant stain that covers critical components and affects signal reception and transmission; it is recommended to clean or replace the chip.

[0077] refer to Figure 4 In step S13, multiple abnormal functional areas are determined based on multiple functional areas, the first surface defect area, and the fault signal of the display chip.

[0078] In the specific implementation of this invention, the specific steps are as follows:

[0079] S131: Collect fault signals from the display chip, determine the fault content of the display chip based on the analysis of the fault signals, and determine multiple fault items of the display chip based on the division of the fault content.

[0080] S132: Mark the surface area of ​​multiple functional regions on the surface of the display chip, and determine the first sub-abnormal functional region based on the matching of the surface area of ​​multiple functional regions and multiple fault items of the display chip;

[0081] S133: Determine the second sub-abnormal functional region based on the surface region of multiple functional regions and the first surface defect region. Determine multiple abnormal functional regions based on the mapping relationship between the first sub-abnormal functional region, the second sub-abnormal functional region and the functional region. The mapping relationship between the functional regions is obtained by matching the display chip model and the display chip database.

[0082] In the embodiments of this application, fault signals of the display chip are collected, the fault content of the display chip is determined based on the analysis of the fault signals of the display chip, and multiple fault items of the display chip are determined based on the division of the fault content of the display chip.

[0083] At this point, fault signals generated by the display chip during operation are collected. These fault signals manifest as voltage fluctuations, abnormal current, timing errors, signal loss, etc. The key to collecting fault signals is to ensure the accuracy and reliability of the test equipment so as to accurately capture the signal characteristics when the chip malfunctions. Optionally, test equipment such as oscilloscopes, logic analyzers, and power supplies can be connected to the display chip. Test parameters, such as sampling rate and trigger conditions, are set to ensure that fault signals can be captured. The test equipment is then started to collect signals from the display chip during operation.

[0084] After acquiring fault signals, these signals need to be analyzed. The purpose of analysis is to identify the characteristics of the fault signals, such as the signal amplitude, frequency, phase, timing, etc., and the differences between these characteristics and normal signals. By analyzing the fault signals, the type and cause of the chip fault can be preliminarily determined. Optionally, the acquired signals can be preprocessed by filtering, amplification, noise reduction, etc. Analyze the waveform, spectrum, timing, and other characteristics of the signals and compare them with normal signals. Based on the differences in signal characteristics, the type and cause of the chip fault can be preliminarily determined.

[0085] Based on the analysis of the fault signal, it is necessary to further determine the fault content of the display chip. The fault content usually includes the specific type of fault, the location of occurrence, and the scope of impact. Determining the fault content requires comprehensive consideration of the chip's working principle, circuit design, and the characteristics of the fault signal. Optionally, the correlation between the fault signal and the chip's internal components and circuits can be analyzed in conjunction with the display chip's working principle and circuit design. Based on the characteristics of the fault signal and the chip's working principle, the specific type of fault can be determined, such as power supply failure, signal processing failure, display driver failure, etc. The scope of the fault's impact on the chip's function should be assessed to determine whether the fault affects the entire chip or only some of its functions.

[0086] Based on the identified fault content, it is necessary to further divide the fault content into specific fault items. Fault items refer to specific, operable repair or replacement parts, or parameters or settings that need to be adjusted within the fault content. Dividing fault items helps in subsequent location, repair, or replacement work. Optionally, the fault content can be divided into specific fault items according to the type and scope of impact of the fault content. Each fault item should be described and defined in detail, including the fault phenomenon, cause, repair or replacement parts, and adjusted parameters or settings. Fault items should be recorded for subsequent analysis and processing.

[0087] Specifically, suppose we are analyzing a display chip. When collecting fault signals, an oscilloscope connected to the signal output of the display chip is used, and obvious distortion of the signal waveform is found. When analyzing the fault signal, it is found that the frequency and phase of the distorted signal are significantly different from those of the normal signal. After further analysis, the fault is determined to be a signal processing fault, specifically an abnormality in the signal amplification circuit. When classifying the fault, this fault is classified as a "signal amplification circuit fault," and the fault phenomenon, cause, and components that were repaired or replaced (such as signal amplifiers, related resistors, capacitors, etc.) are described in detail.

[0088] Furthermore, a surface area with multiple functional regions is marked on the surface of the display chip. The first sub-abnormal functional region is determined based on the matching of the surface area with multiple functional regions and multiple fault items of the display chip. This takes into account the overall consideration of matching the surface area with multiple functional regions and multiple fault items of the display chip, ensuring the accuracy of the first sub-abnormal functional region.

[0089] At this point, based on the display chip's design drawings or technical documents, mark the surface areas of multiple functional regions on the chip's surface image. These functional regions include power management areas, signal processing areas, display driver areas, interface connection areas, etc. The purpose of marking is to accurately match faulty items with these functional regions later. Optionally, obtain the display chip's design drawings or technical documents to understand the chip's functional area division; use image processing software or manually mark the boundaries of each functional region on the chip's surface image; ensure the accuracy and clarity of the markings for subsequent analysis and matching work.

[0090] The first sub-abnormal functional area is determined by matching the surface area of ​​the functional area with the fault items. After marking the surface area of ​​the functional area, these areas need to be matched with several previously identified fault items. The purpose of matching is to identify the functional areas directly related to the fault items, which are often the core locations of the fault. Through matching, the first sub-abnormal functional area is determined, i.e., the functional area most likely to have a fault. Optionally, the previously identified fault items are reviewed to understand the specific content and scope of impact of each item. Each fault item is matched one by one with the marked functional areas to analyze the correlation between the fault items and the functional areas. Based on the matching results, the functional area directly related to the fault items is determined as the first sub-abnormal functional area. The first sub-abnormal functional area is described and recorded in detail, including its location, size, and involved components or circuits.

[0091] Specifically, suppose we are analyzing a display chip. In previous steps, several fault items have been identified, including "power management fault items" and "display driver fault items." The power management area and display driver area have been marked on the surface image of the display chip. Matching the "power management fault items" with the power management area reveals a direct correlation between the fault item and a component (such as the power management IC) within that area. Similarly, matching the "display driver fault items" with the display driver area reveals a direct correlation between the fault item and a circuit (such as the display driver circuit) within that area. Through these matching steps, two primary sub-abnormal functional areas have been identified: one is the area containing the power management IC within the power management area, and the other is the area containing the display driver circuit within the display driver area. These two areas are the core locations where the faults occur, therefore, they require further inspection and testing.

[0092] Therefore, a second sub-abnormal functional region is determined based on the surface region of multiple functional regions and the first surface defect region. Multiple abnormal functional regions are determined based on the mapping relationship between the first sub-abnormal functional region, the second sub-abnormal functional region, and the functional regions. This functional region mapping relationship is obtained by matching the display chip model and the display chip database, which is compatible with the overall consideration of the first sub-abnormal functional region, the second sub-abnormal functional region, and the functional region mapping relationship. At the same time, it is compatible with the overall consideration of multiple functional regions, the first surface defect region, and the fault signals of the display chip, thus ensuring the accuracy of multiple abnormal functional regions.

[0093] At this point, the second sub-abnormal functional area is determined based on the surface area of ​​multiple functional areas and the first surface defect area. This determination is made by comprehensively considering the previously identified surface areas of multiple functional areas and the first surface defect area (such as scratches, stains, cracks, and other physical damage). The second sub-abnormal functional area refers to those functional areas that, although not directly identified through fault signal analysis, are affected by physical damage. Optionally, the specific locations and extents of the previously identified surface areas of multiple functional areas and the first surface defect area are reviewed. The spatial relationship between the first surface defect area and each functional area is analyzed to determine whether the defect affects the normal operation of the functional area. Based on the analysis results, the second sub-abnormal functional areas affected by the first surface defect area are determined; these areas experience performance degradation or complete failure due to physical damage.

[0094] The first sub-abnormal functional region (derived through fault signal analysis) and the second sub-abnormal functional region (derived through physical damage analysis) are combined, and the final multiple abnormal functional regions are determined by referring to the functional region mapping relationship. The functional region mapping relationship is obtained by matching the display chip model with the display chip database, and it describes the connection and dependency relationship between the functional regions inside the chip. Optionally, the display chip model information is obtained, and the functional region mapping relationship related to the model is retrieved from the database. The functional region mapping relationship is analyzed to understand the connection and dependency relationship between the functional regions. The first and second sub-abnormal functional regions are matched with the functional region mapping relationship to determine their mutual influence and correlation. Based on the matching result, the final multiple abnormal functional regions are determined. These regions include direct fault points, potential fault points, and other key functional regions related to the fault.

[0095] Specifically, suppose we are analyzing a display chip; in the previous steps, we have identified the first sub-abnormal functional area (such as the area where the power management IC is located and the area where the display driver circuit is located) and the first surface defect area (such as a scratch that runs through the signal processing area); now, we need to determine the second sub-abnormal functional area based on this information; by analyzing the spatial relationship between the scratch and the signal processing area, we find that the scratch has damaged a key component or circuit in the signal processing area, so this area is identified as the second sub-abnormal functional area.

[0096] Next, referring to the display chip model and the functional area mapping relationship in the database, the final multiple abnormal functional areas were determined. Through the mapping relationship, it was found that there is a close dependency between the power management area and the display driver area, while the signal processing area is directly connected to the display driver area. Therefore, the area where the power management IC is located, the area where the display driver circuit is located, and the signal processing area (affected by scratches) were all identified as abnormal functional areas. These abnormal functional areas are the direct or potential causes of tablet computer display failure. Through further inspection and testing, the specific fault points were determined, and corresponding repair measures were taken.

[0097] In one embodiment of this application, it is assumed that the weights of the power management area, signal processing area, display driving area, and interface connection area are 3, 4, 5, and 2, respectively (a larger weight indicates that the area is more important or more related to the fault); the score of the first sub-abnormal functional area (such as a power management IC fault) is its weight value of 3; the score of the second sub-abnormal functional area (such as a scratch in the signal processing area) is its weight value of 4 plus the correlation score with the first sub-abnormal functional area (assumed to be 1, because although the power management area does not directly affect signal processing, power instability affects signal processing); the scores of other functional areas (such as the display driving area and the interface connection area) are calculated based on whether they are directly related to the first or second sub-abnormal functional area; for example, the display driving area is directly related to the signal processing area, so its score is its weight value of 5 plus the correlation score with the signal processing area (assumed to be 2).

[0098] Power management area: 3 points (first sub-abnormal function area); Signal processing area: 5 points (second sub-abnormal function area + correlation score with power management area); Display driver area: 7 points (direct correlation score with signal processing area); Interface connection area: 2 points (only surface defects exist, no direct correlation); Based on the scores, the display driver area and signal processing area are identified as the most important abnormal function areas and need to be inspected and repaired first; Although the power management area is the first sub-abnormal function area, its score is low, indicating that the scope of the fault impact is limited or that other factors have caused the fault not to be fully manifested; The interface connection area has the lowest score and only surface defects exist, which is not the main cause of the fault.

[0099] refer to Figure 5 In step S14, multiple surface defect events are determined based on multiple abnormal functional areas, the database of display chips, and the model of display chips, and a second surface defect area is determined based on the multiple surface defect events and the surface image of the display chip; the second surface defect area is a surface defect area that cannot be directly observed from the surface image of the display chip.

[0100] In the specific implementation of this invention, the specific steps are as follows:

[0101] S141: Collect the locations of multiple abnormal functional areas, determine the transition area between multiple abnormal functional areas based on the locations of multiple abnormal functional areas, and determine whether the transition area is abnormal based on the detection of the transition area.

[0102] S142: If there is an anomaly in the transition area, the overall abnormal area of ​​the display chip is determined based on the abnormal transition area and multiple abnormal functional areas; the first defect event is determined based on the overall abnormal area and the database of the display chip; and the second defect event is determined based on the overall abnormal area and the model of the display chip.

[0103] S143: Determine the second surface defect region based on the first defect event, the second defect event, and the defect event mapping relationship. The second surface defect region and the first surface defect region are distributed on the same surface of the display chip. The second surface defect region is a surface defect region that cannot be directly observed by the surface image of the display chip.

[0104] In the embodiments of this application, the locations of multiple abnormal functional areas are collected, and a transition region between the multiple abnormal functional areas is determined based on the locations of the multiple abnormal functional areas. Based on the detection of the transition region, it is determined whether the transition region is abnormal.

[0105] At this point, the location information of each abnormal functional area on the display chip is obtained. This usually involves using high-precision measurement tools or image recognition technology to locate the boundaries of the abnormal functional area. The location information includes coordinates, dimensions, and relative position with respect to other parts of the chip. Optionally, images of the display chip are taken using a microscope or a high-resolution camera. The boundaries of the abnormal functional areas are identified and marked using image processing software. The coordinates and dimensions of each abnormal functional area are recorded.

[0106] After obtaining the location information of the abnormal functional regions, it is necessary to identify and determine the transition zones between these regions. The transition zones are located at the edges of the abnormal functional regions or on the paths connecting different abnormal functional regions. These regions function as bridges or buffers, so their abnormal states are crucial for understanding the functional failures of the entire chip. Optionally, based on the coordinates and dimensions of the abnormal functional regions, their boundaries are drawn on the chip image. The paths or edge regions connecting different abnormal functional regions are observed and marked as transition zones. The coordinates and boundaries of the transition zones are recorded.

[0107] Once the transition regions are identified, they need to be thoroughly inspected to determine if any anomalies exist. Inspections include physical checks (such as observing cracks, scratches, or contamination) and electrical tests (such as measuring resistance, capacitance, or signal integrity). These tests help determine if the transition regions are maintaining their intended function or if there are defects that could cause the entire chip to malfunction. Optionally, the physical condition of the transition regions can be observed using a microscope or scanning electron microscope; electrical tests can be performed, such as measuring resistance with a multimeter or observing signal waveforms with an oscilloscope; based on the results of the physical and electrical inspections, it can be determined whether any anomalies exist in the transition regions.

[0108] Specifically, suppose we are analyzing a display chip that has been identified in previous steps as having multiple abnormal functional areas, including a power management area and a display driver area; images of the chip have been taken using a high-resolution camera, and the boundaries of the power management area and the display driver area have been marked using image processing software; the coordinates and dimensions of these two areas have been recorded.

[0109] On the chip image, a narrow path connecting the power management area and the display driver area was observed; this path was marked as a transition area and its coordinates were recorded; microscopic observation of the transition area revealed tiny cracks; electrical testing revealed abnormally high resistance in the transition area, indicating an open circuit or poor contact; based on the above steps and observation results, it was determined that the transition area was abnormal, which obstructed signal transmission between the power management area and the display driver area, thus affecting the function of the entire chip. This discovery provided crucial information for subsequent repair or replacement work.

[0110] Furthermore, if an anomaly exists in the transition area, the overall abnormal area of ​​the display chip is determined based on the abnormal transition area and multiple abnormal functional areas; a first defect event is determined based on the overall abnormal area and the database of the display chip, and a second defect event is determined based on the overall abnormal area and the model of the display chip. This approach takes into account both the overall abnormal area and the model of the display chip, ensuring the accuracy of the second defect event.

[0111] At this point, when a transition area is identified as an anomaly, it needs to be combined with multiple known anomalous functional areas to determine a larger overall anomaly area. This overall anomaly area encompasses all affected functional areas and the transition zones between them, serving as the basis for further analysis of defect events and the development of remediation strategies. Optionally, review the locations and boundaries of multiple known anomalous functional areas; add the confirmed anomaly transition area to these functional areas; use image processing or Geographic Information System (GIS) tools to merge these areas into a single overall anomaly area; and record the coordinates, size, and shape of the overall anomaly area.

[0112] After identifying the overall anomaly area, the display chip's database is used to find known defect events that match that area. The database contains records of historical defect events, including the type, cause, scope of impact, and repair recommendations. The first defect event is identified by matching the overall anomaly area with the records in the database. Optionally, the display chip's database is accessed. The coordinates, size, and shape of the overall anomaly area are used as query criteria. Defect event records similar to the overall anomaly area are searched in the database. The first defect event is identified based on the degree of matching and relevance.

[0113] In addition to utilizing the database, it is also necessary to consider the display chip model information to determine the second defect event. Different display chip models have different design features, manufacturing processes, or known model-specific issues. Therefore, it is necessary to combine the overall abnormal area and the chip model to analyze and determine the second defect event that is related to both factors. Optionally, obtain the display chip model information; review the historical issues and known defects of the chip model; combine the location, size, and shape of the overall abnormal area to analyze the correlation between these defects and model-specific issues; and determine the second defect event based on the analysis results.

[0114] Specifically, suppose we are analyzing a display chip; it is known that there are anomalies in the power management area and the display driver area, and the transition area connecting these two areas is also confirmed to be anomaly; using image processing tools, we merge these three areas into a single abnormal area that covers a portion of the chip's core functional areas.

[0115] The first defect event was identified by accessing the display chip's database and inputting the coordinates and dimensions of the overall abnormal area. The database returned several defect event records similar to the overall abnormal area. One of the records showed that the abnormality in this area was usually related to "signal transmission failure between the power management module and the display driver module". Therefore, the first defect event was identified as "signal transmission failure between the power management module and the display driver module".

[0116] The second defect event was identified as follows: The display chip model was determined to be XYZ123; a review of historical issues and known defects of this chip model revealed a specific manufacturing defect that caused instability in the connection between the power management module and the display driver module; based on the location and size of the overall abnormal area and the description of the specific problem, the second defect event was determined to be "instable connection between the power management module and the display driver module caused by a unique manufacturing defect of the XYZ123 chip"; through this series of steps, not only was the overall abnormal area of ​​the display chip identified, but two defect events related to the abnormal area were also identified based on the database and chip model information. This information provided crucial basis for subsequent repair or replacement work.

[0117] Therefore, the second surface defect region is determined based on the first defect event, the second defect event, and the defect event mapping relationship. The second surface defect region and the first surface defect region are distributed on the same surface of the display chip. The second surface defect region is a surface defect region that cannot be directly observed by the surface image of the display chip. This method takes into account the overall consideration of the first defect event, the second defect event, and the defect event mapping relationship, and ensures the accuracy of the second surface defect region.

[0118] At this point, the defect event mapping relationship is a relational dataset that describes how different types of defect events generate visible and invisible defect areas on the display chip. This mapping relationship is established based on a deep understanding of historical data, physical principles, chip design knowledge, and manufacturing processes. It can help predict other unknown defect areas on the chip given certain known defect events. Optionally, you can access the database or model of the defect event mapping relationship; familiarize yourself with how the mapping relationship works, including how it predicts unknown defect areas based on known defect events; and ensure that the mapping relationship matches the display chip model and defect event type currently being analyzed.

[0119] Integrate the previously identified first and second defect events, which describe anomalies at different locations on the chip but are related or causally related. Integrating this information helps to gain a more comprehensive understanding of the defect situation on the chip. Optionally, review the descriptions and location information of the first and second defect events; analyze whether there is a correlation or causal relationship between the two events; and integrate the relevant information into a unified defect event report.

[0120] With the integrated defect event information and defect event mapping relationship, this step will use this information to predict the presence of second surface defect regions on the chip. These regions are hidden and cannot be directly observed through surface images. Optionally, the integrated defect event information can be input into the defect event mapping relationship. The mapping relationship is used to predict and determine the location, size, and nature of the second surface defect region. The prediction results are recorded, including the coordinates, size, and relationship of the second surface defect region to the first surface defect region.

[0121] Specifically, suppose we are analyzing a display chip with the model number ABC456, and the following two defect events have been identified: First defect event: signal transmission failure between the power management module and the display driver module; Second defect event: unstable connection between the power management module and the display driver module caused by a process defect specific to the ABC456 model chip.

[0122] Now, the defect event mapping relationship will be used to determine the second surface defect area; the defect event mapping relationship database for the ABC456 model chip was accessed; the working principle of the mapping relationship was familiarized, especially how it predicts other potential defect areas based on the defects of the power management module and the display driver module; the descriptions of the two defect events were reviewed and it was found that they both involved connection problems between the power management module and the display driver module; the analysis concluded that there was a causal relationship between the two events, that is, the process defect caused the signal transmission failure.

[0123] The integrated defect event information is input into the mapping relationship; the mapping relationship predicts that there is a hidden second surface defect area on the back of the display chip (i.e., the other side opposite to the first surface defect area), near the connection between the power management module and the display driver module; this second surface defect area is a tiny crack or internal poor connection, which cannot be detected by directly observing the surface image of the chip; through this series of steps, the second surface defect area on the display chip is successfully identified. This information is crucial for subsequent repair or replacement work because it points out other potential problems that need to be addressed in addition to the visible surface defects.

[0124] In one embodiment of this application, a defect event matching table is constructed based on historical data, physical principles, and chip design knowledge. This defect event matching table lists the correspondence between different types of defect events and the second surface defect regions they cause; the defect event matching table is shown in Table 2; Table 2 Defect Event Matching Table

[0125]

[0126] The known first and second defect events are matched with entries in the matching table to find the second surface defect area. At this time, the known first defect event is a signal transmission failure between the power management module and the display driver module. The known second defect event is an unstable connection between the power management module and the display driver module caused by a process defect specific to the ABC456 chip. The matching table is used to find the second surface defect area corresponding to these two defect events: a tiny crack or poor connection on the back side near the connection between the power management module and the display driver module.

[0127] refer to Figure 6 In step S15, the type of surface defect of the display chip is determined based on the second surface defect region and the first surface defect region.

[0128] In the specific implementation of this invention, the specific steps are as follows:

[0129] S151: Collect the second surface defect area and the first surface defect area, determine the overall defect area of ​​the display chip based on the second surface defect area and the first surface defect area, and determine multiple abnormal components of the display chip based on the overall defect area of ​​the display chip and the surface distribution map of the display chip.

[0130] S152: Determine multiple component combinations based on the location, shape, and combination relationship of multiple abnormal components, and determine multiple component defect events based on the identification of multiple component combinations;

[0131] S153: Collect the usage environment and service life of the display chip, and determine the type of surface defect of the display chip based on multiple component defect events, the usage environment and service life of the display chip.

[0132] In the embodiments of this application, a second surface defect region and a first surface defect region are collected, and the overall defect region of the display chip is determined based on the second surface defect region and the first surface defect region. Multiple abnormal components of the display chip are determined based on the overall defect region of the display chip and the surface distribution map of the display chip. This approach takes into account both the overall defect region of the display chip and the surface distribution map of the display chip, ensuring the accuracy of the multiple abnormal components of the display chip.

[0133] At this point, the second surface defect area and the first surface defect area are collected and integrated into a unified coordinate system; the overlap, adjacency, or mutual relationship between the first and second surface defect areas is analyzed; based on this information, a comprehensive defect area covering all known defects is determined; optionally, GIS (Geographic Information System) or CAD (Computer-Aided Design) software is used to integrate and analyze the data; spatial analysis methods are applied to identify the relationship between the first and second surface defect areas.

[0134] Obtain a surface map of the display chip, which details the location, type, and interconnections of all components on the chip; compare the overall defect area with the surface map to mark the components located within the defect area; analyze the function and importance of these components and their relationship with the defect area to determine which components are abnormal or affected by defects; optionally, use image processing software or CAD software to overlay the defect area with the surface map; apply algorithms to automatically identify components located within the defect area and generate a report.

[0135] Specifically, suppose we are analyzing a display chip with the model number XYZ123, which is used in high-end smartphones; First surface defect area: The first surface of the chip is photographed using a high-resolution camera, and a crack extending from the edge of the chip to the inside is found; Second surface defect area: Through X-ray inspection, a tiny cavity corresponding to the crack on the first surface is found on the back side (second surface) of the chip, which is caused by poor internal soldering or material defects.

[0136] By integrating the defect areas of the first and second surfaces into a single coordinate system, it was found that they almost completely overlapped, forming a continuous defect area extending from the chip edge to the interior. A surface distribution map of the XYZ123 chip was obtained, revealing that the defect area covered the power management module, several capacitors, and the connected signal transmission lines. Analysis of the function and importance of these components identified the power management module and the affected capacitors as anomalous components, as they are directly located within the defect area and are crucial to the normal operation of the chip. Through this series of steps, multiple anomalous components on the display chip were successfully identified, providing key information for subsequent analysis and repair work.

[0137] Furthermore, multiple component combinations are determined based on the location, shape, and combination relationship of multiple abnormal components, and multiple component defect events are determined based on the identification of multiple component combinations. This approach takes into account the overall consideration of the location, shape, and combination relationship of multiple abnormal components, ensuring the accuracy of multiple component combinations.

[0138] At this point, examine the physical location of each anomalous component on the display chip, paying particular attention to whether they are adjacent, located within the same functional module, or interconnected via circuitry. Observe the morphological characteristics of the anomalous components, such as size variations, color changes, and physical damage, as these characteristics indicate the failure mode or degree of damage. Based on the analysis of location and morphology, group anomalous components with logical relationships or physical connections together to form one or more component combinations. These combinations represent specific functional modules or circuit paths on the chip. Optionally, use CAD software or specialized electronic design automation (EDA) tools to visualize the location and morphology of the anomalous components; apply spatial clustering algorithms or graph theory methods to identify the relationships and combinations between components.

[0139] Each identified component assembly undergoes further review to identify key components within the assembly, their interconnections, and functional impacts. Referring to known defect patterns, historical data, and component specifications, defect events occurring in each component assembly are analyzed, including component damage, poor connections, and performance degradation. Based on this analysis, one or more specific defect events are identified for each component assembly; these events will serve as the basis for subsequent troubleshooting, repair, or replacement work. Optionally, Fault Tree Analysis (FTA) is used to identify and analyze defect events. A defect event learning model is applied to predict and classify defect events.

[0140] Specifically, suppose we are analyzing a display chip with the model number ABC789. In previous steps, we have identified several abnormal components in this display chip. The abnormal components are mainly concentrated in the power management area of ​​the chip, including a damaged power management IC, two swollen capacitors, and multiple signal lines connected to them. Through analysis of their location and shape, we can combine these components to form a component combination that represents the power management function.

[0141] Further examination of the component assembly revealed that the power management IC was damaged due to overheating, causing unstable output voltage; the swollen capacitors were due to electrolyte leakage caused by prolonged exposure to excessively high voltage; and the affected signal lines were transmitting incorrect signals due to the damage to the power management IC. Based on the above analysis, the following component defect events were identified: unstable output voltage caused by power management IC damage, electrolyte leakage in capacitors, and incorrect signal transmission in signal lines. Through this series of steps, not only were multiple component assemblies on the display chip identified, but specific defect events were also determined for each assembly, providing more detailed and accurate information for subsequent analysis and repair work.

[0142] Therefore, by collecting data on the operating environment and lifespan of the display chip, and determining the types of surface defects based on multiple component defect events, the operating environment, and the lifespan of the display chip, the system takes into account the overall factors of multiple component defect events, the operating environment, and the lifespan of the display chip, ensuring the accuracy of the types of surface defects. At the same time, by fully considering the second and first surface defect areas, the accuracy of the types of surface defects is further guaranteed.

[0143] At this stage, environmental conditions experienced by the display chip throughout its lifecycle are collected, including but not limited to temperature, humidity, vibration, and electromagnetic interference. This data is obtained through sensor monitoring, user feedback, or historical records. The potential impact of these environmental conditions on the display chip's performance and lifespan is analyzed; particular attention is paid to environmental factors that lead to component damage, performance degradation, or accelerated aging. Optionally, environmental monitoring systems or data analysis platforms are used to collect and analyze environmental data; statistical analysis and machine learning techniques are applied to assess the impact of environmental factors on chip performance.

[0144] Obtain information on the lifespan of the display chip from production to the present, which can be achieved by querying production records, user purchase records, or maintenance logs; analyze the impact of lifespan on the aging and performance degradation of display chip components; pay special attention to defect patterns that gradually emerge over time, such as material fatigue and loose connections; optionally, use a database management system or data warehouse to store and query lifespan information; apply lifespan prediction models or reliability analysis methods to assess the aging status of the chip.

[0145] This process integrates information on multiple component defect events, the display chip's operating environment, and its service life; analyzes the correlations and causal relationships between this information to determine the root causes of surface defects; based on the comprehensive analysis results, it identifies the types of surface defects present on the display chip, including physical damage (such as scratches and cracks), chemical corrosion (such as oxidation and corrosion), and electrical faults (such as short circuits and open circuits); based on the identified defect types, it develops targeted repair strategies or recommendations, including replacing damaged components, repairing connection problems, and adjusting the operating environment; optionally, it uses data fusion and decision support systems to integrate and analyze multiple data sources; and applies a pre-defined defect type learning model to identify and classify surface defect types.

[0146] Specifically, suppose we are analyzing a display chip of model XYZ456. This chip has already been identified as having multiple component defects in previous steps, and its operating environment and lifespan information have been collected. It has been found that the chip has been operating under extreme temperature conditions (up to 80°C) and frequently exposed to high humidity environments for the past few years. These environmental conditions have caused accelerated aging of certain materials on the chip, such as corrosion of metal wires and degradation of the insulation layer. This display chip has been used for 5 years, exceeding its design life of 3 years; during these 5 years, the chip has experienced multiple performance degradations and required repairs.

[0147] Based on component defect events (such as overheating damage to the power management IC and electrolyte leakage from capacitors), operating environment (extreme temperature and high humidity), and service life (exceeding design life), the following types of surface defects were identified: corrosion of metal wires and degradation of insulation due to prolonged high-temperature operation; short circuits and performance degradation due to capacitor electrolyte leakage; and overall performance degradation due to excessive service life and extreme environmental conditions. It is recommended to replace the damaged power management IC and capacitors, and to thoroughly clean and test the chip. Additionally, it is recommended to improve the chip's operating environment by reducing temperature and humidity to extend its remaining lifespan.

[0148] In one embodiment of this application, a defect type matching table is collected, as shown in Table 3:

[0149] Table 3 Defect Type Matching Table

[0150] Types of defects Typical component defect events Environmental characteristics Service life range Physical damage Scratches, cracks High temperature, mechanical stress any Chemical corrosion Oxidation and corrosion spots High humidity, corrosive gases >3 years Electrical fault Short circuit, open circuit, component overheating damage Voltage fluctuations, electromagnetic interference any Material aging Performance degradation, poor connection Long-term high temperature operation >5 years

[0151] Assume the display chip has scratches and cracks (component defect events), and the chip has been operating in a high-temperature environment for a long time (use environment characteristics), with a service life of 4 years; according to the defect type matching table, the most matching defect type is "physical damage".

[0152] Please see Figure 7 , Figure 7 This is a schematic diagram of the structural composition of the surface defect detection system for a display chip in an embodiment of the present invention; the surface defect detection system for the display chip includes:

[0153] Image module 21 is used to acquire surface images and internal structure images of the display chip when the display chip is in a fault state;

[0154] The first surface defect region module 22 is used to determine multiple functional regions based on the matching of the surface image and the internal structure image of the display chip, and to mark the first surface defect region of the surface image.

[0155] The abnormal function area module 23 is used to determine multiple abnormal function areas based on multiple function areas, the first surface defect area, and the fault signal of the display chip.

[0156] The second surface defect region module 24 is used to determine multiple surface defect events based on multiple abnormal functional regions, the database of display chips, and the model of display chips, and to determine a second surface defect region based on multiple surface defect events and the surface image of the display chip; the second surface defect region is a surface defect region that cannot be directly observed from the surface image of the display chip.

[0157] The surface defect type module 25 is used to determine the surface defect type of the display chip based on the second surface defect area and the first surface defect area.

[0158] The technical features of the above embodiments can be combined arbitrarily. To make the description more concise, not all combinations of the technical features in the above embodiments are described. However, as long as there is no technical contradiction in the combination of these technical features, they should be considered as the main scope of this specification.

Claims

1. A method of detecting surface defects of a display chip, characterized by, include: When the display chip is in a faulty state, acquire surface images and internal structure images of the display chip; Multiple functional regions are determined by matching the surface image and internal structure image of the display chip, and the first surface defect region of the surface image is marked. Multiple abnormal functional areas are identified based on multiple functional areas, the first surface defect area, and the fault signal of the display chip. Multiple surface defect events are determined based on multiple abnormal functional areas, the database of display chips, and the model of display chips, and a second surface defect area is determined based on multiple surface defect events and the surface image of display chips; The second surface defect region is a surface defect region that cannot be directly observed from the surface image of the display chip. It includes: acquiring the locations of multiple abnormal functional regions, determining transition regions between these regions based on their locations, and determining whether these transition regions are abnormal based on their detection; if these transition regions are abnormal, determining the overall abnormal region of the display chip based on the abnormal transition regions and the multiple abnormal functional regions; determining a first defect event based on the overall abnormal region and the display chip's database, and determining a second defect event based on the overall abnormal region and the display chip's model; determining the second surface defect region based on the mapping relationship between the first defect event, the second defect event, and the defect event itself. The second surface defect region and the first surface defect region are distributed on the same surface of the display chip, and the second surface defect region is a surface defect region that cannot be directly observed from the surface image of the display chip; the transition region is located on the path connecting different abnormal functional regions. The process of determining the types of surface defects in a display chip based on the second and first surface defect regions includes: acquiring the second and first surface defect regions; determining the overall defect region of the display chip based on the second and first surface defect regions; identifying multiple abnormal components of the display chip based on the overall defect region and the surface distribution map of the display chip; integrating the first and second surface defect regions into a unified coordinate system; analyzing whether the first and second surface defect regions overlap, are adjacent, or are related to each other; based on this information, determining an overall defect region covering all known defects; comparing the overall defect region with the surface distribution map to mark the components located within the defect region; analyzing the function, importance, and relationship of these components to the defect region to determine which components are abnormal or affected by defects.

2. The display chip surface defect inspection method according to claim 1, wherein When the display chip is in a faulty state, the acquisition of surface images and internal structure images of the display chip includes: Collect multiple operating parameters of the display chip, and determine multiple fault parameters of the display chip based on the multiple operating parameters and fault signals. Determine the fault status of the display chip based on the multiple fault parameters, the model of the display chip, and the fault status mapping relationship. The system monitors the fault status of the display chip in real time, determines the detection parameters of the visual inspection section based on the fault status, size, and previous detection data of the display chip, and performs surface inspection on the display chip to output a surface image of the display chip. The X-ray inspection parameters are determined based on the fault status of the display chip, the thickness of the display chip, and the previous inspection data of the display chip. The X-ray inspection section performs internal inspection on the display chip to output an image of the internal structure of the display chip.

3. The display chip surface defect inspection method according to claim 1, wherein The process of determining multiple functional regions based on the matching of the surface image and the internal structure image of the display chip, and marking the first surface defect region of the surface image, includes: Acquire surface and internal structure images of the display chip, and determine the stacked structure model of the display chip based on the surface and internal structure images. At this time, the stacked structure model contains multiple functional circuit paths. Multiple functional circuit paths and surface images based on the stacked structure model are used to determine multiple functional regions of the display chip, which are then presented on the surface of the display chip. Multiple surface anomaly features are determined based on surface detection of the surface image of the display chip. The first surface defect region of the surface image is determined according to the location, type, and influence range of the multiple surface anomaly features. The first surface defect region of the surface image is the surface defect region directly observed by the surface image of the display chip.

4. The surface defect detection method for a display chip according to claim 1, characterized in that, The determination of multiple abnormal functional regions based on multiple functional regions, a first surface defect region, and fault signals from the display chip includes: The fault signals of the display chip are collected, and the fault content of the display chip is determined by analyzing the fault signals. Based on the division of the fault content of the display chip, multiple fault items of the display chip are determined.

5. The surface defect detection method for a display chip according to claim 4, characterized in that, The method of determining multiple abnormal functional regions based on multiple functional regions, a first surface defect region, and fault signals from the display chip further includes: A surface region with multiple functional areas is marked on the surface of the display chip, and a first sub-abnormal functional area is determined based on the matching of the surface region with multiple fault items of the display chip. The second sub-abnormal functional region is determined based on the surface region of multiple functional regions and the first surface defect region. Multiple abnormal functional regions are determined based on the mapping relationship between the first sub-abnormal functional region, the second sub-abnormal functional region, and the functional region. This functional region mapping relationship is obtained by matching the display chip model and the display chip database.

6. The surface defect detection method for a display chip according to claim 1, characterized in that, The step of determining the type of surface defect in the display chip based on the second surface defect region and the first surface defect region further includes: Multiple component combinations are determined based on the location, shape, and combination relationship of multiple abnormal components, and multiple component defect events are determined based on the identification of multiple component combinations; The system collects information on the operating environment and lifespan of the display chip, and determines the types of surface defects in the display chip based on multiple component defect events, the operating environment, and the lifespan of the display chip.

7. A surface defect detection system for a display chip, characterized in that, The surface defect detection system for the display chip is applied to the surface defect detection method for the display chip as described in any one of claims 1-6, and the surface defect detection system for the display chip comprises: The image module is used to acquire surface and internal structure images of the display chip when the display chip is in a faulty state. The first surface defect region module is used to determine multiple functional regions based on the matching of the surface image and the internal structure image of the display chip, and to mark the first surface defect region of the surface image. An abnormal functional area module is used to determine multiple abnormal functional areas based on multiple functional areas, a first surface defect area, and fault signals from the display chip. The second surface defect region module is used to determine multiple surface defect events based on multiple abnormal functional regions, the display chip's database, and the display chip's model, and to determine a second surface defect region based on the multiple surface defect events and the display chip's surface image. The second surface defect region is a surface defect region that cannot be directly observed from the display chip's surface image. This includes: acquiring the positions of multiple abnormal functional regions, determining transition regions between these regions based on their positions, and determining whether the transition region is abnormal based on its detection. If the transition region is abnormal, the module determines the overall abnormal region of the display chip based on the abnormal transition region and the multiple abnormal functional regions. It also determines a first defect event based on the overall abnormal region and the display chip's database, and a second defect event based on the overall abnormal region and the display chip's model. The module determines the second surface defect region based on the mapping relationship between the first defect event, the second defect event, and the defect event. The second surface defect region and the first surface defect region are distributed on the same surface of the display chip, and the second surface defect region is a surface defect region that cannot be directly observed from the display chip's surface image. The transition region is located on the path connecting different abnormal functional regions. The surface defect type module is used to determine the surface defect type of the display chip based on the second surface defect region and the first surface defect region. This includes: acquiring the second and first surface defect regions; determining the overall defect region of the display chip based on the second and first surface defect regions; identifying multiple abnormal components of the display chip based on the overall defect region and the surface distribution map of the display chip; integrating the first and second surface defect regions into a unified coordinate system; analyzing whether the first and second surface defect regions overlap, are adjacent, or are related; based on this information, determining an overall defect region covering all known defects; comparing the overall defect region with the surface distribution map to mark the components located within the defect region; and analyzing the function, importance, and relationship of these components to the defect region to determine which components are abnormal or affected by defects.

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