Quasi-cyclic double-diagonal LDPC (Low Density Parity Check) coding device, system and method for efficiently utilizing resources

By optimizing the design of the quasi-cyclic double-diagonal LDPC encoder, using RAM storage modules and exclusive OR operations to dynamically adjust the encoder status, the problem of resource waste in medium and low-speed communication is solved, and an efficient and flexible encoding solution is achieved, and the overall performance of the spread spectrum communication system is improved.

CN120546709APending Publication Date: 2025-08-2610TH RES INST OF CETC
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Patent Information

Application Number
CN202510552675.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-04-29
Publication Date
2025-08-26

AI Technical Summary

Technical Problem

The existing quasi-cyclic double-diagonal LDPC encoder consumes too much resource in medium and low-speed communication scenarios, lacks overall optimization of the encoder and the entire spread spectrum communication system, and the existing research focuses on the design of separate encoders, and fails to effectively utilize resources.

Method used

A quasi-cyclical double-diagonal LDPC encoding device with efficient resource utilization is designed, including a RAM storage module, a read address calculation module and a control module. By cyclically reading RAM data and performing XOR operations to generate verification data, dynamically adjust the encoder state to adapt to different spread spectrum rates, avoiding storing intermediate variables and complex mathematical operations.

Benefits of technology

It significantly reduces the computational complexity and storage resource consumption, improves the integration and reliability of the encoder, realizes good coordinated work between the encoder and subsequent modules, adapts to the information transmission needs of different rates, and improves the stability and performance of the system.

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Abstract

The invention discloses a quasi-cyclic double diagonal LDPC (Low Density Parity Check) coding device, system and method capable of efficiently utilizing resources, and belongs to the field of LDPC coding, and the device comprises an RAM (Random Access Memory) storage module, a read address calculation module, a check bit operation module and a control module; the RAM storage module is used for storing data to be coded; the read address calculation module is used for circularly reading the data to be coded in the RAM; the check bit operation module is used for executing exclusive-or operation on the read data to be coded to directly generate check data; and the control module is used for dynamically adjusting the working state of the encoder so as to realize compatibility with different spread spectrum rates. The method is suitable for a spread spectrum communication system, and has the advantages of few storage resources, simplicity in operation, controllable coding rate and high universality.
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