Display panel, driving method thereof, driving circuit and display device

Abstract

The application provides a display panel, a driving method and circuit thereof, and a display device. The display panel comprises a plurality of scanning lines, a plurality of data lines, and pixel circuits arranged in an array. Each pixel circuit comprises a light emitting unit, a light emitting driving unit, a storage capacitor, a switching circuit, a data switch, and a logic circuit. The logic circuit performs AND operation on an input row scanning signal and a data signal, and outputs a corresponding first level signal or a second level signal. The switching circuit stores a data signal of a next frame to the storage capacitor or maintains a data signal of a previous frame in a sampling period, and drives the light emitting unit to emit light in a light emitting period by triggering a driving tube to output a current signal by the light emitting signal. By selecting whether to input the data signal and the row scanning signal to the data line and the scanning line, the corresponding pixel circuit can be controlled to maintain a current picture and switch a display picture, independent control of a single pixel circuit can be realized, and display requirements of different refresh rates can be met.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display panels, and particularly relates to a display panel, a driving method thereof, a driving circuit and a display device. BACKGROUND

[0002] With the development of display technology and market demand, high refresh rate display devices gradually enter people's visual field. Compared with traditional display devices, high refresh rate display devices have the advantages of smoother visual experience, faster response speed, and reduced visual fatigue. However, at the same time, high refresh rate also brings higher power consumption demand.

[0003] In view of the contradiction between visual picture pursuit and power consumption demand, a local refresh rate differentiation FFR (free frame rate) technology is proposed. When displaying a static picture, when it is judged that the local display content of the picture does not change, it is low refresh rate, and when the picture content changes in the next frame, it is high refresh rate.

[0004] However, the current FRR technology is based on the timing adjustment of multiple GOA units of the gate driving circuit, which has great limitations. First, in the gate driving circuit, the GOA unit controls the picture in at least one line unit, and the local adjustment of the refresh rate based on the picture content change is complex. For example, when the same line has different positions that require different refresh rates, it cannot be realized.

[0005] In addition, due to the design characteristics of the GOA unit, the FFR technology based on the timing adjustment of the GOA requires that the refresh rate of the previous row is higher than that of the next row, which greatly limits the application scenarios of the technology. SUMMARY

[0006] The purpose of the present application is to provide a display panel, which aims to solve the problem that the driving architecture in the traditional display device cannot meet the different refresh rate requirements of different positions.

[0007] The first aspect of the embodiment of the present application proposes a display panel, comprising a plurality of scan lines, a plurality of data lines and an array of pixel circuits, the pixel circuit comprising:

[0008] a light emitting unit;

[0009] a light emitting driving unit, connected in series between the anode voltage end and the cathode voltage end, the light emitting driving unit comprising a first light emission switch, a driving tube and a second light emission switch connected in series, the driving tube being used for converting a data signal input in a sampling period into a current signal, the first light emission switch and the second light emission switch being used for being triggered to conduct to output the current signal in a light emitting period;

[0010] A storage capacitor, wherein a first terminal of the storage capacitor is connected to the anode voltage terminal or the cathode voltage terminal;

[0011] A switching circuit is connected to the second terminal of the storage capacitor, the anode voltage terminal, the control terminal and the output terminal of the driving transistor, respectively. The switching circuit is triggered by a first level signal to connect the anode voltage terminal and the control terminal of the driving transistor, and to connect the second terminal of the storage capacitor and the output terminal of the driving transistor. It is also triggered by a second level signal to connect the second terminal of the storage capacitor and the control terminal of the driving transistor.

[0012] A data switch is connected to the input terminals of the data line, the scan line, and the driving transistor, respectively. The data switch is triggered to turn on by a row open signal and transmits the data signal on the data line to the driving transistor, and is triggered to turn off by a row close signal.

[0013] A logic circuit, connected to the data line, the scan line, and the switch circuit respectively, is used to trigger the output of the first level signal to the switch circuit when the row enable signal and the data signal are received simultaneously, and to trigger the output of the second level signal to the switch circuit when the row enable signal and the data signal are not received simultaneously.

[0014] Optionally, the first optical emission switch includes a first transistor, the second terminal of the first transistor is connected to the input terminal of the driving transistor, and the control terminal of the first transistor is used to input the optical emission signal;

[0015] The second light-emitting switch includes a second transistor, the first terminal of which is connected to the output terminal of the driving transistor, the control terminal of which is connected to the control terminal of the first transistor, the first terminal of which is connected to the anode voltage terminal, and the second terminal of which is connected to the light-emitting unit; or, the first terminal of which is connected to the light-emitting unit and the second terminal of which is connected to the cathode voltage terminal.

[0016] Optionally, the switching circuit includes a third transistor, a fourth transistor, and a fifth transistor;

[0017] The first terminal of the third transistor and the first terminal of the storage capacitor are connected to the anode voltage terminal. The second terminal of the third transistor and the second terminal of the fourth transistor are connected to the control terminal of the driving transistor. The first terminal of the fourth transistor, the first terminal of the fifth transistor, and the second terminal of the storage capacitor are connected. The control terminals of the third transistor, the fourth transistor, and the fifth transistor are connected to the output terminal of the logic circuit.

[0018] Optionally, the logic circuit comprises a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor.

[0019] The first end of the sixth transistor is configured to input the first level signal, the second end of the sixth transistor is connected with the first end of the seventh transistor, the control end of the sixth transistor, the control end of the eighth transistor and the scan line are connected, the second end of the seventh transistor, the first end of the eighth transistor and the first end of the ninth transistor are connected to form an output end of the logic circuit, the control end of the seventh transistor and the control end of the ninth transistor are connected with the data line, and the second end of the eighth transistor and the second end of the ninth transistor are connected and configured to input the second level signal.

[0020] Optionally, the pixel circuit further comprises:

[0021] a reset switch, the first end of the reset switch is configured to input a reset signal, the second end of the reset switch is connected with the light emitting unit, the control end of the reset switch is connected with the output end of the logic circuit, and the reset switch is triggered to be turned on by the first level signal and is triggered to be turned off by the second level signal.

[0022] A second aspect of the embodiment of the present application provides a driving method of a display panel, configured to drive the display panel as described above, and the driving method of the display panel comprises:

[0023] determining whether the picture content of the next frame of the target local picture of the display panel changes;

[0024] when the picture content of the next frame of the target local picture does not change, switching to a maintenance mode, outputting a corresponding row enable signal and not outputting a data signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, and controlling the storage capacitor of the target pixel circuit to maintain the data signal of the previous frame;

[0025] when the picture content of the next frame of the target local picture changes, switching to a working mode, outputting a corresponding data signal and the row enable signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, and controlling the storage capacitor of the target pixel circuit to input the data signal of the current frame.

[0026] Optionally, when the picture content of the next frame of the target local picture does not change, switching to the maintenance mode, and outputting a corresponding row enable signal and not outputting a data signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, comprises:

[0027] In the sampling period of the maintaining mode, the row-on signal is output to the scan line, and the data signal is not output to the data line.

[0028] In the light-emitting period of the maintaining mode, the row-on signal is not output to the scan line, and the data signal of the next frame is output to the data line or the data signal is not output to the data line.

[0029] Optionally, when the picture content of the next frame of the target local picture changes, the working mode is switched to, and in the next frame scanning driving, the corresponding data signal and the row-on signal are output to the target pixel circuit corresponding to the target local picture.

[0030] In the sampling period of the working mode, the row-on signal is output to the scan line and the data signal is output to the data line.

[0031] In the light-emitting period of the working mode, the row-on signal is not output to the scan line, and the data signal of the next frame is output to the data line or the data signal is not output to the data line.

[0032] A third aspect of the embodiment of the present application provides a driving circuit of a display panel, comprising a source driving circuit, a gate driving circuit and a timing controller, the source driving circuit is connected with a plurality of data lines of the display panel respectively, the gate driving circuit is connected with a plurality of scan lines of the display panel respectively.

[0033] The timing controller is connected with the source driving circuit and the gate driving circuit respectively, and is used for outputting a control signal to the source driving circuit and the gate driving circuit, so as to realize the driving method of the display panel.

[0034] A fourth aspect of the embodiment of the present application provides a display device, comprising the display panel and the driving circuit of the display panel, the driving circuit of the display panel is connected with the display panel.

[0035] Compared with the prior art, the display panel provided by the embodiment of the present application has the beneficial effects that: the display panel includes a plurality of scanning lines, a plurality of data lines and arrayed pixel circuits, the pixel circuit includes a light emitting unit, a light emitting driving unit, a storage capacitor, a switching circuit, a data switch and a logic circuit, the logic circuit performs AND operation on the input row scanning signal and data signal, and outputs the corresponding first level signal or second level signal to the switching circuit, so as to control the switching circuit to store the data signal of the next frame to the storage capacitor in the sampling period or control the storage capacitor to maintain the data signal of the last frame, and the light emitting unit is driven by the current signal output by the driving tube triggered by the light emission signal in the light emitting period, so as to control the corresponding pixel circuit to maintain the current picture and switch the display picture, and the independent control of the single pixel circuit can be realized, and the display requirement of different refresh rates can be met. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A first structure schematic diagram of the display panel provided by the embodiment one of the present application is provided.

[0037] Figure 2 A second structure schematic diagram of the display panel provided by the embodiment one of the present application is provided.

[0038] Figure 3 A first circuit schematic diagram of the pixel circuit provided by the embodiment one of the present application is provided.

[0039] Figure 4 A first signal timing schematic diagram of the pixel circuit provided by the embodiment one of the present application is provided.

[0040] Figure 5 A second signal timing schematic diagram of the pixel circuit provided by the embodiment one of the present application is provided.

[0041] Figure 6 A third signal timing schematic diagram of the pixel circuit provided by the embodiment one of the present application is provided.

[0042] Figure 7 A fourth signal timing schematic diagram of the pixel circuit provided by the embodiment one of the present application is provided.

[0043] Figure 8 A second circuit schematic diagram of the pixel circuit provided by the embodiment one of the present application is provided.

[0044] Figure 9 A circuit schematic diagram of the pixel circuit provided by the embodiment two of the present application is provided.

[0045] Figure 10 A flow schematic diagram of the driving method of the display panel provided by the embodiment three of the present application is provided.

[0046] Figure 11For Figure 10 The flowchart of step S20 of the driving method of the display panel shown in FIG. 10;

[0047] Figure 12 For Figure 10 The flowchart of step S30 of the driving method of the display panel shown in FIG. 11;

[0048] Figure 13 The structural schematic diagram of the driving circuit and the display device of the display panel provided in Embodiment Four and Embodiment Five of the present application.

[0049] In the drawings, various reference signs are used as follows:

[0050] 100, display panel; 200, driving circuit of the display panel; 210, source driving circuit; 220, gate driving circuit; 230, timing controller; 10, pixel circuit; 20, light emitting unit; 101, light emitting driving unit; 11, first light emission switch; 12, second light emission switch; 13, switch circuit; 14, data switch; 15, logic circuit; 16, reset switch;

[0051] SD, driving tube; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; Cst, storage capacitor; OLED, light emitting diode; S1, first data line; S2, second data line; S3, third data line; S4, fourth data line; G1, first scanning line; G2, second scanning line; G3, third scanning line; G4, fourth scanning line; G5, fifth scanning line; G6, sixth scanning line;

[0052] VDD, anode voltage; VSS, cathode voltage; Da, data signal; Sc, row scanning signal; Sc1, first row scanning signal; Sc2, second row scanning signal; Sc3, third row scanning signal; Da1, first data signal; Da2, second data signal; Da3, third data signal; Vint, reset signal; EM, light emission signal; VGH, row opening signal; VGL, row closing signal; Vd, end voltage of the light emitting unit;

[0053] t11, sampling period of the first frame; t12, light emitting period of the first frame; t21, sampling period of the second frame; t22, light emitting period of the second frame; t31, sampling period of the third frame; t32, light emitting period of the third frame. DETAILED DESCRIPTION

[0054] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0055] The terms "first", "second" are only for descriptive purposes and cannot be understood to indicate or imply relative importance or implicitly indicate the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0056] Embodiment one

[0057] The first aspect of the embodiment of the present application proposes a display panel 100, as shown in Figure 1 and Figure 2 It includes a plurality of scan lines, a plurality of data lines and an array of pixel circuits 10, for example Figure 1 As shown in Figure 2 The first row and the first column of the pixel circuit 10 are connected with the first scan line G1 and the first data line S1 and input the first row scan signal Sc1 and the first data signal Da1, the second row and the second column of the pixel circuit 10 are connected with the second scan line G2 and the second data line S2 and input the second row scan signal Sc2 and the second data signal Da2, the third row and the third column of the pixel circuit 10 are connected with the third scan line G3 and the third data line S3 and input the third row scan signal Sc3 and the third data signal Da3, the pixel circuit 10 is used to generate a current signal to the light emitting unit 20 inside the pixel circuit 10 according to the received row scan signal Sc and data signal Da, and the light emitting unit 20 corresponds to light up.

[0058] Among them, in order to realize the independent control of each pixel circuit 10 or target pixel circuit of the target local picture, meet the demand of different refresh rate, the pixel circuit 10 includes:

[0059] The light emitting unit 20;

[0060] The light emitting driving unit 101 is connected in series between the anode voltage end and the cathode voltage end, the anode voltage end is used to input the anode voltage VDD, the cathode voltage end is used to input the cathode voltage VSS, and the anode voltage VDD is greater than the cathode voltage VSS.

[0061] The relative positions of the light emitting unit 20 and the light emitting driving unit 101 can be set according to requirements. In an optional embodiment, as shown in FIG. 1, the anode voltage terminal, the light emitting driving unit 101, the light emitting unit 20 and the cathode voltage terminal are connected in sequence, or in another optional embodiment, the anode voltage terminal, the light emitting unit 20, the light emitting driving unit 101 and the cathode voltage terminal are connected in sequence. Figure 3

[0062] As shown in FIG. 2, the light emitting driving unit includes a first light emission switch 11, a driving tube SD and a second light emission switch 12 connected in sequence, the driving tube SD is used to convert the data signal Da input in the sampling period into a current signal, and the first light emission switch 11 and the second light emission switch 12 are used to be turned on to output the current signal under the triggering of the light emission signal EM in the light emitting period. Figure 3

[0063] The storage capacitor Cst has a first end connected to the anode voltage terminal, or in another optional embodiment, a first end connected to the cathode voltage terminal. The storage capacitor Cst can be connected to a voltage terminal with a stable voltage.

[0064] The switch circuit 13 is connected to the second end of the storage capacitor Cst, the anode voltage terminal, the control end and the output end of the driving tube SD respectively. The switch circuit 13 is triggered to connect the anode voltage terminal and the control end of the driving tube SD and to connect the second end of the storage capacitor Cst and the output end of the driving tube SD under the triggering of the first level signal, and is triggered to connect the second end of the storage capacitor Cst and the control end of the driving tube SD under the triggering of the second level signal.

[0065] The data switch 14 is connected to the data line, the scanning line and the input end of the driving tube SD respectively. The data switch 14 is triggered to be turned on and to transmit the data signal Da on the data line to the driving tube SD under the triggering of the row opening signal VGH, and is triggered to be turned off under the triggering of the row closing signal VGL.

[0066] The logic circuit 15 is connected to the data line, the scanning line and the switch circuit 13 respectively, and is used to trigger to output the first level signal to the switch circuit 13 when the row opening signal VGH and the data signal Da are received at the same time, and is used to trigger to output the second level signal to the switch circuit 13 when the row opening signal VGH and the data signal Da are not received at the same time.

[0067] ​​In this embodiment, the driving transistor SD can be a P-channel thin-film transistor or an N-channel thin-film transistor. The row scanning signal Sc consists of a row enable signal VGH and a row disable signal VGL. In each frame, each pixel circuit 10 can operate sequentially in the sampling period and the emission period. When the current frame is scanned to the pixel circuit 10 of the corresponding row, during the sampling period, the row enable signal VGH is input to the scan line connected to the corresponding pixel circuit 10, and the data line connected to the corresponding pixel circuit 10 inputs the data signal Da or does not input the data signal Da. During the emission period, the row disable signal VGL is input to the corresponding scan line. At the same time, the pixel circuit 10 receives the light emission signal EM and generates a current signal to the light-emitting unit 20, and drives the light-emitting unit 20 to light up.

[0068] The pixel circuit 10 can switch between working mode and holding mode according to the received data signal Da and line scan signal Sc. The working mode can refresh the input data signal Da, and the holding mode can retain the data signal Da of the previous frame.

[0069] In progressive scan, when scanning to a number of pixel circuits 10 of a target local image, the number of target pixel circuits may include one or more.

[0070] Taking the first terminal of the storage capacitor Cst connected to the anode voltage terminal as an example, refer to... Figure 4 As shown, Vd represents the terminal voltage of the light-emitting unit 20. In the working mode, during the sampling period of the pixel circuit 10, such as the sampling period t11 of the first frame, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row enable signal VGH, the data line connected to the pixel circuit 10 inputs the data signal Da, the logic circuit 15 outputs the first level signal, and the switch circuit 13 connects the anode voltage terminal and the control terminal of the driving transistor SD, as well as the second terminal of the storage capacitor Cst and the output terminal of the driving transistor SD. At this time, no light emission signal EM is input, and the first light emission switch 11 and the second light emission switch 2 are connected. When the transmit switch 12 is turned off, the data signal Da is output to the storage capacitor Cst through the driver transistor SD and the switching circuit 13. In the loop formed by the anode voltage terminal, the storage capacitor Cst, the switching circuit 13, the driver transistor SD and the data line, according to Kirchhoff's law, VDD-Vdata+Vcst-VDD-Vth=0, that is, Vcst=Vdata+Vth, where Vcst is the storage voltage of the storage capacitor Cst, Vth is the threshold voltage of the driver transistor SD, and Vdata is the data voltage of the data signal Da. The pixel circuit 10 completes the sampling of the data signal Da.

[0071] Then, in the light emitting period, such as the light emitting period t12 of the first frame, when the scanning of the current line ends and no data signal Da is input to other lines, at this time, the row close signal VGL is input to the scanning line connected to the pixel circuit 10, no data signal Da is input to the data line connected to the pixel circuit 10, the second level signal is output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the drive tube SD by the switch circuit 13, the storage voltage of the storage capacitor Cst is output to the drive tube SD, at this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the drive tube SD and the second light emission switch 12 form a current loop, the drive tube SD generates a current signal and outputs the current signal to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data of the sampling stage and normally emits light, and high refresh rate is realized.

[0072] Alternatively, in the light emitting period, when scanning to other lines, the data signal Da is switched to be input to the data signal Da by the data line of other lines, at this time, the row close signal VGL is input to the scanning line connected to the pixel circuit 10, the second level signal is still normally output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the drive tube SD by the switch circuit 13, the storage voltage of the storage capacitor Cst is output to the drive tube SD, at this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the drive tube SD and the second light emission switch 12 form a current loop, the drive tube SD generates a current signal and outputs the current signal to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data of the sampling stage and normally emits light, and high refresh rate is realized.

[0073] When switching to the maintenance mode of the next frame, in the sampling period of the pixel circuit 10, such as the sampling period t21 of the second frame, when scanning to the line where the pixel circuit 10 is located, the row open signal VGH is input to the scanning line connected to the pixel circuit 10, no data signal Da is input to the data line connected to the pixel circuit 10, at this time, the data line is in a low level state, the second level signal is output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the drive tube SD by the switch circuit 13, at this time, no light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned off, the data signal Da stored in the storage capacitor Cst of the previous frame cannot be output to the storage capacitor Cst through the drive tube SD and the switch circuit 13 or be refreshed by the new data signal Da, and the storage capacitor Cst will keep the storage voltage of the previous frame.

[0074] Then, in the light emitting period, such as the light emitting period t22 of the second frame, when the scanning of the current line ends and no data signal Da is input to other lines, at this time, the row close signal VGL is input to the scanning line connected to the pixel circuit 10, no data signal Da is input to the data line connected to the pixel circuit 10, the second level signal is output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the driving tube SD by the switch circuit 13, and the storage voltage of the storage capacitor Cst, i.e., the storage voltage of the previous frame, is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the driving tube SD, and the second light emission switch 12 form a current loop, the driving tube SD generates a current signal and outputs the current signal to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data of the sampling stage and normally emits light, and the low refresh rate of the local picture is realized.

[0075] Alternatively, in the light emitting period, when the scanning is performed on other lines, the data signal Da is switched to be input to the data line by the data signal Da of the other lines, at this time, the row close signal VGL is input to the scanning line connected to the pixel circuit 10, the second level signal is still normally output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the driving tube SD by the switch circuit 13, and the storage voltage of the previous frame is output to the driving tube SD. At this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the driving tube SD, and the second light emission switch 12 form a current loop, the driving tube SD generates a current signal and outputs the current signal to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data of the previous frame and normally emits light, the same display information is displayed by the pixel circuit 10 based on the same data signal Da in the previous and next frames, and the low refresh rate of the local picture is realized.

[0076] When the working mode of the next frame is switched, such as the sampling period t31 of the third frame, when the scanning is performed on the line where the pixel circuit 10 is located, the row open signal VGH is input to the scanning line connected to the pixel circuit 10, the data signal Da is input to the data line connected to the pixel circuit 10 again, the first level signal is output by the logic circuit 15, the anode voltage end is connected to the control end of the driving tube SD by the switch circuit 13, and the second end of the storage capacitor Cst is connected to the output end of the driving tube SD. At this time, the light emission signal EM is not input, the first light emission switch 11 and the second light emission switch 12 are turned off, the input data signal Da is output to the storage capacitor Cst through the driving tube SD and the switch circuit 13, and the sampling of the data signal Da is completed by the pixel circuit 10.

[0077] Then, in the light emitting period, such as the light emitting period t32 of the third frame, the logic circuit 15 outputs the second level signal, the switch circuit 13 connects the second end of the storage capacitor Cst and the control end of the drive tube SD, the refreshed storage voltage stored in the storage capacitor Cst is output to the drive tube SD, at this time, the input light emission signal EM, the first light emission switch 11 and the second light emission switch 12 are turned on, the drive tube SD generates a current signal and is output to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the refreshed gray scale data in the sampling stage and normally emits light.

[0078] The data signal Da is used as a data voltage for display and as a control signal of the logic circuit, when the pixel circuit 10 of the target local picture needs to be in a low refresh rate, the data signal Da can be selected to be cut off to the data line connected to the pixel circuit 10 when scanning to the row where the pixel circuit 10 is located, that is, the pixel circuit 10 can be switched to the maintenance mode, that is, the low refresh rate is realized.

[0079] Therefore, the pixel circuit 10 can be refreshed or maintained under the control of the double signals of the data signal Da and the input row scanning signal Sc, so as to realize the control of the refresh rate of the target pixel circuit.

[0080] When it is needed to realize the local low refresh rate in the column direction of the display panel 100, as shown in Figure 2 and Figure 5 When the pixel circuit 10 in the second column needs to be in a low refresh rate, the first data line S1 and the third data line S3 can normally input the first data signal Da1 and the third data signal Da3 in the row-by-row scanning, and the second data line S2 is selected not to input the second data signal Da2 and is correspondingly pulled down to the low level, so that in the row-by-row scanning, the pixel circuit 10 in the second column maintains the gray scale data of the last frame and emits light, realizing the low refresh rate, while the pixel circuit 10 in the first column and the pixel circuit 10 in the third column refresh the input gray scale data of the next frame and emit light, realizing the high refresh rate, and further realizing the local low refresh rate in the column direction of the display panel 100.

[0081] When it is needed to realize the local low refresh rate in the row direction of the display panel 100, as shown in Figure 2 and Figure 6As shown, if the pixel circuit 10 of the second row needs to be at a low refresh rate, during line-by-line scanning, when scanning to the pixel circuit 10 of the first row and the pixel circuit 10 of the third row, each data line can normally input data signal Da. The pixel circuit 10 of the first row and the pixel circuit 10 of the third row refresh input the grayscale data of the next frame and emit light, achieving a high refresh rate. However, when scanning to the pixel circuit 10 of the second row, each data line does not input data signal Da and is pulled low. The pixel circuit 10 of the second row maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate, thereby achieving a local low refresh rate in the row direction of the display panel 100.

[0082] And when individual pixel circuits 10 need to be at a low refresh rate, such as Figure 2 and Figure 7 As shown, when the pixel circuit 10 in the second row and second column and the pixel circuit 10 in the third row and third column need to be at a low refresh rate, when scanning to each pixel circuit 10 in the first row, each data line can normally input data signal Da, and each pixel circuit 10 in the first row refreshes the input grayscale data of the next frame and emits light, thus achieving a high refresh rate.

[0083] When scanning to each pixel circuit 10 in the second row, the first data line S1 and the third data line S3 normally input the first data signal Da1 and the third data signal Da3. The two pixel circuits 10 in the first column of the second row and the third column of the second row refresh the input of the grayscale data of the next frame and emit light to achieve a high refresh rate. The second data line S2 does not input the second data signal Da2 and is pulled low. The pixel circuit 10 in the second column of the second row maintains the grayscale data of the previous frame and emits light to achieve a low refresh rate.

[0084] When scanning to the pixel circuits 10 in the third row, the first data line S1 and the second data line S2 normally input the first data signal Da1 and the second data signal Da2. The two pixel circuits 10 in the first column of the third row and the second column of the third row refresh the input of the grayscale data of the next frame and emit light to achieve a high refresh rate. The third data line S3 does not input the third data signal Da3 and is pulled low. The pixel circuit 10 in the third column of the third row maintains the grayscale data of the previous frame and emits light to achieve a low refresh rate, thereby achieving a low refresh rate for individual pixel circuits 10.

[0085] Furthermore, since the light-emitting unit 20 may store the charge of the previous frame in each frame, there may be charge accumulation during the frame scanning process, which may cause abnormal grayscale display of the light-emitting unit 20.

[0086] Therefore, in one alternative embodiment, such as Figure 8 As shown, the pixel circuit 10 also includes:

[0087] A reset switch 16, a first end of the reset switch 16 is used for inputting a reset signal Vint, a second end of the reset switch 16 is connected with the light emitting unit 20, a control end of the reset switch 16 is connected with an output end of the logic circuit 15, the reset switch 16 is triggered to turn on by the first level signal and is triggered to turn off by the second level signal.

[0088] The conventional pixel circuit 10 works in a reset period, a sampling period and a light emitting period in sequence to complete the reset, sampling and light emitting work in sequence, while in the present application, the reset switch 16 is connected to the output end of the logic circuit 15, and the reset, sampling and light emitting work can be completed by working in the sampling period and the light emitting period in sequence.

[0089] In the sampling period of the working mode, the logic circuit 15 outputs the first level signal, the reset switch 16 turns on and resets the gray scale data of the previous frame received by the light emitting unit 20 to zero, at the same time, the switch circuit 13 refreshes the data signal Da of the next frame and completes the sampling, and in the sampling period of the working mode, the reset and sampling work are completed synchronously.

[0090] Then, in the light emitting period of the working mode, the logic circuit 15 outputs the second level signal, the reset switch 16 turns off and does not perform the reset work.

[0091] And in the sampling period of the maintaining mode, the logic circuit 15 outputs the second level signal, the reset switch 16 turns off and does not perform the reset work, so that the pixel circuit 10 maintains the gray scale data of the previous frame.

[0092] Similarly, in the light emitting period of the maintaining mode, the logic circuit 15 maintains outputting the second level signal, the reset switch 16 turns off and does not perform the reset work, so that the pixel circuit 10 lights up with the current signal corresponding to the gray scale data of the previous frame.

[0093] Among them, the first light emitting switch 11, the second light emitting switch 12, the switch circuit 13, the data switch 14, the logic circuit 15 and the reset switch 16 can be composed of corresponding thin film transistors, and the specific structure is not limited.

[0094] The light emitting unit 20 is an organic light emitting diode OLED.

[0095] The beneficial effects of the embodiment of the present application compared with the prior art are: the display panel 100 includes a plurality of scan lines, a plurality of data lines and arrayed pixel circuits 10, the pixel circuit 10 includes a light emitting unit 20, a light emitting driving unit, a storage capacitor Cst, a switch circuit 13, a data switch 14 and a logic circuit 15, the logic circuit 15 performs AND operation on the input row scan signal Sc and the data signal Da, and outputs the corresponding first level signal or the second level signal to the switch circuit 13, so as to control the switch circuit 13 to store the data signal Da of the next frame to the storage capacitor Cst in the sampling period or control the storage capacitor Cst to maintain the data signal Da of the last frame, and the light emitting unit 20 is driven to emit light by the current signal output by the light emission signal EM and the driving tube SD in the light emitting period, by selecting whether to input the data signal Da and the row scan signal Sc to the data line and the scan line, the corresponding pixel circuit 10 can be controlled to maintain the current picture and switch the display picture, and the independent control of the single pixel circuit 10 can be realized, and the display requirements of different refresh rates can be met.

[0096] Embodiment two

[0097] In an optional embodiment, as shown in Figure 9 The first light emission switch 11 includes a first transistor T1, the second end of the first transistor T1 is connected with the input end of the driving tube SD, and the control end of the first transistor T1 is used for inputting the light emission signal EM.

[0098] The second light emission switch 12 includes a second transistor T2, the first end of the second transistor T2 is connected with the output end of the driving tube SD, the control end of the second transistor T2 is connected with the control end of the first transistor T1, the first end of the first transistor T1 is connected with the anode voltage end, the second end of the second transistor T2 is connected with the light emitting unit 20, or the first end of the first transistor T1 is connected with the light emitting unit 20, and the second end of the second transistor T2 is connected with the cathode voltage end.

[0099] The switch circuit 13 includes a third transistor T3, a fourth transistor T4 and a fifth transistor T5.

[0100] The first end of the third transistor T3, the first end of the storage capacitor Cst and the anode voltage end are connected, the second end of the third transistor T3 and the second end of the fourth transistor T4 are connected with the control end of the driving tube SD, the first end of the fourth transistor T4, the first end of the fifth transistor T5 and the second end of the storage capacitor Cst are connected, and the control end of the third transistor T3, the control end of the fourth transistor T4 and the control end of the fifth transistor T5 are connected with the output end of the logic circuit 15.

[0101] The logic circuit 15 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9.

[0102] The first end of the sixth transistor T6 is used for inputting a first level signal, the second end of the sixth transistor T6 is connected with the first end of the seventh transistor T7, the control end of the sixth transistor T6, the control end of the eighth transistor T8 and the scanning line are connected, the second end of the seventh transistor T7, the first end of the eighth transistor T8 and the first end of the ninth transistor T9 are connected to constitute the output end of the logic circuit 15, the control end of the seventh transistor T7 and the control end of the ninth transistor T9 are connected with the data line, the second end of the eighth transistor T8 and the second end of the ninth transistor T9 are connected and used for inputting a second level signal.

[0103] The data switch 14 comprises a tenth transistor T10, the first end of the tenth transistor T10 is used for inputting a data signal Da, the second end of the tenth transistor T10 is connected with the input end of the drive tube SD, and the control end of the tenth transistor T10 is used for inputting a row scanning signal Sc.

[0104] The reset switch 16 comprises an eleventh transistor T11, the first end of the eleventh transistor T11 is used for inputting a reset signal Vint, the second end of the eleventh transistor T11 is connected with the light emitting unit 20, and the control end of the eleventh transistor T11 is connected with the output end of the logic circuit 15.

[0105] In the embodiment, based on the connection position of the light emitting driving unit 101, the first transistor T1 and the second transistor T2 can be connected with the anode voltage end and the light emitting unit 20 respectively, in the working mode, taking the drive tube SD as a P channel thin film transistor as an example, in the sampling period of the pixel circuit 10, when scanning to the row where the pixel circuit 10 is located, the scanning line connected with the pixel circuit 10 inputs a row opening signal VGH, the data line connected with the pixel circuit 10 inputs a data signal Da, the sixth transistor T6 and the seventh transistor T7 are turned on, the eighth transistor T8 and the ninth transistor T9 are turned off, the logic circuit 15 outputs a first level signal, in an optional embodiment, the first level signal is a row closing signal VGL, and the second level signal is a row opening signal VGH, at the same time, the tenth transistor T10 is turned on, the data signal Da is transmitted to the input end of the drive tube SD through the tenth transistor T10, the first level signal is output to the switch circuit 13, the third transistor T3 and the fifth transistor T5 are turned on, the fourth transistor T4 is turned off, the switch circuit 13 connects the anode voltage end and the control end of the drive tube SD, and connects the second end of the storage capacitor Cst and the output end of the drive tube SD, at this time, the light emitting signal EM is not input, the first transistor T1 and the second transistor T2 are turned off, the data signal Da is output to the storage capacitor Cst through the drive tube SD and the fifth transistor T5, the anode voltage end, the storage capacitor Cst, the fifth transistor T5, the drive tube SD and the data line constitute a loop, the storage voltage Vcst of the storage capacitor Cst = Vdata+Vth, and the pixel circuit 10 completes the sampling work of the data signal Da.

[0106] At the same time, during the sampling period, the eleventh transistor T11 of the reset switch 16 receives the first level signal and triggers to turn on, the reset signal Vint resets the light emitting unit 20, and the reset and sampling operations are completed synchronously during the sampling period of the working mode.

[0107] Then, during the light emitting period, when the scanning of the current line is completed and no data signal Da is input to other lines, at this time, the scan line connected to the pixel circuit 10 inputs the row off signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da, the sixth transistor T6 and the seventh transistor T7 are turned off, the eighth transistor T8 and the ninth transistor T9 are turned on and output the second level signal, at this time, the tenth transistor T10 is turned off, no data signal Da is input, the fourth transistor T4 receives the second level signal to trigger the second end of the storage capacitor Cst and the control end of the driving tube SD, the storage voltage of the storage capacitor Cst is output to the driving tube SD, at this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, the anode voltage end, the first transistor T1, the driving tube SD and the second transistor T2 form a current loop, the driving tube SD generates a current signal and outputs it to the light emitting unit 20 through the second transistor T2, the light emitting unit 20 displays the gray scale data of the sampling stage and emits light normally, and high refresh rate is realized.

[0108] At the same time, the eleventh transistor T11 of the reset switch 16 triggers to turn off and does not perform the reset operation.

[0109] Alternatively, during the light emitting period, when scanning to other lines, the data line switches the input data signal Da due to the data signal Da of other lines, at this time, the scan line connected to the pixel circuit 10 inputs the row off signal VGL, the sixth transistor T6 and the ninth transistor T9 are turned off, the seventh transistor T7 and the eighth transistor T8 are turned on, the logic circuit 15 still normally outputs the second level signal, the fourth transistor T4 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, the storage voltage of the storage capacitor Cst is output to the driving tube SD, at this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, the anode voltage end, the first transistor T1, the driving tube SD and the second transistor T2 form a current loop, the driving tube SD generates a current signal and outputs it to the light emitting unit 20 through the second transistor T2, the light emitting unit 20 displays the gray scale data of the sampling stage and emits light normally, and high refresh rate is realized.

[0110] At the same time, the eleventh transistor T11 of the reset switch 16 triggers to turn off and does not perform the reset operation.

[0111] When switching to the sustain mode of the next frame, during the sampling period of the pixel circuit 10, when scanning to the row where the pixel circuit 10 is located, the scan line connected to the pixel circuit 10 inputs the row-on signal VGH, the data line connected to the pixel circuit 10 does not input the data signal Da, at this time, the data line is in a low state, the sixth transistor T6 and the ninth transistor T9 are turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, the logic circuit 15 outputs the second level signal, the fourth transistor T4 is turned on and connects the second end of the storage capacitor Cst and the control end of the driving tube SD, at this time, the light emission signal EM is not input, the first transistor T1 and the second transistor T2 are turned off, the data signal Da stored on the storage capacitor Cst in the last frame cannot be output to the storage capacitor Cst through the driving tube SD and the switching circuit 13 or be refreshed by the new data signal Da, and the storage capacitor Cst will maintain the storage voltage of the last frame.

[0112] At the same time, the eleventh transistor T11 of the reset switch 16 is triggered to be turned off, and the reset work is not performed.

[0113] Then, during the light emitting period, when the scanning of the current row is completed and no data signal Da is input to other rows, at this time, the scan line connected to the pixel circuit 10 inputs the row-off signal VGL, the data line connected to the pixel circuit 10 does not input the data signal Da, the sixth transistor T6 and the seventh transistor T7 are turned off, the eighth transistor T8 and the ninth transistor T9 are turned on and output the second level signal, at this time, the tenth transistor T10 is turned off, no data signal Da is input, the fourth transistor T4 receives the second level signal to trigger the connection between the second end of the storage capacitor Cst and the control end of the driving tube SD, and the storage voltage of the storage capacitor Cst is output to the driving tube SD, at this time, the light emission signal EM is input, the first transistor T1 and the second transistor T2 are turned on, the anode voltage end, the first transistor T1, the driving tube SD and the second transistor T2 form a current loop, the driving tube SD generates a current signal and outputs it to the light emitting unit 20 through the second transistor T2, the light emitting unit 20 displays the gray scale data in the sampling stage and normally emits light, and the low refresh rate of the local picture is realized.

[0114] Alternatively, during the light-emitting period, when other rows are scanned, the data line switches its input data signal Da due to the data signal Da of other rows. At this time, the scan line input row turn-off signal VGL connected to the pixel circuit 10 turns off the sixth transistor T6 and the ninth transistor T9, and turns on the seventh transistor T7 and the eighth transistor T8. The logic circuit 15 still outputs the second level signal normally. The fourth transistor T4 connects the second terminal of the storage capacitor Cst and the control terminal of the driving transistor SD. The storage voltage of the previous frame is output to the driving transistor SD. At this time, the input light emission signal EM is emitted, and the first transistor T1 and the second transistor T2 are turned on. The anode voltage terminal, the first transistor T1, the driving transistor SD and the second transistor T2 form a current loop. The driving transistor SD generates a current signal and outputs it to the light-emitting unit 20 through the second transistor T2. The light-emitting unit 20 displays the grayscale data of the previous frame and emits light normally. The pixel circuit 10 displays the same display information based on the same data signal Da in the two frames, realizing a low refresh rate for the local screen.

[0115] Corresponding to the above signal types and the on / off modes of each transistor, in an optional embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 are P-channel thin-film transistors, and the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are N-channel thin-film transistors.

[0116] Example 3

[0117] A second aspect of this invention provides a driving method for a display panel 100, used to drive the display panel 100, such as... Figure 10 As shown, the driving method for the display panel 100 includes:

[0118] S10. Determine whether the content of the next frame of the target partial image of the display panel 100 has changed;

[0119] S20. When the content of the next frame of the target local image remains unchanged, switch to the maintenance mode, and when the next frame is scanned, output the corresponding row enable signal VGH and do not output the data signal Da to the target pixel circuit corresponding to the target local image, and control the storage capacitor Cst of the target pixel circuit to maintain the data signal Da of the previous frame.

[0120] S30. When the content of the next frame of the target local image changes, switch to the working mode. When the next frame is scanned, output the corresponding data signal Da and the line open signal VGH to the target pixel circuit corresponding to the target local image, and control the storage capacitor Cst of the target pixel circuit to input the data signal Da of the current frame.

[0121] In this embodiment, when a static image is displayed in the target local image, the feature values ​​of the subsequent images can be analyzed to determine whether the target local image has changed. When it is determined that the display content of the target local image remains unchanged, the target local image has a low refresh rate. At this time, the image is switched to the sustain mode. During line-by-line scanning, the image can be switched to the sustain mode, i.e., the low refresh rate is achieved.

[0122] When it is determined that the target local image changes in the next frame, the target local image is at a high refresh rate. At this time, the working mode is switched. During progressive scanning, the output data signal Da can be selected to the pixel circuit 10 of the corresponding target local image, which can complete the switching of the pixel circuit 10 of the target local image to the working mode, that is, to achieve a high refresh rate.

[0123] The pixel circuit 10 can refresh or maintain the data signal Da under the control of the dual signals of the data signal Da and the input row scan signal Sc, so as to realize the control of the refresh rate of the target pixel circuit.

[0124] For example, when it is necessary to achieve localized low refresh rates and localized high refresh rates along the column direction of the display panel 100, such as Figure 2 and Figure 5 As shown, if the pixel circuit 10 of the second column needs to be at a low refresh rate, during progressive scanning, the first data line S1 and the third data line S3 can normally input the first data signal Da1 and the third data signal Da3 line by line, while the second data line S2 selects not to input the second data signal Da2 and is correspondingly pulled low. In this way, during progressive scanning, the pixel circuit 10 of the second column maintains the grayscale data of the previous frame and emits light, realizing a low refresh rate in the column direction, while the pixel circuit 10 of the first column and the pixel circuit 10 of the third column refresh the input of the grayscale data of the next frame and emit light, realizing a high refresh rate in the column direction, thereby realizing different refresh rates in the column direction of the display panel 100.

[0125] When a localized low refresh rate is required in the row direction of the display panel 100, such as Figure 2 and Figure 6 As shown, if the pixel circuit 10 of the second row needs to be at a low refresh rate, during line-by-line scanning, when scanning to the pixel circuit 10 of the first row and the pixel circuit 10 of the third row, each data line can normally input data signal Da. Each pixel circuit 10 of the first row and each pixel circuit 10 of the third row refreshes the input grayscale data of the next frame and emits light, achieving a high refresh rate in the row direction. However, when scanning to the pixel circuit 10 of the second row, each data line does not input data signal Da and is pulled low. The pixel circuit 10 of the second row maintains the grayscale data of the previous frame and emits light, achieving a low refresh rate in the row direction, thereby achieving different refresh rates in the row direction of the display panel 100.

[0126] When scanning to each pixel circuit 10 of the second row, the first data line S1 and the third data line S3 normally input the first data signal Da1 and the third data signal Da3, two pixel circuits 10 of the first column of the second row and the third column of the second row refresh the input gray scale data of the next frame and emit light, realizing high refresh rate, the second data line S2 does not input the second data signal Da2 and is pulled low, the pixel circuit 10 of the second column of the second row maintains the gray scale data of the last frame and emits light, realizing low refresh rate, thereby realizing low refresh rate of individual pixel circuit 10.

[0127] When scanning to each pixel circuit 10 of the third row, the first data line S1 and the second data line S2 normally input the first data signal Da1 and the second data signal Da2, two pixel circuits 10 of the first column of the third row and the second column of the third row refresh the input gray scale data of the next frame and emit light, realizing high refresh rate, the third data line S3 does not input the third data signal Da3 and is pulled low, the pixel circuit 10 of the third column of the third row maintains the gray scale data of the last frame and emits light, realizing low refresh rate, thereby realizing low refresh rate of individual pixel circuit 10.

[0128] In an optional embodiment, as shown in FIG. 20, S20 specifically includes: Figure 11

[0129] S21, during the sampling period of the maintenance mode, outputting the row enable signal VGH to the scanning line, and not outputting the data signal Da to the data line.

[0130] During the sampling period of the pixel circuit 10, when scanning to the row where the pixel circuit 10 is located, the scanning line connected to the pixel circuit 10 inputs the row enable signal VGH, and the data line connected to the pixel circuit 10 does not input the data signal Da, at this time, the data line is in a low state, the logic circuit 15 of the pixel circuit 10 outputs the second level signal, and the switch circuit 13 of the pixel circuit 10 connects the second end of the storage capacitor Cst and the control end of the driving tube SD, at this time, the pixel circuit 10 does not input the light emission signal EM, and the storage capacitor Cst will keep the storage voltage of the last frame.

[0131] S22, during the light emitting period of the maintenance mode, not outputting the row enable signal VGH to the scanning line, and outputting the data signal Da of the next frame to the data line or not outputting the data signal Da to the data line.

[0132] ​In the light emitting period, when the scanning of the row ends and the data signal Da is not input to other rows or the data signal Da is switched by the data signal Da of other rows, at this time, the row off signal VGL is input to the scanning line connected to the pixel circuit 10, the second level signal is output by the logic circuit 15 of the pixel circuit 10, the second end of the storage capacitor Cst is connected to the control end of the drive tube SD by the switch circuit 13 of the pixel circuit 10, and the storage voltage of the storage capacitor Cst, i.e. the storage voltage of the previous frame, is output to the drive tube SD. At this time, the light emission signal EM is input, the drive tube SD generates a current signal and outputs it to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data of the sampling stage and normally emits light, and the low refresh rate of the local picture is realized.

[0133] In an optional embodiment, as shown in Figure 12 S30 includes:

[0134] S31, in the sampling period of the working mode, outputting the row on signal VGH to the scanning line and outputting the data signal Da to the data line;

[0135] S32, in the light emitting period of the working mode, not outputting the row on signal VGH to the scanning line, and outputting the data signal Da of the next frame to the data line or not outputting the data signal Da to the data line.

[0136] In the sampling period of the working mode, such as the sampling period of the first frame, when the scanning is to the row where the pixel circuit 10 is located, the row on signal VGH is input to the scanning line connected to the pixel circuit 10, the data signal Da is input to the data line connected to the pixel circuit 10, the first level signal is output by the logic circuit 15 of the pixel circuit 10, the anode voltage end is connected to the control end of the drive tube SD by the switch circuit 13 of the pixel circuit 10, and the second end of the storage capacitor Cst is connected to the output end of the drive tube SD. At this time, the light emission signal EM is not input, the storage voltage Vcst of the storage capacitor Cst = Da + Vth, and the sampling of the data signal Da is completed by the pixel circuit 10.

[0137] Then, in the light emitting period, when the scanning of the current row is finished and no data signal Da is input to other rows, at this time, the row off signal VGL is input to the scanning line connected to the pixel circuit 10, no data signal Da is input to the data line connected to the pixel circuit 10 or the data signal Da of other rows is input to the data line, the second level signal is output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the driving tube SD by the switch circuit 13, the storage voltage of the storage capacitor Cst is output to the driving tube SD, at this time, the light emission signal EM is input, the first light emission switch 11 and the second light emission switch 12 are turned on, the anode voltage end, the first light emission switch 11, the driving tube SD and the second light emission switch 12 form a current loop, the driving tube SD generates a current signal and outputs the current signal to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data in the sampling stage and emits light normally, and high refresh rate is realized.

[0138] Alternatively, in the light emitting period, when scanning to other rows, the data signal Da of other rows is input to the data line, at this time, the row off signal VGL is input to the scanning line connected to the pixel circuit 10, the second level signal is still output by the logic circuit 15, the second end of the storage capacitor Cst is connected to the control end of the driving tube SD by the switch circuit 13, the storage voltage of the storage capacitor Cst is output to the driving tube SD, at this time, the light emission signal EM is input, the driving tube SD generates a current signal and outputs the current signal to the light emitting unit 20 through the second light emission switch 12, the light emitting unit 20 displays the gray scale data in the sampling stage and emits light normally, and high refresh rate is realized.

[0139] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0140] Embodiment four

[0141] As Figure 13 shown, the third aspect of the embodiment of the present application proposes a driving circuit 200 of a display panel, comprising a source driving circuit 210, a gate driving circuit 220 and a timing controller 230, the source driving circuit 210 is connected with a plurality of data lines of the display panel 100 respectively, the gate driving circuit 220 is connected with a plurality of scanning lines of the display panel 100 respectively;

[0142] the timing controller 230 is connected with the source driving circuit 210 and the gate driving circuit 220 respectively, the timing controller 230 is used for outputting a control signal to the source driving circuit 210 and the gate driving circuit 220, so as to realize the driving method of the display panel 100 as above.

[0143] In this embodiment, the source driving circuit 210 is used to output or not output the data signal Da under control, and the gate driving circuit 220 is used to output the row opening signal VGH and the row closing signal VGL row by row under control.

[0144] The timing controller 230 analyzes the feature value of the subsequent frame when the target local picture displays a static picture, and judges whether the target local picture changes or not.

[0145] When it is judged that the target local picture changes in the next frame, the target local picture is high refresh rate, at this time, the working mode is switched to, and the timing controller 230 controls the source driving circuit 210 to output the data signal Da to the target pixel circuit of the target local picture in the sampling period, so as to control the target pixel circuit to switch to the data signal Da and display the picture of the next frame, and realize high refresh rate.

[0146] Embodiment Five

[0147] The fourth aspect of the embodiment of the present application provides a display device, as shown in the figure, which comprises a display panel 100 and a driving circuit 200 of the display panel. Figure 13 The display device adopts all the technical solutions of the above-mentioned embodiments, and therefore has all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here. The driving circuit 200 of the display panel is connected with the display panel 100.

[0148] The above-mentioned embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that the technical solutions recorded in the above-mentioned embodiments can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The pixel circuit comprises a plurality of scanning lines, a plurality of data lines and an array of pixel circuits, and the pixel circuit comprises: a light emitting unit; a light emitting driving unit connected in series between an anode voltage terminal and a cathode voltage terminal, the light emitting driving unit comprising a first light emission switch, a driving tube and a second light emission switch connected in series, the driving tube being configured to convert a data signal input in a sampling period into a current signal, the first light emission switch and the second light emission switch being configured to be turned on by a light emission signal to output the current signal in a light emitting period; a storage capacitor, a first end of the storage capacitor being connected to the anode voltage terminal or the cathode voltage terminal; a switch circuit connected to a second end of the storage capacitor, the anode voltage terminal, a control terminal of the driving tube and an output terminal of the driving tube, the switch circuit being configured to connect the anode voltage terminal and the control terminal of the driving tube and to connect the second end of the storage capacitor and the output terminal of the driving tube when triggered by a first level signal, and to connect the second end of the storage capacitor and the control terminal of the driving tube when triggered by a second level signal; a data switch connected to the data line, the scanning line and an input terminal of the driving tube, the data switch being configured to be turned on and to transmit a data signal on the data line to the driving tube when triggered by a row opening signal, and to be turned off when triggered by a row closing signal; a logic circuit connected to the data line, the scanning line and the switch circuit, the logic circuit being configured to output the first level signal to the switch circuit when the row opening signal and the data signal are received simultaneously, and to output the second level signal to the switch circuit when the row opening signal and the data signal are not received simultaneously.

2. The display panel of claim 1, wherein, The first light emission switch comprises a first transistor, a second end of the first transistor being connected to the input terminal of the driving tube, and a control terminal of the first transistor being configured to input the light emission signal; The second light emission switch comprises a second transistor, a first end of the second transistor being connected to the output terminal of the driving tube, a control terminal of the second transistor being connected to the control terminal of the first transistor, a first end of the first transistor being connected to the anode voltage terminal, a second end of the second transistor being connected to the light emitting unit, or a first end of the first transistor being connected to the light emitting unit, and a second end of the second transistor being connected to the cathode voltage terminal.

3. The display panel of claim 1, wherein, The switch circuit comprises a third transistor, a fourth transistor and a fifth transistor; a first end of the third transistor, a first end of the fourth transistor and a second end of the storage capacitor being connected, a second end of the third transistor and a second end of the fourth transistor being connected to the control terminal of the driving tube, control terminals of the third transistor, the fourth transistor and the fifth transistor being connected to an output terminal of the logic circuit.

4. The display panel of claim 1, wherein, The logic circuit comprises a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; A first end of the sixth transistor is configured to input the first level signal, a second end of the sixth transistor is connected with a first end of the seventh transistor, a control end of the sixth transistor, a control end of the eighth transistor and the scan line are connected, a second end of the seventh transistor, a first end of the eighth transistor and a first end of the ninth transistor are connected to form an output end of the logic circuit, a control end of the seventh transistor and a control end of the ninth transistor are connected with the data line, a second end of the eighth transistor and a second end of the ninth transistor are connected and configured to input the second level signal.

5. The display panel according to any one of claims 1 to 4, wherein The pixel circuit further comprises: a reset switch, a first end of the reset switch is configured to input a reset signal, a second end of the reset switch is connected with the light emitting unit, a control end of the reset switch is connected with the output end of the logic circuit, the reset switch is triggered to be turned on by the first level signal and is triggered to be turned off by the second level signal.

6. A driving method of a display panel, for driving the display panel according to any one of claims 1 to 5, characterized by, The driving method of the display panel comprises: judging whether the picture content of the next frame of the target local picture of the display panel changes; when the picture content of the next frame of the target local picture does not change, switching to a maintenance mode, outputting a corresponding row enable signal and not outputting a data signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, and controlling the storage capacitor of the target pixel circuit to maintain the data signal of the last frame; when the picture content of the next frame of the target local picture changes, switching to a working mode, outputting a corresponding data signal and the row enable signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, and controlling the storage capacitor of the target pixel circuit to input the data signal of the current frame.

7. The driving method of a display panel according to claim 6, wherein The switching to the maintenance mode when the picture content of the next frame of the target local picture does not change, and outputting a corresponding row enable signal and not outputting a data signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, comprises: outputting a row enable signal to the scan line and not outputting a data signal to the data line during a sampling period of the maintenance mode; not outputting a row enable signal to the scan line and outputting a data signal of the next frame to the data line or not outputting a data signal to the data line during a light emitting period of the maintenance mode.

8. The driving method of a display panel according to claim 6, wherein The switching to the working mode when the picture content of the next frame of the target local picture changes, and outputting a corresponding data signal and the row enable signal to the target pixel circuit corresponding to the target local picture during the next frame scanning driving, comprises: outputting a row enable signal to the scan line and outputting a data signal to the data line during a sampling period of the working mode; not outputting a row enable signal to the scan line and outputting a data signal of the next frame to the data line or not outputting a data signal to the data line during a light emitting period of the working mode.

9. A drive circuit of a display panel, characterized by comprising: The display panel comprises a source driving circuit, a gate driving circuit and a timing controller, the source driving circuit is connected with a plurality of data lines of the display panel respectively, and the gate driving circuit is connected with a plurality of scan lines of the display panel respectively. The timing controller is connected with the source driving circuit and the gate driving circuit respectively, and is used for outputting a control signal to the source driving circuit and the gate driving circuit to realize the driving method of the display panel as any one of claims 6-8.

10. A display device, characterized by comprising: The display panel comprises a source driving circuit, a gate driving circuit and a timing controller, the source driving circuit is connected with a plurality of data lines of the display panel respectively, and the gate driving circuit is connected with a plurality of scan lines of the display panel respectively.

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