Source driving circuit and display panel

Abstract

The invention provides a source electrode driving circuit and a display panel, and the source electrode driving circuit is applied to the display panel, and comprises a data receiving unit which is configured to receive original display data line by line; the first latch unit group comprises a plurality of first latch units, the plurality of first latch units are respectively connected with the data receiving unit, and each first latch unit is configured to cache a column of original display data; the data processing unit group comprises a plurality of data processing units, the plurality of data processing units are respectively connected with the first latch unit group, the data processing unit group is configured to expand and recombine the original display data to obtain recombined display data, and the recombined display data comprises the original display data and expanded display data; and the second latch unit group comprises a plurality of second latch units, the plurality of second latch units are respectively connected with the data processing unit group, and each second latch unit is configured to cache a column of recombined display data.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a source driving circuit and a display panel. Background Art

[0002] With the convergence of high refresh rate and high-resolution display demands, dual-mode variable resolution / refresh rate display panels are becoming a new trend. For example, a monitor with a physical resolution of 4K×2K can operate in two modes: 4K×2K@60Hz and 2K×1K@120Hz. In 4K×2K@60Hz display mode, the refresh rate is lower, but the image quality is more detailed, making it suitable for viewing movies or playing AAA games, which require higher image quality. In 2K×1K@120Hz display mode, the refresh rate is higher, making it suitable for competitive gaming, sacrificing some image quality in exchange for smoother operational response. Switching between these two modes involves scanning two rows of the panel simultaneously to achieve a doubled refresh rate.

[0003] In 2K×1K@120Hz display mode, the display's SOC performs horizontal data expansion, which is then transmitted to the pixels via the timing controller and source driver. However, due to the need to pass through multiple chips, the data transmission bandwidth is limited, and the refresh rate can only be increased from 60Hz to 120Hz, a doubling of the frequency. This limits the refresh rate of the display panel.

[0004] Some current solutions propose using source drivers to horizontally expand display data. Display data output from the source drivers directly acts on pixels, and data transmission bandwidth is not limited. However, existing solutions using source drivers to horizontally expand display data have poor display effects. Summary of the Invention

[0005] The present invention mainly provides a source driving circuit and a display panel, which can improve the display effect.

[0006] To solve the above technical problems, the first technical solution adopted by the present invention is to provide a source driver circuit applied to a display panel, comprising: a data receiving unit configured to receive original display data line by line; A first latch unit group includes a plurality of first latch units, and the plurality of first latch units are respectively connected to the data receiving unit, and each first latch unit is configured to cache a column of original display data; a data processing unit group, comprising a plurality of data processing units, wherein the plurality of data processing units are respectively connected to the first latch unit group, and the data processing unit group is configured to expand and reorganize the original display data to obtain reorganized display data, wherein the reorganized display data includes the original display data and the expanded display data; The second latch unit group includes multiple second latch units, and the multiple second latch units are respectively connected to the data processing unit group. Each second latch unit is configured to cache a column of reorganized display data, wherein the cached column of reorganized display data is a column of original display data or a column of expanded display data.

[0007] In one embodiment, each column of extended display data is determined by an adjacent column of original display data; or Each column of extended display data is determined by at least two adjacent columns of original display data.

[0008] In one embodiment, each column of extended display data is determined by combining a first portion of an adjacent column of original display data and a second portion of another adjacent column of original display data; or When the data receiving unit receives the nth row of original display data, each column of extended display data is determined by an adjacent column of original display data; when the data receiving unit receives the n+1th row of original display data, each column of extended display data is determined by another adjacent column of original display data; or When the data receiving unit receives the original display data of the mth frame image, each column of extended display data is determined by an adjacent column of original display data; when receiving the original display data of the m+1th frame image, each column of extended display data is determined by another adjacent column of original display data.

[0009] In one embodiment, each first latch unit includes a plurality of first latches, each first latch is configured to cache a column of original display data, and original display data cached by different first latches in each first latch unit correspond to different pixel colors; Each second latch unit includes a plurality of second latches, each second latch is configured to cache a column of reorganized display data, and the reorganized display data cached by different second latches in each second latch unit correspond to different pixel colors; Each data processing unit includes a plurality of data processing sub-units, and each data processing sub-unit is configured to expand and reorganize the original display data to obtain reorganized display data.

[0010] In one embodiment, the data processing subunit includes a first data processing path and a second data processing path. The first data processing path is connected to a first latch and a second latch, and is configured to transfer a column of original display data cached in the first latch to a corresponding second latch as original display data in the reconstructed display data. The second data processing path is connected to the first data processing path and a second latch, and is configured to transfer the original display data to the corresponding second latch as extended display data in the reconstructed display data. The second latch connected to the second data processing path and the second latch connected to the first data processing path are respectively located in two adjacent second latch units.

[0011] In one embodiment, each first latch includes a plurality of first registers, each of which is configured to cache one bit of data in a column of original display data; each second latch includes a plurality of second registers, each of which is configured to cache one bit of data in a column of reorganized display data; The data processing subunit includes a first data processing path and a second data processing path, each first data processing path includes a plurality of first data transmission channels, each second data processing path includes a plurality of second data transmission channels, each first data transmission channel is respectively configured to transmit one bit of data in a column of original display data; a portion of the second data transmission channels in the second data processing path is connected to a portion of the first data transmission channels in an adjacent first data processing path, and another portion of the second data transmission channels in the second data processing path is connected to another portion of the first data transmission channels in another adjacent first data processing path.

[0012] In one embodiment, when receiving the nth row of raw display data or the mth frame of raw display data, the first data processing path is configured to transfer a column of raw display data cached in the first latch to the corresponding second latch as the raw display data in the reconstructed display data, and the second data processing path is configured to transfer the raw display data to the corresponding second latch as the extended display data in the reconstructed display data.

[0013] In one embodiment, the data processing subunit further includes a third data processing path, the third data processing path connecting the first data processing path and a second latch. When receiving the (n+1)th row of original display data or the (m+1)th frame of original display data, the first data processing path is configured to transfer a column of original display data buffered in the first latch to the corresponding second latch as the original display data in the reconstructed display data, and the third data processing path is configured to transfer the original display data to the corresponding second latch as the extended display data in the reconstructed display data. The second latch unit corresponding to the second latch connected to the third data processing path and the second latch unit corresponding to the second latch connected to the second data processing path are two adjacent second latch units of the second latch unit corresponding to the second latch connected to the first data processing path.

[0014] In one embodiment, the number of the first latch units is the same as the number of the second latch units.

[0015] In order to solve the above technical problems, the second technical solution adopted by the present invention is: providing a display panel, including a timing control circuit and a source driving circuit connected to the timing control circuit, the source driving circuit receives the original display data from the timing control circuit, and the source driving circuit includes any one of the above source driving circuits.

[0016] The beneficial effects of the present invention are as follows: Unlike the prior art, the source driver circuit of the present invention is provided with a first latch unit group, a data processing unit group, and a second latch unit group. The data processing unit group is used to expand and reorganize the original display data cached in the first latch unit group to obtain reorganized display data, which is then cached in the second latch unit group. This enables horizontal expansion of display data in the source driver circuit, and because the reorganized display data is obtained by expanding and reorganizing the original display data, the display effect can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a schematic structural diagram of a first embodiment of the source driver circuit of the present application; Figure 2 A schematic diagram of a first embodiment of the present application for reorganizing display data; Figure 3 To get Figure 2A structural diagram of an embodiment of a source driving circuit corresponding to the reorganized display data shown; Figure 4 for Figure 3 A schematic structural diagram of a first embodiment of a first latch unit and a second latch unit; Figure 5 for Figure 3 Schematic diagram of the source driving circuit at a low refresh rate; Figure 6 for Figure 3 A structural diagram of a second embodiment of the first latch unit and the second latch unit; Figure 7 A schematic diagram of a second embodiment of the present application for reorganizing display data; Figure 8 To get Figure 7 A structural diagram of an embodiment of a source driving circuit corresponding to the reorganized display data shown; Figure 9 A schematic diagram of a third embodiment of the present application for reorganizing display data; Figure 10 for Figure 9 A schematic diagram of an embodiment of a source driving circuit corresponding to the reconstructed display data is shown; Figure 11 for Figure 10 a timing diagram of switches of the first data processing path, the second data processing path, and the third data processing path; Figure 12 A schematic diagram of a fourth embodiment of the present application for reorganizing display data; Figure 13 Schematic diagram of the structure of the second embodiment of the source driver circuit of the present application; Figure 14 FIG. 1 is a schematic structural diagram of an embodiment of a display panel of the present application.

[0019] Explanation of the accompanying drawings: source driver circuit 10, data receiving unit 11, first latch unit group 12, first latch unit 121, data processing unit group 13, data processing unit 131, second latch unit group 14, second latch unit 141, first latch 120, first data processing path Ia, second data processing path Ib, second latch 140, first register 1200, second register 1400, first data transmission channel A, second data transmission channel B, third data processing path Ic, level conversion unit 15, digital-to-analog conversion unit 16, output buffer unit 17, display panel 40, timing control circuit 41. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0021] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0022] The term "and / or" in this document simply describes a relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the related objects are in an "or" relationship. Furthermore, "many" in this document means two or more than two.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0024] Before further describing the embodiments of the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations.

[0025] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0026] See also Figure 1 , Figure 1 Schematic diagram of the structure of the first embodiment of the source driver circuit of the present application. The source driver circuit 10 specifically includes: a data receiving unit 11, a first latch unit group 12, a data processing unit group 13 and a second latch unit group 14.

[0027] The data receiving unit 11 is configured to receive raw display data row by row. The first latch unit group 12 includes a plurality of first latch units 121, each of which is connected to the data receiving unit 11. Each first latch unit 121 is configured to cache a column of raw display data. The data processing unit group 13 includes a plurality of data processing units 131, each of which is connected to the first latch unit group 12. The data processing unit group 13 is configured to expand and reorganize the raw display data to obtain reorganized display data, wherein the reorganized display data includes the raw display data and the expanded display data. The second latch unit group 14 includes a plurality of second latch units 141, each of which is connected to the data processing unit group 13. Each second latch unit 141 is configured to cache a column of reorganized display data, wherein the cached column of reorganized display data is a column of raw display data or a column of expanded display data.

[0028] In the source driving circuit of this embodiment, a data processing unit group 13 is provided between the first latch unit group 12 and the second latch unit group 14. The data processing unit group 13 is used to expand and reorganize the original display data to obtain reorganized display data, which can expand the resolution of the original display data and thus increase the resolution of the display panel.

[0029] In one embodiment, each column of extended display data is determined by an adjacent column of original display data. For example, in the reorganized display data, the display data in the odd columns are original display data, and the display data in the even columns are extended display data. Then, the display data in the even columns (extended display data) are determined by the adjacent odd columns of original display data. Figure 2 As shown, columns 2, 4, 6, ..., 2n are extended display data, and columns 1, 3, 5, ..., 2n-1 are original display data. Therefore, the extended display data in columns 2, 4, 6, ..., 2n is copied from the original display data in columns 1, 3, 5, ..., 2n-1. Specifically, the extended display data in column 2 is copied from the original display data in column 1, the extended display data in column 4 is copied from the original display data in column 3, and the extended display data in column 2n is copied from the original display data in column 2n-1.

[0030] Further integration Figure 3 and Figure 4 Each first latch unit 121 includes a plurality of first latches 120, each of which is configured to cache a column of raw display data. Different first latches 120 in each first latch unit 121 cache raw display data corresponding to different pixel colors. Specifically, the first latch unit 121 includes three first latches 120, each of which caches raw display data corresponding to a column of red pixels, green pixels, and blue pixels, respectively. It will be appreciated that each second latch unit 141 includes a plurality of second latches 140, each of which is configured to cache a column of reorganized display data. Different second latches 140 in each second latch unit 141 cache reorganized display data corresponding to different pixel colors. Specifically, the second latch unit 141 includes three second latches 140, and the three second latches 140 cache the reconstructed display data corresponding to a column of red pixels, the reconstructed display data corresponding to green pixels, and the reconstructed display data corresponding to blue pixels, respectively. Furthermore, the data processing unit 131 includes multiple data processing sub-units, each of which is configured to expand and reconstruct the original display data to obtain reconstructed display data. Specifically, each data processing unit 131 includes three data processing sub-units (one for example, Figure 4 As shown by the thin solid line, a Figure 4 As shown by the dotted line, a Figure 4 The data processing subunit shown by the thin solid line is configured to expand the original display data corresponding to the red pixels to obtain reconstructed display data corresponding to the red pixels; the data processing subunit shown by the dotted line is configured to expand the original display data corresponding to the green pixels to obtain reconstructed display data corresponding to the green pixels; and the data processing subunit shown by the thick solid line is configured to expand the original display data corresponding to the blue pixels to obtain reconstructed display data corresponding to the blue pixels.

[0031] Furthermore, each data processing subunit includes a first data processing path 1a and a second data processing path 1b. In this embodiment, the data processing subunit corresponding to the red pixel (ie Figure 4 The following describes a data processing subunit (denoted by the thin solid line) as an example. A first data processing path 1a connects a first latch 120 and a second latch 140 and is configured to transfer a column of original display data buffered in the first latch 120 to the corresponding second latch 140 as the original display data in the reconstructed display data. A second data processing path 1b connects the first data processing path 1a and a second latch 140 and is configured to transfer the original display data to the corresponding second latch 140 as the extended display data in the reconstructed display data. It should be noted that the second latch 140 connected to the second data processing path 1b and the second latch 140 connected to the first data processing path 1a are respectively located in two adjacent second latch units 141.

[0032] by Figure 4 The embodiment shown is used as an example for illustration. Assuming that the original display data has n columns, corresponding to n first latch units 121 , the three first latches 120 in the nth first latch unit 121 respectively cache the original display data Rn corresponding to the nth column of red pixels, the original display data Gn corresponding to the nth column of green pixels, and the original display data Bn corresponding to the nth column of blue pixels. Assuming that the number of columns of the reconstructed display data is twice that of the original display data, the reconstructed display data has 2n columns, corresponding to 2n second latch units 141 .

[0033] The three first latches 120 in the nth first latch unit 121 buffer the raw display data for the three colors, respectively. For the raw display data Rn corresponding to red pixels, the first data processing path Ia in the data processing subunit, shown by the thin solid line, connects the first first latch 120 in the nth first latch unit 121 and the first second latch 140 in the 2n-1th second latch unit 141. The second data processing path Ib connects the first data processing path Ia and the first second latch 140 in the 2nth second latch unit 141. The first data processing path Ia transfers the raw display data Rn corresponding to the red pixels in the nth column from the corresponding first latch 120 to the corresponding second latch 140, generating reconstructed display data R2n-1 corresponding to the red pixels in the 2n-1th column. The second data processing path Ib transfers the raw display data Rn corresponding to the red pixels in the nth column to the corresponding second latch 140, generating reconstructed display data R2n corresponding to the red pixels in the 2nth column. The process of converting the original display data corresponding to the green pixels and the blue pixels into the reconstructed display data is the same as above and will not be described in detail here.

[0034] In one embodiment, a switch is provided on the second data processing path Ib. In the source driving circuit of this embodiment, a data processing unit group 13 is provided between the first latch unit group 12 and the second latch unit group 14 to realize data expansion and reorganization and complete the horizontal expansion of the display data. It should be noted that the data processing unit group 13 is controlled by the timing control circuit. When the system is in the low refresh rate mode, the timing control circuit outputs a low-level enable signal to the switch on the second data processing path Ib to control the second data processing path Ib to be closed. At this time, the display data is not expanded, that is, the reorganized display data is the same as the original display data, and the circuit structure is equivalent to Figure 5 When the system is in high refresh rate multiplication mode, the timing control circuit outputs a high level enable signal to control the second data processing path Ib to be turned on. At this time, display data expansion is performed, that is, the reorganized display data includes the original display data and the expanded display data. At this time, the structure is Figure 3 It can be understood that the resolution of the display panel in the row direction can be expanded by 2 times through the method of the present application, such as from 2K to 4K.

[0035] In another embodiment of the present application, a switch is also provided on the first data processing path 1a, such as Figure 6As shown, the switches on the first data processing path Ia are also controlled by the timing control circuit. Specifically, when the system is in low refresh rate mode, the timing control circuit outputs a high-level enable signal to the switch on the first data processing path Ia, turning it on, and outputs a low-level enable signal to the switch on the second data processing path Ib, turning it off. In this case, display data expansion is not performed, meaning the reconstructed display data is identical to the original display data. When the system is in high refresh rate and frequency multiplication mode, the timing control circuit outputs a high-level enable signal to the switch on the first data processing path Ia and the switch on the second data processing path Ib, turning them on. In this case, display data expansion is performed, meaning the reconstructed display data includes both the original display data and the expanded display data. In one embodiment, the enable signal on the switch on the first data processing path Ia is later than the enable signal on the switch on the second data processing path Ib, ensuring that both the original display data and the expanded display data are transmitted to the second latch unit 141 simultaneously.

[0036] In the above embodiment, the display data is simply copied from the original display data to obtain the extended display data. The original display data and the extended display data are separated to form the reconstructed display data. When displaying based on the reconstructed display data, jagged edges may occur, for example, when displaying text content.

[0037] In another embodiment, each column of extended display data is determined by at least two adjacent columns of original display data. For example, in the reorganized display data, the display data in the odd columns are original display data, and the display data in the even columns are extended display data. Then, the display data in the even columns (extended display data) is determined by at least two adjacent columns of original display data in the odd columns. Figure 7 As shown, the 2nd, 4th, 6th, ..., 2nth columns are extended display data, and the 1st, 3rd, 5th, ..., 2n-1th columns are original display data. The extended display data of the 2nd column is obtained by combining the original display data of the 1st column and the original display data of the 3rd column, the extended display data of the 4th column is obtained by combining the original display data of the 3rd column and the original display data of the 5th column, and the extended display data of the 2nth column is obtained by combining the original display data of the 2n-1th column and the original display data of the 2n+1th column.

[0038] It should be noted that each column of extended display data is determined by combining the first portion of the original display data in one adjacent column with the second portion of the original display data in another adjacent column. Specifically, the extended display data in the second column is determined by combining the first portion of the original display data in the first column with the second portion of the original display data in the third column. The extended display data in the fourth column is determined by combining the first portion of the original display data in the third column with the second portion of the original display data in the fifth column. The extended display data in the 2nth column is determined by combining the first portion of the original display data in the 2n-1th column with the second portion of the original display data in the 2n+1th column.

[0039] It should be noted that the original display data of each color is generally 8-bit data. Taking the red pixel as an example, the original display data of the red pixel is generally recorded as R[7:0]. The green pixel and the blue pixel are the same, so they are not described in detail.

[0040] Combine Figure 8 , the original display data of the red pixel is used as an example for explanation. Each first latch 120 includes a plurality of first registers 1200, and each first register 1200 is configured to cache one bit of data in a column of original display data. It is understandable that the original display data of the red pixel includes 8 bits of data, so each first latch 120 includes 8 first registers 1200, each of which caches one bit of data in the 8-bit original display data. Each second latch 140 includes a plurality of second registers 1400, and each second register 1400 is configured to cache one bit of data in a column of reorganized display data. It is understandable that the reorganized display data of the red pixel also includes 8 bits of data, so each second latch 140 includes 8 second registers 1400, each of which caches one bit of data in the 8-bit reorganized display data.

[0041] The data processing subunit includes a first data processing path and a second data processing path, each first data processing path includes a plurality of first data transmission channels A, each second data processing path includes a plurality of second data transmission channels B, each first data transmission channel A is respectively configured to transmit one bit of data in a column of original display data; a portion of the second data transmission channels B in the second data processing path is connected to a portion of the first data transmission channels A in an adjacent first data processing path, and another portion of the second data transmission channels B in the second data processing path is connected to another portion of the first data transmission channels A in another adjacent first data processing path.

[0042] Specifically, the second register 1400 in the 2n-2 second latch 140 is connected to the first register 1200 in the n-1 first latch 120 via a first data transmission channel A. The first data transmission channel A is configured to transmit the original display data buffered by the first register 1200 in the n-1 first latch 120 to the second register 1400 in the 2n-2 second latch 140 to obtain the reconstructed display data of the 2n-2 column. The second register 1400 in the 2n second latch 140 is connected to the first register 1200 in the n first latch 120 via the first data transmission channel A. The first data transmission channel A is configured to transmit the original display data buffered by the first register 1200 in the n first latch 120 to the second register 1400 in the 2n second latch 140 to obtain the reconstructed display data of the 2n column. Part of the second register 1400 in the 2n-1th second latch 140 is connected to part of the first register 1200 in the n-1th first latch 120 through a part of the second data transmission channel B, and another part of the second register 1400 is connected to another part of the first register 1200 in the n-th first latch 120 through another part of the second data transmission channel B. The data cached in part of the first register 1200 in the n-1th first latch 120 and the data cached in another part of the first register 1200 in the n-1th first latch 120 are combined to obtain the 2n-1th column of reorganized display data. In this embodiment, the reorganized display data in column 2n is identical to the original display data in column n, the reorganized display data in column 2n-2 is identical to the original display data in column n-1, and the reorganized display data in column 2n-1 is derived by combining the first portion of the original display data in column n (i.e., the reorganized display data in column 2n-2) with the second portion of the original display data in column n-1 (i.e., the reorganized display data in column 2n). This method can resolve edge jaggedness.

[0043] In one embodiment, R2n-1[7:0] = Rn-1[7:4] + Rn[3:0], i.e., the reconstructed display data of the 2n-1th column is obtained by combining the upper four bits of the original display data of the n-1th column (i.e., the reconstructed display data of the 2n-2th column) and the lower four bits of the original display data of the nth column (i.e., the reconstructed display data of the 2nth column). Specifically, the upper four bits and the lower four bits are concatenated. Of course, the upper three bits and the lower five bits can also be concatenated, and the specific details are not limited. In another embodiment, the average value of R2n-2[0] to R2n-2[7] and R2n [0] to R2n [7] can also be calculated to obtain R2n-1[0] to R2n-1 [7].

[0044] Let's analyze the specific effect after splicing using the method R2[7:0] = R1[7:4] + R3[3:0]. For example, if R1 is 150 grayscale, represented by binary as 10010110, and R3 is 170 grayscale, represented by binary as 10101010, after splicing (the upper four bits of R1 and the lower four bits of R3), R2 becomes 10011010, which is 154 grayscale, meaning the grayscale after splicing is between R1 and R3. For another example, if R1 is 120 grayscale, represented by binary as 01111000, and R3 is 200 grayscale, represented by binary as 11001000, after splicing (the upper four bits of R1 and the lower four bits of R3), it becomes 01111000, which is still 120 grayscale. For example, if R1 has a grayscale of 30, represented by binary as 00011110, and R3 has a grayscale of 247, represented by binary as 11110111, then after splicing (the upper four bits of R1 and the lower four bits of R3), the value becomes 00010111, which is grayscale 23. This proves that when the grayscale difference between R1 and R3 is small (for example, less than 15 grayscales), it is more likely that the resulting R2 after splicing will be between R1 and R3. Therefore, the splicing solution can optimize the display effect to a certain extent.

[0045] In this embodiment, switches are provided on both the first data transmission channel A and the second data transmission channel B. The switches are controlled by a timing control circuit. The control of the switches is the same as that described above. Figure 6 The control method of the switch of the first data processing path 1a and the switch of the second data processing path 1b are the same and will not be repeated here.

[0046] Furthermore, in order to solve the display aliasing phenomenon and improve the display effect, when the data receiving unit 11 in the source driving circuit of the present application receives the original display data of the nth row, each column of extended display data is determined by the adjacent column of original display data; when the data receiving unit 11 receives the original display data of the n+1th row, each column of extended display data is determined by the adjacent column of original display data. Figure 9That is, when the data receiving unit 11 receives original display data in odd rows, the display data in even columns (extended display data) is determined by the original display data in the adjacent odd columns. For example, if columns 2, 4, 6, ..., 2n are extended display data and columns 1, 3, 5, ..., 2n-1 are original display data, then the extended display data in columns 2, 4, 6, ..., 2n are copied from the original display data in columns 1, 3, 5, ..., 2n-1. When the data receiving unit 11 receives original display data in even rows, the display data in even columns (extended display data) is determined by the original display data in the adjacent odd columns. For example, if columns 2, 4, 6, ..., 2n are extended display data and columns 1, 3, 5, ..., 2n-1 are original display data, then the extended display data in columns 2, 4, 6, ..., 2n-2 are copied from the original display data in columns 3, 5, 7, ..., 2n-1. In the reorganized display data formed in this embodiment, two adjacent columns of reorganized display data will not be completely identical, which can reduce the aliasing phenomenon.

[0047] Combine Figure 10 In this embodiment, each data processing subunit includes a first data processing path Ia and a second data processing path Ib. In this embodiment, the data processing subunit corresponding to the red pixel (ie Figure 10 The data processing subunit (shown by the thin solid line) is used as an example for explanation. A first data processing path 1a connects a first latch 120 and a second latch 140. A second data processing path 1b connects the first data processing path 1a and a second latch 140. When the data receiving unit 11 receives the nth row of original display data, the first data processing path 1a is configured to transfer a column of original display data buffered in the first latch 120 to the corresponding second latch 140 as the original display data in the reconstructed display data. The second data processing path 1b is configured to transfer the original display data to the corresponding second latch 140 as the extended display data in the reconstructed display data. It should be noted that the second latch 140 connected to the second data processing path 1b and the second latch 140 connected to the first data processing path 1a are respectively located in two adjacent second latch units 141.

[0048] Furthermore, each data processing sub-unit further includes a third data processing path Ic, which connects the first data processing path Ia and a second latch 140. When the data receiving unit 11 receives the (n+1)th row of raw display data, the first data processing path Ia is configured to transfer a column of raw display data buffered in the first latch 120 to the corresponding second latch 140 as raw display data in the reconstructed display data. The third data processing path Ic is configured to transfer the raw display data to the corresponding second latch 140 as extended display data in the reconstructed display data. It should be noted that the second latch unit 141 corresponding to the second latch 140 connected to the third data processing path Ic and the second latch unit 141 corresponding to the second latch 140 connected to the second data processing path Ib are adjacent second latch units 141 of the second latch 140 connected to the first data processing path.

[0049] Specifically, when the data receiving unit 11 receives the original display data of the nth row, the first data processing path Ia transfers the original display data Rn corresponding to the red pixels in the nth column in the corresponding first latch 120 to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n-1 corresponding to the red pixels in the 2n-1th column. The second data processing path Ib transfers the original display data Rn corresponding to the red pixels in the nth column to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n corresponding to the red pixels in the 2nth column. When the data receiving unit 11 receives the original display data of the n+1th row, the first data processing path Ia transfers the original display data Rn corresponding to the red pixels in the nth column in the corresponding first latch 120 to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n-1 corresponding to the red pixels in the 2n-1th column. The third data processing path Ic transfers the original display data Rn corresponding to the red pixels in the nth column to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n-2 corresponding to the red pixels in the 2n-2th column.

[0050] It is understandable that the third data processing path Ic of this embodiment is also provided with a switch. Figure 11In high refresh rate multiplication mode, when the data receiving unit 11 receives the nth row of raw display data, the timing control circuit outputs a high-level TP signal and a high-level EN1 signal to turn on the switches of the first data processing path Ia and the second data processing path Ib, and outputs a low-level EN2 signal to turn off the switch of the third data processing path Ic. When the data receiving unit 11 receives the n+1th row of raw display data, the timing control circuit outputs a high-level TP signal and a high-level EN2 signal to turn on the switches of the first data processing path Ia and the third data processing path Ic, and outputs a low-level EN1 signal to turn off the switch of the second data processing path Ib. It should be noted that the high-level EN1 signal is earlier than the high-level TP signal; or the high-level EN2 signal is earlier than the high-level TP signal. Specifically, the purpose of setting the high-level EN1 signal earlier than the high-level TP signal is to enable all switches of the second data processing path 1b to be turned on before the switches of the first data processing path 1a are turned on, so that each column of reorganized display data reaches the second latch 140 at the same time. The principle of setting the high-level EN2 signal earlier than the high-level TP signal is the same.

[0051] In this embodiment, although the jagged phenomenon of the display screen can be improved and the display effect can be enhanced, the switch needs to be switched once when scanning each line, which will increase the power consumption of the source driver circuit. Therefore, this application also proposes an embodiment, such as Figure 12 As shown. Combined Figure 10 When the data receiving unit 11 receives the mth frame of raw display data, the first data processing path 1a is configured to transfer a column of raw display data buffered in the first latch 120 to the corresponding second latch 140 as the raw display data in the reconstructed display data. The second data processing path 1b is configured to transfer the raw display data to the corresponding second latch 140 as the extended display data in the reconstructed display data. When the data receiving unit 11 receives the m+1th frame of raw display data, the first data processing path 1a is configured to transfer a column of raw display data buffered in the first latch 120 to the corresponding second latch 140 as the raw display data in the reconstructed display data. The third data processing path 1c is configured to transfer the raw display data to the corresponding second latch 140 as the extended display data in the reconstructed display data.

[0052] Specifically, when the data receiving unit 11 receives the original display data of the m-th frame Frame_m, the first data processing path Ia transmits the original display data Rn corresponding to the red pixels in the n-th column in the corresponding first latch 120 to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n-1 corresponding to the red pixels in the 2n-1-th column. The second data processing path Ib transmits the original display data Rn corresponding to the red pixels in the n-th column to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n corresponding to the red pixels in the 2n-th column. When the data receiving unit 11 receives the original display data of the (m+1)th frame Frame_m+1, the first data processing path Ia transfers the original display data Rn corresponding to the red pixels in the nth column in the corresponding first latch 120 to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n-1 corresponding to the red pixels in the 2n-1th column. The third data processing path Ic transfers the original display data Rn corresponding to the red pixels in the nth column to the corresponding second latch 140, thereby obtaining the reconstructed display data R2n-2 corresponding to the red pixels in the 2n-2nd column.

[0053] In this embodiment, due to the accumulation of time, the display effect of the pixels in the even-numbered columns is an average value of 1 / 3 of the original display effect (3 refers to the three colors of red, green and blue), so that the display effect in the horizontal direction is more uniform.

[0054] In the solution of this embodiment, the switch is switched once per frame, and it is not necessary to switch each row. Figure 9 The embodiment shown reduces the power consumption of the source driver circuit.

[0055] This application Figure 2 、 Figure 7 、 Figure 9 and Figure 12 A schematic diagram of reorganizing and displaying data is provided respectively; Figure 2 The reorganized display data shown, in which the extended display data is obtained by directly copying the adjacent original display data, requires a small number of switches to be set, has a simple circuit structure, and low power consumption, but the display will have a jagged phenomenon and the display effect is poor. Figure 7 The reorganized display data shown in FIG. 1 is composed of two adjacent columns of original display data. The display effect is better than that of FIG. Figure 2 The embodiment shown is preferred. Figure 9 The reorganized display data shown achieves color mixing in space, which has a better display effect. However, a larger number of switches need to be set, and each row needs to be switched once, resulting in increased power consumption. Figure 12The recombined display data shown in FIG. 1 realizes color mixing in time, and has a good display effect. Although a large number of switches need to be set, the switch is switched once per frame, which is better than Figure 9 For the embodiment shown, the power consumption is small.

[0056] In the above embodiment, it is assumed that the original display data has a total of n columns, corresponding to n first latch units 121, and the reorganized display data has a total of 2n columns, corresponding to 2n second latch units 141. That is to say, the second latch unit 141 is twice the number of the first latch unit 121. However, in actual production, it is necessary to prepare all the second latch units 141 on the same device, and all the first latch units 121 on the same device, so that two devices with different structures need to be produced, which is not conducive to mass production. Therefore, the present application sets the first latch unit and the second latch unit to be the same in number, so that they can be mass-produced as one device. In actual applications, the unused first latch unit can be made to transmit an empty signal or a zero signal, as long as it does not affect the overall operation of the source driver circuit.

[0057] For further information, see Figure 13 , and the above Figure 1 Compared with the embodiment shown, the source driver circuit 10 of the present application also includes a level conversion unit 15, a digital-to-analog conversion unit 16, and an output buffer unit 17. Among them, the level conversion unit 15 is a signal adapter of the source driver circuit 10, which is mainly responsible for the amplitude conversion of the voltage signal to ensure signal compatibility between different circuit modules. In the liquid crystal display panel, the reconstructed display data is generally a low voltage, which needs to be converted into a high voltage by the level conversion unit 15 to drive the deflection of the liquid crystal molecules. The digital-to-analog conversion unit 16 is a signal converter of the source driver circuit 10, which is used to convert the digital image signal into an analog voltage signal. The output buffer unit 17 is a power amplifier of the source driver circuit 10, which is used to amplify the analog voltage signal and drive the pixel electrode of the display panel. Usually, the analog voltage signal output by the digital-to-analog conversion unit 16 has a small current and cannot directly drive the pixel electrode. Therefore, it is necessary to perform power amplification through the output buffer unit 17 to improve the driving capability.

[0058] See also Figure 14 , Figure 14 It is a structural schematic diagram of the display panel of the present application. The display panel 40 includes a timing control circuit 41 and a source driving circuit 10 connected to the timing control circuit 41. The source driving circuit 10 receives original display data from the timing control circuit 41. The source driving circuit 10 includes any one of the above-mentioned source driving circuits 10.

[0059] The above are merely embodiments of the present invention and are not intended to limit the scope of patent protection of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention's description and drawings, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present invention.

Claims

1. A source driver circuit, applied to a display panel, characterized in that: include: a data receiving unit configured to receive original display data line by line; a first latch unit group, comprising a plurality of first latch units, wherein the plurality of first latch units are respectively connected to the data receiving unit, and each of the first latch units is configured to cache a column of the original display data; a data processing unit group, comprising a plurality of data processing units, wherein the plurality of data processing units are respectively connected to the first latch unit group, and the data processing unit group is configured to expand and reorganize the original display data to obtain reorganized display data, wherein the reorganized display data includes the original display data and the expanded display data; The second latch unit group includes multiple second latch units, and the multiple second latch units are respectively connected to the data processing unit group. Each second latch unit is configured to cache a column of the reorganized display data, wherein the cached column of the reorganized display data is a column of the original display data or a column of the extended display data.

2. The source driver circuit according to claim 1, wherein: Each column of the extended display data is determined by an adjacent column of the original display data; or Each column of the extended display data is determined by at least two adjacent columns of the original display data.

3. The source driver circuit according to claim 2, wherein: Each column of the extended display data is determined by combining the first part of the original display data in an adjacent column and the second part of the original display data in another adjacent column; or When the data receiving unit receives the original display data of the nth row, the extended display data of each column is determined by the original display data of an adjacent column; when the data receiving unit receives the original display data of the n+1th row, the extended display data of each column is determined by the original display data of another adjacent column; or When the data receiving unit receives the original display data of the mth frame image, each column of the extended display data is determined by an adjacent column of the original display data; when receiving the original display data of the m+1th frame image, each column of the extended display data is determined by another adjacent column of the original display data.

4. The source driver circuit according to claim 3, wherein: Each of the first latch units includes a plurality of first latches, each of the first latches is configured to cache a column of the original display data, and the original display data cached by different first latches in each of the first latch units correspond to different pixel colors; Each of the second latch units includes a plurality of second latches, each of the second latches is configured to cache a column of the reorganized display data, and different second latches in each of the second latch units cache the reorganized display data corresponding to different pixel colors; Each of the data processing units includes a plurality of data processing sub-units, and each of the data processing sub-units is configured to expand and reorganize the original display data to obtain the reorganized display data.

5. The source driver circuit according to claim 4, wherein: The data processing subunit includes a first data processing path and a second data processing path. The first data processing path connects a first latch and a second latch, and is configured to transfer a column of the original display data cached in the first latch to the corresponding second latch as the original display data in the reorganized display data. The second data processing path connects the first data processing path and a second latch, and is configured to transfer the original display data to the corresponding second latch as the extended display data in the reorganized display data. The second latch connected to the second data processing path and the second latch connected to the first data processing path are respectively located in two adjacent second latch units.

6. The source driving circuit according to claim 4, wherein: Each of the first latches includes a plurality of first registers, each of which is configured to cache one bit of data in a column of the original display data; each of the second latches includes a plurality of second registers, each of which is configured to cache one bit of data in a column of the reorganized display data; The data processing subunit includes a first data processing path and a second data processing path, each of the first data processing paths includes a plurality of first data transmission channels, each of the second data processing paths includes a plurality of second data transmission channels, each of the first data transmission channels is configured to transmit one bit of data in a column of the original display data; A portion of the second data transmission channel in the second data processing path is connected to a portion of the first data transmission channel in an adjacent portion of the first data processing path, and another portion of the second data transmission channel in the second data processing path is connected to another portion of the first data transmission channel in another adjacent portion of the first data processing path.

7. The source driver circuit according to claim 5, wherein: When receiving the original display data of the nth row or the original display data of the mth frame of image, the first data processing path is configured to transfer a column of the original display data cached in the first latch to the correspondingly connected second latch as the original display data in the reconstructed display data, and the second data processing path is configured to transfer the original display data to the correspondingly connected second latch as the extended display data in the reconstructed display data.

8. The source driver circuit according to claim 7, wherein: The data processing subunit further includes a third data processing path, which connects the first data processing path and one of the second latches. When receiving the n+1th row of original display data or the m+1th frame of original display data, the first data processing path is configured to transfer a column of the original display data cached in the first latch to the corresponding second latch as the original display data in the reconstructed display data, and the third data processing path is configured to transfer the original display data to the corresponding second latch as the extended display data in the reconstructed display data. The second latch unit corresponding to the second latch connected to the third data processing path and the second latch unit corresponding to the second latch connected to the second data processing path are two adjacent second latch units of the second latch unit corresponding to the second latch connected to the first data processing path.

9. The source driver circuit according to claim 4, wherein: The number of the first latch units is the same as the number of the second latch units.

10. A display panel, characterized in that: It includes a timing control circuit and a source driving circuit connected to the timing control circuit, the source driving circuit receives original display data from the timing control circuit, and the source driving circuit includes the source driving circuit according to any one of claims 1 to 9.

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