Display device and driving method thereof

Abstract

A display device includes: a pixel including a light emitting element and an initialization transistor controlling an amount of current flowing from a first power supply line to a second power supply line via the light emitting element, and obtaining a voltage supply of an initialization power supply from a third power supply line; and an initialization power supply unit that supplies a first voltage of the initialization power supply and a second voltage greater than the first voltage. The initialization power supply section supplies the second voltage to the third power supply line during an offset period in which a load connected to the third power supply line decreases in one frame period.

Description

Technical Field

[0001] The present invention relates to a display device and a driving method thereof. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become increasingly prominent. In response to this, the use of display devices such as liquid crystal display devices (LCDs) and organic light emitting display devices (OLEDs) has gradually increased.

[0003] A display device can display images using pixels. The pixels included in the display device can be set to a non-luminous state at least twice during a frame period. As an example, the pixels are connected to an initialization power line, and the light-emitting element included in each pixel can receive a voltage supply of the initialization power supply at least twice during a frame period. If the load of the initialization power line is not constant, the voltage of the initialization power supply supplied to each pixel may be different. Summary of the Invention

[0004] An object of the present invention is to provide a display device and a driving method thereof that supplies a constant initialization power supply voltage to pixels by applying an offset voltage.

[0005] A display device according to an embodiment of the present invention includes: a pixel including a light-emitting element and an initialization transistor that controls the amount of current flowing from a first power line to a second power line via the light-emitting element, and receives a voltage supply of initialization power from a third power line; and an initialization power supply unit that supplies a first voltage of the initialization power and a second voltage greater than the first voltage. During an offset period in a frame period in which a load connected to the third power line is reduced, the initialization power supply unit supplies the second voltage to the third power line.

[0006] In one embodiment, the initialization power supply section supplies the first voltage to the third power line during a period other than the offset period in the one frame period.

[0007] In one embodiment, the second voltage has a value obtained by adding the first voltage and an offset voltage, and the offset voltage has a value of the voltage of the initialization power source that decreases as a load connected to the third power line decreases.

[0008] In one embodiment, the system further includes a sensing unit configured to sense a voltage of the third power line and control the initialization power supply unit in accordance with the sensed voltage.

[0009] In one embodiment, when the sensing unit senses that the voltage of the third power line decreases, the sensing unit outputs an offset signal to the initialization power supply unit. When the initialization power supply unit receives the offset signal, the sensing unit supplies the second voltage to the third power line.

[0010] In one embodiment, the display device further includes a memory storing a value of the second voltage, and when the initialization power supply unit receives the offset signal, the second voltage is supplied to the third power line based on the value of the second voltage stored in the memory.

[0011] In one embodiment, the device further includes: a memory for storing the start and end points of the offset period and the value of the second voltage; and a control unit for controlling the initialization power supply unit.

[0012] In one embodiment, the control unit controls the initialization power supply unit to supply the second voltage to the third power line during the offset period.

[0013] In one embodiment, when the first scan signal is supplied to the first scan line, the initialization transistor is turned on, and the first scan signal is supplied at least twice within the one frame period.

[0014] A method for driving a display device according to an embodiment of the present invention includes: supplying initialization power having a first voltage to a pixel via an initialization power line during a first period in a frame period; and supplying the initialization power having a second voltage to the pixel during a second period following the first period in the frame period. The second voltage is greater than the first voltage, and the second period is a period in the frame period during which a load connected to the initialization power line is reduced.

[0015] In one embodiment, a load connected to the initialization power line during the first period is different from a load connected to the initialization power line during the second period.

[0016] In one embodiment, the second voltage has a value obtained by adding the first voltage and an offset voltage, and the offset voltage has a value of the voltage of the initialization power source that decreases as the number of loads connected to the initialization power source line decreases.

[0017] In one embodiment, the method further includes supplying the initialization power having the first voltage to the pixel during a third period following the second period in the one frame period.

[0018] In one embodiment, the pixel is supplied with the voltage of the initialization power supply at least twice during the one frame period.

[0019] (Effects of the Invention)

[0020] According to the display device of the embodiment of the present invention, by applying the offset voltage during a period when the load of the initialization power line is reduced, initialization power having substantially the same voltage is supplied to pixels, thereby improving display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a diagram showing a display device according to an embodiment of the present invention.

[0022] Figure 2 It shows Figure 1 FIG. 1 is a diagram of an embodiment of a scan driving unit included in a display device.

[0023] Figure 3 It shows Figure 1 FIG. 1 is a diagram of an embodiment of a pixel included in a display device.

[0024] Figure 4 It shows Figure 3 The waveform diagram of the pixel driving method shown is shown.

[0025] Figure 5 is a diagram illustrating a first scan signal supplied to a first scan line during one frame period.

[0026] Figure 6 is a graph showing a voltage applied to the third power line during one frame period.

[0027] Figure 7 This is a diagram showing a power supply unit according to an embodiment of the present invention.

[0028] Figure 8 This is a diagram showing a power supply unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various forms and is not limited to the embodiments described herein.

[0030] In order to clearly illustrate the present invention, parts not related to the description of the present invention will be omitted, and the same or similar components will be given the same reference numerals throughout the specification. Therefore, the reference numerals described above can also be used in other drawings.

[0031] Furthermore, when the term "same" is used in the specification, it may mean "substantially the same." That is, it may be identical to the extent that a person of ordinary skill in the art would consider it identical. Other expressions may also omit the term "substantially."

[0032] Some embodiments will be described in the accompanying drawings in relation to functional blocks, units, and / or modules. Those skilled in the art will appreciate that such functional blocks, units, and / or modules can be physically implemented using logic circuits, individual components, microprocessors, hard-wired circuits, memory elements, wiring connections, and other electronic circuitry. This can be achieved using semiconductor-based or other manufacturing technologies. In the case of functional blocks, units, and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software to perform the various functions discussed herein and can optionally be driven by firmware and / or software. Furthermore, each functional block, unit, and / or module can be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs other functions. Furthermore, in some embodiments, a functional block, unit, and / or module can be physically separated into two or more interacting individual functional blocks, units, and / or modules without departing from the scope of the present invention. Furthermore, in some embodiments, the functional blocks, units and / or modules may be physically combined into more complex functional blocks, units and / or modules without departing from the scope of the present invention.

[0033] The term "connection" between two structures may refer to both electrical and physical connections, but is not necessarily limited to these terms. For example, "connection" used in reference to a circuit diagram may refer to an electrical connection, while "connection" used in reference to a cross-sectional view or a top view may refer to a physical connection.

[0034] Although the terms "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0035] In addition, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms. Moreover, each embodiment disclosed below can be implemented alone or in combination with at least one other embodiment.

[0036] Figure 1 This is a diagram showing a display device according to an embodiment of the present invention.

[0037] Reference Figure 1 The display device 10 according to an embodiment of the present invention may include a pixel unit 100 , a scan driving unit 200 , a light emitting driving unit 300 , a data driving unit 400 , a timing control unit 500 , and a power supply unit 600 .

[0038] The display device 10 can display images at various frame rates (driving frequency, refresh rate, or frame rate) depending on the driving conditions. The frame rate refers to the frequency per second at which data voltages are actually applied to the drive transistors of the pixels PX. For example, the frame rate, also known as the frame scan rate or frame rate, indicates the frequency at which the displayed images are displayed per second.

[0039] In one embodiment, the frequency of the second scan signal supplied to the second scan line SL2 for supplying the data signal can be changed in accordance with the frame frequency. For example, the frame frequency for driving a dynamic image can be a frequency of approximately 60 Hz or higher (e.g., 60 Hz, 120 Hz, or 240 Hz). When the frame frequency is 60 Hz, the second scan signal can be supplied to each horizontal line (or pixel row) 60 times per second.

[0040] In one embodiment, the display device 10 can adjust the output frequency of the scan driver 200 and the light driver 300, and the corresponding output frequency of the data driver 400, according to driving conditions. For example, the display device 10 can display images corresponding to various frame frequencies ranging from 1 Hz to 120 Hz. However, this is merely illustrative, and the display device 10 can also display images at frame frequencies above 120 Hz (e.g., 240 Hz, 480 Hz).

[0041] The pixel unit 100 may include scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, SL41 to SL4n, light emission control lines EL1 to ELn, and data lines DL1 to DLm, and may include pixels PX (where n and m are natural numbers greater than or equal to 2) connected to the scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, SL41 to SL4n, light emission control lines EL1 to ELn, and data lines DL1 to DLm. Each pixel PX may include a light emitting element and a driving transistor.

[0042] The timing control unit 500 can receive input data Din and control signals CS from a host system such as an application processor (AP) through a specified interface. The timing control unit 500 can control the driving timing of the scan driver 200, the light driver 300, and the data driver 400. The timing control unit 500 can also control the power supply unit 600.

[0043] The timing control unit 500 can generate a scan drive signal SCS, a light-emission drive signal ECS, a data drive signal DCS, and a power drive signal PCS. The scan drive signal SCS, the light-emission drive signal ECS, the data drive signal DCS, and the power drive signal PCS can be supplied to the scan drive unit 200, the light-emission drive unit 300, the data drive unit 400, and the power supply unit 600, respectively. Furthermore, the timing control unit 500 can correct (or reorder) the input data Din to generate output data Dout, and supply the output data Dout to the data drive unit 400.

[0044] The scan driver 200 can supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4, respectively, based on the scan driver signal SCS. For example, the scan driver 200 can sequentially supply the first scan signal to the first scan lines SL11 to SL1n. For example, the scan driver 200 can sequentially supply the second scan signal to the second scan lines SL21 to SL2n. For example, the scan driver 200 can sequentially supply the third scan signal to the third scan lines SL31 to SL3n. For example, the scan driver 200 can sequentially supply the fourth scan signal to the fourth scan lines SL41 to SL4n.

[0045] Each scan signal in the first scan signal to the fourth scan signal can be set using a gate-on voltage corresponding to the type of transistor receiving the corresponding scan signal. The transistor receiving the scan signal can be set to be in a turn-on state when supplied with a scan signal. For example, the gate-on voltage of the scan signal supplied to a P-type channel metal oxide semiconductor (PMOS) transistor can be a logic low level, and the gate-on voltage of the scan signal supplied to an N-type channel metal oxide semiconductor (NMOS) transistor is a logic high level. Hereinafter, the meaning of "supplied with a scan signal" can be understood as that the scan signal is supplied at a logic level that can turn on the transistor controlled by it. And, the meaning of "interrupting the supply of the scan signal" can be understood as that the scan signal is supplied at a logic level that can turn off the transistor controlled by it.

[0046] The light emitting driving part 300 may supply a light emitting control signal to the light emitting control lines EL1 to ELn based on the light emitting driving signal ECS. The light emitting driving part 300 may supply the light emitting control signal to the light emitting control lines EL1 to ELn in sequence.

[0047] The light-emission control signal can be set using a gate cutoff voltage. A transistor receiving the light-emission control signal can be set to an off state when the light-emission control signal is supplied, and to an on state otherwise. Hereinafter, "supplied with the light-emission control signal" can be understood to mean that the light-emission control signal is supplied at a logic level that can turn off the transistor controlled by it. Furthermore, "interrupted supply of the light-emission control signal" can be understood to mean that the light-emission control signal is supplied at a logic level that can turn on the transistor controlled by it.

[0048] Although Figure 1 For ease of explanation, the scan driver 200 and the light driver 300 are shown as a single structure, but the present invention is not limited to this. Depending on the design, the scan driver 200 may include multiple scan driver units that each supply at least one of the first to fourth scan signals. Furthermore, at least a portion of the scan driver 200 and the light driver 300 may be integrated into a single driver circuit, module, or the like.

[0049] Additionally, the number of scan lines SL1, SL2, SL3, and SL4 can be set differently depending on the structure of the pixel PX. For example, the third scan line SL3 and / or the fourth scan line SL4 can be omitted depending on the structure of the pixel PX. Furthermore, the emission control lines EL1 to ELn can be omitted depending on the structure of the pixel PX.

[0050] The data driver 400 may receive a data drive signal DCS and output data Dout from the timing control unit 500. The data driver 400 may convert the digital output data Dout into an analog data signal (or data voltage) in response to the control of the data drive signal DCS. The data driver 400 may supply data signals to the data lines DL1 to DLm. For example, the data driver 400 may supply data signals to the data lines DL1 to DLm in synchronization with the second scan signals sequentially supplied to the second scan lines SL21 to SL2n.

[0051] The power supply unit 600 can generate voltages of a first driving power source VDD, a second driving power source VSS, a first initialization power source Vint1, and a second initialization power source Vint2 based on a power driving signal PCS and supply the voltages to the pixels PX. The first driving power source VDD can be supplied to the pixels PX via a first power line PL1. The second driving power source VSS can be supplied to the pixels PX via a second power line PL2. The first initialization power source Vint1 can be supplied to the pixels PX via a third power line PL3. The second initialization power source Vint2 can be supplied to the pixels PX via a fourth power line PL4.

[0052] Figure 2 It shows Figure 1 FIG. 1 is a diagram of an embodiment of a scan driving unit included in a display device.

[0053] Reference Figure 2 The scan driving unit 200 may include a first scan driving unit 220 , a second scan driving unit 240 , a third scan driving unit 260 and a fourth scan driving unit 280 .

[0054] The scan drive signal SCS may include a first start signal FLM1, a second start signal FLM2, a third start signal FLM3, and a fourth start signal FLM4. The first start signal FLM1, the second start signal FLM2, the third start signal FLM3, and the fourth start signal FLM4 may be supplied to the first scan drive unit 220, the second scan drive unit 240, the third scan drive unit 260, and the fourth scan drive unit 280, respectively. The widths and supply timings of the first to fourth start signals FLM1 to FLM4 may be determined according to the driving conditions and frame frequency of the pixel PX.

[0055] The first scan driver 220 can sequentially supply a first scan signal to the first scan lines SL11 to SL1n in response to the first start signal FLM1. The second scan driver 240 can sequentially supply a second scan signal to the second scan lines SL21 to SL2n in response to the second start signal FLM2. The third scan driver 260 can sequentially supply a third scan signal to the third scan lines SL31 to SL3n in response to the third start signal FLM3. The fourth scan driver 280 can sequentially supply a fourth scan signal to the fourth scan lines SL41 to SL4n in response to the fourth start signal FLM4.

[0056] Figure 3 It shows Figure 2 A diagram of one embodiment of a pixel is shown.

[0057] exist Figure 3 In the figure, for ease of explanation, a pixel PXij located on the i-th horizontal line (or, the i-th pixel row) and connected to the j-th data line DLj is shown (where i is a natural number less than n, and j is a natural number less than m).

[0058] Reference Figure 3 In one embodiment of the present invention, a pixel PXij may include a light emitting element LD and a pixel circuit PXC.

[0059] A first electrode (or anode electrode) of the light-emitting element LD may be connected to the pixel circuit PXC, and a second electrode (or cathode electrode) may be connected to a second power line PL2 supplied with a second driving power source VSS. The light-emitting element LD may generate light of a predetermined brightness corresponding to the amount of current supplied by the pixel circuit PXC.

[0060] The light emitting element LD may be an organic light emitting diode. Furthermore, the light emitting element LD may be an inorganic light emitting diode such as a micro LED or a quantum dot light emitting diode. Furthermore, the light emitting element LD may be a composite element of organic and inorganic substances. Figure 3 1 and 2. It is shown that the pixel PX includes a single light emitting element LD. However, in other embodiments, the pixel PX may include a plurality of light emitting elements, and the plurality of light emitting elements may be connected to each other in series, in parallel, or in series and parallel.

[0061] The pixel circuit PXC can control the amount of current supplied to the light-emitting element LD in response to the data signal supplied by the data line DLj. As an example, the pixel circuit PXC can control the amount of current supplied from the first power line PL1 (or the first driving power source VDD) via the light-emitting element LD to the second power line PL2 (or the second driving power source VSS) in response to the data signal. To this end, the pixel circuit PXC can include at least one transistor and a capacitor. The pixel circuit PXC can be implemented using various types of currently known circuits.

[0062] In one embodiment, the pixel circuit PXC may be connected to the second scan line SL2i, the third scan line SL3i, the fourth scan line SL4i, and the light emission control line ELi. The pixel circuit PXC may be connected to a first power line PL1 supplied with a first driving power source VDD, a third power line PL3 supplied with a first initialization power source Vint1, a fourth power line PL4 supplied with a second initialization power source Vint2, and a fifth power line PL5 supplied with a bias power source VOBS.

[0063] The pixel circuit PXC may include first to eighth transistors T1 to T8 and a storage capacitor Cst.

[0064] A first electrode of the first transistor T1 (or, the driving transistor) may be connected to the third node N3, and a second electrode thereof may be connected to the second node N2. Furthermore, a gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD in accordance with the voltage of the first node N1. To this end, the first driving power supply VDD may be set to a higher voltage than the second driving power supply VSS.

[0065] The second transistor T2 may be connected between the data line DLj and the third node N3. Furthermore, a gate electrode of the second transistor T2 may be connected to the second scan line SL2i. When the second scan line SL2i is supplied with a second scan signal, the second transistor T2 is turned on, thereby electrically connecting the data line DLj and the third node N3.

[0066] The third transistor T3 may be connected between the first node N1 and the second node N2. Furthermore, a gate electrode of the third transistor T3 may be connected to a third scan line SL3i. When a third scan signal is supplied to the third scan line SL3i, the third transistor T3 is turned on, thereby electrically connecting the first node N1 to the second node N2. When the third transistor T3 is turned on, the first transistor T1 is connected in a diode-like manner.

[0067] The fourth transistor T4 is connected between the first node N1 and a fourth power line PL4 supplied with a second initialization power source Vint2. Furthermore, a gate electrode of the fourth transistor T4 is connected to a fourth scan line SL4i. When the fourth scan line SL4i is supplied with a fourth scan signal, the fourth transistor T4 is turned on, thereby supplying the voltage of the second initialization power source Vint2 to the first node N1. The voltage of the second initialization power source Vint2 can be set to a voltage lower than that of the data signal supplied to the data line DLj.

[0068] The fifth transistor T5 is connected between a first power line PL1 supplied with a first driving power source VDD and a third node N3. Furthermore, a gate electrode of the fifth transistor T5 may be connected to a light emission control line ELi. The fifth transistor T5 is turned off when a light emission control signal is supplied to the light emission control line ELi, and is turned on otherwise.

[0069] The sixth transistor T6 is connected between the second node N2 and the fourth node N4. In addition, the gate electrode of the sixth transistor T6 can be connected to the light emitting control line ELi. When the light emitting control line ELi is supplied with a light emitting control signal, the sixth transistor T6 is turned off, and is turned on in other cases. In addition, although Figure 4In the figure, the fifth transistor T5 and the sixth transistor T6 are connected to the same emission control line ELi, but the present invention is not limited thereto. In an embodiment, the fifth transistor T5 and the sixth transistor T6 may be connected to different emission control lines.

[0070] Furthermore, the first initialization power supply Vint1 and the second initialization power supply Vint2 can be set to different voltages. That is, the voltage supplied to the first electrode of the light-emitting element LD and the voltage supplied to the gate electrode of the first transistor T1 can be set to be different from each other. However, this is merely illustrative, and the voltage of the first initialization power supply Vint1 and the voltage of the second initialization power supply Vint2 can also be substantially the same.

[0071] The seventh transistor T7 can be connected between the first electrode of the light-emitting element LD and the third power line PL3 supplied with the first initialization power supply Vint1. Furthermore, the gate electrode of the seventh transistor T7 can be connected to the first scan line SL1i. When the first scan line SL1i is supplied with the first scan signal, the seventh transistor T7, as described above, turns on, thereby supplying the voltage of the first initialization power supply Vint1 to the first electrode of the light-emitting element LD. The scan driver 200 can supply the first scan signal to the first scan line SL1i at least twice within one frame period.

[0072] When the voltage of the first initialization power supply Vint1 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitance of the light-emitting element LD is discharged. As the residual voltage stored in the parasitic capacitance of the light-emitting element LD is discharged (or removed), unexpected micro-luminescence can be prevented. As a result, the black expression capability of the pixel PXij can be improved.

[0073] The eighth transistor T8 may be connected between the third node N3 and a fifth power line PL5 to which a bias power source VOBS is supplied. Furthermore, a gate electrode of the eighth transistor T8 may be connected to the first scan line SL1i. When the first scan line SL1i is supplied with a first scan signal, the eighth transistor T8 is turned on, thereby supplying the voltage of the bias power source VOBS to the third node N3.

[0074] The storage capacitor Cst is connected between the first power line PL1 and the first node N1. The storage capacitor Cst may store a voltage applied to the first node N1.

[0075] Figure 4 It shows Figure 3 The waveform diagram of the pixel driving method shown is shown. Figure 4 A driving waveform supplied in one frame period can be represented.

[0076] Reference Figure 4, a frame period may include a light emitting period EP and a non-light emitting period. In the drawings, a period other than the light emitting period EP corresponds to a non-light emitting period.

[0077] The non-light emitting period may include a first bias period OBS1 and a second bias period OBS2 .

[0078] To explain the operation process, first, during the non-light-emitting period, the fifth transistor T5 and the sixth transistor T6 are turned off by the light-emission control signal EM supplied to the light-emission control line ELi. When the fifth transistor T5 and the sixth transistor T6 are turned off, the electrical connection between the first power line PL1 and the light-emitting element LD is cut off, thereby setting the light-emitting element LD to a non-light-emitting state.

[0079] During the first bias period OBS1, the first scan signal GB is supplied to the first scan line SL1i, turning on the seventh transistor T7 and the eighth transistor T8. When the seventh transistor T7 and the eighth transistor T8 are turned on, the voltage of the first initialization power supply Vint1 is supplied to the fourth node N4, and the voltage of the bias power supply VOBS is supplied to the third node N3. As a result, the first electrode of the light-emitting element LD can be initialized to the voltage of the first initialization power supply Vint1, and the bias of the first transistor T1 can be initialized.

[0080] Subsequently, the fourth scan line SL4i is supplied with the fourth scan signal GI to turn on the fourth transistor T4. When the fourth transistor T4 is turned on, the voltage of the second initialization power supply Vint2 is supplied to the first node N1, thereby initializing the first node N1 to the voltage of the second initialization power supply Vint2.

[0081] Subsequently, the second scan line SL2i is supplied with the second scan signal GW, and the third scan line SL3i is supplied with the third scan signal GC. When the second scan line SL2i is supplied with the second scan signal GW, the second transistor T2 is turned on. When the third scan line SL3i is supplied with the third scan signal GC, the third transistor T3 is turned on.

[0082] When the second transistor T2 is turned on, the data line DLj and the third node N3 are electrically connected, thereby supplying a data signal from the data line DLj to the third node N3. When the third transistor T3 is turned on, the first transistor T1 is connected in a diode-like manner. In this case, the data signal supplied to the third node N3 passes through the diode-connected first transistor T1 and is supplied to the first node N1. Therefore, a voltage corresponding to the data signal and the threshold voltage of the first transistor T1 can be applied to the first node N1. The storage capacitor Cst stores the voltage applied to the first node N1.

[0083] After a voltage corresponding to the data signal and the threshold voltage of the first transistor T1 is stored in the storage capacitor Cst, a first scan signal GB is supplied to the first scan line SL1i during a second bias period OBS2. When the first scan signal GB is supplied to the first scan line SL1i, the seventh transistor T7 and the eighth transistor T8 are turned on. When the seventh transistor T7 and the eighth transistor T8 are turned on, the voltage of the first initialization power supply Vint1 is supplied to the fourth node N4, and the voltage of the bias power supply VOBS is supplied to the third node N3. As a result, the first electrode of the light-emitting element LD can be initialized to the voltage of the first initialization power supply Vint1, and the bias of the first transistor T1 is initialized.

[0084] Subsequently, the supply of the emission control signal EM to the emission control line ELi is interrupted. When the supply of the emission control signal EM is interrupted, the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 and the sixth transistor T6 are turned on, the first power line PL1 can be electrically connected to the first electrode of the light-emitting element LD via the fifth transistor T5, the first transistor T1, and the sixth transistor T6. At this time, the first transistor T1 supplies a drive current corresponding to the voltage applied to the first node N1 to the light-emitting element LD, and the light-emitting element LD emits light at a brightness corresponding to the drive current. In other words, the light-emitting element LD can emit light at a brightness corresponding to the drive current during the emission period EP.

[0085] Although Figure 4 Although not shown, one frame period may include a porch period. The porch period may be a period after a scan signal is applied to the last scan line of one frame and data is output, and before a scan signal is applied to the first scan line of the next frame and data is output.

[0086] Figure 5 is a diagram illustrating a first scan signal supplied to a first scan line during one frame period.

[0087] Reference Figure 4 and Figure 5 One frame period includes a first bias period OBS1 and a second bias period OBS2. In addition, the scan driving part 200 may sequentially supply the first scan signal GB to the first scan lines SL11 to SL1n during the first bias period OBS1 and the second bias period OBS2.

[0088] In this case, the first scan signal GB may be supplied to two of the first scan lines SL11 ˜ SL1 n in a first period of one frame period, and supplied to one first scan line in a second period different from the first period.

[0089] For example, at the first time point t1, the first scan signal GB supplied to the first scan line SL11 corresponding to the first bias period OBS1 and the first scan signal GB supplied to the first scan line SL1i+1 corresponding to the second bias period OBS2 may overlap. As an example, the first period in which the first scan signal GB is supplied to the two first scan lines may include a period from the first time point t1 to the second time point t2 and a period exceeding the third time point t3.

[0090] In addition, referring to the offset period OP between the second time point t2 and the third time point t3, the first scan signal GB may be supplied only to the first scan line SL1i corresponding to the first offset period OBS1, while the first scan signal corresponding to the second offset period OBS2 may not be supplied. In one embodiment, the offset period OP may be a porch period within a frame. Thus, the second period during which the first scan signal GB is supplied to one first scan line may be the offset period OP.

[0091] Furthermore, if the number of first scan lines supplied with the first scan signal GB is different, the load on the third power line PL3 may be different. For example, the load connected to the third power line PL3 during the first period may be different from the load connected to the third power line PL3 during the second period. In other words, the second period may be a period during which the load connected to the third power line PL3 is reduced within a frame period.

[0092] As described above, if the load of the third power line PL3 is different during the first period and the second period, the voltage of the first initialization power Vint1 supplied during the first period and the second period may be different.

[0093] More specifically, during the offset period OP between time point t2 and time point t3 when the load is reduced, the voltage of the first initialization power source Vint1 may decrease. If different voltages of the first initialization power source Vint1 are supplied to the pixels PX during the first and second periods, the pixels PX may display uneven brightness for the same data signal.

[0094] In order to prevent such a situation, an embodiment of the present invention proposes a method of applying an offset voltage VOS during the second period.

[0095] Figure 6 is a graph showing a voltage applied to the third power line during one frame period. Figure 6 The first scan signals GB supplied to the first scan lines SL11 to SL1n during one frame period are shown in FIG. Figure 5The first scan signals GB shown supplied to the first scan lines SL11 ˜SL1 n during one frame period are similar, and thus repeated description thereof will be omitted.

[0096] Reference Figure 5 and Figure 6 , which shows the offset voltage VOS applied in the second period so as to keep the voltage of the first initialization power Vint1 supplied in the first period and the second period constant.

[0097] Voltage supply unit 600 (see Figure 1 ) may apply a first voltage to the third power line PL3 during a first period, and apply a second voltage to the third power line PL3 during a second period. The second voltage may be greater than the first voltage.

[0098] More specifically, during the offset period OP between time points t2 and t3 when the load decreases, the voltage supply unit 600 may apply a second voltage having a value obtained by adding the first voltage and the offset voltage VOS to the third power line PL3 to compensate for the decrease in the first initialization power source Vint1. The offset voltage VOS may have a value corresponding to the voltage of the initialization power source Vint1 that decreases as the load connected to the third power line PL3 decreases.

[0099] Thus, during the first period and the second period, the voltage of the first initialization power source Vint1 output to the pixel circuit PXC can be kept constant.

[0100] In another embodiment, the time for applying the first initialization power Vint1 may be shortened by reducing the pulse width of the first scan signal GB applied during the offset period OP.

[0101] By applying a voltage having a value obtained by adding the offset voltage VOS during the offset period OP in which the load of the initialization power line is reduced, initialization power having substantially the same voltage is supplied to the pixels, thereby improving display quality.

[0102] Figure 7 This is a diagram showing a power supply unit according to an embodiment of the present invention. Figure 7 Only the structures necessary for explaining the present invention are shown.

[0103] Reference Figure 7 The voltage supply unit 600 may include: a first initialization power supply unit 610 , a sensing unit 620 and a memory 630 .

[0104] The first initialization power supply unit 610 can supply the voltage of the first initialization power source Vint1 (or initialization power source) to the third power line PL3 (or initialization power line). As an example, the first initialization power supply unit 610 can be composed of a DC-DC converter, a low dropout regulator (LDO), or other types of regulators.

[0105] The sensing unit 620 may be connected to the third power line PL3 and sense the voltage and / or current of the third power line PL3. Hereinafter, for convenience of description, it will be described that the voltage of the third power line PL3 is sensed by the sensing unit 620.

[0106] The voltage sensed by the sensing unit 620 may be different in the first period and the second period. For example, the first period has a higher load than the second period, so the voltage of the third power line PL3 may be different in the first period and the second period.

[0107] In a case where the voltage of the third power line PL3 corresponds to the second period, the sensing part 620 may generate the offset signal OS to apply the second voltage to the third power line PL3 .

[0108] The first initialization power supply unit 610 supplies the second voltage to the third power line PL3 when receiving the shift signal OS, and supplies the first voltage to the third power line PL3 when not receiving the shift signal OS.

[0109] The memory 630 may store the value of the second voltage. Upon receiving the offset signal OS, the first initialization power supply unit 610 supplies the second voltage to the third power line PL3 based on the value of the second voltage stored in the memory 630.

[0110] Figure 8 This is a diagram showing a power supply unit according to an embodiment of the present invention. Figure 8 In the process of explanation, Figure 7 The same structures will be given the same reference numerals and repeated descriptions thereof will be omitted.

[0111] Reference Figure 8 The voltage supply unit 600 may include: a first initialization power supply unit 610 , a memory 630 and a control unit 640 .

[0112] The memory 630 may store the start and end points of the second period and the value of the second voltage.

[0113] The control part 640 may control the first initialization power supply part 610 based on the memory 630. For example, the control part 640 may control the first initialization power supply part 610 based on data stored in the memory 630 to supply the second voltage to the third power line PL3 during the second period.

[0114] Although the above description refers to the embodiments of the present invention, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the scope of the invention and the technical field described in the appended claims.

Claims

1. A display device, in, include: a pixel including a light emitting element and an initialization transistor that controls the amount of current flowing from a first power line to a second power line via the light emitting element and obtains a voltage supply of initialization power from a third power line; and an initialization power supply unit for supplying a first voltage of the initialization power supply and a second voltage greater than the first voltage; The initialization power supply section supplies the second voltage to the third power line during an offset period in which a load connected to the third power line is reduced in one frame period.

2. The display device according to claim 1, wherein The initialization power supply section supplies the first voltage to the third power line during a period other than the offset period in the one frame period.

3. The display device according to claim 1, wherein The second voltage has a value obtained by adding the first voltage and an offset voltage. The offset voltage has a value of the voltage of the initialization power source that decreases as a load connected to the third power source line decreases.

4. The display device according to claim 1, wherein Also includes: The sensing unit senses a voltage of the third power line and controls the initialization power supply unit according to the sensed voltage.

5. The display device according to claim 4, wherein When the sensing unit senses that the voltage of the third power line decreases, the sensing unit outputs an offset signal to the initialization power supply unit. When the initialization power supply unit receives the shift signal, the initialization power supply unit supplies the second voltage to the third power line. The display device according to claim 5 , wherein: The display device further includes a memory storing a value of the second voltage, When the initialization power supply section receives the shift signal, the second voltage is supplied to the third power line based on the value of the second voltage stored in the memory.

7. The display device according to claim 1, wherein Also includes: a memory storing a start point and an end point of the offset period and a value of the second voltage; and The control unit controls the initialization power supply unit.

8. The display device according to claim 7, wherein: The control section controls the initialization power supply section to supply the second voltage to the third power line during the offset period.

9. The display device according to claim 1, wherein When the first scan signal is supplied to the first scan line, the initialization transistor is turned on. The first scanning signal is supplied at least twice within the one frame period.

10. A method for driving a display device, wherein: include: a step of supplying initialization power having a first voltage to the pixel through the initialization power line during a first period in one frame period, and supplying the initialization power source having a second voltage to the pixel during a second period after the first period in the one frame period; the second voltage is greater than the first voltage, The second period is a period in which a load connected to the initialization power line is reduced in the one frame period.

11. The method for driving a display device according to claim 10, wherein: A load connected to the initialization power line during the first period is different from a load connected to the initialization power line during the second period.

12. The method for driving a display device according to claim 10, wherein: the second voltage has a value obtained by adding the first voltage and an offset voltage, The offset voltage has a value of the voltage of the initialization power source that decreases as the number of loads connected to the initialization power source line decreases.

13. The method for driving a display device according to claim 10, wherein: Also includes: The step of supplying the initialization power having the first voltage to the pixel during a third period following the second period in the one frame period.

14. The method for driving a display device according to claim 10, wherein: The pixel receives the voltage supply of the initialization power source at least twice during the one frame period.

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