Communication methods, systems and chips

Abstract

This application provides a communication method, system, and chip. The method includes: a first chip sequentially sending first data packets to a second chip, each first data packet including a cyclic redundancy check (CRC) code and a sequence identifier. The second chip verifies each received first data packet according to the CRC code, and if it determines that the target first data packet fails verification, it sends a first response message to the first chip, the first response message containing the sequence identifier of the target first data packet. The first chip determines that the target first data packet has failed to be received based on the sequence identifier contained in the first response message, and resends the target first data packet to a second execution module. Through this method, in the event that any data packet fails verification, the sending end can accurately retransmit the data packet based on its SID, achieving accurate retransmission of data packets, improving retransmission efficiency, and reducing the occupation of transmission resources.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method, system and chip. Background Technology

[0002] Currently, error detection and correction mechanisms for chip interconnects are typically implemented based on the Peripheral Component Interconnect Express (PCIe) protocol. When the receiving end determines that the received data contains errors, the sending end cannot accurately retransmit the erroneous data. Each retransmission may include the retransmission of a large amount of invalid data, reducing the efficiency of data retransmission. Summary of the Invention

[0003] In view of this, embodiments of this application provide a communication method, system, and chip to at least partially solve the above-mentioned problems.

[0004] According to a first aspect of the embodiments of this application, a communication method is provided, applied to a target communication system, the target communication system including a first chip and a second chip, the first chip including a first execution module located in an adaptation layer, and the second chip including a second execution module located in an adaptation layer; the method includes:

[0005] The first execution module sequentially sends each first data packet to the second execution module, and each first data packet includes a cyclic redundancy check code and a sequence identifier.

[0006] The second execution module verifies each received first data packet according to the cyclic redundancy check code, and if it determines that the target first data packet fails the verification, it sends a first response message to the first execution module. The first response message contains the sequence identifier of the target first data packet.

[0007] The first execution module determines that the target first data packet reception failed based on the sequence identifier contained in the first response message;

[0008] The first execution module resends the target first data packet to the second execution module according to the sequence identifier contained in the first response message.

[0009] According to a second aspect of the embodiments of this application, a communication system is provided, the system being configured in an electronic device, the system including a first chip and a second chip, the first chip including a first execution module located in an adaptation layer, and the second chip including a second execution module located in an adaptation layer; the system is capable of improving the retransmission efficiency of erroneous data packets by executing the communication method described in the first aspect.

[0010] According to a third aspect of the embodiments of this application, a chip is provided that can be applied to the system described in the second aspect.

[0011] According to a fourth aspect of the embodiments of this application, a computer storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.

[0012] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including computer instructions that instruct a computing device to perform an operation corresponding to the communication method described in the first aspect.

[0013] Through the technical solution of this application embodiment, in the event that any data packet fails to be verified, the sending end can accurately retransmit the data packet according to the sequence identifier of the data packet, without having to send other data packets that follow at the same time, thereby realizing accurate retransmission of data packets, improving retransmission efficiency, and reducing the occupation of transmission resources. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0015] Figure 1 This is a schematic diagram of the communication system provided in an embodiment of this application;

[0016] Figure 2 A timing diagram of a communication method provided in an embodiment of this application;

[0017] Figure 3 Another timing diagram of the communication method provided in the embodiments of this application;

[0018] Figure 4 Another timing diagram of the communication method provided in the embodiments of this application;

[0019] Figure 5 Another timing diagram of the communication method provided in the embodiments of this application;

[0020] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0022] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0023] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0024] It should also be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0025] Furthermore, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0026] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0027] Currently, the error detection and correction mechanism for chip interconnects is usually based on the Peripheral Component Interconnect Express (PCIe) standard protocol. It mainly achieves data transmission and error correction between chips through Cyclic Redundancy Check (CRC) and Retry mechanism.

[0028] For cyclic redundancy check (CRC) of data packets, the protocol layer uses a flow control unit (Flit) as the smallest unit of data transmission, with a length of 256 bytes. However, the protocol specifies that CRC uses 128-byte data as a check unit, generating one check byte. Therefore, 256 bytes of data to be transmitted require two check bytes, adding extra overhead beyond the data payload.

[0029] Furthermore, when the receiving end determines that the received data contains errors, based on the current retransmission mechanism, the sending end cannot accurately retransmit the erroneous data. Each retransmission requires sending both the erroneous data and all data sent after it, resulting in the retransmission of a large amount of invalid data and reducing the efficiency of data retransmission. For example, suppose there are 16 data items transmitted, numbered Flit0 to Flit15. Suppose Flit11 has a transmission error, while Flit0 to Flit10 and Flit12 to Flit15 were transmitted correctly. Based on the current retransmission mechanism, the sending end needs to retransmit Flit11 to Flit15, and cannot accurately transmit Flit11. Meanwhile, Flit12 to Flit15 are all correctly transmitted data, and retransmitting Flit12 to Flit15 wastes transmission resources and reduces transmission efficiency.

[0030] Furthermore, the data and control characters transmitted between the sending and receiving ends currently use the same encoding method for Flit. However, since the control characters have a small payload, using the encoding method for Flit for the control characters will result in a waste of Flit's encoding space.

[0031] This application is submitted to address the aforementioned issues.

[0032] This application provides a communication system. Figure 1 A schematic diagram of the communication system provided in an embodiment of this application is given. For example... Figure 1 As shown, the communication system may include a first chip and a second chip, with a data transmission link between them, enabling data communication. It should be understood that the data transmission between the first chip and the second chip is bidirectional; that is, the first chip can send data to the second chip, and the second chip can also send data to the first chip. In subsequent embodiments, for ease of description and understanding, the technical solution provided in this application is mainly described using the scenario of the first chip sending data to the second chip and the second chip receiving data. However, this should not be construed as a limitation of this application; in actual application scenarios, the second chip may also send data to the first chip, and the first chip may receive data.

[0033] Furthermore, the first chip and the second chip adopt a layered architecture, which, from bottom to top, may include a physical layer, an adapter layer, and a protocol layer. The physical layer may include a transmission module, the adapter layer may include an execution module, and the protocol layer may include a receiving module. Different functional modules located at different layers can be used to execute different method flows of the communication method provided in the embodiments of this application, which will be described in detail in subsequent embodiments.

[0034] For ease of distinction, in this embodiment of the application, the transmission module located in the first chip is referred to as the first transmission module, and the transmission module located in the second chip is referred to as the second transmission module. The same applies to other functional modules located at other levels, which will not be described in detail.

[0035] It should be understood that Figure 1 This is merely one example of a communication system provided in this application. In other implementations, the communication system may include more chips, and each chip may include a data transmission link for data transmission. Furthermore, each chip may include more functional modules at different levels.

[0036] The following is based on, Figure 1 The communication system with the structure shown will be used to illustrate the specific implementation of the communication method provided in the embodiments of this application.

[0037] Figure 2 A timing diagram illustrating the data transmission process between the first and second chips is provided, assuming no errors occur during multiple consecutive data transmissions. (Reference) Figure 2 The communication method provided in this application embodiment may include the following steps:

[0038] 101. The first execution module located in the first chip adaptation layer sequentially sends each first data packet to the second execution module located in the second chip adaptation layer.

[0039] In this embodiment, after the target data located at the first chip protocol layer enters the adaptation layer, the first execution module located at the adaptation layer can be used to load the protocol bytes of the adaptation layer into the target data. These protocol bytes may specifically include a portion of the header (HDR) data. Furthermore, the first execution module can be used to perform cyclic redundancy check (CRUD) on the target data, generate a CRUD code, and load the obtained CRUD code into the target data. The target data is at least 256 bytes long and can be a Flit. In this embodiment, CRUD uses 256-byte data as a check unit. Through this implementation, each Flit to be transmitted only needs to undergo CRUD once, carrying one CRUD code, reducing the additional load overhead besides the data load. Simultaneously, in this embodiment, CRUD can be performed using a combination of serial and parallel methods, with 16 bytes as the unit. Each 16 bytes is processed in parallel, and the CRUD result is calculated in one cycle and then cached. For a Flit, 256 bytes require 16 cycles. Using a serial approach, 16 intermediate results of cyclic redundancy check (CRC) are calculated sequentially. Through iterative accumulation of CRC results, a CRC result of 256 bytes can be calculated.

[0040] Furthermore, after the aforementioned information loading is completed, each target data can be sequentially distributed to a transmission buffer queue. In this embodiment, each target data in the transmission buffer queue can have a unique number, which can be a sequence identifier (SID). The first execution module can sequentially output each data packet to the first transmission module located at the physical layer according to the order of each target data in the transmission buffer queue, and the first transmission module will then sequentially send it to the second chip. Each data packet may include target data, a cyclic redundancy check code, and a SID. In this embodiment, for ease of distinction, the data packet sent from the first chip to the second chip is referred to as the first data packet, and the data packet sent from the second chip to the first chip is referred to as the second data packet.

[0041] 102. The second execution module verifies each received first data packet in sequence according to the cyclic redundancy check code.

[0042] After receiving each first data packet, the second transmission module located at the physical layer of the second chip can sequentially send each first data packet to the second execution module located at the adaptation layer. The second execution module can sequentially parse each received first data packet to obtain the SID corresponding to each first data packet, and can sequentially perform cyclic redundancy check on each first data packet according to the cyclic redundancy check code carried by each first data packet.

[0043] 103. The second execution module determines that each first data packet has passed the verification and sends the second response message corresponding to each first data packet to the first execution module in sequence.

[0044] If the cyclic redundancy check passes, the second execution module can generate a second control character, which can be an acknowledgment character (ACK). In this embodiment, the encoding method for the control character can be different from the encoding method for the data. The control character can use a short frame encoding method, thereby improving bandwidth utilization and response speed, and solving the problem of wasted encoding space in Flit caused by using a Flit-specific encoding method for the control character in related technologies.

[0045] Then, the second execution module can sequentially encode the second control character and the SID of each first data packet using Error Correcting Code (ECC) to obtain the second response message. ECC encoding enables the receiving end to detect a 2-bit error and correct a 1-bit error. In this embodiment, after detecting either type of error, the receiving end can send an interrupt signal to the processor, allowing the processor to detect the transmission error and promptly notify the application layer of the device to handle the underlying error. Specifically, for a 1-bit error, since it can be automatically corrected, it does not affect data transmission; for a 2-bit error, it affects data transmission, and the device can reset the entire transaction stream and re-initialize.

[0046] Furthermore, the second execution module can sequentially send the second response message corresponding to each first data packet to the first execution module of the first chip.

[0047] After receiving the second response message corresponding to each first data packet, the first execution module can determine each successfully received first data packet based on the SID of the first data packet carried in the second response message. The first execution module can also maintain a first buffer queue, which can be a retransmission buffer queue. The first buffer queue can store copies of each first data packet sent by the first chip. The first execution module can also delete the copy of any first data packet from the first buffer queue after any first data packet is successfully received. Specifically, after determining that a first data packet has been successfully received based on the second response message, the first execution module can determine the target buffer area from the first buffer queue based on the SID carried in the second response message and clear the target first data packet stored in the target buffer area.

[0048] In this embodiment, the first buffer queue is prohibited from being cleared before the second response message is received. After the second response message is received, the first data packet of the corresponding buffer area in the first buffer queue is cleared, and after the first data packet of the corresponding buffer area is deleted, the buffer area should remain idle. The first data packet of other buffer areas or a new first data packet cannot reoccupy the cleared buffer area. When the first buffer queue is fully occupied, it can be pushed forward.

[0049] The above technical solution enables reliable data transmission between chips. In this solution, firstly, the transmission of the second response message employs ECC, which can detect 2-bit errors and correct 1-bit errors. Furthermore, the second response message does not undergo CRC, simplifying the data frame and improving transmission efficiency. Secondly, the maximum data length of the Cyclic Redundancy Check (CRC) can reach 256 bytes, so each Flit only requires one byte of CRC code overhead. Moreover, the CRC uses a combined serial and parallel approach, making hardware implementation easier.

[0050] Figure 3 A timing diagram illustrating the data transmission process between the first and second chips is provided, assuming multiple consecutive data transmissions result in transmission errors. (Reference) Figure 3 The communication method provided in this application embodiment may include the following steps:

[0051] 201, the first execution module located in the first chip adaptation layer sends each first data packet to the second execution module located in the second chip adaptation layer in sequence.

[0052] 202. The second execution module verifies each received first data packet in sequence according to the cyclic redundancy check code.

[0053] 203. The second execution module determines that each first data packet verification has failed, and sends the first response message corresponding to each first data packet to the first execution module in sequence.

[0054] If the cyclic redundancy check fails, the second execution module can discard the corresponding data and generate a first control character, which can be a negative acknowledgment (NACK). In this embodiment, the encoding method for the control character can differ from the encoding method for the data. The control character can use a short frame encoding method, thereby improving bandwidth utilization and response speed, and solving the problem of wasted encoding space in Flit caused by using a Flit-specific encoding method for the control character in related technologies.

[0055] Then, the second execution module can sequentially perform ECC encoding on the first control character and the SID of each first data packet to obtain the first response message, and sequentially send the first response message corresponding to each first data packet to the first execution module of the first chip. Furthermore, if it is determined that the cyclic redundancy check has failed, the second execution module can also send the information about the failure of each first data packet check to the processor, for example, by sending an interrupt signal to the processor, so that the processor can notify the application layer of the device to perform relevant processing.

[0056] 204. The first execution module resends the corresponding first data packets to the second execution module according to the sequence identifier contained in each first response message.

[0057] After receiving the first response message corresponding to each first data packet, the first execution module can determine each failed first data packet based on the SID of the first data packet carried in the first response message. Furthermore, it can resend the first data packet identified by the SID carried in the first response message to the second execution module sequentially.

[0058] Specifically, before retransmitting any first data packet, the first execution module can first determine whether there is a data packet to be transmitted. If there is no data packet to be transmitted, the first execution module can directly retransmit the first data packet to the second execution module. If there is a data packet to be transmitted, the first execution module can wait for the data packet to be transmitted completely before retransmitting the first data packet to the second execution module. Figure 2 As shown, assuming that the first data packet 2 is in a pending transmission state before retransmitting the first data packet 0, the first execution module can wait for the first data packet 2 to be transmitted before retransmitting the first data packet 0.

[0059] Furthermore, in this embodiment, when the number of data retransmissions exceeds a set threshold, the system can be reinitialized. The initialization reset can be triggered by software or hardware. The set threshold can be flexibly set according to actual needs.

[0060] With the above technical solution, if any data packet fails to be verified, the sending end can accurately retransmit the data packet based on its SID without simultaneously sending other data packets that follow it. This achieves accurate retransmission of data packets, improves retransmission efficiency, and reduces the occupation of transmission resources.

[0061] Figure 4 A timing diagram illustrating the data transmission process between the first and second chips is provided, assuming a first data transmission error and a second successful data transmission. Figure 4As shown, since the first data packet 0 sent by the first execution module has a transmission error, the second execution module can send a first response message to the first execution module to trigger the first execution module to retransmit the first data packet 0. Before retransmitting the first data packet 0, the first execution module determines that the first data packet 1 is in a pending transmission state. Therefore, the first execution module can wait for the first data packet 1 to be transmitted completely before retransmitting the first data packet 0.

[0062] After the second execution module receives the first data packet 1, it determines that the first data packet 1 has passed the verification. At this time, it can send a second response message to the first execution module. The second execution module can also send the successfully received first data packet 1 to the second receiving module of the protocol layer.

[0063] In one specific implementation, to ensure correct data parsing, the second execution module can sequentially output each received first data packet to the second receiving module of the protocol layer according to the SID encoding order.

[0064] Specifically, in this embodiment, the second execution module can determine whether there are any unreceived data packets preceding the target first data packet based on the SID of the verified target first data packet. If it is determined that there are no unreceived data packets preceding the target first data packet, the target first data packet can be directly sent to the second receiving module. If it is determined that there are unreceived data packets preceding the target first data packet, after confirming that the unreceived data packet has been received, the unreceived data packet and the target first data packet can be sent to the second receiving module in the order indicated by the SID.

[0065] refer to Figure 4 After confirming that the first data packet 1 has passed verification, the second execution module determines, based on the SID of the first data packet 1, that there is a first data packet 0 that was not successfully received before the first data packet 1. Therefore, the second execution module can wait to receive the first data packet 0. After confirming that the first data packet 0 has been successfully received, the second execution module can sequentially send the first data packet 0 and the first data packet 1 to the second receiving module.

[0066] The above technical solutions can ensure the correct transmission and parsing of data.

[0067] In another embodiment of this application, after verifying the received first data packet, the second execution module in the second chip can first determine whether there is a second data packet to be sent to the first execution module before sending a response message (first response message or second response message) to the first execution module in the first chip. If there is a second data packet to be sent to the first execution module, the second execution module can arbitrate the sending order of the second data packet and the response message based on a preset rule. Then, the second execution module can send the second data packet and the first response message sequentially according to the arbitrated sending order. If there is no second data packet to be sent to the first execution module, the second execution module can directly send a response message to the first execution module. The preset rule can be flexibly set according to actual needs, and this embodiment of the application does not limit it.

[0068] refer to Figure 5 The first execution module of the first chip sends a first data packet 0 to the second execution module of the second chip. The second execution module determines that the verification of the first data packet 0 has failed and decides to send a first response message to the first execution module. At this time, the second execution module determines that there is a second data packet 0 waiting to be sent to the first execution module. The second execution module can then arbitrate the sending order of the first response message and the second data packet 0. Following the arbitrated sending order, the second data packet 0 is sent to the first execution module first. After the second data packet 0 has been sent, the second execution module sends the first response message to the first execution module.

[0069] The above technical solutions can further ensure the correctness of data transmission and improve data transmission efficiency.

[0070] Figure 6 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. The electronic device may be configured with a communication system provided in the embodiment of the present application. The communication system can be used to execute the communication method provided in the embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the electronic device.

[0071] like Figure 6 As shown, the electronic device may include: a processor 502, a communications interface 504, a memory 506, and a communications bus 508.

[0072] The processor 502, communication interface 504, and memory 506 communicate with each other via communication bus 508. Communication interface 504 is used to communicate with other electronic devices or servers. The processor 502 executes program 510, specifically performing the relevant steps described in the above communication method embodiment.

[0073] Specifically, program 510 may include program code that includes computer operation instructions.

[0074] Processor 502 may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0075] Memory 506 is used to store program 510. Memory 506 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0076] Specifically, program 510 can be used to cause processor 502 to perform the following operations: In an optional implementation, program 510 is further used to cause processor 502 to perform each step in program 510. The specific implementation of each step in program 510 can be found in the corresponding steps in the above-described communication method embodiments and the corresponding descriptions in the system, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0077] This application also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to any of the communication methods in the above-described plurality of method embodiments. It should be noted that, depending on implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0078] This application also provides a computer-readable storage medium in which the methods described in this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the communication methods described herein are implemented. Furthermore, when a general-purpose computer accesses the code used to implement the communication methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the communication methods shown herein.

[0079] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0080] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0081] Furthermore, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0082] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0083] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0084] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0085] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0086] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A communication method, characterized in that, The method is applied to a target communication system, the target communication system including a first chip and a second chip, the first chip including a first execution module located in an adaptation layer, and the second chip including a second execution module located in an adaptation layer; the method includes: The first execution module sequentially sends each first data packet to the second execution module, and each first data packet includes a cyclic redundancy check code and a sequence identifier. The second execution module verifies each received first data packet according to the cyclic redundancy check code, and if it determines that the target first data packet fails the verification, it sends a first response message to the first execution module. The first response message includes a first control character and a sequence identifier of the target first data packet. The first control character is encoded in a short frame encoding method, and the encoding method of the first control character is different from the encoding method of each first data packet. The first execution module determines that the target first data packet reception failed based on the sequence identifier contained in the first response message; The first execution module resends the target first data packet to the second execution module.

2. The method according to claim 1, characterized in that, Before the second execution module sends the first response message to the first execution module, the method further includes: The second execution module generates the first control character; The second execution module performs error correction code (ECC) encoding on the first control character and the sequence identifier of the target first data packet to obtain the first response message.

3. The method according to claim 1, characterized in that, If the second execution module determines that the target first data packet verification fails, it sends a first response message to the first execution module, including: If the second execution module determines that the first data packet fails the verification, it then determines whether there is a second data packet to be sent to the first execution module. If the second data packet exists, the second execution module arbitrates the sending order of the second data packet and the first response message based on preset rules; The second execution module sends the second data packet and the first response message in the order of the arbitration. If the second data packet does not exist, the second execution module directly sends the first response message to the first execution module.

4. The method according to claim 1, characterized in that, If the second execution module determines that the target first data packet verification fails, the method further includes: The second execution module sends the information that the target first data packet failed verification to the processor.

5. The method according to claim 1, characterized in that, Before the first execution module resends the target first data packet to the second execution module based on the sequence identifier included in the first response message, the method further includes: The first execution module determines that there are currently no data packets to be transmitted; or, The first execution module determines that there is a data packet to be transmitted and waits for the data packet to be transmitted to be transmitted to be completed.

6. The method according to claim 1, characterized in that, The method further includes: If the second execution module determines that the target first data packet has passed verification, the second execution module sends a second response message to the first execution module. The second response message contains the sequence identifier of the target first data packet.

7. The method according to claim 6, characterized in that, The second chip also includes a second receiving module located at the protocol layer; If the second execution module determines that the target first data packet verification is successful, the method further includes: The second execution module determines whether there are any unreceived data packets preceding the target first data packet based on the sequence identifier of the target first data packet; If no unreceived data packets are found before the target first data packet is determined, the target first data packet is sent to the second receiving module; If there are unreceived data packets before the target first data packet is determined, after the unreceived data packet is determined to have been received, the unreceived data packet and the target first data packet are sent to the second receiving module in the order indicated by the sequence identifier.

8. The method according to claim 6, characterized in that, The method further includes: The first execution module determines that the target first data packet was successfully received based on the sequence identifier contained in the second response message; The first execution module determines the target cache region from the first cache queue based on the sequence identifier contained in the second response message, and clears the target first data packet stored in the target cache region; The first buffer queue is used to store a copy of the first data packet sent by the first chip.

9. The method according to claim 1, characterized in that, The cyclic redundancy check code is generated based on the cyclic redundancy check of the target data, the target data is 256 bytes long, and the number of cyclic redundancy check codes is one.

10. A communication system, characterized in that, The system includes a first chip and a second chip, the first chip including a first execution module located in an adaptation layer, and the second chip including a second execution module located in an adaptation layer; the system is used to perform the method as described in any one of claims 1 to 9.

11. A chip, characterized in that, Applied to the system as described in claim 10.

12. A computer storage medium storing at least one piece of program code, the program code being loaded and executed by a processor to implement the communication method as described in any one of claims 1 to 9.

13. A computer program product comprising computer instructions that instruct a computing device to perform an operation corresponding to the communication method as described in any one of claims 1 to 9.

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