Analog video transmission to display panel and source driver integrated with display panel

Abstract

The transmitter includes an allocator that receives a stream of digital video samples and allocates the digital video samples in permutation into vectors in a buffer. A digital-to-analog converter (DAC) for each vector receives digital video samples from its corresponding vector and converts the digital video samples into analog video samples. The wire harness transfers each series of analog video samples to a source driver of a display panel of the display unit. Each source driver includes a collector that receives analog video samples from each DAC and stores analog video samples of a corresponding vector, and an amplifier that receives the stored analog video samples from the collector in parallel and amplifies the stored analog video samples onto a column of the display panel. Synchronization employs improved MFM and sampling phase alignment. The source driver is integrated with a substrate of the display panel using a transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 500,341 (filing number HYFYP0015P2) entitled “ANALOG VIDEO TRANSMISSION TO A DISPLAY PANEL AND SOURCE DRIVER INTEGRATED WITH A DISPLAY PANEL,” filed on May 5, 2023, and U.S. Provisional Patent Application No. 63 / 447,241 (filing number HYFYP0015P) entitled “ANALOG VIDEO TRANSMISSION TO A DISPLAY PANEL,” filed on February 21, 2023, which are incorporated herein by reference.

[0003] This application claims priority to U.S. Provisional Patent Application No. 63 / 611,274 (docket number HYFYP0017P2), entitled “Video Transmission within a Mobile Device,” filed on December 18, 2023, and U.S. Provisional Patent Application No. 63 / 516,220 (docket number HYFYP0017P), filed on July 28, 2023, which are incorporated herein by reference.

[0004] This application claims priority to U.S. Provisional Patent Application No. 63 / 625,473 (filing number HYFYP0018P), entitled “In-Vehicle Signal Transmission,” filed on January 26, 2024, which is incorporated herein by reference.

[0005] This application incorporates by reference U.S. patent application Ser. No. 17 / 900,570 (HYFYP009), filed on August 31, 2022, U.S. patent application Ser. No. 18 / 098,612 (HYFYP013), filed on January 18, 2023, now U.S. Patent No. 11,769,468, and U.S. patent application Ser. No. 18 / 117,288 (HyfyP014), filed on March 3, 2023, now U.S. Patent No. 11,842,671.

[0006] This application incorporates by reference U.S. Patent Application No. 18 / 442,447 (HYFYP017), filed on the same date. Technical Field

[0007] The present invention relates generally to video transmission and more particularly to transmitting analog video samples within or to a display unit, for example. Background Art

[0008] Image sensors, display panels, and video processors are all in a constant race to achieve larger formats, higher color depths, higher frame rates, and higher resolutions. Local video transmission includes performance scaling bottlenecks that hinder throughput, impact performance, and consume more cost and power. Removing these bottlenecks can bring advantages.

[0009] For example, as display resolution increases, the data rate of video information transmitted from the video source to the display screen has also increased exponentially: from 3Gbps for full HD a decade ago to 160Gbps for new 8K screens. Typically, a display with a 4K display resolution requires about 18Gbps of bandwidth at 60Hz and 36Gbps of bandwidth at 120Hz (divided into P physical channels). An 8K display requires 72Gbps of bandwidth at 60Hz and 144Gbps of bandwidth at 120Hz.

[0010] Until now, data has been transmitted digitally using a variation of low-voltage differential signaling (LVDS) data transmission, with each signal pair using a bit rate of 16Gbps, and the required total bit rate achieved by processing the signal pairs in parallel. With a wiring delay of 5ns / m, the wavelength of each bit on the digital connection is 12mm, approaching the limit of this type of connection and requiring extensive data synchronization to obtain usable data. The digital information is then converted to analog pixel information on the fly using either ultra-high-speed digital-to-analog (D-to-A) conversion or ultra-parallel slow conversion at the display's source driver.

[0011] Today, D-to-A converters use 8 bits; soon, D-to-A conversions may require 10 or even 12 bits, making it difficult to perform accurate conversions at fast enough data rates. Consequently, displays must complete the D-to-A conversion in a very short time, and the time available for conversion is getting shorter and shorter, making the stability of the D-to-A conversion an issue.

[0012] Therefore, new devices and techniques are desired to eliminate the need for D-to-A conversion at the display source driver, increase bandwidth, utilize analog video signals within the display unit, and transmit the video signals to other locations. Summary of the Invention

[0013] To achieve the above objectives, the present invention discloses a sampled analog video transmission (SAVT) technology to address the above defects in the prior art. The technology may also be referred to as "clocked analog video transmission" or CAVT.

[0014] It was recognized that the requirements for bit-perfect communication between computing devices (e.g., text, spreadsheets) were very different from the requirements for transmitting video content to humans for viewing. Fundamentally, because a video signal is a list of luminance values, it was recognized that accurately maintaining luminance values ​​with a fixed bit width (i.e., digital) would be inefficient for video transmission, and that analog voltages could provide higher resolution because there was no requirement for bit-accurate reproduction of these luminance values. The unnecessary requirement for bit-perfect video transmission imposed a costly burden—"digital overhead." Therefore, the present invention proposes transmitting video signals as analog rather than digital signals.

[0015] Conventional digital transmission uses expensive high-speed digital circuit mixed-signal processes, while the embodiments of the present invention use completely undervalued analog processes for greater flexibility and lower production costs. In addition, using analog signals for data transmission between a display controller (for example) and the source driver of a display panel can reduce complexity compared to conventional transmission between a signal source (via LVDS or Vx1 transmitter) and a source driver receiver with a D-to-A converter.

[0016] In one embodiment, a transmitter is disclosed for processing incoming digital video samples, converting them to analog, and transmitting them to a display panel; and a source driver for the display panel is also disclosed for receiving the analog samples and driving them to the display panel. The analog signal is used to transmit digital video data received from a video source (or storage device) to a video aggregator for display. The analog signal may originate from a transmitter in a computer (or other processor) and be transmitted to a source driver in a display unit for display on the display panel. Thus, the analog signal may originate from outside the display unit or may be generated at a transmitter within the display unit itself.

[0017] In another embodiment, part or all of the source driver can be integrated with the glass substrate of the display panel, given the necessary analog speed and accuracy. Due to the complexity of high-speed digital circuits, and the large area required for D-to-A conversion, source drivers in the prior art have been mounted on the edge of the display panel (but not integrated with it). The present invention is able to integrate the source driver with the glass itself because no D-to-A converter is required in the source driver, no decoder is required, and because the sample transmission frequency of the SAVT signal is low; for example, the frequency at which the SAVT video signal arrives at the source driver is one-tenth the data rate of a 3 GHz digital video signal.

[0018] The present invention can be used with any active-matrix display substrate. High-mobility substrates, such as low-temperature polysilicon (LTPS) or oxide (IGZO) TFTs, are particularly well-suited. By integrating the entire source driver, the resulting display panel can be connected to the GPU using only signal cables and power supplies of arbitrary length. This eliminates the need for further electronics connected to the glass, creating significant opportunities for further reducing edge widths and module thickness.

[0019] The present invention is particularly applicable to displays used in computer systems, televisions, monitors, gaming monitors, home theater monitors, retail signs, outdoor signs, and the like. Embodiments of the present invention are also applicable to video transmission within vehicles such as cars, trains, airplanes, and ships, not only for video transmission from a transmitter to a display or monitor of the vehicle, but also for video transmission within such a display or monitor. The present invention is also applicable to video transmission to or within a mobile device (such as a phone). In a specific embodiment, the present invention can be used within a display unit for transmission and reception of video signals. For example, the transmitter of the present invention can be used to implement the transmitter described in U.S. Patent No. 11,769,468 (HYFYP013), and the receiver of the present invention can be used to implement the receiver described in U.S. Application No. 17 / 900,570 (HYFYP009). BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention and further advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 Demonstrates the use of conversion within a display unit to transmit electromagnetic (EM) analog signals to a display panel of the display unit;

[0022] Figure 2 shows the structure of the emitter within the display unit;

[0023] Figure 3 Embodiments of dispensers are shown in which different predetermined arrangements are used;

[0024] Figure 4 is a block diagram of another embodiment of each DAC following the image processor;

[0025] Figure 5 shows the structure of the source driver of the display panel;

[0026] Figure 6 Another structure of a source driver of a display panel is shown;

[0027] Figure 7 is a block diagram showing an integrated emitter and timing controller immediately following the SoC of a display unit;

[0028] Figure 8 The integrated transmitter and timing controller are shown in more detail;

[0029] Figure 9 is a block diagram showing an integrated emitter, timing controller, and SoC within a display unit;

[0030] Figure 10 The video transmission system within the display unit is demonstrated;

[0031] Figure 11 A specific sub-pixel transfer order is demonstrated, where sub-pixels are grouped by color to minimize the transfer bandwidth;

[0032] Figure 12A A specific sub-pixel transfer order is shown, where the sub-pixels are still grouped by color to minimize transfer bandwidth, and the control signals all arrive at one dedicated amplifier channel;

[0033] Figure 12B A specific sub-pixel transmission sequence is shown, where sub-pixels are grouped by color with transition bands in between;

[0034] Figure 13 A SAVT receiver integrated with source drivers is shown, where each divider amplifier drives adjacent columns while all control signals are processed by a single amplifier;

[0035] Figure 14 shows source driver inputs for source driver 820 for interleaving multiple input amplifiers, allowing speed requirements to be met;

[0036] Figure 15 is an overview of the pixel transfer sequence, showing how the pixels and control signals are transferred from the emitter to the Figure 13 The source driver, and which amplifier each pixel and control signal is assigned to;

[0037] Figure 16 is a block diagram of the input vector to the transmitter, which has a predetermined arrangement, providing Figure 15 the required sequence of sub-pixel transfers;

[0038] Figure 17A Shown Figure 13 source driver, showing in more detail the control channel and the three comparators used to extract phase alignment information from the control signal;

[0039] Figure 17B Shows alternative Figure 17A Another source driver 820" of the source driver of FIG. 1 shows more details and control signals at the first amplifier;

[0040] Figure 17C Shows the Figure 17B The preferred source driver of the source driver 820 '";

[0041] Figure 17D yes Figure 17C Summary of the sub-pixel sequence collected by the input amplifier;

[0042] Figure 18 Techniques for introducing timing references into control signal sequences are demonstrated;

[0043] Figure 19A Control sequence commands and parameters are presented;

[0044] Figure 19B Demonstrates another technique for sending commands and parameters using MFM;

[0045] Figure 20A Techniques for performing phase alignment are demonstrated;

[0046] Figure 20B The sampling phase adjustment circuit is demonstrated;

[0047] Figure 20C A special synchronized video mode is shown for easy locking;

[0048] Figure 20D Shows an example of losing the MFM flag due to PLL phase wraparound;

[0049] Figure 20E An example showing the loss of the MFM flag when the phase exceeds the end of the control bit is shown;

[0050] Figure 20F is a flowchart describing how to perform phase alignment through MFM mark search;

[0051] Figure 21 shows the analog data path of one channel of the example source driver;

[0052] Figure 22 is a block diagram showing the transmission of analog video samples within a mobile phone;

[0053] Figure 23 Demonstrates the implementation of integration of source driver functionality in various embodiments;

[0054] Figure 24A Demonstrates the placement of gate and source drivers on the display panel glass;

[0055] Figure 24B shows a source driver implemented entirely on glass;

[0056] Figure 25Another embodiment of placing an EM signal is shown;

[0057] Figure 26 shows the simulation structure for issuing commands and receiving feedback;

[0058] Figure 27 shows latching the value from the column amplifier;

[0059] Figure 28 The digital structure used to issue commands and receive feedback is shown;

[0060] Figure 29 shows latching the value from the column amplifier;

[0061] Figure 30 A SAVT transmitter is demonstrated for transmitting various video samples from various sources; and

[0062] Figure 31 The SAVT receiver is shown at the SoC, processor, traditional display or other locations. DETAILED DESCRIPTION

[0063] It is recognized that the wiring loops within the display unit are very close to their design values, so the resilience provided by using spread spectrum codes (to encode and decode video samples for transmission within the display unit, as described in U.S. Patent No. 10,158,396) may be offset by the circuit overhead of decoding at the source driver. In particular, the use of spread spectrum codes in the transmitter's digital-to-analog converter (DAC) and the source driver's sample-and-hold amplifier can provide a degree of resilience against thermal noise. However, it is also recognized that this thermal noise is random and should be imperceptible. Therefore, in some applications, spread spectrum codes are not absolutely necessary, eliminating the need for encoding and decoding in the source driver. Therefore, it is recommended to transmit the video data as an analog signal from the transmitter to any number of source drivers of the display panel.

[0064] It was further recognized that video signals are typically digitized at the system's signal source (usually the GPU), then transmitted to the display panel source driver, typically via a combination of high-performance cabling systems. There, the digital signal is converted back to analog again for application to the display pixels. Therefore, the sole purpose of digitization is data transmission from the video source to the display pixels. Consequently, it was realized that it would be more advantageous to avoid digitization altogether (where possible) and transmit analog data directly from the video source (or suitable transmitter) to the display source driver. This analog signal is highly accurate (subject to circuit imperfections) and continuous in value, meaning that the possible resolution of its value is always higher than that of a digital representation of any length. This means that the sampling rate can be at least 10 times lower than that of digital transmission, leaving more room for bandwidth expansion.

[0065] Furthermore, it's easier to perform D-to-A conversion where less power is required than at the endpoint driving the display panel. Therefore, instead of transmitting a digital signal from the video source (or from an SoC or timing controller) to where an analog signal needs to be generated, we convert it to analog near the SoC or timing controller within the transmitter. The analog signal is then transmitted to the display panel at a much lower sampling rate than would typically be required in a digital environment. This means that instead of sending gigabits per second over multiple lines, we only need to send a few hundred megasamples per second with analog signals, reducing the required channel bandwidth. This rate is approximately one-tenth the digital rate required for the same number of physical communication paths. Furthermore, in existing digital transmission techniques, each bit only occupies approximately 1.25 cm (given that the propagation speed in a cable is approximately 0.2 m / s, 16 Gbps means 1 / 16 nanosecond per bit, so one bit is 0.2 / 16 m). Transmitting analog data increases the available time tenfold, which means increased available bandwidth. Furthermore, the bits in the digital data must be well defined. This limitation is quite sensitive to errors and noise and requires the ability to detect highs and lows very accurately.

[0066] The present invention is particularly suitable for use in high-resolution, high-dynamic-range display units used in computer systems, televisions, monitors, machine vision, automotive displays, aviation displays, virtual or augmented reality displays, mobile phones, billboards, scoreboards, and the like.

[0067] Transmit analog signal to display panel

[0068] Figure 1 Transmission of electromagnetic (EM) analog signals to the display panel 150 of the display unit 100 is shown utilizing conversion within the display unit. In this embodiment, the conversion of digital video signals to analog signals occurs within the display unit 100 itself, thereby improving display connectivity.

[0069] The figure shows a video signal 110 being transmitted to a display unit using an HDMI interface (LVDS, HDBaseT, MIPI, IP video, and other interfaces may also be used). Typically, a system-on-chip (SoC) 120 and a timing controller (TCON) 130 are shown, which transmit the digital video samples in the video signal to a transmitter 140. The SoC 120 performs functions such as display control, inverse compression, some digital signal processing, and outputs the video signal to the TCON. Typically, digital video data 122 is transmitted from the SoC to the TCON using LVDS or V-by-One. If using LVDS pairs (for example), the number of pairs depends on the specific implementation and the data rate of each pair, as well as the panel resolution, frame rate, bandwidth, and so on. Additionally, various physical layers may be used to transmit video data from SoC 120 to TCON 130, including a serializer-deserializer or SerDes layer (as is known in the art); if transmitter 140 is integrated with TCON 130, the physical layer transmits video data from SoC 120 to the integrated TCON and transmitter, such as Figure 7 For example, up to 48 or more SerDes channels can be used to transmit video data.

[0070] It is also possible to perform some or all of the digital or image processing in the SoC, in which case the Figure 2 No image processing is performed after the row buffers in the DAC and before the DAC. Preferably, the image processing includes some form of gamma correction and demura correction, and may also include image enhancement or modification (e.g., motion compensation or compensation to adjust between the bottom and top of the panel). Image processing is more easily performed in a parallel format, but can also be performed in a serial format (e.g., in processors 250-259), or even using sequential pixel conversion to a serial format.

[0071] There are several possible implementations: a discrete implementation, where the transmitter 140 is embedded in a mixed-signal integrated circuit, with the TCON and SoC being separate components; a hybrid implementation, where the transmitter 140 is integrated with the TCON in a single IC, with the SoC being separate; and a fully integrated implementation, where as much functionality as possible is integrated in a custom mixed-signal integrated circuit, with the transmitter integrated with the TCON and SoC.

[0072] exist Figure 1In this example, the display panel 150 is located within the panel frame 151 of the display unit. As shown, the emitter 140 and the panel frame 151 are both within the display unit 100. The display panel 150 can be a display panel of any size, such as a monitor, a large-screen TV, a billboard, a scoreboard, or one or more displays in a VR headset, or a head-up display (HUD) where the display is projected onto a screen on a windshield, a sun visor, etc. For the purposes of this disclosure, "display panel" refers to the internal part of the display unit (usually called "glass") that implements the pixels and produces light for viewing, while "display unit" refers to the entire (usually) rectangular housing, including the display panel, panel assembly, frame, driver, cables, and related electronics for producing video images. Generally speaking, a mass-produced display panel containing N^2 pixels is controlled by N voltages, each of which is updated N times per display interval (the inverse of the frame rate).

[0073] Using analog signals for transmission within the display unit has great advantages, even if the signal input to the display unit is a digital video signal. In prior art display units, the HDMI signal must first be decompressed before the complete full-bit-rate digital data can be obtained, which must be transmitted from the receiving point of the display unit to all the source drivers within the display unit. For a 65 or 80-inch display, these connections can be quite long; the digital data must be transmitted from one location inside the unit where it is input to another location (possibly on the other side) where the final source driver is located. Therefore, it is advantageous to convert the digital signals internally to analog signals and then send these analog signals to the source drivers (such as using lower frequency signals).

[0074] Figure 1 Also shown is an emitter 140, which generates analog EM signals 192 for source drivers 186. This includes a rigid printed circuit board (PCB) 182 and a separate flexible PCB 184, each of which holds a source driver 186 that generates the source voltage for the display panel. As will be described in detail below, signal 180 can optionally feed information about the display panel back to the emitter 140 to assist in processing video samples. The generation of gate driver control signals 190 can be performed by a timing controller (or other specialized hardware) as is known in the art and can be based on synchronization information from the source driver.

[0075] Typically, the transmitter 140 and the receiver (in this case, the source driver 186) are connected by a transmission medium. In different embodiments, the transmission medium can be a cable (such as HDMI, flat cable, fiber optic cable, metallic cable, non-metallic carbon rail flexible cable, metallic traces, etc.) or wireless. The transmission medium may have many electromagnetic paths, one path for each EM signal 192. The transmitter includes a distributor to distribute the incoming video samples to the EM paths. The number of paths can vary from one to more than one. In this example, the transmission medium will be a combination of cables, traces on a PCB, internal connections within an IC, and other media used by those skilled in the art.

[0076] During operation, a stream 110 of time-ordered digital video samples containing color values ​​and pixel-related information is received from a video source at the display unit 100 and sent to the transmitter 140 via the SoC and TCON. The number and content of the input video samples received from the video source depends on the color space of operation at the source (and the samples may be black and white). Regardless of the color space used, each video sample represents the amount of sensed or measured light in the specified color space.

[0077] The signal from the SoC (typically an LVDS digital signal, but others can be used) transmits pixel values ​​in row-major order across successive video frames. More than one pixel value may arrive at a time (e.g., two, four, etc.); they are serial, meaning groups of pixels are transmitted incrementally from one side of the row to the other. For example, a processing unit such as a depacketizer in a timing controller can be used to unpack (or expose) these serial pixel values ​​into parallel RGB values. Furthermore, it should be understood that the exposed color information for each sample set can be any color information (e.g., Y, C, Cr, Cb, etc.), not limited to RGB. Using color information other than RGB subpixels may require additional processing before the source driver can drive the columns (which are naturally subpixel intensity values). The number of output sample values ​​S in each pixel sample set is determined by the color space used by the video source. For RGB, S = 3; for YCbCr 4:2:2, S = 2. In other cases, each sample set may contain only one or more than three sample values ​​S.

[0078] The unpacker can also unpack framing information from the digital signal in the form of framing flags that appear along with the pixel values. The framing flags indicate the location of the pixel in a particular video frame; they mark the start of a row, the end of a row, the active video area, the horizontal blanking area, the vertical blanking area, etc., as known in the art. The framing flags are used to tell the gate driver which row is currently being sent to the display panel and to control the timing of the gate driver's actions. As is well known in the art, the framing flags can be included in the gate driver control signal 190. Generally speaking, symbol and sampling synchronization occurs before extracting framing information (such as Hsync and Vsync) (and other row control information).

[0079] The TCON 130 provides a reference clock 170 to each source driver 186. That is, each source driver chip (e.g., HyphyHY1002 chip) has a clock input provided by the TCON (whether it is an FPGA or an IC). For clarity, the clock 170 is only shown as an input to the first source driver, but each source driver receives a reference clock. The frequency of this reference clock may be relatively low, such as around 10.5 MHz. More details about the reference clock are in Figure 17C Available in.

[0080] transmitter

[0081] Figure 2 The structure of the emitter 140 within a display unit is shown. The figure shows a distributor 240, including two row buffers 241 and 242, a distributor controller 230, P image processors 250-259, digital-to-analog converters 260-269 following each image processor, and analog EM signals 270-279 output by each DAC. In this example, there are 24 source drivers, or 24 EM paths, or P = 24; there may be a single EM path or multiple EM paths. Depending on the implementation and design decisions, multiple output paths can improve performance but require more paths.

[0082] The controller 630 stores a row of pixels for display in a row buffer and then outputs it when the row is complete (to a DAC or another row buffer as described below). Typically, the pixels for a row of the display panel arrive serially from the SoC, but because the gate driver will enable a row of pixels to be displayed at the same time, the source driver requires the entire row of pixels to be ready at the same time. Therefore, each row buffer can store a row of pixels. In addition, sometimes the gate driver only enables half of a row of pixels on the display panel, so a row is stored in the row buffer, and then the stored row is extracted half by half for transmission while the new row is stored.

[0083] In general, when a stream of input digital video samples is received in row-major order at the transmitter 140, the input digital video samples are repeatedly: (1) assigned to one of the EM paths according to a predetermined arrangement (in this case, row-major order, i.e., identification arrangement); (2) converted to analog; and (3) transmitted over the transmission medium as analog EM signals, one EM signal per EM path. At each source driver 186, the incoming analog EM signal is received at the input and each analog sample is sequentially assigned to the memory cells of a particular column driver through a sampling circuit using the inverse of the predetermined arrangement used in the transmitter. Once all samples for that source driver are in place, they are driven to the display panel. Thus, a stream of raw, time-sequentially ordered video samples containing color and pixel-related information is transmitted from the video source to the video sink. The inverse arrangement effectively stores the incoming samples as a row in the memory array (for display on the panel) in the same order as the rows of samples were received at the distributor. The samples can arrive serially, e.g., R first, then G, then B, or in parallel, e.g., RGB as three separate signals arriving in parallel. Using the allocator 240, we can reorder the samples as needed.

[0084] In an embodiment, four control signals for every 60 video samples are inserted into the stream of samples in the distributor to be sent to the source drivers. As shown, each input vector 280 in the line buffer includes a total of 1024 values, including four control signals for every 60 video samples. The control signals can be inserted at different locations in the input vectors; for example, "samples" 960-1023 of input vectors 280-288 can actually be control signals. Any number of control signals can be used in each input vector. Furthermore, an arbitrary but finite number of control signals can be used. The more control signals transmitted, the higher the required data transmission rate. Ideally, the number of control signals should be limited to a number that is consistent with the blanking period, so that there is a correspondence between the transmission rate and the display lines (thereby reducing the amount of storage required or any additional resynchronization). Furthermore, the control signals can be inserted into the stream of samples at the distributor or at other locations.

[0085] Distributor 240 is configured to receive pixel color information (e.g., R, G, and B values) exposed in a set of input samples. Distributor 240 receives the exposed color information and writes a plurality of input vectors 280-288 into a first row buffer 241 (one input vector for each EM path) according to a predetermined arrangement. Once row buffer 241 is full, each input vector 280-288 is read out through its corresponding output port 281-289 and fed into its corresponding DAC or, alternatively, into its corresponding image processor 250-259. As these input vectors are read out of row buffer 241 (or once row buffer 241 is full), the next row of RGB input samples is written into input vectors 290-298 in second row buffer 242. Thus, once second row buffer 242 is full (and the DAC or image processor has finished reading input vectors from first row buffer 241), the DAC or image processor begins reading samples from second row buffer 242 through its output ports 291-299. As long as input samples arrive at the transmitter, samples continue to be written and read to the first and second row buffers in this "ping-pong" fashion. Output ports 281-289 and 291-299 may be bit serial communication, but more likely sequential word-wide samples, or even parallel word-wide samples.

[0086] In a preferred embodiment of writing to and reading from line buffers, samples arriving at transmitter 140 are written to only one line buffer, such as buffer 241. Once that buffer is full, all samples are written in parallel from buffer 241 to line buffer 242. Samples are then output to the DAC (or image processor) only from buffer 242. This process is continuous: as buffer 242 outputs its samples, buffer 241 is filled; once buffer 242 is empty, all samples from buffer 241 are written to buffer 242, and so on. Samples can be written from buffer 241 to buffer 242 during the horizontal blanking period.

[0087] The number of row buffers required depends on the relative times required to load and unload the buffers. The RGB inputs will have a continuous stream of data arriving. If it takes time T to load all samples into the buffer, and the same time T to unload them, then we need to use two buffers (so that one buffer can be loaded while the other is unloaded). If the unloading time becomes shorter or longer, the length of the buffer can be adjusted at any time (i.e., adjust the number of input vectors or adjust N for each input vector) so that the number of row buffers required is always two. However, more than two buffers can be used if desired, and any of the above embodiments can be used to write to and read from the buffers.

[0088] The allocator controller 230 controls the operation and timing of the line buffer. In particular, the controller is responsible for defining the arrangement and number of samples N used to create the four input vectors. In this example, N = 1024. The controller 230 may also include an arrangement controller that controls the allocation of RGB samples to positions within the input vectors.

[0089] The controller 230 may also include an arrangement controller that controls the allocation of samples to positions within the input vector. The controller is also responsible for coordinating the transition of the clock domain from a first clock frequency to a second clock frequency. In a particular embodiment, samples are clocked in at the frequency of FPIXEL, and samples are serially clocked out from each input vector at the sampled analog video transmission (SAVT) frequency of Fsavt. It is also possible to clock in two samples at a time instead of one at a time, or three samples at a time, and so on. The analog samples are transmitted as analog EM signals 270-279 along the electromagnetic path of the transmission medium to the SAVT receiver.

[0090] In one particular embodiment, each row buffer 241 or 242 has three input ports for incoming RGB samples, which are clocked in at the FPIXEL frequency. Each row buffer also has 24 output ports, such as 281 or 291 (in the case of 24 EM signals, each signal is sent to one of the 24 source drivers), with samples clocked out from each input vector at the Sampled Analog Video Transport (SAVT) frequency of Fsavt. It is also possible to clock in two R, two G, and two B samples at a time instead of one each, or three at a time, etc. In one embodiment, for 24 channels, Fsavt = 663.552 MHz.

[0091] For ease of explanation, one possible arrangement is that each input vector includes N samples of color information and control signals. In this example, the RGB samples exposed in the sample set are assigned to the input vectors from left to right. In other words, the "R", "G" and "B" values ​​of the first sample set, the "R", "G" and "B" values ​​of the next sample set, and so on are all assigned to the input vector 280 in this order (i.e., RGBRGB, etc.). Once the input vector 280 is assigned its N samples and control signals, the other input vectors will repeat the above process in sequence until each input vector has N values. The number of N values ​​for each input vector can vary greatly. As shown in this example, this predetermined arrangement retains the row-major order of the incoming samples, i.e., the first input vector 280 includes samples 0 to 1023 of the first row in this order, and subsequent input vectors continue this arrangement (including control signals). Therefore, the distributor controller 230 performs the arrangement by assigning the incoming samples to specific addresses within the row buffer. It should also be understood that the distributor 230 can use any permutation scheme, and that, regardless of which permutation scheme the emitters use, the control logic in each source driver will use its inverse to distribute incoming samples to the column drivers. In the case where only one electromagnetic path is used and video samples are received at the SAVT emitters, the distributor writes to one input vector in each row buffer.

[0092] Image processors 250-259 are shown after the line buffers and before the DACs, but it is preferable to have one (or more) image processors before the line buffers to reduce the number required, i.e., image processing is performed as RGB samples arrive, and then the samples are distributed to the line buffers. Pixels are shown arriving one at a time; if pixels arrive one at a time, one image processor is used, if they arrive two at a time, two are used, and so on. Even if the image processors are located before the line buffers, some processing, such as gain management, can be performed after the line buffers.

[0093] Typical image processing is: a) applying gamma correction to each sample; b) level shifting each gamma-corrected sample, mapping the range (0...255) to (-128...127) to remove DC from the signal; c) applying path-specific amplifier variance correction to each gamma-corrected and level-shifted sample; performing gain compensation on each sample; performing offset adjustment on each sample; and performing de-lighting correction on each sample. Other corrections and adjustments may also be performed depending on the target display panel. Individual image processors 250-259 can process a stream of samples for each output (e.g., 281 and 291), or a single monolithic image processor can process all outputs at once (e.g., 281 and 291, 285 and 295, etc.). To avoid image processing on control signals in the row buffer, the timing and position of the control signals in the buffer are known, so logic can determine that image processing should not be performed on the control signals. As described above, image processing does not need to be performed in the transmitter 140, but can be performed in the SoC 120, the TCON, or elsewhere (e.g., the receiver). For example, gamma correction is traditionally done in the receiver (source driver), but performing de-glare and more complex image processing in the source driver is not feasible.

[0094] The processed digital samples of each input vector are serially input to one of the DACs 260-269 (regardless of whether image processing occurs before or after the line buffer). Each DAC converts these modified digital samples at a frequency of Fsavt and transmits the modified analog samples as analog EM signals 270-279 along the electromagnetic path of the transmission medium to the source driver of the display element. Each DAC converts the samples it receives from the digital domain into a single analog level, which can be transmitted as a differential pair of voltage signals whose amplitude is proportional to its incoming digital value. The analog level is transmitted serially at the output of each DAC. The DAC output can range from a maximum to a minimum voltage of approximately 1 volt to 4 volts (Vpp); approximately 2 volts Vpp works well. In a specific embodiment, we represent a signal range of + / - 500mV, or 1V dynamic range (in practice, the dynamic range at the input is approximately 30% higher, or approximately 1.3V).

[0095] While two row buffers are shown in the distributor 240 (which is ideal), a single row buffer could be used, and as samples from a particular input vector are read into its image processor (or its DAC), the distributor backfills the incoming samples into that input vector. This allows for uninterrupted serial transmission of samples from the row buffer to the DAC or image processor. Alternatively, each DAC (or multiple DACs on each electromagnetic path) could be placed after the distributor and before the image processor (if present) to perform image processing on the analog samples, although this is less ideal.

[0096] Figure 3 An embodiment of the distributor 240' is shown in which a different predetermined arrangement is used. This predetermined arrangement is used to reduce the wiring complexity of each source driver. The distributor 240' arranges the samples and control signals in each input vector 380-388 in the following order: 0, 64, 128, ... 960, 1, 65, 129, ... 961, and so on, up to 63, 127, 255, ... 1023. (These indices are similar to Figure 6 The indices shown correspond to the values ​​for each amplifier processing 64 samples and control signals. Thus, each input vector inputs 1024 values ​​at a time for its specific EM path (assuming 64 control signals are added to every 960 actual samples from the TCON), and the controller distributes the samples to each input vector using a predetermined arrangement, as shown. Although not shown in the figure, 64 control signals can be added to the end of each input vector, thereby distributing four control signals to each amplifier, as shown. Figure 6 Note that the numbers 64 and 960 are implementation dependent; a different number of control signals and a different number of columns per vector can be used.

[0097] The samples of the input vectors 380-388 are then output from the line buffer 245 to the image processors 250-259 via output ports 381-389. Figure 2 Like the distributor in FIG, the distributor alternately writes samples to and reads samples from row buffer 245 or row buffer 246. Row buffer 246 outputs its samples to the image processor via output ports 391-399. Thus, by reordering the samples in the emitters, the source driver (e.g., Figure 6 Each interleaved input sampling amplifier (shown) can drive adjacent columns when operated in sequence. Output ports 381-389 and 391-399 may be bit serial communication, but more likely sequential word-wide samples, or even parallel word-wide samples.

[0098] In another embodiment (not shown), the predetermined arrangement used by distributor 240 arranges the samples by color for each input vector, i.e., all 320 red subpixels are sent, followed by all 320 green subpixels, followed by all 320 blue subpixels, and then all 64 subband signals. Thus, for the first input vector, sample positions 0-319 contain red subpixels, sample positions 320-639 contain green subpixels, sample positions 640-959 contain blue subpixels, and positions 960-1023 contain the 64 subband signals for a particular row. The samples are then sent to the image processor (all red, all green, all blue, all subbands). The same arrangement of grouping samples by color is used for the remaining input vectors. Of course, the color grouping of the subpixels in the input vector can be in any order (not necessarily red, green, blue), and the 64 subband signals can be inserted at any position within the grouping. The reason for this ordering is to exploit the heuristic principle of natural images: individual color components tend not to exhibit high spatial frequencies, thus reducing the potential electromagnetic interference signals generated by the system when grouping samples in this manner. In fact, simply grouping a substantial portion of the subpixels of a particular color together can significantly reduce electromagnetic interference (EMI). Furthermore, this ordering not only allows the use of slower S / H amplifiers in the source drivers but also reduces the bandwidth requirements of the transmitter-to-receiver communication channel. The control logic in each source driver then uses the inverse of this arrangement to direct incoming samples to the correct column driver.

[0099] Figure 4is a block diagram of another embodiment of each DAC following an image processor. As shown, instead of a single DAC following image processor 250 (for example), four interleaved DACs 361-364 are used to process the modified samples output by the image processor. Any number of DACs can be used, but a common number of DACs is a multiple of 2 (e.g., 2, 4, 8, 16). Latches 351-354 are used to sample and then transfer a particular sample output by the image processor to a corresponding DAC. Thus, for example, using four DACs, the first four samples (Sample0, Sample1, Sample2, Sample3) are sequentially transferred to DACs 361-364, and the last four samples (Sample4, Sample5, Sample6, Sample7) are also sequentially transferred to DACs 361-364. Multiplexer 340 is used to multiplex the analog samples output from each DAC so that their order in EM signal 270 is the same as the order output from image processor 250. Multiplexer 340 can be implemented as a selector, controlled by either a rotation enable bit in a shift register or a counter plus decoder. Although not shown, each of the other image processors has a similar interleaved DAC. This embodiment allows for the use of slower DACs. Image processor 250 can also follow the DAC, in which case it is an analog signal processor.

[0100] Source driver structure

[0101] Figure 5 An embodiment of the structure of a source driver 400 for a display panel is shown. Typically, a display panel may have 24 such source drivers, i.e., P is equal to 24 (for 8K displays, less for 4K displays). Note that no analog-to-digital converter (ADC) is required in the source driver to convert the samples to analog for display. Table 1 shows the parameters, values, and units of the source driver used with an 8K144 display panel. Thus, each of the 24 source drivers can drive 960 columns, providing sub-pixels for the rows of the display (23,040 sub-pixels per row).

[0102]

[0103] Table 1

[0104] Input to the source driver 400 at input terminal 410 is one of the EM signals from the transmitter 140. In this example, terminal 410 receives 1024 analog values ​​serially at a time and then stores them in rows of the A or B memory array 434 or 436 via S / H amplifiers 420-429. The analog video samples are stored as Figure 2The predetermined arrangement shown in the example arrives in their natural order, but this would require more complex wiring in the source driver as shown. Other arrangements can also be used.

[0105] Source driver 400 consists of 16 interleaved sample-and-hold input amplifiers 420-429, sampling input 410 at Fsavt / 16. There are 16 blocks (430 is the first block) for 60 video channels and 4 control signals. Each S / H amplifier 420-429 sequentially samples a specific analog sample and stores it in one of 64 storage arrays 434 or 436, 60 of which feed directly into column driver 440. Because the input amplifiers 420-429 are interleaved, they can run 16 times slower than the input signal, with each amplifier's phase shifted by one SAVT interval. As shown, S / H amplifier #0 420 drives columns 0, 16, 32, and so on, while S / H amplifier #1 421 drives columns 1, 17, 33, and so on. Therefore, the output of each S / H amplifier spans all 960 columns (one amplifier output for every 16 columns).

[0106] In one embodiment, each storage element in memory array A or B is a memory cell, such as a switched capacitor. Other terms for a memory cell are "sampler capacitor" or "analog latch." Additionally, there are 960 high-voltage column drivers 440, each driving a column 450 (via an output pin) to provide the voltages required by the display panel 480. As shown, there are 16 blocks, each with 60 video channels and four synchronization signals 460 (e.g., Hsync, Vsync, CTRL).

[0107] Once stored (e.g., in row A), these 960 samples are driven to each output column 450 via column driver 440, while the next set of 960 analog samples is stored to the other row (e.g., B). Thus, as an incoming set of 960 samples is driven to the columns from either row A or B, the next set of 960 samples is stored to the other row. In one particular embodiment, each analog level is a differential signal arriving at S / H amplifier 420, swinging between approximately +0.5 or -0.5V, with a maximum swing of approximately 18V near the mid-range voltage of each single-ended column driver, thus requiring amplification. Note that in addition to amplification, the differential signal (-full scale for dark, +full scale for light) is at some point converted to single-ended and a drive polarity is applied, resulting in a voltage of 9V for dark sub-pixels and a voltage of either full-scale positive voltage (e.g., 18V) or minimum voltage (e.g., 1V) for light sub-pixels, depending on the polarity setting. Figure 21 An example source driver is shown in more detail.

[0108] Control logic 470 implements the inverse of the predetermined arrangement used in emitter 140 and controls the timing of the S / H amplifiers (when each amplifier samples a particular incoming analog sample) via control line 471, the timing of the storage elements in rows A and B (when each row latches a particular analog sample) via control line 472, and the timing of each column driver 440 driving each column via control line 473. For example, if the emitter uses the predetermined arrangement described above, where specific sub-pixel colors are grouped together in the input vector and then these groups are transmitted in the EM signal, then control logic 470 will use the inverse of this predetermined arrangement to route the incoming samples to the correct column drivers. At the very least, control logic 470 knows how the distributor controller 242 places the incoming samples into the input vector and uses this a priori knowledge to direct the incoming samples to the correct column drivers so that the samples appear as they would in the original source image.

[0109] Note that the number of S / H amplifiers 420-429 represents a trade-off between quantity and quality. More amplifiers run slower, becoming smaller and noisier, and each amplifier drives a smaller load. However, the load on input 410 increases with the number of S / H amplifiers, which affects transmission quality. Therefore, the number of input amplifiers used is a design decision. The interval between each clock cycle can be slightly varied to address any RFI / EMI emissions. The inputs of the SHA amplifiers have a swing of only + / -250mV around their common-mode voltage (each of the positive and negative inputs), resulting in a + / -500mV signal (1V dynamic range). This is similar to the voltage swings of traditional digital signaling systems such as CEDS or LVDS. In both cases, clock modulation can be used to reduce RFI / EMI emissions, but such modulation consumes the sampling window and is therefore not preferred. Additionally, to optimize the performance of the source driver (e.g., to offset any process variations in the S / H amplifiers), a low-frequency feedback network can be added off-chip to characterize the gain and offset of each amplifier of the source driver, but this technique is not preferred due to area and performance limitations.

[0110] Another way to optimize the performance of the source driver output is to leverage existing compensation techniques within the display unit itself. Modern OLED (and Micro-LED) manufacturing techniques characterize the response of each subpixel in the array and pre-compensate for individual offsets from a manufacturing data table stored in the TCON and used when generating samples. Consequently, depending on the physical characteristics of the entire display unit (including the emitter, amplifier, source driver, and each pixel), each subpixel may have a different characteristic response—that is, it may be too bright or too dark. This table includes the respective offsets for each characteristic response.

[0111] Note that in the source driver structure 400 or 500, a predetermined amplifier in the interleaved sampling amplifiers 420-429 or 520-529 stores the pixel voltage into a switched capacitor and then amplifies it into a given column. Therefore, each column is driven by the same amplifier on each row. Any linearity errors (such as gain errors) in the amplifier during the manufacturing process will be superimposed on any other errors measured for the individual sub-pixels along the column in a regular pattern by existing compensation techniques. Therefore, these existing OLED error compensation techniques will also compensate for any linearity errors in the amplifier of the proposed source driver. This observation suggests that it is possible to relax design requirements (such as those in terms of gain accuracy), thereby reducing implementation costs. In a particularly preferred embodiment, there are three amplifier stages, and the amplifiers include common-mode feedback amplifiers.

[0112] Figure 6 FIG. 5 shows another embodiment of the structure of the source driver 500 of the display panel. Figure 5 As shown, input terminal 510, input S / H amplifiers 520-529, rows of storage elements in arrays 534 and 536, column drivers 540, output 550, sub-band signals 560 (e.g., synchronization signals such as Hsync, Vsync and CTRL), control logic 570 and display panel 580 are shown.

[0113] In this embodiment, each S / H amplifier 520-529 drives 64 adjacent locations (60 columns plus 4 sub-band values), reducing the routing complexity of the source driver, reducing the physical distance that one of the amplifiers 520-529 must drive, and facilitating de-lighting correction. For example, the first block 530 of 60 video channels and 4 sub-band signals is driven by amplifier 520, block 531 is driven by amplifier 521, and block 539 is driven by amplifier 529. Because this configuration also causes the gain error of any given input sampling amplifier to be reflected in 60 adjacent columns, it facilitates traditional high-MTF mura compensation solutions and makes de-lighting systems easier to detect.

[0114] like Figure 3 As shown, to implement this embodiment, the distributor 240' sends samples in the following order: 0, 64, 128, ... 960, 1, 65, 129, ... 961, and so on, up to 63, 127, 255, ..., 1023, with the last 64 values ​​being the control signal. Thus, by reordering the samples in the transmitter, each interleaved sampling amplifier can drive adjacent columns when operating sequentially. The control logic 570 implements Figure 3The controller 570 utilizes a predetermined arrangement that is the inverse of the predetermined arrangement used in the distributor 240′ of FIG. 5 and controls the timing of the S / H amplifiers (when each amplifier samples a particular incoming analog sample) via control line 571, the timing of the storage elements of rows A and B (when each row latches a particular analog sample) via control line 572, and the timing of each column driver 540 driving each column via control line 573. Note that in this embodiment, each sampling amplifier drives 60 columns and 4 sub-band signals.

[0115] Example of a source driver structure

[0116] above Figure 5 and Figure 6 The source driver architecture is disclosed. Other architectures can also be used, where the order of transmission from the emitter subpixels can be manipulated so that the control signals can be dispersed across the amplifiers, the control signal can be sent to a single amplifier via only one channel, or the subpixels can be grouped together by color, all for various reasons depending on the specific implementation.

[0117] Figure 11 A specific sub-pixel transmission order is shown, where the sub-pixels are grouped by color to minimize transmission bandwidth. Table 800 shows the RGB sub-pixel indexes of the sub-pixels collected by each input amplifier of the source driver. As shown, each amplifier 802 first receives the control signal and then receives a series of sub-pixels 804, in this case, first receiving red, then green, and finally blue. As shown, the sub-pixels are transmitted from the emitter in the order from top to bottom and left to right and received at a specific amplifier. Since color information tends to change more slowly than brightness information in a given video image, by grouping the sub-pixels by color, the number of transitions can be reduced and bandwidth can be reduced.

[0118] Although this structure is ideal in some applications, it is not ideal when the control signal is distributed to all S / H amplifiers (such as Figure 5 and Figure 6 ), it is difficult to extract the control information, and this structure (such as Figure 5 ) also requires each amplifier to drive all 960 columns of the display, thereby increasing the load on each amplifier channel.

[0119] Figure 12AA specific subpixel transmission order is shown, where the subpixels are still grouped by color to minimize transmission bandwidth, and the control signals all arrive at one dedicated amplifier channel. Table 810 shows the RGB subpixel index of the subpixels collected by each input amplifier of the source driver. As shown, the amplifiers 812 are numbered 0 to 15, and each amplifier 0-14 receives a series of subpixels 804, in this example, first red, then green, and then blue. Amplifier 15 specifically receives the control rail 816 for the control signals. The advantages of this include: reduced conversion times, lower bandwidth, and simpler extraction of control information, as mentioned above. In addition, each amplifier only spans 320 columns, rather than the full 960 columns.

[0120] While color grouping offers some advantages and is ideal for some applications, the video data must be padded because 960 subpixels / 15 amplifiers / 3 colors is not an integer. The additional overhead of padding means that 66 samples per amplifier are sent per row, rather than 64. This means the transmission frequency must be increased by a factor of 64 or 66, somewhat defeating the purpose of reducing transmission bandwidth through color grouping. Furthermore, driving across 320 columns is less optimal than driving only 64 columns.

[0121] Figure 12B A specific embodiment is shown in which subpixels are grouped by color with transition bands between groups. This embodiment can be implemented in the HYPHY integrated circuit chip "1002". It is recognized that because color has a lower frequency content than brightness, when color changes, the change may be abrupt, so it is necessary to make such changes more slowly. For example, if the bandwidth of the transmit channel is not wide enough, it will take a certain amount of time to go from pixel index 958 to 2 (from green to blue). Therefore, a blanking transition band 817 is added to slow down such changes and help minimize bandwidth.

[0122] To minimize SAVT bandwidth requirements, the 1002 chip uses the arrangement shown, whereby all subpixels of each color are transmitted as a group, with blanking transition bands (i.e., bands of blanking transition signals) between groups to reduce the required bandwidth between groups. SHA amplifier 0 is control channel 818, displaying control signals 0 to 64, meaning 65 samples are transmitted per line. As shown, the red subpixel indices range from 0 to 957, green from 1 to 958, and blue from 2 to 959. Sample 815 is the red blanking transition signal (tr0...tr4), sample 816 is the green blanking transition signal (tg0...tg4), and sample 817 is the blue blanking transition signal (tb0...tb4). These bands 815, 816, and 817 provide blanking transitions between colors.

[0123] In view of this, recognizing that bandwidth limitations may not be important in certain applications, control information is essentially random, padding may be undesirable, and grouping control signals on one channel may be advantageous, an alternative structure is proposed.

[0124] Figure 13 An alternative structure for the source driver is shown, where each divider amplifier drives adjacent columns and all control signals are processed by a single amplifier. If the bandwidth is sufficient, Figure 13 A structure is provided that minimizes routing. Shown is an input terminal 822, which demultiplexes incoming pixel data and control signals from the transmitter and distributes them to S / H amplifiers 824 (inputting pixel data numbered 0 to 14) and amplifiers 826 that receive control signals. As described above, the pixel data from amplifier 824 is transmitted to storage array A 828 or storage array B 830, and the control signals are processed by component 836 and output at 838. Then, as described above, the pixel data from either storage array is input to column driver 832 and output on column 834. The control logic for controlling the timing of the input amplifiers, storage arrays, and column drivers is not shown in the figure, although it has been referenced above. Figure 5 and Figure 6 Since the pixel data is received sequentially on a single channel (per chip), it is stored sequentially (one Fsavt cycle apart) into the A / B collectors, but 15 sub-pixels can also be stored into the array in parallel from the 15 SHA amplifiers.

[0125] Thus, 15 interleaved S / H amplifiers receive incoming pixel data, with each amplifier driving 64 adjacent columns, or 64 video tracks, minimizing the span of columns driven by each amplifier. This structure provides 15 blocks of 64 video samples and one 64-bit sub-band channel (control signal) for each display row (each source driver). For example, amplifier 0 drives columns 0-63, the second amplifier drives columns 64-127, and so on. The 15th amplifier drives columns 896-959, and amplifier 826 drives the control signal. All control signals are on a single channel, meaning there are no differences in amplitude, delay, or other aspects between the signals (if they were on different channels). It is also possible for the control signal to arrive on channel 0 (i.e., amplifier 0) rather than amplifier 15; the advantage of this is that the control information arrives earlier than the pixel data. Another advantage of this structure is that the control signal can be extracted by looking at only one deinterleaved amplifier output, rather than having to be distributed across all amplifiers, thus simplifying synchronization.

[0126] There are 15 video amplifiers in the diagram, each driving 64 subpixels = 960 subpixels / chip. One channel is dedicated to control, carrying 64 symbols per line (per source driver). By using MFM for timing synchronization (described below), the 64 symbols are transition-encoded, leaving 24 or 25 control bits per line after accounting for flag and command bits.

[0127] As shown, the control channel receives a control signal at amplifier 826, which is input to a comparator 836. The comparator has a reference voltage of 0V and operates at 16 / 1 of Fsavt, or approximately 41.5MHz. Assuming the control signal range is -.5V to +.5V, the comparator will detect whether the control signal is greater than 0V (indicating a digital 1) or less than 0V (indicating a digital 0). The digital data is then output at 838, providing one control bit every 16 samples. As described below, the control signal provides synchronization and phase alignment.

[0128] This particular embodiment is suitable for 8K144 displays, and example parameter values ​​are shown in Table 1 above. Those skilled in the art can directly modify this structure to accommodate other display sizes and speeds. By reordering the samples in the transmitter, each interleaved S / H amplifier can drive adjacent columns while operating sequentially as described below.

[0129] Figure 14 The source driver inputs of the source driver 820 are shown for interleaving multiple input amplifiers, allowing speed requirements to be met. (A single amplifier could also be used, but the transmission speed would be reduced). Shown are the input terminals 822, distribution amplifiers 0-14 824 and amplifiers 826 and associated switches 842, which can be rotated so that one amplifier is effectively connected at a time to receive one of the incoming sub-pixels or control signals (as the case may be). In this way, the inputs are interleaved 16 ways and the outputs of the switches are demultiplexed into 16 channels, running at 1 / 16 the data rate. The 960 sub-pixels in a row are conveniently divided into 15 groups of 64 sub-pixels each, and one channel is dedicated to detecting and processing the control signals.

[0130] Figure 15 is an overview of the pixel transfer sequence 300, showing how pixels 0-959 and control signals 0-63 are transferred from the transmitter to the Figure 13The source driver of the S / H amplifier 302 is shown, along with which amplifier each pixel is assigned. The figure shows the natural order in which the sub-pixels are transferred from the TCON to the source driver via a traditional CEDS, for example, the sub-pixels arrive as if read from left to right and then from top to bottom. Since the input data at the source driver is 16-way interleaved, the preferred method of transferring the sub-pixels to the source driver is to start from the top left, go from top to bottom, and then from left to right, i.e., the sub-pixels (and control signals) transferred are indexed 0, 64, 128, etc. Shown are the indexes of the S / H amplifier 302, an example of the sub-pixel index 304, and the control rail 306 for the 16th amplifier.

[0131] In this arrangement, 15 amplifiers (0-14) each drive 64 adjacent columns with a sub-pixel value, while amplifier 15 handles all 64 control signals. This variation minimizes the hardware in the source drivers and the wiring load on the input amplifiers. Furthermore, since no padding is required in the data sequence, this variation allows for the slowest possible SAVT (sampled analog video transmission) transmission rate (64x16 samples per line). To optimally display text and other sharp changes in intensity, the sampling amplifiers ideally adjust to the new value every 1 / Fsavt, or approximately 1.5ns per sample. To implement this structure, the sequence of sub-pixel indices used for transmission in the transmitter is: 0, 64, 128, .832,896; 1, 65, ..., 897; ...; 63, 127, 191, ..., 895, 959.

[0132] Figure 16 is a block diagram of an input vector 320 to a transmitter having a predetermined arrangement for providing Figure 15 As previously mentioned, when the sub-pixels arrive at the distributor from the timing controller, they are distributed to the input vector 320 in the order shown. When the input vector is full, the samples in the input vector are serially output to the above-mentioned image processor through the output port 321, and are converted and then transmitted to the Figure 13 The figure does not show the other input vectors of the row buffer; each input vector has a similar arrangement, and the other source drivers corresponding to each input vector also have the same Figure 13 The structure shown in the figure. The control samples at specific locations are also shown in the figure. Figure 5 、 Figure 6 、 Figure 11 、 Figure 12A 、 Figure 12B 、 Figure 13 and Figure 16As with any sync signals, subbands, control tracks, digital data in the video, i.e., those sent for control purposes rather than actual video samples to be displayed, these signals may be spread over many S / H amplifiers as shown, or sent on dedicated channels or tracks, e.g. Figure 12A Track 15 or Figure 12B Track 0.

[0133] Figure 13 The above structure of the source driver 820 and the above transmission order have the above advantages and also retain the slowest possible SAVT clock rate. As described below, each sub-pixel can be accurately sampled within the available time through synchronization.

[0134] Transmitter integrated with timing controller

[0135] As mentioned above, in another embodiment, the transmitter is integrated with the timing controller instead of Figure 1 Discrete implementation shown.

[0136] Figure 7 is a block diagram illustrating an integrated transmitter and timing controller 640 located immediately after the system-on-chip 120 of the display unit 600. The diagram shows that a digital video signal 110 is input to the system-on-chip 120 via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.), which performs functions such as display control, inverse compression, brightness, contrast, and overlay. The modified digital video signal 664 is then transmitted to the integrated transmitter and timing controller 640 via LVDS, V-by-one, or other methods. In this embodiment, the timing controller is integrated with the transmitter, both implemented in a single circuit, preferably an integrated circuit on a semiconductor chip. Note that the transmitter and timing controller chip 640 is located immediately after the SoC chip 120, facilitating the transmission of digital signals. Preferably, the chip 640 is approximately 10 cm or less from the SoC chip, in another embodiment, approximately 5 cm or less, and in another embodiment, approximately 2 cm or less. The physics of LVDS limits the maximum chip-to-chip communication distance to about a few inches.

[0137] The integrated emitter / timing controller 640 receives the digital video signal 664, distributes it into one or more row buffers, performs image processing and converts the digital samples to analog samples, and then transmits the EM signal to the source drivers, as described above. Typically, the EM signal 192 is transmitted to the source drivers 186 via differential line pairs (or metal lines), such as one pair for each source driver. The gate driver control signal 190 controls the gate driver 160 to enable the correct row of the display in synchronization with the source driver. A single reference clock 170 from the emitter and timing controller 640 can be fanned out to all source drivers because each source driver chip performs its own synchronization, but drive strength realities may mean that it is better to distribute multiple clocks. In any case, frequency lock between the source driver chips is maintained.

[0138] Figure 8 use Figure 2 6 shows the integrated emitter and timing controller 640 in more detail. Signal 664 is typically the LVDS digital signal described above. Depacketizer 620 depackets (or exposes) these serial pixel values ​​into parallel RGB values ​​and outputs a framing flag 627 to distributor controller 630 and gate driver controller 650. Distributor 642 is arranged to receive the exposed color information (e.g., RGB) from depacketizer 620 and fill row buffers 241 and 242 according to a predetermined arrangement.

[0139] As described above, controller 630 coordinates the storage and retrieval of pixel values ​​in the row buffer.

[0140] As previously described, framing flags 627 are generated by the unpacker 620 and input to the distributor controller 630, which uses these flags to determine the position of pixels in a row so that they can be stored and placed into the correct input vector. After the framing flags are output from the controller 630 (typically with a delay), they are input to the gate driver controller 650, which then generates a number of gate driver control signals 671 to control the timing of the gate drivers. These signals 671 will include at least one clock signal, at least one frame strobe signal, and at least one row strobe signal. Once the pixel values ​​are pushed into the source drivers for a particular row, the row strobe signal is applied to the specific row that the panel gate driver controller has enabled. This ensures that the row strobe signal drives the selected row at the correct time. Gate driver timing control can be performed in a manner known to those skilled in the art. Also shown is bidirectional communication 637 between the controller 630 and the gate driver controller 650; this communication is used to manage the timing between the source drivers and the gate drivers.

[0141] The operation of the two line buffers, image processors 250-259, and DACs 260-269 is as described above. Preferably, image processing is performed after the depacketizer 620 and before the line buffers. In this case, image processing blocks 250-259 are removed and replaced by a single image processing block between 620 and 241 and 242. Furthermore, as described above, image processing does not necessarily need to occur within the transmitter 640; it can also occur in the SoC 120 or elsewhere.

[0142] Transmitter integrated with timing controller and system on chip

[0143] As mentioned above, in another embodiment, the transmitter is integrated with the timing controller and SoC instead of Figure 1 Discrete implementation shown.

[0144] Figure 9 is a block diagram illustrating the transmitter, timing controller, and SoC 684 integrated within the display unit 680. In this embodiment, the conversion of the digital video signal 110 to the analog signal 192 occurs in a single chip 684 that integrates the transmitter, timing controller, and SoC.

[0145] As shown, the digital video signal 110 is input to the display unit 680 via an HDMI connector (or via LVDS, HDBaseT, MIPI, IP video, etc.) and then transmitted internally 111 to the integrated SoC. The SoC performs its traditional functions, such as display controller, inverse compression, brightness, contrast, overlay, etc. After the SoC performs its traditional functions, the modified digital video signal (not shown) is transmitted internally to the integrated transmitter and timing controller using a suitable protocol (such as LVDS, V-by-one, etc.). In this embodiment, the timing controller and transmitter are integrated with the SoC, and all three are implemented in a single circuit, preferably an integrated circuit on a semiconductor chip.

[0146] The transmitter within the circuit 684 converts the modified digital video signal into an analog EM signal 192, which is transmitted to the display panel 690. Preferably, the signal 192 is transmitted to the source driver 186 using a differential pair of wires (or metal lines), for example, one pair for each source driver. The gate driver control signal 190 controls the gate driver 160 to enable the correct row of the display in synchronization with the source driver. Typically, the distance between the chip 684 and the source driver 186 is in the range of about 5 cm to 1.5 meters, depending on the panel size. A single reference clock 170 from the transmitter, timing controller, and SoC 684 can be fanned out to all source drivers.

[0147] The integrated chip 684 can be implemented as described herein, i.e. Figure 1-4 and Figure 7 、 Figure 8 As shown, keep in mind that the functions of the transmitter, timing controller, and SoC are all integrated on the same chip or circuit. Figure 9 This embodiment has the above-mentioned Figure 7 The same advantages as listed above are achieved by integrating the transmitter and timing controller into the SoC chip, which offers further advantages such as fewer chips, reduced complexity, smaller required area, and lower power consumption. Furthermore, no DAC (digital-to-analog converter) is required within the display panel or source driver to convert the video signal.

[0148] Video transmission system embodiment

[0149] Figure 10 The video transmission system 700 within a display unit is shown. Shown is a timing controller 702, which outputs the aforementioned set of color samples, such as digital sub-pixel values, representing the brightness values ​​of the image or video to be displayed on a display panel 710. These samples are input to an emitter 704, converted into analog signals, and transmitted via a low-voltage wiring harness 706 to a source driver array 708 for display on the display panel 710.

[0150] The distributor of the transmitter includes a row buffer 720, any number of input vectors (or banks) 722-726 and a distributor controller 728. RGB samples (or black and white or any other color space) are received continuously at the distributor, and the RGB samples are distributed into the input vectors according to a predetermined arrangement controlled by the distributor controller 728. In this example, a row major order arrangement is used, and the first part of the row of the incoming video frame (or image) is stored from left to right into the input vector 722, and so on, and the last part of the row is stored into the input vector 726. Therefore, when the row buffer 720 is full, it will contain all the pixel information of the first row of the video frame, which will then be transmitted and displayed in the first row of the video frame of the display panel 710. Each input vector is read serially into its corresponding DAC 732-736, and each sample is converted to analog for transmission. As the samples arrive continuously from the timing controller 702, they are distributed, converted, transmitted, and finally displayed as video on the display panel 710. As shown Figure 2 、 Figure 3 and Figure 8 As shown, there can be two or more line buffers.

[0151] Connecting transmitter 704 and source driver array 708 is a low-voltage wiring harness 706 consisting of differential wire pairs 742-746, each of which transmits a continuous stream of analog samples (electromagnetic or EM signals) from one of the DACs 732-736. Each differential wire pair terminates at an input 760 of one of the source drivers 752-756. Other transmission media (e.g., wireless, optical) can also be used instead of a wiring harness.

[0152] Each source driver in the source driver array (e.g., source driver 752) includes an input terminal 760, a collector 762, and a number of column drivers 764 (corresponding to the number of samples in each input vector, 1,024 in this example). The samples are received serially at terminal 760 and then collected into collector 762, which can be implemented as one or more one-dimensional memory arrays with a length equal to the size of the input vector. Each collector can use Figure 5 or Figure 6 This is achieved using the A / B samplers (storage arrays) shown. Once each collector is fully loaded, all collected samples are output in parallel to all column drivers 764 of all source drivers, amplified to the appropriate high voltage required by the display panel, and output to columns 766 using a single-ended format. As samples continue to arrive through the harness, each collector continues to collect samples and output them to the display panel, thereby affecting the presentation of the video.

[0153] Synchronization of sampled analog video transmission

[0154] Synchronization can be used to provide horizontal synchronization (where a display line starts), vertical synchronization (the first display line of a frame), and sample phase alignment (when to sample an incoming subpixel sample). In other words, the receiver (such as a source driver that receives a stream of video pixels) needs information from the transmitter telling it where the frame starts, where the line starts, and at what point to sample the data representing a particular subpixel. For example, each switch 842 needs to know when the sample on its input is valid and stable so that it can sample the correct value; a process called sample phase alignment determines when to sample. Sample phase alignment takes into account the different delays of the geographically distributed source drivers from the TCON to the display; we optimize the phase of the locally generated clock 171 (derived from the reference clock 170) relative to the locally transmitted sample, as described below.

[0155] Synchronization is useful (and can be difficult) for a variety of reasons. First, the constant stream of video subpixels doesn't inherently carry information indicating the start of a frame, the start of a line, or phase-aligned data. Furthermore, the delay in the cable from transmitter to receiver can be variable and often unknown. Furthermore, the attenuation on the cable (which can differ between the paths to different source driver chips) can also cause problems. Finally, the waveform of the incoming subpixel value can be unknown and variable due to ringing, overshoot, filtering, the rate of change of the input value, or other distortions of the signal.

[0156] Recognizing the importance of synchronization, and the difficulties that can arise from the factors mentioned above, the techniques described in this paper provide commands for synchronization and phase alignment of analog samples.

[0157] The timing reference we use (i.e., a special timing violation that does not occur during normal data transmission) is called a "flag" here, which notifies the receiver, i.e., the source driver, that it can reset its clock and that what follows is a known command or data used for synchronization. For example, once the flag is received, we receive a command to start phase alignment and then determine the optimal sampling phase to sample the incoming sub-pixels. First, we need to understand the frequency of sample transmission (i.e., the rate at which samples arrive at the input of the source driver); in this case, Fsavt is approximately 664MHz (673.92MHz for HY1002). Since transmitting this high-frequency clock may not be practical, in one embodiment, we transmit a slower clock to each source driver, Fsavt / 64=10.375MHz (10.53MHz for HY1002), and each source driver uses a phase-locked loop to multiply this frequency to a higher frequency clock. We also know that there are 15 sub-pixel data streams arriving at each input amplifier at a frequency of Fsavt / 16, each input amplifier providing 64 samples, and there is a control stream (analog or digital control signal) arriving at the 16th amplifier, with 64 control signals per row.

[0158] Figure 17A Shown Figure 13 Figure 8 shows a source driver of a control channel in more detail, and the three comparators used to extract phase alignment information from the control signal. In this particular embodiment, the control channel processed by amplifier 826 includes three comparators 835-837. Comparator 836, as described above, outputs a logic "1" or a logic "0" depending on the value of the control signal. Comparator 835 has a high reference voltage for detecting the upper threshold, and comparator 837 has a low reference voltage for detecting the lower threshold; these references can be set by the DAC. Comparators 835-837 operate at Fsavt = 650MSPS.

[0159] The center comparator will be reliable (because it is a zero-crossing detector), and generally speaking, the data extracted from this center comparator will correspond to the data extracted from the high and low channels, assuming all is working correctly (i.e., if the control signal is +.4V, both the center comparator 836 and the high comparator 835 will detect a logic "1"). However, if the sampling occurs at the wrong time, the center comparator will likely provide the correct bit, but the high and low values ​​from the other two comparators will be off. The concept here is that the high and low data require the input to be nearly stable in order to receive the correct value, while the zero-crossing detector is correct even when the input sample is still converting. It is also possible to use only one high or low comparator along with the center comparator. The use of this information will be discussed below with respect to phase alignment.

[0160] Figure 17B Shown Figure 17A Another source driver of the source driver 820" shows more details and control signals at the first amplifier. The figure shows the timing generation 821 (discussed below), the input terminal 822, the DAC 838 for the adjustable threshold and the sampler block 839. Comparators 835-837 are clocked comparators used to extract the control signal. Amplifier 832 is an amplifier stage, including a preamplifier, level shifting and a high voltage driver. Shown are 16 interleaved sampling amplifiers with offset cancellation (SHA amplifier and offset control) including amplifier 826. Preferably, in this embodiment, for the control signal, we use amplifier 0 (826) (instead of Figure 17A The amplifier 15 in the display is used so that the control information arrives with a certain amount of time before the end of the display line time. This provides a small amount of time for decoding the control channel and setting up the signal to be used in the next line time.

[0161] Figure 17C Shown Figure 17B The preferred source driver 820"' of the source driver is shown in the figure. The timing generation 821, the input terminal 822 and the sampling block 839 are shown. The comparator 836 is a comparator for extracting the control signal. The amplifier 832 is an amplifier stage, including a preamplifier, a level shifter and a high-voltage driver. 16 interleaved sampling amplifiers with offset cancellation (SHA amplifier and offset control) including the amplifier 826 are shown. Preferably, in this embodiment, for the control signal, we use amplifier 0 (826) (instead of Figure 17A The amplifier 15 in the display is used so that the control information arrives with a certain amount of time before the end of the display line time. This provides a small amount of time for decoding the control channel and setting up the signal to be used in the next line time.

[0162] In this embodiment, it is recognized that synchronization only requires a single comparator 836 (zero-crossing detector) on a single SHA channel, and no DAC is required to set the comparison threshold. The synchronization algorithm operates in the digital domain (zero-crossing detector output) and performs both clock-level synchronization (alignment of the SHA outputs so that the side channel is seen at a specific SHA output) and phase-level synchronization (selection of the optimal sampling phase within the clock cycle).

[0163] At input 822, there is an analog input differential with matched termination and ESD protection. It is driven by a source impedance of 50R on each side through a 50R transmission line. Therefore, the received voltage will be reduced by 50% compared to the transmitted voltage. The PLL of 821 multiplies the relatively slow reference clock 170 from TCON (e.g. Fsavt / 64) to the full speed Fsavt clock 171 (e.g. about 675MHz in HY1002), with 11 phases selectable per clock cycle (for example). In addition, there is high speed timing generation that generates sampling strobes, reset signals and output transmission strobes for SHA amplifiers 0-15. As shown Figure 14 As shown, a 16-way deinterleaver 840 is constructed using SHA amplifiers; their on-off switches rotate so that only one is actually on at a time. (In the HY1002, both amplifiers are always on simultaneously, overlapping by one SAVT cycle.) Thus, 16 consecutive samples are deinterleaved across the 16 amplifiers in sequence, giving each amplifier more time to settle. As shown, each of the 15 SHAs drives 64 adjacent subpixel columns, including preamplifiers, level shifters (differential to single-ended), and high-voltage drivers to drive the display columns. One SHA drives control samples (note that each control sample is 16 samples apart). The control samples represent digital values ​​and provide timing and control information using a form of transition coding (such as MFM), thereby maintaining system robustness. A bandgap reference circuit 840 provides current and voltage references for the various input amplifiers.

[0164] Figure 17D yes Figure 17C The schematic shows how pixels 0-959 and control signals 0-63 are transmitted to Figure 17C The source drivers for each subpixel are shown, along with which amplifier each subpixel is assigned. Due to the 16-way interleaving at the source drivers, the preferred method for transferring subpixels to the source drivers is to start from the top left, work from top to bottom, and then from left to right, i.e., the subpixels (and control signals) transferred are indexed as ctrl0, 0, 64, 128, and so on, to the 16 amplifiers in sequence. Shown in the figure is an example of the index of the S / H amplifier 842, the subpixel index 844, and the control signal 306 for the 0th amplifier 826.

[0165] This sub-pixel order minimizes the hardware in the source driver and also minimizes the wiring load on the input amplifier. To optimally display text and other sharp transitions in intensity, the sampling amplifier should ideally settle to a new value every 1 / Fsavt, or about 1.5ns per sample. As shown, SHA0 carries control and timing; SHA1-15 carry video data, so that each SHA drives 64 adjacent columns of the display. Since the SHAs are sampled sequentially, this results in a transmission order of CTL[0], V[0], V

[64] , ... V

[896] , CTL[1], V[1], V

[65] , ... V

[897] , ..., CTL

[63] , V

[63] , V

[127] , ... V

[959] . This order provides 64 control bits per row and 960 video samples per row, for a total of 1024 samples per row (per source driver).

[0166] Figure 18 A technique is presented for introducing a timing reference into a sequence of control signals to provide synchronization and other commands on the control channels of the source drivers. Since the control signals look like a continuous bit stream, a timing reference is introduced into the control sequence to facilitate interpretation of the sequence. MFM (Modified Frequency Modulation) is commonly used in radio transmissions to provide a timing reference. While MFM is well known in the art, encoding of control sequences for video transmission has not previously been available. We realized that it could be used in the present invention to introduce a timing reference and send commands and data. Furthermore, MFM has not been used in the past to send these types of commands in video transmissions. For example, the use of horizontal and vertical synchronization commands and their specific parameters allows the transmission of all parameters supported by CEDS. Additionally, the phase alignment command and the specific phase alignment techniques described below are also novel.

[0167] The timing reference represents the point in time after which the command and data in the control sequence will follow; the timing reference is the MFM flag, an intentional timing violation. We assume that the line length from Tx to Rx is greater than one SAVT cycle, and that the line length may vary. Since we extract digital data on the control channel, it is robust even if the analog sample is not perfect. Furthermore, the level value is irrelevant; what matters is that the transition, true value, and two's complement value have the same meaning.

[0168] Timing signal 852 is Fsavt / 16, corresponding to the output timing of the input amplifiers, i.e., the rate at which each amplifier outputs data. Control bit cell 854 represents the 64-bit sequence received as a control signal at the output 838 of one source driver. MFM cells 856 represent the MFM encoding bits, with one MFM cell for every two control bits. Payload 858 is the command and data. For example, control sequence 860 is a control bit sequence received on the control channel of one of the source drivers and output at the control 838 of source driver 820″.

[0169] As shown in the figure, the control sequence includes MFM flag 862, a sequence not typically found in a stream of control bits. Flag 862 consists of a sequence of transitions spaced 4, 3, and 4 control bits apart, with the end of the fifth transition marking the end of the flag (a timing violation). This is followed by trailing zeros 864, MFM-encoded zeros that are ignored by the data receiver before the actual payload begins. The payload is then transmitted, typically LSB first, but MSB first is also possible. The value of LSB 866, in position 0 of MFM bit cell 856, shown in the control sequence, is "0." A total of 25 MFM-encoded cells are transmitted, with payload 867 shown to the right of the control sequence. A second control sequence, shown at 868, differs from sequence 860 but shares the same MFM flags and trailing zeros. The payload transmitted is different, reflecting the different commands and data that can be sent over a single control channel. Another example of a control sequence is at 869. The transmitted payload can represent commands, parameters, or be reserved for future use.

[0170] Since we receive data from the deinterleaving amplifiers across 16 channels, synchronization is complex. Until synchronization occurs, the source driver doesn't know which channel has the control sequence. One recommended approach is to use a flag sequence that appears on only one channel's output. Recognition of the MFM flag tells the source driver chip to resynchronize and prepare to receive commands or data, such as horizontal or vertical sync commands or phase alignment patterns. At power-up (or after power-down), the transmitter transmits the MFM flag and control sequence on all channels. The correct control channel (in this case, the 16th channel) recognizes the flag, resynchronizes timing, and recognizes the command and parameters. Once resynchronization has occurred, the control sequence only needs to be sent on the control channel, and video data can be sent on the other 15 channels.

[0171] A more preferred approach is to transmit the MFM flag on one channel, rather than all 16 channels initially. The receiver looks for the flag on one channel (which may be the wrong channel until synchronization is complete). If the flag is not detected after one line time (~1.5µs), the clock slips (skips) a cycle, effectively rotating the amplifier usage. Therefore, synchronization with the clock cycle requires a maximum of 16 display line times.

[0172] Because the control flow is continuous, commands and parameters can be extended across multiple display lines if necessary. While traditional CEDS transmits approximately 28-32 control bits per display line, we recognize that some of these bits don't need to be transmitted on every line (such as low-temperature mode, power control, and perhaps frame parameters). In other words, less frequent transmission is sufficient. Because we extract digital data, while the same channel transmits analog video samples with 10-bit precision, the control channel disclosed here is robust enough to not require a CRC. However, a CRC can be added. Another advantage of using MFM for video transmission is that it provides an immediate, accurate timing reference when a flag appears; there's no need to wait for correlation as with other techniques such as Kronecker. Furthermore, this control channel is sufficient to transmit commands such as frame synchronization, line synchronization, parameter data, and phase alignment information. Commands are transmitted in a distributed manner (one symbol at a time, sequentially within a line cycle), and received control information applies to the next display line. Typically, the control sequence never ends. A control packet is transmitted per line cycle. Information such as column driver polarity and driver strength is carried on a line-by-line basis.

[0173] Figure 19A An embodiment of sending commands and parameters via MFM encoding is shown. The figure shows the aforementioned timing clock Fsavt / 16 at the bottom and the control bit field 879 used to encode MFM data. Control sequence 870 is shown, including the initial MFM flag, followed by the aforementioned 25 MFM cells. Control sequence 871 illustrates how three MFM cells are used to store a 3-cell command, leaving 21 cells for parameters. More or fewer than three cells can be used for commands, depending on the implementation. Sequence 872 shows the position of the MFM flag relative to the MFM cells. Sequence 873 shows a 3-cell horizontal synchronization command, followed by 21 cells for parameters. Sequence 874 shows a 3-cell vertical synchronization command, followed by 21 cells for parameters. Sequence 875 shows a set phase alignment mode command; subsequent parameters may include comparator thresholds. Sequence 876 shows an exit phase alignment mode command. This command is not strictly required, as receiving any other command will exit phase alignment mode. Sequence 877 shows possible values ​​and parameter spaces for commands reserved for future use.

[0174] The synchronization stream 878 is the stream that is continuously transmitted on the control channel during phase alignment mode. It is envisioned that to determine the threshold of the upper comparator 835 (if phase alignment is used in Figure 20), this stream will be modulated to include two levels, namely 1V every other pulse and 1.2V every other pulse, although these voltages may vary. Phase alignment is typically performed before turning on the display and during frame blanking (because thermal or other effects may change the optimal sampling phase). Once phase alignment has been set, phase alignment mode will be exited and the video will display normally.

[0175] Figure 19B Another embodiment of sending commands and parameters through MFM encoding is shown. Figure 19A shows different command lines and each command is identified by a different 3-unit command, while Figure 19B A single command line including parameters for various commands is shown. The figure shows control bits 854 including flags 862, trailing zeros 864, and MFM cells 856 that hold command / parameters 858. As shown, each MFM cell is represented using two samples, one MFM packet per line, and an MFM flag is added before each MFM packet with a (4, 3, 4, 2) transition. This results in 25 MFM cells per line. After the flag is received, any data reception is terminated; the 25 command / parameter cells will only take effect after all 25 cells have been received, and if a new flag is received before then, it will be ignored. Either normal message (1) or (2) can be used, depending on the last state of the previous message. During initial synchronization, fast flag messages can be used, sending up to four flags per line, to speed up synchronization and provide control signals to channel 0 more quickly. The key is that parameter and control information can be passed line by line along with the sampled analog video data.

[0176] When valid, VSYNC 881 indicates that the currently received row is in the vertical blanking period, so no data will be displayed and the video controller state machine will be reinitialized. The polarity control bit 882 determines the polarity of the columns driven in pairs relative to the black level. Each pair of columns is driven in a complementary manner (one column output is driven to a more positive value and the adjacent column output is driven to a more negative value compared to the black level), and the polarity control of the column pair determines the direction. The four polarity controls independently control the four column pairs in the 8-column group, and this pattern is repeated for all sub-pixel columns in a row every 8 columns. The polarity control can be updated in each row. In practical applications, the polarity control bits are changed at most once per row (to reduce power consumption).

[0177] The short circuit control bits 883 include "short_gena", which, when valid, shorts adjacent columns only when the corresponding polarity control bit changes, unless short_all is also valid. When invalid, no short circuit operation is performed at all. "Short_all" shorts all column pairs regardless of the state of the polarity control bits, but is only valid when short_gena is also valid. The drive time control 884 specifies the number of Fsavt / 16 cycles from the start of the high voltage driver drive cycle to the driver tri-stating or charge sharing (depending on SHORTCTL). The sampling phase 885 of the high voltage driver is a chopping clock used to swap the input and output of the main amplifier to eliminate offsets. The SHA calibration control signals 886 include two SHA calibration control signals: sha_video (sha_cal[0]) and sha_meas (sha_cal[1]), both of which can be directly controlled by the side channel control bits. These signals control the Calibration_Phase1 and Calibration_Phase_2 signals of the SHA, respectively.

[0178] Phase alignment technology

[0179] As mentioned above, due to delays and attenuation in the cable, ringing in the input samples, intersymbol interference, and other factors, it is desirable to determine the optimal sampling phase for incoming samples for a particular source driver. This phase alignment can be performed at power-up or at regular intervals, such as during frame synchronization or during frame blanking. Phase alignment mode can be entered by issuing the "Set Phase Alignment Mode" command described above. Two phase alignment techniques are presented below.

[0180] Figure 20A A technique for performing phase alignment is presented for Figure 17A and 17B A source driver with three comparators in FIG. The diagram shows the synchronization stream 878 in greater detail 890; for ease of explanation, a square wave is shown. Preferably, each sample or pulse in stream 890 is 16 SAVT samples long (i.e., the sampled output of a single channel of the deinterleaver amplifier); if we compare to a threshold at the SAVT rate, we see 16 identical values. The stream is preferably modulated (e.g., using a triangle or trapezoidal wave) to produce two distinct voltage levels 891 and 892 (and corresponding negative voltage levels 897 and 898). For ease of explanation, the levels are shown as approximately 1.0V and 1.2V (with corresponding negative voltage levels of -1.0V and -1.2V), but in practice, consider a positive voltage level of approximately 0.5V and a negative voltage level of approximately -0.5V. As shown, the synchronization stream continuously repeats two positive and two negative voltage levels until the phase alignment mode is exited.

[0181] Once in phase alignment mode, a synchronization stream 878 is sent along the source driver's control channel. For example, the synchronization stream reaches input amplifier 826 and is detected by central comparator 836 and upper and lower threshold comparators 835 and 837. This synchronization stream is preferably a valid MFM data stream (i.e., MFM zero and MFM one) with a regular 50% duty cycle pattern of positive and negative values ​​of known amplitude. Because this is a valid MFM data stream, an "exit phase alignment mode" command can be issued at any time. Comparators 835 and 837 should be sufficiently fast, but they do not need to be absolutely accurate, as long as the offset is less than the difference between the last two amplitude levels.

[0182] Essentially, center comparator 836 provides zero-crossing detection and indicates whether the detected input is positive or negative. When the sample is positive and the sampling phase is correct, upper threshold comparator 835 should also produce a positive value. If not, this means the sample occurred too early or too late, i.e., before or after the transition to a positive value. Lower threshold comparator 837 provides similar information when the sample is negative. If the upper or lower comparator disagrees with the center comparator, the sampling phase is adjusted. Techniques for adjusting the phase to correctly sample positive inputs are detailed below, but those skilled in the art can also apply this technique to negative inputs.

[0183] The upper comparator (for example) should report the same value as detected by the zero-crossing detector. As the sampling phase rotates (by advancing the phase of the PLL), we will eventually reach a point where the next transition begins to occur. This transition will cause the upper comparator to provide a result that is inconsistent with the zero-crossing detector. At this point, we know that a transition has been detected and can move the sampling phase back one (or two, to be safe) phase, allowing us to sample late in the symbol period, after the sample is determined but before the transition to the next sample. Note that if the transition is very fast, the zero-crossing detector may also flip when the symbol transition occurs. In this case, there is no need to check the upper comparator, so the "transition" can be determined by the OR of these two events.

[0184] As previously mentioned, the first step is to enter phase alignment mode and send synchronization stream 890 along the control channel. Amplitudes 891 and 892 are preferably set far enough apart to account for any ringing on the input, and to provide a window (approximately 0.2V in this example) within which upper threshold 893 can be set so that when the sampling phase is approximately correct, pulse 891 will not trigger the upper comparator, while pulse 892 will. In one example, if the expected amplitude of the control signal is approximately 1.5V and approximately -1.5V, the amplitudes of pulses 891 and 892 are set below the expected amplitude, as shown. The corresponding amplitudes of pulses 897 and 898 can be set in the same manner.

[0185] One purpose of choosing the initial voltages for these two pulse amplitudes is to set the modulation level so that we can detect transitions. One embodiment uses a 50% amplitude and a 75% amplitude (of the positive pulse) for the two amplitudes of the synchronization stream. This makes it easy to set the DAC threshold between the two amplitudes (taking into account factors such as noise) while also providing a good indication of when the transition occurs (when the 75% amplitude pulse falls below the DAC upper threshold).

[0186] The initial sampling phase can be chosen randomly, from a reset value (such as phase 0), or from another phase choice. Since the zero-crossing detector is used to determine the expected signal level, it's unlikely (~1 / 16 probability, but possible) that the sampling phase will be chosen at a symbol transition, where the zero-crossing output would appear random. However, if this happens and we still haven't seen the symbol after skipping all 16 clocks, we advance the phase to a point where the zero-crossing detector operates normally. In our implementation, there are 11 phases; it's expected that shifting the phase by two or three positions is sufficient. Other implementations will vary.

[0187] Once the synchronization stream arrives, the logic and circuitry in the source driver (not shown) can adjust the upper threshold by sliding it up and down to determine its optimal voltage. For example, if the upper threshold is too low, the upper comparator will trigger on both pulses 891 and 892; if the upper threshold is too high, it will not trigger on pulse 892; when the upper threshold is set correctly, it will not trigger on pulse 891, but it will trigger on pulse 892. Due to attenuation and other reasons, the source driver does not know what the amplitudes of pulses 891 and 892 are, but as long as the amplitudes are large enough apart to accurately set the upper threshold, the source driver does not need to know the exact value. The sampling phase used in this adjustment process is roughly correct, but not optimal. Once the upper threshold is set correctly, any ringing on pulse 891 will not trigger the upper threshold, but pulse 892 will trigger the upper threshold. A DAC can be used to adjust the upper threshold.

[0188] Once the upper threshold is set, the logic and circuitry within the source driver begins rotating the sampling phase around 11 different phase positions to determine the optimal sampling phase. For example, the initial sampling phase might occur roughly in the middle of pulse 892, but this is likely not the optimal sampling point because the pulse may be unstable at this point, potentially producing an erroneous value. Typically, the optimal sampling point is immediately before processing the next pulse, when the signal is most stable—that is, before the trailing edge of the pulse. When the sampling phase rotates to point 894, both the center and upper comparators trigger, signaling a positive value. At point 895, both the center and upper comparators trigger again. However, at point 896, the upper comparator suddenly stops triggering, indicating that a transition has just passed. There is no correspondence between the upper and center comparators. (Despite displaying a perfect square wave, the center comparator still signals a positive value because the transition is not a sharp drop to -1.2V, but rather a more gradual decline.) Therefore, by backing off one or two phase taps, to point 895 or 894, we can find the optimal sampling phase. Another number of phase positions can also be used; 11 phase positions is determined by the process (suitable for the number of inversions within a 1.5ns clock period). Depending on the VCO structure, an odd number of positions may also work well.

[0189] Using two pulses 891 and 892 to set the upper threshold ensures that the upper threshold is sufficiently high to facilitate the search for an optimal sampling phase as described below. Providing an upper threshold below the amplitude of pulse 892 ensures that no correspondence exists between the upper comparator and the center comparator when sampling after the transition of pulse 892, thereby facilitating selection of the optimal sampling phase. While a single sampling phase can be used once detected, it is best to average multiple measurements to account for noise and overshoot.

[0190] Techniques for determining the optimal sampling phase for positive pulses are described above. The same techniques can be used for negative pulses and the results averaged. In one particular embodiment, the lower threshold comparator 837 is not required and only comparators 835 and 836 are used to determine the optimal sampling phase using positive pulses as described above. In another embodiment, the upper threshold comparator is not used for negative pulses and only the lower threshold comparator and the center comparator are used to determine the optimal sampling phase. In another embodiment, the upper threshold comparator is only used for positive pulses of the same amplitude in the synchronization stream; the upper threshold is set below the amplitude of these positive pulses and the sampling phase is rotated back and forth based on when the upper comparator stops triggering. As shown in FIG. Figure 20AAs shown, the upper threshold comparator can also be used exclusively when the synchronization stream includes alternating positive pulses of different amplitudes. Similarly, in another embodiment, the lower threshold comparator is used exclusively for negative pulses of the same amplitude in the synchronization stream; the lower threshold is set below the amplitude of these negative pulses, and the sampling phase rotates back and forth based on the time when the lower comparator stops triggering. In this embodiment, negative pulses can also be Figure 20A shown.

[0191] superior Figure 20A A phase alignment technique is described. While it is possible to use phase alignment commands embedded in the video stream, it is preferred to perform phase alignment using a state machine that monitors the timing of flags in the MFM sequence, without using commands in the video stream; the payload is a dynamically changing parameter. A second preferred technique is described below, in which phase alignment is combined with a search for MFM flags (or other flags) in the control sequence.

[0192] Figure 20B Shown with Figure 17C and Figures 20C-20F The sampling phase adjustment circuit is used in conjunction with the source driver. The input control is the clock period and phase adjustment control, and the sampling_phase output (sampling clock) is sent to each SHA amplifier. Phase rotation (and skipping clock) will affect all samples. Figure 20B As shown, this all happens in the PLL front end. By skipping clock cycles, we can easily change the SHA channel that sees the control information. (Since the sample and hold amplifier / deinterleaver samples a different channel every cycle, the information carried in each channel is rotated once after the clock cycle is skipped). Phase adjustment is accomplished by rotating (selecting) one of the 11 phases of the PLL (only a single phase step is allowed at a time to ensure that there is no flickering clock). The VCO high frequency clock is the clock that produces the sampling clock output after phase adjustment. The input reference clock 170 remains unchanged. The inputs "skip", "adv", and "ret" come from the synchronous state machine in the chip's digital logic, such as Figure 20F shown.

[0193] Figure 20CA special synchronized video pattern is shown to facilitate locking. During synchronization, we use this special video pattern where all video samples in a row (each source driver) are negative constant values ​​942 (the output of the zero-crossing detector 836 is 0), with the exception of the last video sample 944, which is sent as a positive constant value (the output of the zero-crossing detector is 1). Shown is the control data 940 for SHA channel 0 and SH amplifiers 1-15 (Video 0-Video 14). Therefore, using this knowledge, when SHA channel 0 (the control channel) samples the video stream to try to extract the control data, it will know in which direction to adjust the phase in order to sample the control bit at the optimal time. For example, if you sample in data 940 and shift the phase backward, a "1" will appear; if you shift the phase forward, a "0" will appear. Since all SHA channels share the same (relative) timing in terms of sampling phase, this also means that the video samples are optimally sampled (closer to the end of the sample decision time).

[0194] Figure 20D This figure shows an example of missing the MFM flag due to PLL phase wraparound. In this case, clock skipping is necessary. The figure shows 11 sampling phase steps 950, with the optimal step being 952. As shown, the PLL phase rotates from step 10 to step 0, shifting the sampling back to the previously transmitted sample 949. If the currently selected sampling phase is within the CTRL field, a flag (Y) is detected. If it is outside the CTRL field, no flag is seen (N: illegal MFM on the video channel), indicating that we are sampling too late; we can shift the sampling phase forward three steps.

[0195] Figure 20E An example is shown where the MFM flag is lost when the phase exceeds the end of the control bit. Here, the next sample, 942, is entered with samples at steps 9 and 10. In this case, no clock skipping is required; once the MFM flag detection is lost at step 9, we move the phase selection back two steps to the optimal step 7.

[0196] Figure 20F This is a flowchart of the synchronization state machine implemented in the digital logic of the source driver chip, describing how phase alignment is performed through MFM flag search. In the figure, EOL indicates the end of the received display line (a single source driver receives 64 control samples); V = 1 indicates that the zero-crossing detector output = 1, indicating that when the MFM flag disappears, we see the last video sample of the previous line, not the control bit; V = 0 indicates that the zero-crossing detector output = 0, indicating that when the MFM flag disappears, we see the first video sample of the same line, not the control bit; "!" indicates negation, for example, the "! flag" indicates that the flag is not detected.

[0197] In step 974, if no flag is detected and the detector output = 1, go to step 972, as shown in FIG. Figure 20D As shown, because the sampling is too late, it returns to the sample 949 of the previous row. Therefore, step 973 moves the phase forward by three steps. In step 974, if no mark is detected and the detector output = 0, go to step 976, as shown. Figure 20E As shown, the sampling is too early into the next sample 942. Therefore, step 976 shifts the phase back two steps, which will be optimal, and synchronization will be achieved in step 977.

[0198] Once the optimal phase is determined, it can be achieved within the source drivers by sending the output of the sampling phase adjustment circuit as the sampling clock to the SHA amplifiers. Ideally, all amplifiers in all source drivers operate together, meaning there's only one sampling phase alignment circuit and one clock cycle aligned, controlling all SHA amplifiers. Within each source driver, these input SHA amplifiers are time-interleaved and produce sample outputs with a time offset of one Fsavt cycle between adjacent channels. The SHA amplifiers then pass these samples to the collectors (A / B samplers), also with an offset in time. However, after the collectors have collected all samples for a row, the preamplifiers pass all samples together to the next stage (the level shifter). This effectively "wastes" 16 Fsavt cycles of transmission time at the preamplifier outputs, but due to the decimation of the sampling rate, there's enough time to achieve this.

[0199] Other synchronization techniques can also be used. For example, horizontal and vertical synchronization can be achieved by forwarding a low-frequency clock. To phase-adjust the sampling position, another technique is to transmit a known black / white reference in the subband and adjust the receiver's PLL until the blackest black and whitest white are found.

[0200] In another synchronization technique, the reference clock is not just a reference clock; it also includes data (such as parameters), but at a lower frequency. The clock and its parameters are sent over a separate line from the SAVT samples (which already exists). Side channel data does not need to be mixed with the video data, so the SAVT rate is reduced, requiring only 60 * 16 = 960 samples per line, thus reducing the communication bandwidth requirement. Bandwidth requirements are further reduced by using sub-pixel color grouping. This technique also allows for color transition blanking; since the side channel bits are not embedded in the video stream, there is no problem of side channel bits bleeding into the video bits.

[0201] Example source driver

[0202] Figure 21The analog data path for one channel of an example source driver is shown. In this particular example, the source driver drives an LCD display, and the various components shown are specific to that type of display. However, the present invention is also applicable to other types of displays.

[0203] Shown is the input 902 and one of the 16 input distribution amplifiers, in this case SHA[0] 824, shown at 904; not shown are the switches 842 at the input and the other 15 distribution amplifiers that drive the video samples. The input sampling is illustrated by the switches sampling onto the capacitors. The input sampling switches are controlled by the signs of the signals b and t. There are 15 other identical amplifiers (with offset timing) that carry the video, while SHA[0] carries the side channel information. Which SHA channel carries the side channel is arbitrary, but the advantage of using SHA[0] is that the control information arrives before the video samples, rather than after, allowing some time to set up before the control information is needed. The nominal gain of each amplifier 904 is 1, but it may vary.

[0204] Each SHA channel drives 64 columns 920, as indicated by the array symbol [63:0] used in the component designator, through a series of sampling blocks / collectors 908, preamplifiers 910, level shifters 912, HV drivers 914, and column shorting switches 918. Level shifters 912 can also be referred to as differential-to-single-ended converters. Preamplifiers 910 provide the required gain for the signal from the transmission medium.

[0205] Figure 21 Shown in FIG. 1 is one of the 64 A / B sampling capacitor blocks 908 for amplifier 904 and its associated channel preamplifier 910. In one particular embodiment, the timing variations introduced by the deinterleaving process of the input distribution amplifier can be corrected by the timing of the source driver preamplifiers. For example, once all 64 samples arrive at the A or B sampling capacitor block, preamplifier 910 waits 16 clock cycles after the first sample arrives (or until the last sample arrives) and then begins driving all 64 samples to level shifter 912. As a result, all 960 preamplifiers of the source driver will drive samples simultaneously.

[0206] Also shown is one of the channel's 64 level shifters 912, which convert differential signals to single-ended signals, add offset, change signal polarity, and provide amplification. If pol (polarity) = 0, output out_p 913 = vmax + 0.5 * (Vinp - Vinn). If pol = 1, output out_p 913 = vmin - 0.5 * (Vinp - Vinn). A high voltage driver 914 is one of the channel's 64 such drivers, which multiplies the incoming signal to provide the voltage (positive or negative) desired by the display. Column shorting switches 918 provide a short circuit for LCD displays, as is well known in the art. Finally, the desired voltage is output to the column at 920. The preamplifier 910, level shifter 912, and HV driver 914 can be considered as amplifier stages preceding each column, in this case pipeline amplifiers, or simply "amplifiers."

[0207] Figure 14 The switch 842, input amplifier 904, and source driver A / B sampling block 908 may also be referred to as a collector 915 because the collector inputs the incoming serial analog samples and stores (or "collects") them into the sampling block so that the stored analog samples can be output in parallel to the column driver 916 for display as part of a row on the display panel.

[0208] Mobile phone implementation

[0209] Figure 22 is a block diagram illustrating the transmission of analog video samples within a mobile phone. Further details of various techniques are disclosed in U.S. Application No. 18 / 442,447 (docket number HYFYP017), entitled “Video Transmission within Mobile Devices,” which is incorporated by reference. Due to the high refresh rate of 4K smartphone displays, MIPI receivers, SRAM, digital image processing, and the extensive use of analog signals, which require approximately 1,000 digital-to-analog converters, existing displays on existing OLED DDIC devices (such as mobile phones) need to be improved.

[0210] like Figure 22 As shown in Figure 1, the split OLED DDIC structure has the following advantages: it achieves optimal partitioning of DDIC-TCON and DDIC-SD; provides short-distance MIPI transmission from the SoC; optimizes the digital DDIC-TCON for SRAM and image processing; provides a simplified DDIC with full analog; and only requires a small number of digital-to-analog converters to be installed in the DDIC-TCON integrated with the emitter.

[0211] Shown is a mobile phone (or smartphone) 980, which can be any similar handheld mobile device for communication and displaying images or video. Device 980 includes a display panel 982, a conventional mobile SoC 984, an integrated DDIC-TCON (display driver IC - timing controller) and transmitter module 988, and an integrated analog DDIC-SD (DDIC - source driver) and receiver 992. For ease of explanation, mobile SoC 984 and module 988 are shown external to the mobile phone, although they are internal components of the phone.

[0212] The mobile SoC 984 is any standard SoC used in mobile devices and transmits digital video samples to the module 988 via MIPIDSI 986 (Mobile Industry Processor Interface Display Serial Interface), similar to the Vx1 input signal discussed above. The module 988 includes the same transmitter as described above (e.g. Figure 1-4 and Figure 7-10 The DDIC-TCON integrated with the transmitter in the display panel 982 is shown. After reading this disclosure and referring to the preceding figures, one skilled in the art will understand how to implement a transmitter to output any number of analog EM signals 990. In this example, the transmitter outputs 12 pairs of analog EM signals at 380 Msps. The gate driver control signals from module 988 to the gate drivers of the display panel 982 are not shown. Typically, for mobile phones, the DDIC is located at the bottom narrow edge of the phone, while the SoC is approximately in the middle of the device. Therefore, the integrated DDIC-TCON / transmitter is close to the SoC, within approximately 10 cm or less, or even within approximately 1-2 cm or less. Because the transmission frequency of digital data is extremely high, it is advantageous to keep the conductor length as short as possible. For tablets, the distance is approximately 25-30 cm or less.

[0213] These analog signals 990 are received at an integrated analog DDIC-SD and receiver 992. The DDIC-SD receiver 992 receives any number of analog signal pairs and generates voltages for driving the display panel 982, and may be, for example, Figure 5 、 6 , 10, 13 or 17. Advantageously, only a single source driver may be required to drive the display panel 982, and the module 992 does not require any digital-to-analog converter.

[0214] The analog DDIC-SD Rx 992 can be a single integrated circuit containing 12 source drivers (each handling a single pair) or 12 discrete integrated circuits, each of which is a source driver and handles one of the 12 signal pairs. Of course, the number of signal pairs may be reduced, which means that the number of source drivers will also be reduced accordingly.

[0215] Analog video transmission source driver integrated with display panel

[0216] As mentioned above, analog video transmission is used to transmit video information within the display unit to the display panel's source drivers. We further recognized that today's large display architectures consist of large-area active-matrix display pixels. Early display drivers (source and gate) were mounted on the edge of the glass, rather than on the glass itself, providing source and gate driver circuitry. Due to the complexity of high-speed digital circuitry and the large area required for D-to-A conversion, further integration of driver electronics onto the glass has stalled. For example, the digital transmission of the source driver circuitry operates at approximately 3 GHz, which is too high to be integrated onto the glass. We also recognized that to drive a full high-resolution LCD or OLED screen, numerous display drivers must be installed at the edge of the display. A typical driver has approximately 1,000 outputs, so a typical 4K display requires 4,000 x RGB = 12,000 connections, or 12 source drivers. Increasing the panel resolution to 8K increases this number to 24 source drivers. Data rates, synchronization difficulties, and bonding operations make continued progress in this direction difficult.

[0217] Display panels (such as LCD panels) are made of a glass substrate and thin film transistors (TFTs), i.e., field effect transistors, formed by thin film deposition techniques, formed on the glass substrate. These TFTs are used to implement the pixels of the display. It is therefore recognized that these TFTs (along with appropriate capacitors and resistors and other appropriate analog components) can also be used to create logic circuits to implement the elements of the novel source driver described herein, which are then integrated with the glass. These elements are integrated at the very edge of the glass, just outside the pixel display area, but within the peripheral seal of the glass. Therefore, the source driver disclosed herein can be integrated with the glass using these transistors, capacitors, resistors and other required analog components, and can do so in the embodiments described below. Therefore, the source driver (or its elements) that were previously located outside and at the edge of the display panel glass are now moved to the display panel glass itself. In addition, the gate driver function of the gate driver can also be moved to the display panel glass.

[0218] Unlike the existing Vx1 interface, the SAVT video signal can be transmitted along the edge of the display glass using relatively simple wiring and is less sensitive to interference. Due to the lower sampling rate, the required analog electronics for the source driver can be designed on the edge of the TFT panel on the display panel glass itself (less complex). Building the source driver circuit on the edge of the glass integrates the following elements of the source driver with the glass and their typical functions: input terminals and switches (receive analog samples via SAVT signals and distribute them to collectors); collectors (receive analog samples via input amplifiers and collect samples into a storage array or row buffer); level converters (convert to single-ended, provide voltage inversion and voltage offset), and amplifiers such as high-voltage drivers (provide the amplified voltage and current required to charge the display source line capacitance).

[0219] Figure 23 Implementations of the integration of the source driver functionality in different embodiments are shown. Depending on the quality of the transistors used on the glass, the various elements of the source driver can be integrated with the glass. It is well known that (for example) TFTs have gone from handling lower frequencies to higher frequencies. There are three main technologies used to manufacture TFTs: amorphous silicon (a-Si); oxides (indium gallium zinc oxide ("IGZO" or similar materials), which can conventionally handle frequencies from 50kHz to 100kHz, up to about 200kHz depending on the voltage used (for some components, oxides can reach frequencies of 1MHz at 50 volts); and low temperature polysilicon (LTPS), which can handle frequencies on the order of about 5MHz, up to more than 10MHz depending on the voltage used. In addition, crystalline silicon TFTs implemented using CMOS technology can handle higher frequencies. Other types of TFTs can also be used.

[0220] If faster, higher-quality TFT transistors are used, the high-frequency portion of the source driver can be integrated with the glass. Furthermore, the smaller the device size, the faster the transistors can switch, allowing components using these devices to be implemented on glass. For example, the channel length of the TFT affects its size; oxide TFTs preferably have a channel length less than approximately 0.2 μm, and LTPS TFTs preferably have a channel length less than approximately 0.5 μm. Reducing the channel length by 50% can increase the speed by a factor of four. Furthermore, implementation may depend on the type of display; smaller resolutions of 2K, 1K, and smaller display sizes can use components that do not require the high frequencies of 4K and 8K displays. Typically, amorphous silicon transistors are not used because they are prone to threshold shift and instability. Note that the source driver disclosed herein does not require any digital-to-analog converters to convert the video samples, nor does it require any decoders to decode the incoming video samples.

[0221] In the first embodiment 102, the level shifter 620 and amplifier 621 are integrated with the glass because the level shifter only requires a relatively low-frequency clock. Since the level shifter switches once per row, the switching frequency is approximately 50kHz for a 2K display and approximately 100kHz for a 4K display. Therefore, the integrated first embodiment can use TFTs with a clock frequency of at least approximately 50kHz, assuming a 2K panel (100kHz for a 4K panel, etc.). Therefore, IGZO or LTPS TFTs can be used in the first embodiment.

[0222] In the second embodiment 104 using faster transistors, the level shifter 620, amplifier 621, and collector 786 can also be integrated with the glass, thereby integrating the entire source driver. The collector 786 requires a higher frequency clock because each collector operates a sequence of pixels, and for a 2K display, a switching frequency of approximately 50 MHz is required, for a 4K display, a switching frequency of 100 MHz is required, and so on. Therefore, the second integrated embodiment can use TFTs that operate at a clock frequency of at least approximately 50 MHz, assuming a 2K panel. Therefore, LTPS TFTs can be used for 2K panels in the second embodiment.

[0223] Figure 24A The arrangement of the gate driver and source driver on the display panel glass is shown. Typically, the display panel is implemented with two glass substrates, top glass (or ordinary glass) and bottom glass (or active glass), with the bottom glass being smaller than the top glass. The TFT is implemented on the bottom glass, and the following description refers to this bottom glass, only the bottom glass is shown in the figure. The figure shows the display panel glass 150 itself (for clarity, the panel frame or packaged display unit is not shown), with two rectangular areas 130 and 132 on either side of the display panel glass (in this case, the LCD panel), with a width of several millimeters. In this embodiment, the gate driver is also integrated using TFT devices on the glass as switching elements. Since the gate driver is usually implemented as a simple shift register, these shift registers can be located in area 130 or 132.

[0224] Also shown is a rectangular area 140, also located on the glass itself, where the components of the source driver can be located. By using TFT switches on the glass in this area 140, the source driver functionality can be partially or fully integrated with the glass. In the first embodiment, the amplifier and level shifter are integrated on the glass (formed in area 140), while in the second embodiment, the amplifier, level shifter, and collector are integrated (also formed in area 140).

[0225] Because the source drivers disclosed herein do not receive digital signals, lack D-to-A converters and associated circuitry for processing digital video samples, and lack decoders, these drivers operate at lower processing frequencies and are smaller, allowing them to be integrated onto glass. Thus, for example, since a typical 64-inch 4K TV panel has a pixel width of 80 microns (40 microns in the case of an 8K display), there is also sufficient width to integrate the driver directly onto the glass, as the output amplifier size is expected to fit within this space. Depending on the pixel width of a particular implementation, the specific TFT can be selected.

[0226] Interconnect printed circuit board 182 receives EM signal 602 and passes it via flexible PCB 184 to source drivers located on integrated circuit 186a, which are partially integrated with the glass in TFT 186b. Because a portion of each source driver (at least the collector) remains on flexible PCB 184 on IC 186a, while the level shifter and amplifier are located on the glass in TFT 186b, this method of passing EM signals is implemented for Example 1. As shown, each integrated circuit 186a passes analog signal 187 to the corresponding circuit on glass 186b. The nature of these analog signals depends on whether Example 1 or Example 2 is being implemented. The implementation of Example 2 is shown below. Gate clocks 190 and 192 are transmitted to the gate drivers via circuit board 182 and flexible PCB 184. PCB 184 is attached to panel glass 150, as is known in the art.

[0227] Figure 24B A source driver 186 is shown implemented entirely on glass. This second embodiment fully integrates the source driver functionality with the glass. As shown, the flexible PCB 184 includes only the EM signals 602 and not the source driver functionality such as the collector, level shifters, and amplifiers; all source driver functionality is implemented in the TFTs (and other analog components) on the glass at 186. Although not shown, each additional source driver may have its own PCB 184 and EM signals 602 (from the corresponding emitter); in one particular embodiment, there are 24 such source drivers.

[0228] Figure 25 Another embodiment of placing the EM signal 602 when implementing embodiment 2 is shown. As previously mentioned, in embodiment 2, all functions of the source driver are integrated with the glass, so there is no need for Figure 7As shown in Figures 7A and 7B, EM signal 602 is transmitted through a large printed circuit board 182 (the length of the display) and then through many flexible PCBs 184. Therefore, a much smaller printed circuit board 183 and a single flexible PCB 185 are attached to the display panel glass 150 at one location. EM signal 602 is transmitted to the glass via 183 and 185 and then along the glass, where it is transmitted to each source driver 186 on the glass within area 140. Furthermore, the integrated circuit 186 is not required on the flexible PCBs because all functions for each source driver are now on the glass. As shown, EM signal 602 is transmitted in parallel to each source driver.

[0229] Now back Figure 21 While the source driver of the example is shown, it is noted that in many other embodiments, portions of the source driver can be implemented on the glass. For example, only the high-voltage driver 914 (and optional column short 918) can be implemented on the glass in area 186b, while the remaining components are shown implemented on integrated circuit 186a outside the glass edge. Alternatively, the driver 914 and level shifter 912 are implemented on the glass, while the remaining upstream components are implemented outside the glass edge. Alternatively, the driver 914, level shifter 912, and preamplifier 910 are implemented on the glass, while the remaining upstream components are implemented outside the glass edge. Alternatively, the driver 914, level shifter 912, preamplifier 910, and A / B sampling block 908 are implemented on the glass, while the remaining upstream components are implemented outside the glass edge. Alternatively, the driver 914, level shifter 912, preamplifier 910, A / B sampling block 908, and input distribution amplifier 904 are implemented on the glass, while the remaining upstream components are implemented outside the glass edge. Alternatively, all components shown (including the input terminal 902 and its switch 842) are implemented entirely on the glass, and no source driver components are implemented on the flexible PCB 184, such as Figure 24B shown.

[0230] Alternatively, all column drivers 916 of the source driver can be implemented on the glass, while the remaining upstream components (i.e., collector 915) can be implemented outside the edge of the glass. Alternatively, all column drivers 916 and collector 915 of the source driver can be implemented on the glass, while no components of the source driver are implemented on the flexible PCB 184, such as Figure 24B shown.

[0231] In one particular embodiment, the SHA input amplifier operates at an input rate of approximately 664 MHz, the A / B sampling block operates at 1 / 16 of the input rate, and the preamplifier and downstream components operate at 1 / 1024 of the input rate (1 / 64 of 1 / 16 of the input rate). Of course, the input rate may be different, and the fraction of the input rate at which the downstream components operate may also be different, depending on the implementation, the number of columns, the interleaving technique used, etc. In another embodiment, since the output of the level shifter 912 is single-ended (making implementation easier), only the HV driver is implemented on the glass. Alternatively, the preamplifier, level shifter, and HV driver can be implemented on the glass because they require lower frequencies than the SHA amplifier and A / B block. Alternatively, only the SHA amplifier 904 can be implemented in the source driver chip, and all other downstream components can be implemented on the glass because amplifier 904 operates at the highest frequency.

[0232] Improving the video image through feedback from the display's column amplifiers

[0233] Figure 1 An example display panel with (typically) 24 novel source drivers 186 is shown, Figure 13 is an embodiment of a SAVT receiver with integrated source driver; Figure 21 It is shown in more detail how the 64 columns 920 of the source driver are driven, starting from a sample input at 902. Unfortunately, manufacturing variations between display panels and their source drivers can cause the 23,000 (for example) column amplifiers (and the associated analog circuitry preceding them) to produce different output levels when driven with the same input.

[0234] We disclose a technique for compensating for this variation by sending appropriate feedback to the display unit's timing controller (TCON). Thus, the present invention allows 24 (or more) demultiplexer / source driver chips to feed back the levels of a single column amplifier to the TCON. After collecting performance information for all 23,000 column amplifiers, the TCON can prescale the values ​​used for a given column to equalize performance across columns. Advantageously, the present invention does not require high-speed performance, making it suitable for pre-sale screen calibration. In other words, the technique can be used during production test, where all columns are available and driver characteristics can be measured without incurring additional area penalties on the chip (due to the area overhead for sampling each column). This prescaling based on individual column feedback is in addition to any prescaling performed by the TCON to equalize performance across different rows in the display; rows farther from the column driver may require additional current to achieve the same light output.

[0235] There are two main implementations: analog feedback and digital feedback. Both can use interfaces such as JTAG, I2C, or SPI, so that the TCON can issue a command to a specific column driver to send back the value of its column amplifier output. This command can also be issued through the MFM command mentioned above. In the analog version, the value is sampled onto the analog bus (a single analog connector back to the TCON) through an analog switch and shared by all source driver chips. The TCON then performs analog-to-digital conversion (ADC) and digital processing on the result. Since the output of the source driver is high voltage, multiplexing requires the use of high-voltage transistors or generating a low-voltage representation of the column voltage before multiplexing (done with a resistor or capacitor divider). In either case, each column requires area overhead.

[0236] Figure 26 An analog structure 1010 for issuing commands and receiving feedback is shown. The novel pre-scaling control unit 1020 of the TCON 130 uses a protocol and communication line such as JTAG, I2C, or SPI 1022 (or similar) to send a command to a specific column driver (such as driver 916) in any source driver 186 to sample the analog value output by the amplifier in the HV driver 914. Once sampled, the value is returned to the ADC 1032 in the TCON via a single analog bus 1024. The converted digital value is sent to the control unit 1020, which collects all the values ​​from all column amplifiers in a similar manner, processes all the values, determines how to pre-scale each value to equalize them, and outputs the results to the pre-scale value memory 1034, which stores the actual value, offset value, percentage, ratio, etc. for each column. The value 1034 is then used during operation of the display (and any other pre-scaling) to modify the samples sent from the TCON to the display, as is well known in the art.

[0237] Figure 27 shows the sampled values ​​from the column amplifier. Shown is a particular column (in this case, Figure 21 Column 63 of SHA[0] in FIG. 1 shows an HV driver 914 that provides the output of its internal amplifier 1040 to an analog switch 1042. The output of the switch is connected to the analog bus 1024 to feed the column output back to the TCON. Commands arrive via a control signal 1041 (i.e., using JTAG, I2C, SPI, etc.), which samples the value. Switch 1042 is an example; other types of analog switches (e.g., using FETs) and other similar sampling circuits can also be used.

[0238] In the digital version, each source driver chip has its own A-to-D converter, so the column amplifier sampling can be done locally (thereby avoiding any loading effects of the long analog return path) and the digital value can be returned to the TCON via the same JTAG, I2C, or SPI path as the command.

[0239] Figure 28 A digital structure 1050 for issuing commands and receiving feedback is shown. The novel pre-scaling control unit 1020 of the TCON 130 uses a protocol and communication line such as JTAG, I2C, or SPI 1052 (or similar) to send a command to a specific column driver (such as driver 916) in any source driver 186 to sample the analog value output of its amplifier in the HV driver 914. Once sampled and converted, the digital value is also returned to the control unit 1020 in the TCON via line 1052. In a similar manner, the control unit 1020 collects all the values ​​from all column amplifiers, processes all the values, determines how to pre-scale each value to equalize them, and outputs the results to the pre-scale value memory 1034, which stores the actual value, offset, percentage, ratio, etc. for each column. The value 1034 is then used during operation of the display (and any other pre-scaling) to modify the samples sent from the TCON to the display, as is well known in the art.

[0240] Figure 29 The values ​​sampled from the column amplifier are shown. The figure shows a particular column (in this case, Figure 21 63) of SHA[0] in FIG. 1 , which provides the output of its internal amplifier 1040 to an analog switch 1042, which can be implemented and controlled as described above. Each source driver includes an ADC 1060 for converting the analog value of each column amplifier to a digital value to be sent back to the TCON. Each HV driver can also use one or more ADCs (if the column voltage drops low enough to not damage the ADC input circuitry). The result is simple on-screen metering. The display can be self-calibrated after manufacturing (pre-sale during production test), recalibrated on user command, or at other times. The ability to recalibrate after sale is an advantage over having additional hardware installed on the chip rather than performing calibration during production test.

[0241] In another embodiment, we model how a pixel's performance varies with its neighboring pixels (e.g., pixels in the same column). We use this model to pre-scale the subpixel inputs before sending them to the source driver chip to produce the desired brightness. Typically, it's difficult to report the light output of each subpixel; such measurements require a complex test setup. Instead, we measure the current through each subpixel at specific input values ​​and use this measured current as a proxy for the emitted light to model the performance of the pixel (or subpixel).

[0242] In one variation, we use real-screen metrology to model the display's performance, specifically how adjacent subpixel values ​​affect brightness (due to slew rate issues, etc.) We then use this model to pre-scale the subpixel inputs before sending them to the source driver chip to produce the desired brightness.

[0243] Transmitting video signals in other environments

[0244] Described above are embodiments for transmitting video signals to a display panel and within a display unit. The present invention also includes embodiments for transmitting video signals using SAVT in other environments, such as transmitting video signals directly from a camera or other image sensor, from an SoC or other processor, and embodiments for receiving SAVT signals at a SAVT receiver that is not necessarily integrated with the display panel (as described above), such as at an SoC, a computer's processor, or a SAVT receiver that is not integrated within a conventional display panel. U.S. patent application Ser. Nos. 63 / 611,274 and 63 / 625,473 (HYFYP017P2 and HYFYP018P), incorporated by reference above, disclose examples of such other environments, respectively within a mobile device and within a vehicle.

[0245] Figure 30 A SAVT transmitter 1240 is shown which is arranged to transmit various video samples from various sources. Shown is a distributor 1241 which comprises two line buffers 1242 and 1243 with input vectors, a distributor controller 1230, optional digital to analog converters 1260-1269 and analog EM signals 1270-1279 output from each input vector and which can be used as Figure 2 Although outputs 1281 and 1291 represent serial outputs, the outputs can be Figure 2 As described above, in one embodiment, all samples can be output from the first buffer to the second buffer in parallel. Figure 2As shown, each DAC (if present) converts the samples it receives from the digital domain into a single analog level (or outputs the analog level from the line buffer if no DAC is present), which can be transmitted as a differential pair of voltage signals with amplitudes proportional to their incoming digital values. The analog levels are transmitted serially when output from each DAC. Image processors 250-259, although not shown, may optionally be present depending on the implementation and may be present after the buffer or, preferably, before the buffer.

[0246] In this example, there are multiple EM paths; there may be only a single EM path or there may be multiple EM paths. Depending on implementation and design decisions, multiplexing may improve performance but require more paths. To minimize the number of wires in the transmitter 1240, only a single path carrying a single EM signal 1270 may be used. The SAVT transmitter 1240 may be substantially as described with respect to FIG. Figure 2 The transmitter is implemented as described above, but the inputs may vary, an image processor is not necessarily required (it can be implemented downstream in an SoC or other processor), and a DAC is optional. Furthermore, the number of input vectors per line buffer and the number of samples per input vector, N, can vary significantly depending on the implementation, the type of input signal, the required bandwidth, whether the transmitter is located at the camera, implemented on an SoC or other processor, etc. Furthermore, to minimize the wiring of the transmitter 1240, only a single path carrying a single EM signal 270 can be used.

[0247] Depending on the specific embodiment discussed below, the input can be analog RGGB video samples 1239a, analog or digital RGB samples 1239b, digital G samples 1239c, or analog BGBG...RGRG samples 1239d. For digital samples, DACs 1260-1269 are used. In general, the transmitter can accept analog or digital video samples from any color space, not just RGB. Samples can arrive serially, for example, R, then G, then B, or in parallel, with RGB transmitted as three separate signals. Using distributor 1241, the samples can be reordered as needed.

[0248] As mentioned previously, the inputs may vary depending on the implementation. The source of the input 1239d is as follows. The image sensor may output raw analog samples without the use of an ADC or "demosaicing" using interpolation. Thus, the output of the image sensor is a continuous serial stream of analog video samples arranged in time order, with each sample representing a pixel in a row, from left to right, in row major order (for example), one frame after another, as long as the image sensor is sensing. Of course, different orderings may be used. When Bayer filtering is used, the samples are output in rows of BGBG..., followed by rows of RRGG..., commonly referred to as an RGGB format because each 2x2 pattern includes one RGGB. These rows 1239d of analog video samples are input to the SAVT transmitter 1240 for transmission as EM signals 1270-1279 to the Figure 31 The SAVT receiver then serially outputs 1360. Since these samples are still raw data from the image sensor (i.e., the Bayer filter output from the sensor), the ISP uses a downstream ADC (if needed) to perform "demosaicing" and interpolate the "missing" color values ​​at each location to create RGB samples for each pixel.

[0249] The source of input 1239c is as follows. The raw analog samples from the image sensor are converted to digital in the ADC and then "demosaiced" in the image signal processor (ISP) to obtain digital RGB samples for each pixel. Only the green channel of each RGB sample set for each pixel (i.e., one G sample per element of the array) is selected and sent to become input 1239c. The rows 1239c of these G digital video samples are input to the SAVT transmitter 1240 and transmitted as EM signals 1270-1279 to Figure 31 The SAVT receiver then serially outputs the image from the SAVT receiver. This significantly reduces image latency on any display, providing instant feedback to the viewer and is suitable for applications using near-eye displays such as virtual reality and augmented reality.

[0250] Additionally, since only the green channel is sent, interpolation only needs to be performed on the R and B elements of the sensor to obtain its G samples; no interpolation is required at the G elements because the G samples already exist and no R and B samples are needed on these G elements, making interpolation simpler and faster. Since the green channel corresponds to the luminance (or "luma") channel, there is no loss of perceived resolution, although any downstream display will display a monochrome image.

[0251] The source of input 1239a is as follows. Modify the readout of the image sensor to read out at least two rows simultaneously. For example, read out the first two rows from the bottom of the image sensor simultaneously and output a serial stream of values, such as BGRGBGRG... or GBGRGBGR... . Thus, the readout order is: first read out the blue value from the first row, then read out the green and red values ​​from the second row, then read out the green value from the first row, and so on, to obtain the serial output BGRGBGRG. Alternatively, another readout order is: first read out the green value from the second row, then read out the blue and green values ​​from the first row, then read out the red value from the second row, and so on, to obtain the serial output GBGRGBGR. Other readout orders can also be used to mix the color values ​​of two adjacent rows together, and the order of the pixel values ​​can change depending on whether a particular row starts with a red, green, or blue value.

[0252] Since two rows are read out at a time, each set of four values ​​in those two rows (for example, BG at the beginning of the first row and GR at the beginning of the second row, which is two Gs, one R, and one B) can be serially output, resulting in a serial pattern such as BGRG... or GBGR... as shown. After the first two rows are read out, the next two rows are read out, and so on. Similar outputs are possible, where each set of four values ​​includes two green values, one red value, and one blue value. The image sensor can be read from any corner, from top to bottom or bottom to top, by row or column, or in other similar ways. Therefore, the output of the video source is a series of values: BGRGBGRG... or GBGRGBGR, or similar. This series of values ​​can then be used in the analog domain within the SoC for demosaicing, without converting them to digital or performing any digital processing.

[0253] This color value ordering facilitates interpolation in the analog domain. Other color spaces can also be used, reading out two or more lines at a time and mixing the color values ​​of different lines in the serial output, which also facilitates color interpolation in the analog domain. Then, video sources including image sensors will output patterns such as BGRGBGRG... or GBGRGBGR, such as Figure 30 . . 1239a. These RGGB video samples are serially input to the transmitter 1240 and then transmitted as EM signals 1270-1279 to the Figure 31 The SAVT receiver in the system is then serially output from the SAVT receiver.

[0254] The source of input 1239b is as follows. Figure 2 As shown, digital RGB samples can be input; Figure 30As shown, analog RGB samples 1239b may also be input. These analog RGB samples may come from a processor that has performed analog domain demosaicing on the raw image sensor output, from a processor that has received digital RGB samples and converted them to analog RGB samples, or from some other method. These analog RGB video samples are input to the transmitter 1240 and then transmitted as EM signals 1270-1279 to the Figure 31 The SAVT receiver in the system is then serially output from the SAVT receiver.

[0255] Figure 31 A SAVT receiver 1300 is shown located at a SoC, processor, conventional display, or other location. The receiver receives any number of EM signals 1270-1279 and inputs these signals into a collector 1320 having two line buffers 1301 and 1302. Figure 30 Similar to the allocator for the SAVT transmitter in FIG. 1 , each row buffer has an arbitrary number of output vectors 1304, 1306, 1308 (or 1314, 1316, 1318), each vector containing an arbitrary number of video samples corresponding to an input vector (e.g., N = 1024). During operation, each output vector 1304-1308 of the first row buffer 1301 is filled with samples from its corresponding EM signal 1270-1279. As buffer 1301 outputs its samples (via outputs 1305, 1307, 1309) to receiver output 1360, the second row buffer 1302 is filled with samples from the corresponding EM signal 1270-1279. Once the first row buffer is empty, it begins to refill while the second row buffer outputs to receiver output 1360.

[0256] and Figure 30 As with the SAVT transmitter in

[13] , two row buffers are preferred, but more can be used if necessary, and the buffer lengths can be adjusted as described above. In the case of collector 1320, the output is serial, but the output of each buffer may be parallel (i.e., all N samples from each output vector are output at a time), and the output time for each sample may be longer than the input sample time. Therefore, if 100 samples are output at a time, the transfer speed to the output is 100 times slower than the input sample speed (assuming the input samples are one at a time).

[0257] The collector controller 1330 orders the loading of samples from the inputs 1270 ... 1279 and controls the timing for unloading samples for further processing. Since the input stream is continuous, the collector controller loads samples into one row buffer while simultaneously transferring samples from other row buffers to the output for further processing.

[0258] The figure shows the Figure 30 The discussed embodiments are used in conjunction with an embodiment of a receiver in which the rows of the image sensor are serially output, sent to the collector 1320 via the SAVT transmitter 1240 (using input 1239d, i.e., BG...RG...), and then serially output from the collector in the same format as the input, i.e., BG.RG.... Upon output, the samples are sent for further processing or display. As previously mentioned, if parallel input to the processor is required, the collector output can be parallel. Regardless of the arrangement used in the corresponding SAVT transmitter to distribute the incoming samples into the row buffers, the SAVT receiver uses the inverse arrangement so that the receiver output 1360 outputs the samples in the order received at the SAVT transmitter (i.e., the order received at 1239d).

[0259] Although the SAVT receiver 1300 shows only BG....RG... outputs, it can also receive and output using Figure 30 . Thus, if input 1239a is input to a SAVT transmitter, then output 1360 is RGGB... samples; if input 1239c is input to a SAVT transmitter, then output 1360 is G... samples. If input 1239b is input to a SAVT transmitter, then output 1360 is RGB... samples.

[0260] Since the output 1360 is analog samples, the samples can be converted to digital if necessary using one or more ADCs 1362. Thus, each output vector can be output one sample at a time through an analog-to-digital converter (ADC) 1362 to provide a continuous stream 1364 of digital samples.

[0261] Other embodiments

[0262] The present invention includes these additional embodiments.

[0263] C1. A device integrating a DDIC-TCON (display driver integrated circuit-timing controller) with a transmitter, the device comprising:

[0264] a distributor arranged to receive a plurality of streams of digital video samples originating from a system-on-chip of a mobile phone and to distribute said digital video samples into a plurality of input vectors according to a predetermined arrangement;

[0265] a plurality of digital-to-analog converters (DACs), each DAC being arranged to receive the digital video samples from the input vector, convert the digital video samples into a series of analog video samples, and output the series of analog video samples to a display panel of the mobile phone via an electromagnetic path; and

[0266] The gate driver control signal is output to the gate driver of the display panel.

[0267] C2. The transmitter as described in claim C1, wherein the distributor further comprises

[0268] storing a first row buffer of the plurality of input vectors; and

[0269] a second row buffer storing a plurality of second input vectors, wherein the distributor is further arranged to distribute rows of the digital video samples alternately between the input vectors of the first row buffer and the second input vectors of the second row buffer, and wherein the image processor alternately reads from the first row buffer when the distributor writes to the second row buffer and reads from the second row buffer when the distributor writes to the first row buffer.

[0270] C3. A transmitter as described in claim C1, wherein the digital video samples assigned to the input vector constitute rows of an image.

[0271] C4. The transmitter of claim C1, wherein the digital video samples are distributed among the input vectors at a first frequency, and wherein the digital video samples are serially output from each of the input vectors at a second frequency different from the first frequency.

[0272] C8. An integrated transmitter and timing controller as described in claim C1, wherein the device is located within about 2 centimeters of the system-on-chip.

[0273] C9. The apparatus of claim C1, wherein the apparatus is integrated into a single integrated circuit of the mobile phone.

[0274] C10. The transmitter of claim C9, wherein the device is further integrated with the system-on-chip of the mobile phone.

[0275] C11. The apparatus of claim C1, further comprising:

[0276] A plurality of image processors are each arranged to serially read the digital video samples of one of the input vectors and to perform at least gamma correction on the digital video samples of the one input vector.

[0277] D1. Analog DDIC-SD (Display Driver Integrated Circuit - Source Driver) for mobile phones, including:

[0278] an input terminal arranged to receive an analog EM signal via an electromagnetic path, the signal comprising a series of consecutive analog video samples;

[0279] a plurality of sampling amplifiers, each sampling amplifier arranged to specifically sample a portion of the analog video sample and write the portion of the analog video sample to a location in a memory array designated for the each sampling amplifier; and

[0280] a plurality of column drivers, each column driver being arranged to read one of the analog video samples from one of the locations in the storage array, amplify the one of the analog video samples, and drive the one of the amplified analog video samples into a column of a display panel of the mobile phone.

[0281] D2. The analog DDIC-SD of claim D1 further comprising a second memory array having a location designated for each sampling amplifier, wherein the sampling amplifiers are further arranged to alternately write the portions of the analog video samples to the memory array or the second memory array, and wherein the column drivers alternately read from the memory array when the sampling amplifiers write to the second memory array and read from the second memory array when the sampling amplifiers write to the memory array.

[0282] D3. The analog DDIC-SD according to claim D2 further comprises:

[0283] Control logic circuitry is arranged to enable each of the sampling amplifiers to sample the portion of the analog video sample, enable the sampling amplifier to write to the memory array or the second memory array, and enable the column driver to read from the memory array or the second memory array.

[0284] D3. The analog DDIC-SD of claim D1, wherein a portion of the analog video samples are used for synchronization and are not driven into columns of the display panel.

[0285] D4. The analog DDIC-SD of claim D1, wherein the analog DDIC-SD does not include any digital-to-analog converter (DAC) for converting video samples.

[0286] D5. The emulated DDIC-SD of claim D2, wherein the column driver is further arranged to read in parallel from the memory array when the memory array is full, or to read in parallel from the second memory array when the second memory array is full.

[0287] D6. The analog DDIC-SD of claim D1, wherein the series of analog video samples arrive in a predetermined arrangement that determines that each sampling amplifier outputs its respective portion of the analog video samples to consecutive memory locations in the memory array.

[0288] D7. The analog DDIC-SD of claim D1, wherein the electromagnetic signal includes a control signal for synchronization and is not driven to the columns of the display panel, and the source driver further comprises:

[0289] The sample amplifier is specially used to sample the control signal.

[0290] F1. A video transmission device comprising:

[0291] Transmitter, including

[0292] a distributor arranged to receive a stream of digital video samples from a system on a chip of a mobile phone and distribute the digital video samples into a plurality of input vectors in a row buffer according to a predetermined arrangement, and a digital-to-analog converter (DAC) per input vector, each DAC arranged to serially receive the digital video samples from its respective input vector and convert the digital video samples into a series of analog video samples;

[0293] a plurality of electromagnetic pathways, each electromagnetic pathway arranged to transmit one of the series of analog video samples to a display panel of the mobile phone; and

[0294] A source driver array includes a source driver corresponding to each of the DACs, each source driver including:

[0295] a collector arranged to receive the series of analog video samples from each DAC and store the analog video samples of the corresponding input vector; and

[0296] A plurality of column drivers are arranged to receive the stored analog video samples from the collector in parallel and amplify each of the stored analog video samples onto a column of the display panel.

[0297] F2. The apparatus of claim F1, wherein the transmitter is integrated with a DDIC-TCON, the apparatus further comprising:

[0298] The gate driver control signal is output to the gate driver of the display panel.

[0299] F3. An apparatus as described in claim F2, wherein the transmitter is located within approximately 2 centimeters of the system-on-chip.

[0300] F4. The apparatus of claim F2, wherein the transmitter is integrated into a single integrated circuit of the mobile phone.

[0301] F5. The apparatus of claim F2, wherein the transmitter is further integrated with a system-on-chip of the mobile phone.

[0302] F6. The apparatus of claim F1, wherein each source driver is an analog DDIC-SD (display driver integrated circuit - source driver) of a mobile phone.

[0303] F7. An apparatus as described in claim F6, wherein the analog DDIC-SD does not include any digital-to-analog converter (DAC) for converting video samples.

[0304] I1. A source driver for a display unit, comprising:

[0305] an input terminal for receiving analog sample values ​​representing a video stream;

[0306] a collector arranged to receive the analog sample values ​​from the input terminal, store the analog sample values ​​in a storage array, and output the analog sample values ​​in parallel, the input terminal and the collector being implemented outside an edge of a display panel of the display unit; and

[0307] A plurality of column drivers are configured to input the analog sample values ​​in parallel and output voltages to columns of the display panel, wherein the plurality of column drivers are implemented using at least transistors on a glass substrate of the display panel.

[0308] I2. A source driver as described in claim I1, wherein the analog sample value is an ordered sequence of continuous amplitude analog levels.

[0309] I3. The source driver as described in claim 11, wherein the plurality of column drivers are located on the glass substrate of the display panel, between a pixel display area and a periphery of the glass substrate.

[0310] I4. A source driver as described in claim I1, wherein the source driver does not include a digital-to-analog converter for converting video samples.

[0311] I5. A source driver as described in claim I1, wherein the transistor is capable of operating at a clock frequency required by the column driver.

[0312] I6. A source driver as described in claim 15, wherein the transistor is a thin film transistor (TFT) and is a low temperature polysilicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

[0313] I7. A source driver as described in claim I1, wherein the pixels of the display panel are implemented using the same type of transistors as used to implement the column driver.

[0314] I8. The source driver as claimed in claim 11, wherein the display unit is a display of a mobile phone.

[0315] I9. A source driver as described in claim I1, wherein each of the column drivers includes a high-voltage driver.

[0316] I10. The source driver of claim 19, wherein each of the column drivers further comprises a level shifter, each level shifter operative at least to shift an output voltage of the column driver.

[0317] I11. The source driver as described in claim I1, wherein the collector is a two-stage collector.

[0318] J1. A source driver for a display unit, comprising:

[0319] an input terminal for receiving analog sample values ​​representing a video stream;

[0320] a collector arranged to receive the analog sample values ​​from the input, store the analog sample values ​​in a storage array, and output the analog sample values ​​in parallel; and

[0321] A plurality of column drivers are configured to input the analog sample values ​​in parallel and output voltages to columns of the display panel, wherein the collector and the plurality of column drivers are implemented using at least transistors on a glass substrate of the display panel.

[0322] J2. A source driver as described in claim J1, wherein the analog sample value is an ordered sequence of continuous amplitude analog levels.

[0323] J3. The source driver of claim J1, wherein the collector and the plurality of column drivers are located on the glass substrate of the display panel, between a pixel display area and a periphery of the glass substrate.

[0324] J4. The source driver of claim J1, wherein the source driver does not include a digital-to-analog converter for converting video samples.

[0325] J5. The source driver of claim J1, wherein the transistor is operable at a first clock frequency required by the column driver and a second clock frequency required by the collector.

[0326] J6. The source driver as described in claim J5, wherein the transistor is a thin film transistor (TFT) and is a low temperature polysilicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

[0327] J7. A source driver as described in claim J1, wherein the pixels of the display panel are implemented using the same type of transistors as used to implement the collector and the column driver.

[0328] J8. The source driver as described in claim J1, wherein the display unit is a display of a mobile phone.

[0329] J9. A source driver as described in claim J1, wherein each of the column drivers includes a high-voltage driver.

[0330] J10. The source driver of claim J9, wherein each of the column drivers further comprises a level shifter, each level shifter operative at least to shift the output voltage of the column driver.

[0331] J11. The source driver as claimed in claim J1, wherein the input terminal is implemented outside an edge of a display panel of the display unit.

[0332] J12. The source driver as described in claim J1, wherein the input terminal is implemented on a glass substrate of the display panel.

[0333] J13. The source driver of claim J1, wherein the collector is a two-stage collector.

[0334] K1. A display unit comprising:

[0335] a display panel having a glass substrate; and

[0336] Multiple source drivers, each source driver includes

[0337] a collector arranged to receive analog sample values ​​representing a video stream, store the analog sample values ​​in a storage array, and output the analog sample values ​​in parallel; and

[0338] A plurality of column drivers input the analog sample values ​​in parallel and output voltages to columns of the display panel.

[0339] K2. A display unit as described in claim K1, wherein the collector of each source driver is implemented outside the edge of the display panel of the display unit, wherein the column driver is implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at a clock frequency required by the column driver.

[0340] K3. A display unit as described in claim K1, wherein the collector and the column driver of each source driver are implemented using at least transistors on the glass substrate of the display panel, and wherein the transistors are capable of operating at a clock frequency required by the collector and the column driver.

[0341] K4. A display unit as described in claim K1, wherein the analog sample value is an ordered sequence of continuous amplitude analog levels.

[0342] K5. The display unit as described in claim K2, wherein the plurality of column drivers of each of the source drivers are located on the glass substrate of the display panel, between a pixel display area and a periphery of the glass substrate.

[0343] K6. A display unit as described in claim K1, wherein each source driver does not include a digital-to-analog converter for converting video samples.

[0344] K7. The display unit according to claim K2, wherein the transistor is a thin film transistor (TFT) and is a low temperature polysilicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

[0345] K8. The display unit according to claim K3, wherein the transistor is a thin film transistor (TFT) and is a low temperature polysilicon (LTPS) transistor or an indium gallium zinc oxide (IGZO) transistor.

[0346] K9. The display unit as claimed in claim K1, wherein the display unit is a display of a mobile phone.

[0347] K10. The source driver as described in claim K1, wherein each collector of each source driver is a two-stage collector.

[0348] P1. A feedback device for a source driver of a display unit, the feedback device comprising:

[0349] an analog switch having an input connected to an output of an amplifier of a column driver of a display panel of the display unit, a control input arranged to receive a control signal from a timing controller of the display unit, and an output connected to an analog line connected to the timing controller, wherein the analog switch is arranged to latch a voltage value of the amplifier upon receiving the control signal and transmit the voltage value to the timing controller.

[0350] P2. The feedback device of claim P1, wherein the control signal instructs the analog switch to latch the voltage value when the column driver drives a column of the display.

[0351] P3. The feedback device as described in claim P1 further includes

[0352] An analog-to-digital converter is located between the output of the analog switch and the timing controller, the analog-to-digital converter being arranged to convert the voltage value from the output into a digital voltage value to be transmitted to the timing controller.

[0353] P4. The feedback device as described in claim P1, wherein the voltage value transmitted to the timing controller is an analog voltage value.

[0354] P5. A source driver of the display unit, comprising:

[0355] The feedback device as claimed in claim P1, used for each column of the display panel.

[0356] Q1. A method for providing feedback from a source driver to a timing controller of a display unit, the method comprising:

[0357] sending a command from the timing controller to the column driver of the source driver to latch the voltage value output by the amplifier of the column driver to the display panel of the display unit;

[0358] latching the voltage value at an output of the amplifier; and

[0359] The voltage value is received at the timing controller and stored.

[0360] Q2. The method of claim Q1, wherein the received voltage value is an analog voltage value, the method further comprising:

[0361] The analog voltage value in the timing controller is converted into a digital voltage value, and the digital voltage value is stored.

[0362] Q3. The method of claim Q1 , wherein the voltage value is an analog voltage value at the output of the amplifier, the method further comprising:

[0363] converting the analog voltage value into a digital voltage value within the source driver; and

[0364] The digital voltage value is received at the timing controller.

[0365] Q4. The method of claim Q3, further comprising:

[0366] sending the command to the column driver via a digital control interface; and

[0367] The digital voltage value is received at the timing controller through the digital control interface.

[0368] Q5. The method of claim Q2, further comprising:

[0369] sending the command to the column driver via a digital control interface; and

[0370] The analog voltage value is received through an analog line.

[0371] Q6. The method of claim Q1, further comprising:

[0372] performing said transmitting, said latching, and said receiving for a plurality of column drivers; and

[0373] The stored voltage values ​​are used to pre-scale output voltage values ​​of the timing controller to the columns of the display panel.

[0374] R1. A transmitter comprising:

[0375] a distributor arranged to receive a stream of video samples originating from an image sensor and to distribute a first selection of said digital video samples as a plurality of first input vectors into a first row buffer according to a predetermined arrangement and to distribute a subsequent selection of said video samples as a plurality of second input vectors into a second row buffer according to said predetermined arrangement, wherein said distributor is further arranged to alternately distribute the selection of said video samples between said first row buffer and said second row buffer;

[0376] a plurality of output ports, each output port being arranged to alternately read from one of the first input vectors of the first line buffer when the distributor writes to the second line buffer, and to read from one of the second input vectors of the second line buffer when the distributor writes to the first line buffer, and to output as an electromagnetic signal a series of analog levels corresponding to the video samples of the one of the first input vector or the second input vector.

[0377] R2. The transmitter of claim R1, wherein the video samples are analog RGB video samples.

[0378] R3. The transmitter of claim R1, wherein the video samples are digital RGB video samples, the transmitter further comprising:

[0379] A plurality of digital-to-analog converters (DACs), each DAC being arranged to receive the digital RGB video samples from one of the first input vector or the second input vector, convert the digital RGB video samples into analog video samples, and output the analog video samples to one of the output ports.

[0380] R4. The transmitter of claim R1, wherein the video samples are raw analog BGRG video samples.

[0381] R5. The transmitter of claim R1, wherein the video samples are raw analog RGGB video samples output from the image sensor in a modified form.

[0382] R6. The transmitter of claim R1, wherein the video samples are digital G video samples, the transmitter further comprising:

[0383] A plurality of digital-to-analog converters (DACs), each DAC being arranged to receive the G digital video samples from one of the first input vector or the second input vector, convert the digital video samples into analog video samples, and output the analog video samples to one of the output ports.

[0384] S1. A receiver comprising:

[0385] a plurality of inputs, each input receiving an electromagnetic signal via an electromagnetic path, each electromagnetic signal comprising a series of analog levels representing an analog video sample;

[0386] a collector arranged to collect the analog video samples of each electromagnetic signal into one of a plurality of first output vectors in a first row buffer and one of a plurality of second output vectors in a second row buffer, wherein the collector is further arranged to alternately collect a selection of the analog video samples between the first row buffer and the second row buffer, wherein the collector is further arranged to output the analog video samples from the first output vector of the first row buffer according to a predetermined arrangement when the second row buffer is filled, and to output the analog video samples from the second output vector of the second row buffer according to the predetermined arrangement when the first row buffer is filled, so that the receiver continuously outputs a stream of the analog video samples.

[0387] S2. The source driver according to claim S1, further comprising:

[0388] A collector controller is arranged to collect the input analog levels from the electromagnetic signal into the first and second row buffers, and output the analog levels from the first and second row buffers according to the predetermined arrangement.

[0389] S3. A receiver as claimed in claim S1, wherein once the first line buffer is full, the first line buffer outputs analog video samples from the first output vector.

[0390] S4. The receiver of claim S1, wherein the receiver does not include any digital-to-analog converter (DAC) for converting video samples.

[0391] S5. A receiver as claimed in claim S1, wherein the receiver includes at least one analog-to-digital converter to convert the stream of analog video samples into digital video samples.

[0392] G1. A method for sending a command to a source driver of a display unit:

[0393] Sending a control sequence from a transmitter in a display unit to a source driver of the display unit, wherein the control sequence is an MFM (modified frequency modulation) coding sequence;

[0394] Introducing an MFM flag into the control sequence to indicate to the source driver that at least one command complies with the MFM flag; and

[0395] After the MFM mark, at least one video synchronization command in the control sequence is sent to the source driver.

[0396] G2. The method of claim G1, further comprising:

[0397] The video synchronization command is used to perform vertical synchronization or horizontal synchronization on the image displayed on the display panel of the display unit.

[0398] G3. The method of claim G1, further comprising:

[0399] The control sequence is inserted at the transmitter into a stream of analog video samples destined for the source driver such that the control sequence is received at a single input amplifier of the source driver.

[0400] G4. The method of claim G1, further comprising:

[0401] When the display unit is powered on, the MFM flag is introduced into the control sequence.

[0402] G5. The method of claim G1, further comprising:

[0403] sending the control sequence including the introduced MFM flag on all input channels of the source driver until resynchronization occurs; and

[0404] After resynchronization, the control sequence is sent only on a single input channel of the source driver.

[0405] G6. The method of claim G1, further comprising:

[0406] The control sequence and the introduced MFM flag are simultaneously sent to all source drivers of the display unit.

[0407] H1. A method for receiving a command at a source driver of a display unit:

[0408] receiving, at a source driver of the display unit, a control sequence from a transmitter in the display unit, wherein the control sequence is an MFM (modified frequency modulation) coding sequence;

[0409] receiving and identifying an MFM flag of the control sequence, the MFM flag indicating to the source driver that at least one command complies with the MFM flag; and

[0410] After the MFM marker, the next MFM unit of the control sequence is interpreted as a video synchronization command at the source driver.

[0411] H2. The method of claim H1, further comprising:

[0412] The video synchronization command is used to perform vertical synchronization or horizontal synchronization on the image displayed on the display panel of the display unit.

[0413] H3. The method of claim H1, wherein the control sequence is received at a single input amplifier of the source driver.

[0414] H4. The method of claim H1, further comprising:

[0415] When the display unit is powered on, the MFM flag of the control sequence is received.

[0416] H5. The method of claim H1, wherein the source driver receives the control sequence until resynchronization occurs, the control sequence including the introduced MFM flag on all input channels of the source driver; and

[0417] After resynchronization, the control sequence is received only on a single input channel of the source driver.

[0418] H6. The method of claim H1, further comprising:

[0419] The control sequence and the introduced MFM flag are received at all source drivers of the display unit at the same time.

[0420] L1. A method for performing phase alignment to determine a source driver sampling phase, the method comprising:

[0421] receiving a command to enter a phase alignment mode at a source driver of the display unit;

[0422] receiving a synchronous stream of at least positive pulses having a first amplitude;

[0423] Setting an upper threshold of an upper comparator receiving the synchronization stream so that the upper comparator is triggered when receiving the positive pulse;

[0424] rotating a sampling phase of the positive pulse toward a trailing edge of the positive pulse until the upper comparator does not trigger at a specific sampling phase; and

[0425] When it is determined that the upper comparator is not triggered, the sampling phase is rotated backward from the specific sampling phase by at least one tap, and the backward rotated sampling phase is set as a source driver sampling phase for sampling incoming analog video samples at the source driver.

[0426] L2. The method of claim L1, wherein the synchronous stream comprises the positive pulses alternating with second positive pulses, the second amplitude of the second positive pulses being less than the first amplitude, the method further comprising:

[0427] The upper threshold of the upper comparator is set by adjusting the upper threshold of the upper comparator so that the upper comparator is triggered on the positive pulse but not on the second positive pulse.

[0428] L3. The method of claim L1, comprising:

[0429] At least one incoming analog video sample is sampled by the source driver using the source driver sampling phase, and the incoming analog video sample is displayed on a display panel of the display unit.

[0430] L4. The method of claim L1, wherein the source driver includes a central comparator for indicating whether the pulse of the synchronization stream is positive or negative, the method further comprising:

[0431] The sampling phase is rotated backward from the specific sampling phase only when the result of the central comparator is inconsistent with the result of the upper comparator.

[0432] L5. The method of claim L1, wherein the command is an MFM (Modified Frequency Modulation) coded command and the synchronization stream is an MFM coded stream.

[0433] L6. The method of claim L1, wherein the command and the synchronization stream are both received on a single channel of the source driver.

[0434] L7. The method of claim L1, wherein the synchronous stream includes negative pulses alternating with the positive pulses, the negative pulses having a negative amplitude, the method further comprising:

[0435] Setting a lower threshold of a lower comparator receiving the synchronization stream so that the lower comparator is triggered when receiving the negative pulse;

[0436] rotating the second sampling phase of the negative pulse toward the trailing edge of the negative pulse until the lower comparator does not trigger in a specific second sampling phase;

[0437] When it is determined that the lower comparator is not triggered, rotating the second sampling phase backward from the specific second sampling phase by at least one tap, and setting the backward rotated second sampling phase as the source driver second sampling phase; and

[0438] An average of the backward rotated sampling phase and the backward rotated second sampling phase is determined as a source driver sampling phase for sampling incoming analog video samples at the source driver.

[0439] M1. A sampling phase adjustment circuit for a source driver of a display unit, comprising:

[0440] Input reference clock;

[0441] Phase adjustment control;

[0442] a phase selector arranged to shift the sampling phase of the reference clock forward when the phase adjustment control indicates that sampling occurs before the control sequence of the video samples received at the source driver; and arranged to shift the sampling phase of the reference clock backward when the phase adjustment control indicates that sampling occurs after the control sequence of the video samples received at the source driver; and

[0443] An output sampling clock having the sampling phase output by the phase selector is sent to an amplifier of the source driver that receives the video samples.

[0444] M2. The sampling phase adjustment circuit according to claim M1, further comprising:

[0445] An input clock cycle skip control is arranged to cause the sampling phase adjustment circuit to skip one cycle of the reference clock.

[0446] N1. A method for sending a command to a source driver of a display unit, the method comprising:

[0447] receiving a stream of samples at a source driver of a display element;

[0448] interleaving the samples into a plurality of channels;

[0449] Searching for an MFM flag in one of the channels; and

[0450] When it is determined that the MFM flag is not found in the one channel, a next channel among the channels is searched and it is determined that the MFM flag exists in the next channel.

[0451] N2. The method of claim N1, further comprising:

[0452] One clock cycle is skipped to search for the MFM flag in the next channel.

[0453] N3. The method of claim N1, further comprising:

[0454] The deinterleaved samples are sent to a plurality of sample and hold amplifiers, with each SH amplifier implementing one of the channels.

[0455] N4. The method of claim N1, further comprising:

[0456] After determining that the MFM flag exists in the next channel, a display panel identification command is provided for the display unit after the MFM flag in the next channel.

[0457] N5. The method of claim N1, further comprising:

[0458] After determining that the MFM flag exists in the next channel, sampling phase alignment is performed using samples received on the next channel.

[0459] O1. A method for performing phase alignment in a display unit to sample a video signal, the method comprising:

[0460] receiving a plurality of video samples and control samples at a source driver of the display unit, the video samples arriving immediately before the control samples having different analog levels than video samples arriving immediately after the control samples;

[0461] changing a sampling phase of one of the control samples by a phase step so as to sample one of the samples;

[0462] When it is determined that sampling occurs in a sample prior to the control sample, skipping one clock cycle in order to sample in the control sample; and

[0463] When it is determined that the sampling occurs in a sample after the control sample, the sampling phase is shifted backward by at least one phase step.

[0464] O2. The method of claim O1, further comprising:

[0465] After skipping the clock cycle in order to sample in the control sample, the sampling phase is shifted forward by at least one phase step.

[0466] 03. The method of claim 01, further comprising:

[0467] By using a single comparator, it is determined that the sampling occurred in the previous sample, or it is determined that the sampling occurred in the sample after the control sample.

[0468] 04. The method of claim 01, further comprising:

[0469] After skipping the clock cycle or shifting the sampling phase backward, the sampling phase is sent to each amplifier of a plurality of amplifiers that samples the video samples and the control samples.

Claims

1. A transmitter comprising: a distributor arranged to receive a plurality of streams of digital video samples originating from a system-on-chip of a display unit and to distribute said digital video samples into a plurality of input vectors according to a predetermined arrangement; as well as A plurality of digital-to-analog converters (DACs), each DAC being arranged to receive the digital video samples from one of the input vectors, convert the digital video samples of the one input vector into a series of analog video samples, and output the series of analog video samples to a display panel of the display unit over an electromagnetic path.

2. The transmitter of claim 1 , wherein the dispenser further comprises: storing a first row buffer of the plurality of input vectors; as well as a second row buffer storing a plurality of second input vectors, wherein the distributor is further arranged to alternately distribute rows of the digital video samples between the input vectors of the first row buffer and the second input vectors of the second row buffer, and wherein the DAC alternately reads from the first row buffer when the distributor writes to the second row buffer, and reads from the second row buffer when the distributor writes to the first row buffer.

3. The transmitter of claim 1, wherein the digital video samples assigned to the input vector constitute rows of an image.

4. The transmitter of claim 1 , wherein the digital video samples are distributed into the input vectors at a first frequency, and wherein the digital video samples are serially output from each of the input vectors at a second frequency different from the first frequency.

5. The transmitter of claim 1, wherein the predetermined arrangement allows each sampling amplifier of a source driver that receives one of the series of analog video samples to output the analog video samples to consecutive memory locations.

6. The transmitter of claim 1 , wherein the transmitter is integrated with a timing controller of the display unit, the integrated transmitter and timing controller further comprising: The gate driver control signal is output to the gate driver of the display panel.

7. The integrated transmitter and timing controller of claim 6, wherein the integrated transmitter and timing controller is located within approximately 10 centimeters of the system on chip, within approximately 5 centimeters of the system on chip, or within approximately 2 centimeters of the system on chip.

8. The transmitter of claim 1, wherein the integrated transmitter and timing controller are further integrated with the system-on-chip of the display unit.

9. The transmitter of claim 5, wherein the predetermined arrangement allows one of the sampling amplifiers to exclusively sample a control signal.

10. The transmitter of claim 1, further comprising: The image processor is arranged to input the digital video samples, perform at least gamma correction on the digital video samples, and output corrected digital video samples.

11. A source driver for a display unit, comprising: An input terminal receives an analog electromagnetic signal comprising a continuous series of analog video samples through an electromagnetic path; a plurality of sampling amplifiers, each sampling amplifier arranged to specifically sample a portion of the analog video sample and write the portion of the analog video sample to a location in a memory array designated for the each sampling amplifier; as well as a plurality of column drivers, each column driver arranged to read one of the analog video samples from one of the locations in the storage array, amplify the one of the analog video samples, and drive the one of the amplified analog video samples into a column of the display panel.

12. The source driver of claim 11 , further comprising a second memory array having a designated location for each sampling amplifier, wherein the sampling amplifiers are further arranged to alternately write the respective portions of the analog video samples to the memory array or the second memory array, and wherein the column drivers alternately read from the memory array when the sampling amplifiers write to the second memory array and read from the second memory array when the sampling amplifiers write to the memory array.

13. The source driver according to claim 12, further comprising: Control logic circuitry is arranged to enable each of the sampling amplifiers to sample the portion of the analog video sample, enable the sampling amplifier to write to the memory array or the second memory array, and enable the column driver to read from the memory array or the second memory array.

14. The source driver of claim 11 , wherein the electromagnetic signal comprises a control signal for synchronization and not driven to a column of the display panel, the source driver further comprising: The sampling amplifier is specifically used to sample the control signal.

15. The source driver of claim 11, wherein the source driver does not include any digital-to-analog converter (DAC) for converting video samples. 16 . The source driver of claim 12 , wherein the column driver is further arranged to read in parallel from the memory array when the memory array is fully loaded, or to read in parallel from the second memory array when the second memory array is fully loaded.

17. The source driver of claim 11, wherein the series of analog video samples arrive in a predetermined arrangement that allows each sampling amplifier to output its respective portion of the analog video samples to consecutive memory locations in the memory array. 18 . The source driver according to claim 17 , wherein the predetermined arrangement indicates that one of the sampling amplifiers is dedicated to sampling the control signal.

19. A video transmission device, comprising: Transmitter, including: a distributor arranged to receive a stream of digital video samples and distribute said digital video samples into a plurality of input vectors in a line buffer according to a predetermined arrangement, and a digital-to-analog converter (DAC) for each input vector, each DAC being arranged to serially receive digital video samples from its corresponding input vector and convert the digital video samples into a series of analog video samples; a plurality of electromagnetic pathways, each electromagnetic pathway arranged to transmit one of the series of analog video samples to a display panel of a display unit; and A source driver array includes a source driver corresponding to each of the DACs, each source driver including: a collector arranged to receive the series of analog video samples from each DAC and store the analog video samples of the corresponding input vector, and A plurality of column drivers are arranged to receive the stored analog video samples from the collector in parallel and amplify each of the stored analog video samples onto a column of the display panel.

20. The video transmission apparatus of claim 19, wherein the predetermined arrangement allows each collector to store its respective analog video samples into consecutive memory locations.

21. The video transmission device of claim 19, wherein the predetermined arrangement allows a sampling amplifier of the collector to exclusively sample a control signal.

22. The transmitter of claim 1, wherein the dispenser further comprises: First line buffer; as well as a second row buffer, wherein the distributor is further arranged to distribute the input vector of digital video samples into the first row buffer, transfer a row of the input vector into the second row buffer, and output the row from the second row buffer upon distributing the input vector into the first row buffer.

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