Decoding all-in-one machine based on single CPU
By using a single-CPU-based decoding all-in-one machine, the system instability problem caused by the traditional relay method is solved, and efficient processing and fusion of multiple video signals are achieved, which improves the stability and reliability of vehicle function expansion and reduces development costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2026-03-10
AI Technical Summary
Traditional relay-based systems can lead to instability during vehicle function expansion, making it impossible to display both the original vehicle interface and the newly added function interface simultaneously. This is especially problematic with widescreen in-vehicle systems, where it can easily cause signal interference and transmission abnormalities. Furthermore, these systems have long development cycles and high costs.
The system employs a single-CPU-based decoding all-in-one unit, including a video data receiving module, an MCU parsing module, a MIPI_CSI conversion module, a CPU processing module, a DP data output module, and a power management module. It achieves the superposition of multiple video signals through MIPI_CSI signal conversion and CPU processing, supports multi-screen display, and utilizes a CAN bus transceiver and parsing chip for real-time signal parsing and control to ensure system stability.
It achieves efficient processing and fusion of multiple video signals, meets the real-time display requirements of vehicles, improves system stability and reliability, reduces development costs and cycle, and supports unified access of heterogeneous video sources.
Smart Images
Figure CN223987124U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of automotive displays, and in particular to a single-CPU-based decoding all-in-one machine. Background Technology
[0002] Vehicles are subject to various constraints when they leave the factory. On the one hand, the research and development cycle is relatively long; on the other hand, due to cost considerations, manufacturers have to make trade-offs in vehicle functions. This often results in vehicles not keeping pace with the latest technological developments and may even lead to the absence of certain functions.
[0003] To improve this situation, people often extend the functionality of vehicles through aftermarket installations. The traditional method for connecting the original head unit and the screen is to use a relay. However, relay operation only allows users to choose between the original vehicle interface and the newly added function interface. Furthermore, because it achieves this through direct circuit switching, it introduces serious stability issues to the entire system, easily causing signal interference and transmission anomalies, and can disrupt the communication link between the original head unit and the screen.
[0004] For some specialized widescreen in-vehicle infotainment systems, such as ultra-widescreen systems that divide the screen into a left side displaying instrument cluster information and a right side displaying infotainment content, the situation becomes even more challenging. Using relays, adding new functions would cause the original instrument cluster to become unusable, significantly impacting the vehicle's normal operation; therefore, this approach is unsuitable. In such cases, a picture-in-picture (Picture-in-Picture) approach is considered, which can partially cover the original screen. However, this method generally requires FPGAs or dedicated hardware, leading to long development cycles and high costs, increasing the difficulty and cost of functional expansion. Utility Model Content
[0005] To overcome the shortcomings of the existing technology, this application provides a single-CPU-based decoding all-in-one machine.
[0006] This application provides a single-CPU-based decoder / decoder, employing the following technical solution:
[0007] A single-CPU-based decoding all-in-one machine includes: a video data receiving module, an MCU parsing module, a MIPI_CSI conversion module, a CPU processing module, a DP data output module, and a power management module. The video data receiving module receives the original vehicle video signal and the vehicle's auxiliary video signal. The MCU parsing module is connected to the CPU processing module and includes a CAN bus transceiver and a parsing chip. The CAN bus transceiver continuously receives signals from the CAN bus and transmits them to the parsing chip for parsing. The parsing chip then performs corresponding software logic processing based on the signal instructions from the bus. The MIPI_CSI conversion module is connected to the video data receiving module and converts the original vehicle video signal and the auxiliary video signal into a single unit. The signal is converted into a MIPI_CSI signal and then transmitted to the CPU processing module for processing. The MIPI_CSI conversion module includes a deserializer and a signal conversion unit. The CPU processing module is connected to the MIPI_CSI conversion module and is used to perform image processing and superposition on the MIPI_CSI signal. The DP data output module is connected to the CPU processing module. The video signal processed by the CPU processing module is simultaneously output as two independent video streams through the DP interface. The video stream data is output to the vehicle display screen through a serializer. The deserializer and the serializer are connected to the MCU parsing control module and perform corresponding operations according to the received control signals. The power management module is used to convert the vehicle voltage into the adaptation voltage of the internal modules of the decoder.
[0008] By adopting the above technical solution, the video data receiving module receives the original vehicle video signal and the vehicle auxiliary video signal. The MIPI_CSI signal conversion module converts these signals into two MIPI_CSI signals respectively, providing a standardized input format for subsequent image processing. The CAN bus transceiver receives CAN bus signals, which are then parsed by the parsing chip. Software logic processing is executed according to the signal instructions, thereby enabling the reading and response to other vehicle system information, parsing vehicle status signals (such as vehicle speed and steering angle), and triggering video mode switching. The CPU processing module performs image processing and overlay on the MIPI_CSI signals, allowing video signals from different sources to be displayed on the same screen, completing the core processing of the video signals. The processed video signals are output as two independent video streams through the DP interface and transmitted to the vehicle display screen via a serializer, meeting the needs of multi-screen display or displaying different content. The deserializer and serializer connect to the MCU parsing control module and execute corresponding operations based on the received control signals, ensuring coordinated operation between modules and accurate data transmission. End-to-end latency optimization ensures the total latency of the serial-to-deserial (SerDes) link is ≤2ms (including encoding and decoding), meeting the real-time requirements from the ADAS camera to the display (ISO 26262 requires critical path latency <100ms). Frame synchronization technology is supported, with multi-camera input time deviation <1μs, ensuring tear-free stitching in the panoramic surround view system.
[0009] The power management module converts the vehicle voltage into the compatible voltage for the internal modules of the decoder, providing reliable power support for the stable operation of each module.
[0010] Optionally, the signal conversion unit includes an Lt6911 signal conversion chip and a TP2815 signal conversion chip. The signal deserialized by the deserializer is an EDP signal. The EDP signal is converted into a MIPI_CSI signal by the Lt6911 signal conversion chip and input to the CPU. The auxiliary video signal received by the data receiving module is a signal from four AHD analog camera channels. It is converted into a MIPI_CSI signal by the TP2815 signal conversion chip and input to the CPU.
[0011] By adopting the above technical solution, the EDP signal obtained after deserialization by the deserializer is converted into a MIPI_CSI signal by the Lt6911 chip and input to the CPU; the four AHD analog camera signals received by the data receiving module are converted into MIPI_CSI signals by the TP2815 chip and then input to the CPU, thereby adapting to the CPU's requirements for signal format.
[0012] Optionally, the CPU processing module uses the RK3588 chip.
[0013] By adopting the above technical solutions, the RK3588 boasts a rich array of interfaces, including MIPI_CSI and HDMI interfaces. The MIPI_CSI interface offers high-speed data transmission capabilities, meeting the high frame rate and high resolution data transmission requirements of infrared and high-definition cameras. Processed image data can be output to the vehicle's display screen via the HDMI interface for convenient viewing by the driver.
[0014] Optionally, the decoder includes an audio input interface and an audio output interface. The output of the audio input interface is connected to the RK3588 chip via an I2C bus and an I2S bus. The I2C bus is used to input audio control signals, and the I2S bus is used to input and output audio data signals. The output of the RK3588 chip is connected to the audio output interface.
[0015] By adopting the above technical solution, control commands are received via I2C, and bidirectional audio data exchange is achieved with RK3588 via I2S. I2C is used to configure audio peripheral parameters (such as gain and filter settings), while I2S is responsible for the actual audio stream transmission, together constructing a complete audio processing link.
[0016] Optionally, the decoder includes a video input interface and a video output interface. The output of the video input interface is connected to the input of the data receiving module via a coaxial cable or shielded twisted pair cable to receive high-speed serial data from the vehicle video source and transmit it to the deserializer. The output of the DP data output module is connected to the serializer, and the serializer is connected to the video output interface.
[0017] By adopting the above technical solutions and using coaxial cables or shielded twisted-pair cables, external interference can be effectively reduced, ensuring stable signal transmission.
[0018] Optionally, the power management module is powered by a 12V car battery. After passing through a DC / DC step-down module, it provides a stable 5V system voltage and 3.5A system current. The power supply is then stepped down again by the DC / DC converter for use by each module.
[0019] By adopting the above technical solution, the first step, the DC / DC step-down module, needs to handle a wide input voltage range and provide a stable 5V system voltage to ensure that the system can work stably under different operating conditions and avoid voltage fluctuations affecting the performance of the decoder. Then, the 5V voltage is distributed to each module. This distributed power supply can isolate power supply noise between different modules, prevent mutual interference, and improve system stability.
[0020] Optionally, the single-CPU-based decoding all-in-one machine includes: a storage module and a function interface module. The storage module is connected to the CPU processing module and is used to store upgrade and update data of the MCU's internal software. The function interface module is an Ethernet interface used by the decoding all-in-one machine to extend access to video stream data from other input gateways.
[0021] By adopting the above technical solutions, the storage module can conveniently store upgrade and update data of the MCU's internal software, which helps ensure that the software functions of the decoder are always up-to-date and improves the system's performance and stability. For video stream data access expansion, the Ethernet interface, as a functional interface module, enables the decoder to connect to video stream data from other input gateways, increasing the diversity of data sources and providing users with richer video content.
[0022] In summary, this application includes at least one of the following beneficial effects:
[0023] 1. A single-CPU design simplifies the circuit structure and improves system stability;
[0024] 2. Through the MIPI_CSI conversion module, the original vehicle video (such as reversing camera) and auxiliary video (such as high-definition camera) are converted into standard MIPI signals, realizing unified access of heterogeneous video sources (analog / digital);
[0025] 3. The CPU uses a hardware acceleration layer to dynamically overlay multiple video streams with an end-to-end processing latency of <50ms, meeting the real-time display requirements of vehicles. The MCU parsing module monitors the CAN bus in real time, analyzes vehicle status signals to trigger video mode switching, such as automatically activating surround view at low speeds, with a response time of <10ms. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of a module in an embodiment of this application.
[0027] Explanation of reference numerals in the attached diagram: 1. Video data receiving module; 2. MIPI-CSI conversion module; 3. MCU parsing module; 4. CPU processing module; 5. DP data output module; 6. Deserializer; 7. Serializer; 8. CAN bus transceiver; 9. Power management module; 10. Storage module; 11. Functional interface module; 21. Signal conversion unit. Detailed Implementation
[0028] This application discloses a single-CPU-based decoding all-in-one machine, referring to... Figure 1 The decoder includes a video data receiving module 1, an MCU parsing module 3, a MIPI_CSI conversion module 2, a CPU processing module 4, a DP data output module 5, and a power management module 9.
[0029] The video data receiving module 1 is used to receive the original vehicle video signal and the vehicle's auxiliary video signal. The video data receiving module 1 is equipped with an AHD coaxial interface and an EDP shielded twisted pair interface, and supports receiving the original vehicle EDP signal (4-channel LVDS, rate 1.5Gbps / lane) and 4-channel AHD analog signal (1080P@30fps).
[0030] The MCU parsing module 3 is connected to the CPU processing module 4. The MCU parsing module 3 includes a CAN bus transceiver 8 and a parsing chip. The CAN bus transceiver 8 continuously receives signals from the CAN bus and transmits them to the parsing chip for parsing. The parsing chip then performs corresponding software logic processing based on the signal instructions on the bus. The MCU parsing control module KF32F350MQTA chip acts as the main controller, connecting to different networks through two independent CAN interfaces. The TJA1040 transceiver and TJA1041 transceiver are connected to different CAN controllers, forming independent communication paths to enhance system fault tolerance. Dual CAN channel redundancy prevents single-point failures. Critical vehicle systems (such as brake control and battery management) require the TJA1040 high-speed CAN transceiver, supporting a 5Mbps communication rate, suitable for scenarios with high real-time requirements such as powertrain and body control. The other TJA1041 transceiver has a standby current as low as 5μA and supports local wake-up functionality, suitable for body electronic modules requiring power management (such as door control and battery management systems), and is suitable for low-power or backup channels.
[0031] The aforementioned transceiver monitors the CAN bus in real time, receives and parses vehicle status information, and sends the parsed control commands to the RK3588 via SPI to trigger corresponding operations, such as switching video source priority and adjusting picture-in-picture layout parameters. GPIO controls the enable pins of deserializer 6 and serializer 7 to ensure signal timing alignment and guarantee the stability of video transmission.
[0032] The CAN command parsing process involves the TJA1040 transceiver receiving power CAN signals (such as reversing trigger and vehicle speed pulse), and the TJA1041 transceiver receiving CAN commands (such as user button requests to switch picture-in-picture windows). The MCU converts the CAN data into structured information, performs data parsing and encapsulation, and transmits it to the CPU via SPI / USB to trigger corresponding events (such as activating the reversing camera).
[0033] The MIPI_CSI conversion module 2 is connected to the video data receiving module 1 and is used to convert the original vehicle video signal and auxiliary video signal into MIPI_CSI signals. The MIPI_CSI signals are then transmitted to the CPU processing module 4 for processing. The MIPI_CSI conversion module 2 includes a deserializer 6 and a signal conversion unit 21. The CPU processing module 4 is connected to the MIPI_CSI conversion module 2 and is used to perform image processing and overlay on the MIPI_CSI signals to achieve picture-in-picture functionality.
[0034] The signal conversion link of the signal conversion unit 21 is divided into dual-channel parallel processing. The DS90UB984 serializer 7 receives the original vehicle serial signal (such as FPD-Link III) and decodes it into EDP video stream (such as the original vehicle navigation interface and instrument panel data). Then, two LT6911 signal conversion chips convert the EDP signal into MIPI_CSI_2 format signal. The DS90UB984 serializer 7 and the two LT6911 signal conversion chips work together to realize the original vehicle signal recovery. Four TP2815 signal conversion chips convert four 1080P AHD analog cameras (such as reversing, surround view, and blind spot monitoring) into four MIPI_CSI channels and input them into the processor RK3588.
[0035] The two types of signals are respectively connected to the CSI0 and CSI1-CSI4 interfaces of the RK3588 processor, and the timing alignment of multiple video streams is ensured through a hardware synchronization mechanism. The core processor RK3588 is responsible for multi-channel video decoding, picture-in-picture compositing, UI rendering, and logic control. The RK3588 receives multiple video streams through the MIPI_CSI_2 interface, uses NPU / VPU hardware decoding, and the EDP-retrieved images are directly used as UI layers or overlay data sources; the camera images are used for distortion correction, HDR enhancement, and multi-channel image stitching (such as 360° surround view).
[0036] The DP data output module 5 is connected to the CPU processing module 4. The video signal processed by the CPU processing module 4 is simultaneously output as two independent video streams through the DP interface. The video stream data is output to the vehicle display screen through the serializer 7.
[0037] The DP data output module 5 includes the DS90UB984 output signal processing chip. This chip converts the processor's DP output signal into an LVDS signal to drive the original car screen to display navigation, reversing image, etc., without replacing the original car hardware. It bridges the old and new video interfaces and solves the protocol compatibility problem between modern processors and traditional displays. The MCU dynamically adjusts the output mode of the DS90UB984 chip through I2C (such as switching resolutions to adapt to different screens).
[0038] Deserializer 6 and serializer 7 are connected to the MCU parsing control module and execute corresponding operations based on the received control signals. The hardware synchronization process involves the MCU controlling the enable pins of deserializer 6 (DS90UB983) and serializer 7 (DS90UB984) via its GPIO pins. By controlling the level of the enable pins, the MCU ensures that the timing of deserializer 6 and serializer 7 is consistent with the timing of the entire system, thereby guaranteeing the correct transmission and processing of video signals.
[0039] The power management module 9 is powered by a 12V car battery. After passing through a DC / DC step-down module, it provides a stable 5V system voltage and 3.5A system current. The power supply is then stepped down again by the DC / DC converter for use by various modules.
[0040] The power management module 9 adopts a two-stage buck architecture to ensure stable power supply to the system. The first-stage buck converter uses the SY8303 to convert the 12V input of the vehicle into a 5V / 3.5A main power supply for the system. The second-stage buck converter uses the RT8059GJ5 chip to generate multiple outputs of 3.3V / 1.2A (digital circuit), 1.8V / 0.5A (physical layer power supply), and 1.1V / 0.8A (SerDes core). The TPS54332 chip independently provides a 3.3V / 1A main control power supply.
[0041] The decoder also includes a storage module 10 and a function interface module 11. The storage module 10 is connected to the CPU processing module 4 and is used to store upgrade and update data of the MCU internal software. The function interface module 11 is an Ethernet interface and is used for the decoder to access video stream data from other input gateways.
[0042] Storage module 10 is a serial flash memory chip connected to the MCU via an SPI interface. It is used to store MCU firmware and related data, supports OTA upgrades, and can receive new firmware versions via wireless networks or other communication methods, and perform upgrade operations when appropriate to ensure that the MCU's functions are continuously improved and optimized.
[0043] The Ethernet interface (RTL8211F) connects to the external network via an RJ45 interface and connects to the RK3588 via a PCIe channel. As functional interface module 11, it provides wired network connectivity for the device and can also be used to extend access to video stream data from other input gateways. Through the Ethernet interface, the decoder can perform high-speed data transmission with external devices. Update packages downloaded via Ethernet are temporarily stored in the flash memory chip, verified, and then written to the eMMC main storage, ensuring that the upgrade process is recoverable even after power failure.
[0044] The decoder can manage layers using DRM (Direct Rendering Manager). The main screen occupies the entire screen, while the picture-in-picture window floats (scalable / draggable). During user interaction, the user taps the picture-in-picture window on the touchscreen. The RK3588 detects the coordinates and then sends commands to the MCU via UART / SPI. The MCU then notifies the entertainment system to adjust the signal source via CAN.
[0045] Automatic triggering is initiated by the reversing signal. The MCU instructs the RK3588 to switch the picture-in-picture to the rearview camera and overlay radar distance information. The RK3588 then overlays vehicle data (speed, gear) onto the main screen at the top. The picture-in-picture window border / title is rendered in real-time by the GPU (e.g., with a semi-transparent effect). After receiving control commands, the CPU performs corresponding operations, such as switching video source priority and adjusting picture-in-picture layout parameters.
[0046] The highly integrated single-chip RK3588 chip integrates multiple functions such as video processing, encoding, and audio mixing, reducing the complexity of peripheral circuits and improving the system's integration and reliability.
[0047] In summary, the single-CPU-based decoding all-in-one solution, through reasonable hardware design, optimized data flow and processing procedures, and comprehensive performance testing and effect demonstration, achieves efficient processing and fusion of original vehicle video signals and in-vehicle auxiliary video signals, providing drivers with richer and more accurate visual information, while also improving the system's stability, reliability, and scalability.
[0048] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A single-CPU-based decoding all-in-one machine, characterized by comprising: The application relates to a decoding all-in-one machine. The decoding all-in-one machine comprises a video data receiving module (1), an MCU analysis module (2), an MIPI_CSI conversion module (3), a CPU processing module (4), a DP data output module (5) and a power management module (9). The video data receiving module (1) is used for receiving original vehicle video signals and vehicle-mounted auxiliary video signals. The MCU analysis module (2) is connected with the CPU processing module (4), the MCU analysis module (2) comprises a CAN bus transceiver (8) and an analysis chip, the CAN bus transceiver (8) is connected with the analysis chip, the CAN bus transceiver (8) is used for continuously receiving signals on a CAN bus and transmitting the signals to the analysis chip for analysis, then the analysis chip makes corresponding software logical processing according to signal instructions on the bus. The MIPI_CSI conversion module (3) is connected with the video data receiving module (1) and is used for converting the original vehicle video signals and the auxiliary video signals into MIPI_CSI signals and transmitting the MIPI_CSI signals into the CPU processing module (4) for processing, the MIPI_CSI conversion module (3) comprises a deserializer (6) and a signal conversion unit (21), the CPU processing module (4) is connected with the MIPI_CSI conversion module (3) and is used for performing image processing on the MIPI_CSI signals and superimposing. The DP data output module (5) is connected with the CPU processing module (4), the video signals processed by the CPU processing module (4) are output through a DP interface and two independent video streams are simultaneously output, and the video stream data is output to a vehicle-mounted display screen through a serializer (7). The deserializer (6) and the serializer (7) are connected with an MCU analysis control module and perform corresponding operations according to received control signals. The power management module (9) is used for converting a vehicle voltage into an adaptive voltage of internal modules of the decoding all-in-one machine.
2. The single-CPU-based decoding all-in-one machine according to claim 1, wherein, The signal conversion unit (21) comprises an Lt6911 signal conversion chip and a TP2815 signal conversion chip, the deserializer (6) deserializes EDP signals, the EDP signals are converted into MIPI_CSI signals through the Lt6911 signal conversion chip and are input into a CPU, the data receiving module transmits four AHD analog camera analog signals into the TP2815 signal conversion chip through a coaxial cable, and the received auxiliary video signals are converted into two MIPI_CSI signals and are input into the CPU.
3. The single-CPU-based decoding all-in-one machine according to claim 1, wherein, The CPU processing module (4) uses an RK3588 chip.
4. The single-CPU-based decoding all-in-one machine according to claim 3, wherein, The decoding all-in-one machine comprises an audio input interface and an audio output interface, an output end of the audio input interface is connected with the RK3588 chip through an I2C bus and an I2S bus, the I2C bus is used for inputting an audio control signal, the I2S is used for inputting and outputting an audio data signal, and an output end of the RK3588 chip is connected with the audio output interface.
5. The single-CPU-based decoding all-in-one machine according to claim 1, wherein, The decoding all-in-one machine includes a video input interface and a video output interface, an output end of the video input interface is connected with an input end of the data receiving module through a coaxial cable or a shielded twisted pair wire, and is used for receiving high-speed serial data from a vehicle-mounted video source and transmitting the high-speed serial data to the deserializer (6), an output end of the DP data output module (5) is connected with the serializer (7), and the serializer (7) is connected with the video output interface.
6. The single-CPU-based decoding all-in-one machine according to claim 1, wherein, The power management module (9) is powered by a 12V automobile battery, a stable 5V system voltage and a 3.5A system current are provided through a DC / DC voltage reduction module, and then power supply is reduced to DC / DC for use of each module.
7. The single-CPU-based decoding all-in-one machine according to claim 1, wherein, The decoding all-in-one machine includes a CPU processing module (4), a deserializer (6), a DP data output module (5), a serializer (7), a power management module (9), a storage module (10) and a functional interface module (11). The storage module (10) is connected with the CPU processing module (4) and is used for storing upgrade update data of internal software of the MCU; the functional interface module (11) is an Ethernet interface and is used for expanding and accessing video stream data of other input gateways by the decoding all-in-one machine.