An industrial controller fast-slow operation cycle full data backup method

Abstract

This invention discloses a method for full data backup of fast and slow operation cycles of an industrial controller, comprising: FPGA detecting whether there is a main power failure or receiving a backup command; if so, the FPGA compares the integrity markers and timestamps of the fast cycle data in data area A and data area B of the memory chip, and writes the latest fast cycle complete data to the power-loss non-volatile memory chip; then, the FPGA compares the integrity markers and timestamps of the slow cycle data in data area A and data area B of the memory chip, and writes the latest slow cycle complete data to the power-loss non-volatile memory chip. The data backup method of this invention can not only restore a complete cycle of data without selecting data, but also uses common memory chips and power-loss non-volatile memory chips, effectively reducing costs and implementation complexity.

Description

Technical Field

[0001] This invention relates to the field of data protection and backup technology, specifically to a method for full data backup during the fast and slow operation cycles of an industrial controller. Background Technology

[0002] In the field of industrial automation control, the operating environment of controllers is very complex, with strong electromagnetic radiation and harsh ambient temperatures, which can cause controllers to malfunction or crash and restart. During the restart process, the data in memory is lost, and configuration data needs to be reloaded. However, the reloaded data does not contain the previous calculation data.

[0003] Currently, the two most common methods used in the market to solve this problem are: one is to store important data in storage media such as SRAM that can retain data even when power is off, but this type of media not only has a small capacity and requires data selection, but is also expensive and the data will still be lost when power is off; the other is to run both programs and data in magnetic memory media, which can also retain data even when power is off, but this type of media is extremely expensive, and there are currently few domestic manufacturers to choose from. Obviously, how to achieve data backup and complete data recovery at low cost is a technical problem that the industry urgently needs to solve.

[0004] Based on this, the purpose of this invention is to address the shortcomings of the prior art by providing a method for full data backup of fast and slow operation cycles of industrial controllers. This method not only enables the recovery of a complete cycle of data without data selection, but also allows the use of common memory chips and non-volatile memory chips, effectively reducing costs and implementation complexity. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a method for full data backup of fast and slow operation cycles of industrial controllers. This method not only enables the recovery of a complete cycle of data without data selection, but also allows for the restoration of data in both power-off and power-on conditions. Furthermore, it utilizes common memory chips and non-volatile memory chips, effectively reducing costs and implementation complexity, thereby solving the problems existing in data backup and complete data recovery in existing technologies.

[0006] Specifically, the technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a method for full data backup of the fast and slow operation cycles of an industrial controller, comprising:

[0007] The FPGA detects whether the main power supply has failed or a backup command has been received.

[0008] If present, the FPGA writes the latest fast-cycle integrity data to the power-down non-volatile memory chip by comparing the integrity flags and timestamps of the fast-cycle data in data area A and data area B of the memory chip.

[0009] Then, the FPGA compares the integrity markers and timestamps of the slow-cycle data in data area A and data area B of the memory chip, and writes the latest slow-cycle integrity data into the power-down non-volatile memory chip.

[0010] In one embodiment of the industrial controller fast and slow operation cycle full data backup method according to the present invention, the FPGA detects whether there is a main power failure or receives a backup command, including:

[0011] If a main power failure is detected, the FPGA uses the backup power supply and shuts down the backup power supply after the slow cycle data is written to the power-loss non-volatile memory chip.

[0012] If a backup command is received, the backup is reported as complete after the slow-cycle data is written to the power-loss non-volatile memory chip.

[0013] In one embodiment of the industrial controller fast and slow operation cycle full data backup method according to the present invention, the main power supply powers the entire board, and the backup power supply only powers the FPGA, memory chip and power-loss non-volatile memory chip.

[0014] The CPU is responsible for communication and computing, while the FPGA is responsible for data backup and recovery. The CPU and FPGA communicate using a high-speed bus and a low-speed bus. The high-speed bus, with its high bandwidth throughput, is responsible for data transfer that needs to be saved, while the low-speed bus, with its high real-time capability, is responsible for register data transfer between the CPU and FPGA. Data transfer also occurs between the FPGA and memory chips and non-volatile memory chips that are powered down.

[0015] In one embodiment of the industrial controller fast and slow operation cycle full data backup method according to the present invention, the high-speed bus includes, but is not limited to, parallel LVDS or serial Aurora, SRIO, PCIe; the low-speed bus includes, but is not limited to, SPI, LIO, UART.

[0016] In one embodiment of the industrial controller fast and slow operation cycle full data backup method according to the present invention, the memory chip is a DDR chip, and the power-loss non-volatile storage chip includes, but is not limited to, flash and SD card.

[0017] In one embodiment of the industrial controller fast and slow cycle full data backup method according to the present invention, the memory chip is divided into data area A and data area B. The data distribution in data area A and data area B is the same as the data size and relative position in the CPU memory. The last position of the data in data area A and data area B is marked with whether the fast cycle and slow cycle data backup is completed and the timestamp. If the data backup is completed, the data backup completion mark is set and the timestamp of the backup completion is recorded.

[0018] In one embodiment of the industrial controller fast and slow cycle full data backup method according to the present invention, the CPU writes commands to corresponding registers via a low-speed bus, with fast and slow cycles corresponding to registers at different addresses. If a fast cycle command is received, it is cached in a fast cycle queue; if a slow cycle command is received, it is cached in a slow cycle queue. The depth of the fast cycle queue is not less than the number of fast cycle data areas in the CPU memory, and the depth of the slow cycle queue is not less than the number of slow cycle data areas in the CPU memory. The FPGA reads commands from the cache queue, parses the required data length and the address of the data in the CPU memory, and reads the corresponding address and length of data via a high-speed bus.

[0019] In one embodiment of the industrial controller fast and slow operation cycle full data backup method according to the present invention, after the CPU completes the calculation of a data area, it sends a command composed of the data length and the memory base address where the data is located to the corresponding register in the FPGA through the low-speed bus.

[0020] In one embodiment of the industrial controller fast and slow cycle full data backup method according to the present invention, the FPGA cyclically monitors the fast cycle command queue and the slow cycle command queue. When the fast cycle command queue is detected to be non-empty, the FPGA reads a fast cycle command, verifies the correctness of the command, and discards it if it is incorrect. If correct, the base address and length of the data in the CPU memory are parsed from the command, and these two parameters are given to the high-speed bus interface. Upon receiving these two parameters, the high-speed bus interface initiates a read operation command to read the data into the memory chip under the FPGA. After completion, it continues to check whether the fast cycle command queue is empty. If it is not empty, it continues to execute the data reading operation until the fast cycle command queue is detected to be empty. When the fast cycle command queue is empty, the FPGA checks the slow cycle command queue. If it is empty, it checks the fast cycle command queue. If it is not empty, it reads a slow cycle command, verifies the correctness of the command, and discards it if it is incorrect. If the data base address and length are correctly parsed, they are given to the high-speed bus. The high-speed bus reads the data and puts it into the memory chip under the FPGA. After execution, the fast cycle command queue is checked.

[0021] In one embodiment of the industrial controller fast and slow operation cycle full data backup method according to the present invention, when the controller starts up after a power failure, when the data recovery is executed, the CPU starts the FPGA recovery program by writing to the register through the low-speed bus. The FPGA reads the storage status area of ​​the power-down non-volatile memory chip, reads the data starting from the address with the latest timestamp, and writes the read data into the corresponding memory of the CPU to achieve the effect of data recovery.

[0022] When the controller recovers data without power failure, the CPU starts the FPGA recovery program by writing to the register via the low-speed bus. The FPGA reads the fast and slow cycle data integrity flags and timestamps from the data A and data B areas of its underlying memory chip. By comparing the integrity flags and timestamps, the latest fast and slow cycle integrity data is found, and the data is written to the CPU's memory via the high-speed bus, thus achieving the effect of data recovery.

[0023] Compared with the prior art, the positive effects of the present invention are:

[0024] 1. The high-speed bus read operation between the FPGA and CPU proposed in this invention has a fast response time, and the size of the memory chip and the power-down non-volatile storage medium (power-down non-volatile storage chip) under the FPGA can be selected according to actual needs, so that the data in the CPU, including configuration data, calculation data, etc., can be saved and restored at startup without the need to select data.

[0025] 2. This invention proposes to perform integrity marking on the fast and slow cycles of data areas A and B in the FPGA's memory. This can solve the problem of dual-cycle data caused by incomplete calculations during abnormal operations. The fast and slow cycles can be merged using the integrity markings and timestamps of data areas A and B to create a new data set with both fast and slow cycles completed, thus avoiding data incompleteness caused by abnormal CPU crashes.

[0026] 3. Since non-volatile storage media inherently have a limited lifespan, and the lifespan of the media is positively correlated with the number of write operations, reducing the number of write operations can increase the lifespan of the media. Therefore, multiple write operations on the same area should be minimized. Thus, this invention divides the media storage space, allowing for the cyclical use of multiple spaces. By comparing timestamps, the latest data is loaded.

[0027] 4. Since the calculation time of the fast cycle is faster than that of the slow cycle, the data to be backed up needs to be real-time. This invention optimizes the detection frequency of the fast and slow cycles to prioritize the response to the fast cycle command and ensure the real-time performance of the fast cycle data.

[0028] 5. This invention uses a backup power supply, so that data can be saved in a non-volatile memory chip even in the event of a power failure. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the electronic device used in the industrial controller fast and slow operation cycle full data backup method of the present invention.

[0030] Figure 2 This is a schematic diagram of the data distribution in the CPU of this invention;

[0031] Figure 3 This is a schematic diagram of the data distribution in the memory chip under the FPGA of this invention;

[0032] Figure 4 This is a schematic diagram of low-speed bus communication between the CPU and FPGA of this invention.

[0033] Figure 5 This is a schematic diagram of the command format consisting of the data length of the CPU's data area and the base memory address where the data is located in this invention.

[0034] Figure 6 This is a flowchart of the FPGA cyclic monitoring fast-cycle command queue and slow-cycle command queue in this invention;

[0035] Figure 7 This is a flowchart of the full data backup method for the fast and slow operation cycles of the industrial controller in this invention.

[0036] Figure 8 This is a flowchart of the data recovery method in this invention. Detailed Implementation

[0037] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0038] It is understood that the term "a" should be understood as "at least one" or "one or more," meaning that in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple. The term "a" should not be construed as a limitation on the quantity. "Multiple" means two or more.

[0039] While ordinal numbers such as “first,” “second,” etc., will be used to describe various components, there is no limitation on which components are used herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of this application. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0040] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form also includes the plural form, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “having” as used in this specification specify the presence of the described features, numbers, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, operations, components, elements or combinations thereof.

[0041] The following is combined Figure 1-8 The present invention will be further described with reference to specific embodiments.

[0042] like Figure 1 The diagram shown is a schematic representation of the electronic device used in the industrial controller fast and slow operation cycle full data backup method of the present invention.

[0043] The main power supply powers the entire board, while the backup power supply only powers the FPGA, memory chips, and non-volatile memory chips. The CPU handles communication and computation, while the FPGA handles data backup and recovery. Communication between the CPU and FPGA uses high-speed and low-speed buses. High-speed buses include parallel LVDS, serial Aurora, SRIO, and PCIe, while low-speed buses use SPI, LIO, and UART. The high-bandwidth throughput of the high-speed bus handles data transfers that need to be saved. The low-speed bus, with its high real-time capability, handles register data transfer between the CPU and FPGA, and data transfer between the FPGA and memory chips / non-volatile memory chips.

[0044] like Figure 2 The figure shows a schematic diagram of data distribution in the CPU of this invention; the figure illustrates the distribution of fast cycle and slow cycle data in the CPU memory.

[0045] Figure 3This is a schematic diagram of the data distribution in the memory chip under the FPGA of this invention. The memory under the FPGA is divided into data area A and data area B. The data distribution is the same as the data size and relative position in the CPU memory. The last position of the data is marked with a flag indicating whether the fast cycle and slow cycle data backup is complete, and a timestamp. If the data backup is complete, the data backup completion flag is set, and the timestamp of the backup completion is recorded. To address the issue of fast cycle or slow cycle data integrity during abnormal resets, the data area A and data area B in this invention are exactly the same size and distribution, used to alternately save data. That is, if data is written to area A this time, it will be written to area B next time; if data is written to area B this time, it will be written to area A next time, and so on. Because data area A and data area B alternately save data, only one area is completed before switching to the other area. Therefore, the data area not currently in use is the complete data area. Thus, the solution proposed in this invention does not have the situation where data area A and data area B are not completed at the same time. That is, at least one area of ​​fast cycle data is complete, and similarly, at least one area of ​​slow cycle data is complete. When data needs to be restored, first read the data backup completion marker. If one area is marked as complete and the other is marked as incomplete, select the complete area for data restoration; if both areas are marked as incomplete, compare the timestamps and select the data with the most recent timestamp for restoration.

[0046] Figure 4 This is a schematic diagram of the low-speed bus communication between the CPU and FPGA in this invention. The CPU writes commands to the corresponding registers via the low-speed bus, with fast cycle and slow cycle corresponding to different register addresses. If a fast cycle command is received, it is cached in the fast cycle queue; if a slow cycle command is received, it is cached in the slow cycle queue. The depth of the fast cycle queue is not less than the number of fast cycle data areas in the CPU memory, and the depth of the slow cycle queue is not less than the number of slow cycle data areas in the CPU memory. The FPGA reads commands from the cache queue, parses the required data length and the address of the data in the CPU memory, and reads the data of the corresponding address and length via the high-speed bus.

[0047] Figure 5 This is a schematic diagram illustrating the command format consisting of the data length of the CPU's data area and the base address of the memory containing the data, as described in this invention. After the CPU completes calculations for each data area, it assembles the data length and the base address of the memory containing the data into a command, which is then sent to the corresponding register within the FPGA via a low-speed bus. Figure 5 This refers to the command format.

[0048] Figure 6 This is a flowchart of the FPGA cyclic monitoring fast-cycle command queue and slow-cycle command queue in this invention;

[0049] The FPGA continuously monitors the fast-cycle command queue and the slow-cycle command queue. When the fast-cycle command queue is not empty, the FPGA reads a fast-cycle command, verifies its correctness, and discards it if it is incorrect. If correct, it parses the base address and length of the data in the CPU memory from the command and passes these two parameters to the high-speed bus interface. Upon receiving these two parameters, the high-speed bus interface initiates a read operation command to read the data into the memory chip under the FPGA. After completion, it continues to check if the fast-cycle command queue is empty. If not empty, it continues to execute the data read operation until the fast-cycle command queue is found to be empty. When the fast-cycle command queue is empty, the FPGA checks the slow-cycle command queue. If empty, it checks the fast-cycle command queue. If not empty, it reads a slow-cycle command, verifies its correctness, and discards it if it is incorrect. If correct, it parses the data base address and length and passes them to the high-speed bus. The high-speed bus reads the data and puts it into the memory chip under the FPGA. After execution, it checks the fast-cycle command queue.

[0050] Fast cycle commands have the highest priority, so when a fast cycle command needs to be executed, the FPGA will execute the fast cycle command first, increasing the detection frequency of the fast cycle command queue. After each slow cycle command is executed, the FPGA will start detecting from the fast cycle command queue; after each fast cycle command is executed, the FPGA will also start detecting from the fast cycle command queue. This increases the detection frequency of the fast cycle queue and ensures timely response to fast cycle data reads.

[0051] Figure 7 This is a flowchart of the full data backup method for the fast and slow operation cycles of the industrial controller in this invention. The backup power supply area powers the FPGA, memory chips, and non-volatile memory chips. The backup power supply and the main power supply switch seamlessly. When the FPGA detects a main power failure, it initiates a data backup operation and then disconnects the backup power supply. When an active backup command is received, the FPGA also initiates a data backup operation and reports the data backup as complete.

[0052] Figure 8 This is a flowchart of the data recovery method in this invention. When the controller starts up after a power failure, when it is time to recover data, the CPU starts the FPGA recovery program by writing to the register via the low-speed bus. The FPGA reads the storage status area of ​​the power-down non-volatile memory chip, reads data starting from the address with the latest timestamp, and writes the read data into the corresponding memory of the CPU to achieve the effect of data recovery.

[0053] When the controller recovers data without power failure, the CPU starts the FPGA recovery program by writing to the register via the low-speed bus. The FPGA reads the fast and slow cycle data integrity flags and timestamps from the data A and data B areas of its underlying memory chip. By comparing the integrity flags and timestamps, the latest fast and slow cycle integrity data is found, and the data is written to the CPU's memory via the high-speed bus, thus achieving the effect of data recovery.

[0054] In existing controller technologies, when unstable operation or a system crash, a reset and restart can render the data in memory unreliable. If, after restarting, configuration and algorithm data need to be reloaded, the data lost during computation cannot be recovered, leading to sudden control changes and potentially serious accidents. Therefore, controllers need to back up all data as much as possible and be able to restore all data upon restart or manual operation. Controller memory exists in two operating states: fast and slow cycles. However, their presence in memory is determined by configuration parameters and is not continuous. Furthermore, calculations within each computation cycle are not continuous. Therefore, in the event of an anomaly, the computation cycle may not be exactly complete. When calculations are not exactly complete, there are data points in memory that have been calculated but not yet completed. Recovering such data is not practically meaningful; what needs to be recovered is the memory data that has completed calculations for all points. Therefore, it is necessary to recover the data from the previous computation cycle.

[0055] This invention employs a dual data area for data backup. Each area is the same size and contains data for both fast and slow cycles. Each area's fast and slow data is marked with a completion flag and a timestamp. When backup is needed, the completion flag of each area is read first, and the completed data is used preferentially. If both are marked as completed, the data with the larger timestamp is selected. This invention can achieve full data backup for the controller's fast and slow cycles and can separately restore complete data for each cycle.

[0056] This invention employs two power supplies: a primary power supply and a backup power supply. The primary power supply powers the entire device, while the backup power supply is a low-energy power supply within the controller that can power the FPGA, memory, and non-volatile memory chip. When the entire device experiences a power failure, the backup power supply can power the FPGA to complete the data transfer from memory to the non-volatile memory chip. After the data backup is complete, the FPGA can actively disconnect the backup power supply.

[0057] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0058] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems or apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0059] It should be understood that in this invention, "at least one (item)" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0060] It should also be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0061] The steps of the methods or algorithms described in conjunction with the embodiments disclosed in this invention can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0062] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this invention may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An industrial controller fast and slow operating cycle full data backup method, characterized by, This includes: FPGA detection of whether the main power supply has failed or a backup command has been received; If present, the FPGA writes the latest fast-cycle integrity data to the power-down non-volatile memory chip by comparing the integrity flags and timestamps of the fast-cycle data in data area A and data area B of the memory chip. Then, the FPGA compares the integrity markers and timestamps of the slow-cycle data in data area A and data area B of the memory chip, and writes the latest slow-cycle integrity data to the power-down non-volatile memory chip. The CPU writes commands to the corresponding registers via the low-speed bus. The fast cycle and slow cycle correspond to registers at different addresses. If a fast cycle command is received, it is cached in the fast cycle queue. If a slow cycle command is received, it is swapped into the slow cycle queue. The FPGA continuously monitors the fast-cycle command queue and the slow-cycle command queue. When it detects that the fast-cycle command queue is not empty, the FPGA reads a fast-cycle command, verifies the correctness of the command, and discards it if it is incorrect. If correct, the base address and length of the data in the CPU memory are parsed from the command and passed to the high-speed bus interface. Upon receiving these two parameters, the high-speed bus interface initiates a read operation command to read the data into the memory chip under the FPGA. After completion, it continues to check whether the fast cycle command queue is empty. If it is not empty, it continues to execute the data read operation until the fast cycle command queue is found to be empty. When the fast cycle command queue is empty, the FPGA checks the slow cycle command queue. If it is empty, it checks the fast cycle command queue. If not empty, read a slow-cycle command once, verify that the command is correct, and discard it if it is incorrect; If the data base address and length are correctly resolved, they are handed over to the high-speed bus. The high-speed bus reads the data and puts it into the memory chip under the FPGA. After execution, the fast cycle command queue is checked.

2. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 1, characterized in that, The FPGA detects whether there is a main power failure or a backup command has been received. If a main power failure is detected, the FPGA uses the backup power supply and shuts down the backup power supply after the slow cycle data is written to the power-loss non-volatile memory chip. If a backup command is received, the FPGA reports that the backup is complete after the slow cycle data is written to the power-loss non-volatile memory chip.

3. A method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 1 or 2, characterized in that, The main power supply powers the entire board, while the backup power supply only powers the FPGA, memory chips, and non-volatile memory chips. The CPU is responsible for communication and computing tasks, while the FPGA is responsible for data backup and recovery. The CPU and FPGA communicate using a high-speed bus and a low-speed bus. The high-speed bus is responsible for data transfer that needs to be saved, while the low-speed bus is responsible for register data transfer between the CPU and FPGA. Data transfer also occurs between the FPGA and the memory chips and non-volatile memory chips.

4. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 3, characterized in that, High-speed buses include parallel LVDS or serial Aurora, SRIO, and PCIe; Low-speed buses include SPI, LIO, and UART.

5. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 3, characterized in that, The memory chip is a DDR chip, and the non-volatile storage chips that lose power include flash memory and SD cards.

6. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 3, characterized in that, The memory chip is divided into data area A and data area B. The data distribution in data area A and data area B is the same as the data size and relative position in the CPU memory. The last position of the data in data area A and data area B is marked with a fast cycle and a slow cycle data backup completion flag and a timestamp. If the data backup is complete, the data backup completion flag will be set and the backup completion timestamp will be recorded.

7. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 6, characterized in that, The depth of the fast cycle queue is no less than the number of data blocks in the fast cycle data area of ​​the CPU memory, and the depth of the slow cycle queue is no less than the number of data blocks in the slow cycle data area of ​​the CPU memory. The FPGA reads commands from the cache queue, parses the length of the data to be read and the address of the data in the CPU memory, and reads the data of the corresponding address and length through the high-speed bus.

8. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 7, characterized in that, After the CPU completes the calculation of a data block, it combines the data length and the base address of the memory containing the data into a command and sends it to the corresponding register in the FPGA via a low-speed bus.

9. The method for full data backup of fast and slow operation cycles of an industrial controller as described in claim 8, characterized in that, When the controller restarts after a power outage, when it reaches the data recovery stage, the CPU starts the FPGA recovery program by writing to the register via the low-speed bus. The FPGA reads the storage status area of ​​the non-volatile memory chip after the power outage, starting from the address with the latest timestamp, and writes the read data into the corresponding memory of the CPU, thus achieving the data recovery effect. When the controller recovers data without a power outage, the CPU starts the FPGA recovery program by writing to the register via the low-speed bus. The FPGA reads the fast and slow cycle data integrity flags and timestamps from data areas A and B of its underlying memory chip, finds the latest fast and slow cycle integrity data by comparing the integrity flags and timestamps, and writes the data into the CPU's memory via the high-speed bus, thus achieving the data recovery effect.

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