Display device

Abstract

The present invention relates to a display device capable of improving image quality, comprising: a display panel; a first gate line and a second gate line disposed on the display panel; and a gate driving section to which the first gate line and the second gate line are connected. The number of pixels connected with the first gate line is less than the number of pixels connected with the second gate line. The gate driving portion includes: a first stage connected to the first gate line through a first output electrode; and a second stage connected to the second gate line through a second output electrode. Comprising a first compensation capacitor connected with the first output electrode and a second compensation capacitor connected with the second output electrode, and the capacity of the first compensation capacitor is larger than that of the second compensation capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device, and more particularly, to a display device capable of improving image quality. BACKGROUND

[0002] An organic light emitting display apparatus includes a display element whose luminance changes with current, for example, an organic light emitting diode. SUMMARY

[0003] An object of the present application is to provide a display device capable of improving image quality.

[0004] The object of the present application is not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0005] A display device according to an embodiment of the present application for achieving the above object includes a display panel, first and second gate lines disposed on the display panel, and a gate driving portion to which the first and second gate lines are connected. The number of pixels connected to the first gate line is less than the number of pixels connected to the second gate line. The gate driving portion includes a first stage connected to the first gate line through a first output electrode and a second stage connected to the second gate line through a second output electrode. A first compensation capacitor connected to the first output electrode and a second compensation capacitor connected to the second output electrode are included, and the capacity of the first compensation capacitor is greater than the capacity of the second compensation capacitor.

[0006] The length of the first gate line is greater than the length of the second gate line.

[0007] The first and second compensation capacitors are disposed in a non-display area of the display panel.

[0008] The first and second compensation capacitors are disposed in a non-display area between the gate driving portion and a display area of the display panel.

[0009] The first compensation capacitor includes a first-1 capacitor electrode connected to the first output electrode and a first-2 capacitor electrode connected to a power supply line and overlapping the first-1 capacitor electrode.

[0010] The power supply line transmits a direct current voltage.

[0011] The second compensation capacitor includes a 2-1 capacitor electrode connected to the second output electrode, and a 2-2 capacitor electrode connected to the power supply line and overlapping the 2-1 capacitor electrode.

[0012] The 1-1 capacitor electrode of the first compensation capacitor has a larger area than the 2-1 capacitor electrode of the second compensation capacitor.

[0013] The 1-2 capacitor electrode of the first compensation capacitor has a larger area than the 2-2 capacitor electrode of the second compensation capacitor.

[0014] The capacity of the first compensation capacitor is larger than the capacity of the second compensation capacitor, so that the load of the first stage connected to the first gate line and the load of the second stage connected to the second gate line are the same.

[0015] A third gate line adjacent to the first gate line is further included, and the gate driving part further includes a third stage connected to the third gate line through a third output electrode, the number of pixels connected to the third gate line being the same as the number of pixels connected to the first gate line.

[0016] The length of the third gate line is the same as the length of the first gate line.

[0017] A third compensation capacitor connected to the third output electrode is further included.

[0018] The first gate line is disposed between the second gate line and the third gate line.

[0019] The capacity of the third compensation capacitor is the same as the capacity of the first compensation capacitor.

[0020] The capacity of the third compensation capacitor is smaller than the capacity of the first compensation capacitor.

[0021] The display panel includes a display area in which the first gate line and the second gate line are disposed, and a non-display area in which the gate driving part is disposed.

[0022] The display area includes a first sub-display area and a second sub-display area having different sizes.

[0023] The length of the first gate line is larger than the length of the second gate line, and the length of the first sub-display area is larger than the length of the second sub-display area.

[0024] The first gate line is disposed in the first sub-display area, and the second gate line is disposed in the second sub-display area.

[0025] Details of other embodiments are included in the detailed description and drawings.

[0026] (Effects of the Invention)

[0027] According to the display device of the present invention, the image quality of the display device can be improved by using the compensation capacitor.

[0028] In addition, the effects that can be obtained by the present invention are not limited to the effects mentioned above, and those skilled in the art can clearly understand other effects that are not mentioned from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 FIG. 1 is a top view of a display device according to an embodiment.

[0030] Figure 2 FIG. 1 is a circuit diagram related to a pixel of a display device according to an embodiment.

[0031] Figure 3 This is a detailed diagram of the gate drive unit.

[0032] Figure 4 It is a detailed structural diagram of a stage of an embodiment.

[0033] Figure 5 This is a diagram showing an array of stages according to one embodiment.

[0034] Figure 6 is only selectively shown Figure 5 Figure 2 shows the active layer and gate electrode layer in the CMOS process.

[0035] Figure 7 is only selectively shown Figure 5 Figure 1 shows a diagram of the first output electrode and the first capacitor electrode.

[0036] Figure 8 is only selectively shown Figure 5 FIG. 1 shows a diagram of a second power line and a second capacitor electrode in FIG.

[0037] Figure 9 It is along Figure 5 A cross-sectional view taken along line II'.

[0038] Figure 10 This is a diagram for explaining the capacitance of the compensation capacitor in the first sub-display area and the second sub-display area.

[0039] Figure 11 This is a diagram for explaining a first storage capacitor electrode according to an embodiment.

[0040] Figure 12 This is a diagram for explaining a second storage capacitor electrode according to an embodiment.

[0041] Figure 13 FIG. 1 is a top view of a display device according to an embodiment.

[0042] Figure 14 This is a diagram for explaining the size relationship of capacitor electrodes according to one embodiment.

[0043] Figure 15 This is a diagram for explaining the size relationship of capacitor electrodes according to one embodiment.

[0044] Figure 16 A diagram for explaining the effects of a display device according to an embodiment.

[0045] Description of Reference Signs

[0046] VDDL: second drive voltage; CE1: first capacitor electrode; CE2: second capacitor electrode; STG1: first stage; STG3: third stage; OE1: first output electrode; OE3: third output electrode; Ccp1: first compensation capacitor; Ccp3: third compensation capacitor; GL1: first gate line; GL3: third gate line; GCL1: first control gate line; GCL3: third control gate line; SDA1: first sub-display area; SDA2: second sub-display area; DR1: first direction; DR2: second direction; DR3: third direction; L1, L3, LL1, LL3: length DETAILED DESCRIPTION

[0047] By attaching Figure 1 The advantages, features, and methods of implementing the present invention can be clearly understood by referring to the embodiments described in detail below. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in a variety of different ways. However, these embodiments are provided to fully disclose the present invention and to fully inform those skilled in the art of the art to which the present invention belongs. The present invention is defined solely by the scope of the appended claims.

[0048] If an element or layer is described as being "on" another element or layer, this includes the case where it is directly disposed on the other element or other elements are disposed therebetween. Throughout the specification, the same reference numerals refer to the same components. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings used to illustrate the embodiments are merely illustrative and are not intended to limit the present invention.

[0049] Although first, second, and the like are used to describe various constituent elements, the constituent elements are obviously not limited by the terms. The terms are used only to distinguish one constituent element from another. Thus, the first constituent element mentioned below can obviously be the second constituent element within the technical idea of the present application.

[0050] Various features of various embodiments of the present application can be partially or wholly combined or coupled with each other or can be combined, and various linkages and drives can be technically realized, and each embodiment can be implemented independently or in association with each other.

[0051] Specific embodiments will be described below with reference to the accompanying drawings.

[0052] Figure 1 FIG. 1 is a plan view of a display device according to an embodiment.

[0053] Referring to FIG. 1, Figure 1 The display device 10 according to an embodiment can be a device that displays dynamic images or static images. The display device 10 according to an embodiment can be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic book, a portable multimedia player (PMP), a navigation, an ultra mobile PC (UMPC), or the like. For example, the display device 10 according to an embodiment can be used as a display of a television, a notebook computer, a monitor, an advertisement board, or an Internet of Things (IOT). Alternatively, the display device 10 according to an embodiment can be used for a smart watch, a watch phone, a head mounted display (HMD) for implementing virtual reality and augmented reality.

[0054] The display device 10 according to an embodiment can include a display panel 100, a gate driving part GD, an emission driving part ED, and a data driving part DD.

[0055] The display panel 100 can be formed in a planar shape similar to a quadrangle. For example, the display panel 100 can have a planar shape similar to a quadrangle having a side in a first direction DR1 and a side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where the side in the first direction DR1 and the side in the second direction DR2 meet can be formed with an arc having a prescribed curvature or formed at a right angle. The planar shape of the display panel 100 is not limited to a quadrangle, but can be formed similar to other polygons, a circle, or an ellipse. The planar shape of the display apparatus 10 can follow the planar shape of the display panel 100, but embodiments of the present specification are not limited thereto.

[0056] The display panel 100 can include a display area DA in which an image is displayed and a non-display area NDA surrounding the display area.

[0057] In the display area DA, a plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of emission control lines EML can be disposed.

[0058] Each of the plurality of pixels PX can include an emission element that emits light. The plurality of pixels PX can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of gate lines and the plurality of emission control lines can extend along the first direction DR1 and be disposed along the second direction DR2. The plurality of data lines DL can extend along the second direction DR2 and be disposed along the first direction DR1.

[0059] The plurality of gate lines GL can include a plurality of write gate lines, a plurality of control gate lines, a plurality of initialization gate lines, a plurality of bias gate lines.

[0060] Each of the plurality of pixels PX can be connected to one of the plurality of write gate lines, one of the plurality of control gate lines, one of the plurality of initialization gate lines, one of the plurality of bias gate lines, one of the plurality of emission control lines EML, and one of the plurality of data lines DL. Each of the plurality of pixels PX can receive a data voltage of the data line DL according to a write gate signal from the write gate line GWL and cause the emission element to emit light according to the data voltage from the data line.

[0061] The display region DA can include, for example, a first sub-display region SDA1 and a second sub-display region SDA2. The gate lines GL can be separately arranged in the first sub-display region SDA1 and the second sub-display region SDA2. Where one of the gate lines of the first sub-display region SDA1 is defined as a first gate line and one of the gate lines of the second sub-display region SDA2 is defined as a second gate line, the number of pixels PX connected to the first gate line can be different from the number of pixels PX connected to the second gate line. For example, the number of pixels PX connected to the first gate line can be less than the number of pixels PX connected to the second gate line.

[0062] The gate lines GL (e.g., the first gate lines) of the first sub-display region SDA1 can have the same length, and the gate lines GL (e.g., the second gate lines) of the second sub-display region SDA2 can have the same length.

[0063] The first sub-display region SDA1 and the second sub-display region SDA2 can have different sizes. For example, in the first direction DR1, the first sub-display region SDA1 can have a smaller length than the second sub-display region SDA2. Thus, in the first direction DR1, the length of the gate lines GL in the first sub-display region SDA1 can be less than the length of the gate lines GL in the second sub-display region SDA2. For example, the first gate lines (e.g., the first gate lines) of the first sub-display region SDA1 described above can have a smaller length than the second gate lines (e.g., the second gate lines) of the second sub-display region SDA2. Likewise, in the first direction DR1, the length of the emission control lines EML in the first sub-display region SDA1 can be less than the length of the emission control lines EML in the second sub-display region SDA2.

[0064] The non-display region NDA can be configured with a gate drive portion GD connected with the gate lines GL, an emission drive portion ED, and a data drive portion DD connected with the data lines DL.

[0065] The gate drive portion GD can include a write gate signal output portion that outputs a plurality of write gate signals and sequentially supplies the plurality of write gate signals to a plurality of write gate lines, a control gate signal output portion that outputs a plurality of control gate signals and sequentially supplies the plurality of control gate signals to a plurality of control gate lines, an initialization gate signal output portion that outputs a plurality of initialization gate signals and sequentially supplies the plurality of initialization gate signals to a plurality of initialization gate lines, and a bias gate signal output portion that outputs a plurality of bias gate signals and sequentially supplies the plurality of bias gate signals to a plurality of bias gate lines.

[0066] The emission drive portion ED can output a plurality of emission control signals and sequentially supply the plurality of emission control signals to a plurality of emission control lines EML.

[0067] The data driving section DD can convert digital video data into an analog data voltage and output to the data line DL. In this case, the pixel is selected by the write gate signal of the gate driving section GD, and the data voltage can be supplied to the selected pixel.

[0068] A first through-hole 21, a second through-hole 22, and a third through-hole 23 that penetrate the display panel 100 along the third direction DR3 can be provided at one side edge of the display panel 100. At least one electronic component can be provided at the first through-hole 21, the second through-hole 22, and the third through-hole 23. The electronic component can be an electronic element that uses light or sound. For example, the electronic element can be a sensor that measures a distance such as a proximity sensor, a sensor that identifies a part of a user's body such as a fingerprint, an iris, a face, or the like, a small light bulb that outputs light, or an image sensor such as a camera that captures an image, or the like. The electronic element that uses light can use light of various wavelength bands such as visible light, infrared light, ultraviolet light, or the like. The electronic element that uses sound can use sound of an ultrasonic wave or another frequency band. In some embodiments, the electronic component can include a sub-component such as a light emitting portion and a light receiving portion. One pair of the light emitting portion and the light receiving portion constitutes one electronic component, and the light emitting portion and the light receiving portion can be an integrated structure or a physically separated structure.

[0069] Figure 2 is a circuit diagram related to one pixel PX of the display device of an embodiment. For example, Figure 2 may be Figure 1 a circuit diagram related to the pixel PX.

[0070] As Figure 2 illustrated, the pixel PX can be connected to a write gate line GWL, a control gate line GCL, an initialization gate line GIL, a bias gate line EBL, an emission control line EML, a data line DL, a driving voltage line VDL, a common voltage line VSL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0071] The pixel PX can include a pixel circuit PC and a light emitting element LEL. The pixel circuit PC can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor Cst.

[0072] The first transistor T1 can include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 can control a source-drain current (hereinafter, a driving current) according to a data voltage applied to the gate electrode. The driving current (e.g., Isd) flowing through a channel region of the first transistor T1 can be proportional to the square of a difference between a voltage Vsg between the source electrode and the gate electrode of the first transistor T1 and a threshold voltage Vth (Isd = k x (Vsg - Vth) 2 ). Here, k denotes a proportional coefficient determined by a structure and physical properties of the first transistor T1, Vsg denotes a source-gate voltage of the first transistor T1, and Vth denotes a threshold voltage of the first transistor T1.

[0073] The light emitting element LEL can receive the driving current Isd and emit light. An amount of light emission or luminance of the light emitting element LEL can be proportional to a magnitude of the driving current Isd.

[0074] The light emitting element LEL can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. As another example, the light emitting element LEL can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. As still another example, the light emitting element LEL can be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. As still another example, the light emitting element LEL can be a micro light emitting diode.

[0075] The first electrode of the light emitting element LEL can be electrically connected to the fourth node N4. The first electrode of the light emitting element LEL can be connected to the drain electrode of the sixth transistor T6 and the source electrode of the seventh transistor T7 through the fourth node N4. The second electrode of the light emitting element LEL can be connected to the common voltage line VSL. The second electrode of the light emitting element LEL can receive a common voltage VS (e.g., a low potential voltage) from the common voltage line VSL.

[0076] The second transistor T2 can be turned on by a write gate signal GW of the write gate line GWL and electrically connect the data line DL and the first node N1 which is the source electrode of the first transistor T1. The second transistor T2 can be turned on based on the write gate signal GW, thereby supplying the data voltage to the first node N1. The gate electrode of the second transistor T2 can be electrically connected to the write gate line GWL, the source electrode can be electrically connected to the data line DL, and the drain electrode can be electrically connected to the first node N1.

[0077] The third transistor T3 can be turned on by the control gate signal GC of the control gate line GCL and electrically connect the second node N2 which is the drain electrode of the first transistor T1 and the third node N3 which is the gate electrode of the first transistor T1. The third transistor T3 can be connected between the third node N3 and the second node N2. For example, the gate electrode of the third transistor T3 can be electrically connected with the control gate line GCL, the source electrode can be electrically connected with the third node N3, and the drain electrode can be electrically connected with the second node N2. The third transistor T3 can be turned on by the control gate signal GC of the control gate line GCL and electrically connect the second node N2 which is the drain electrode of the first transistor T1 and the third node N3 which is the gate electrode of the first transistor T1. The third transistor T3 can be a dual gate transistor having two gate electrodes (for example, a gate electrode and an opposite gate electrode). The gate electrode and the opposite gate electrode can be configured face to face in different layers. The third transistor T3 can be turned on by the control gate signal GC and connected with the pixel circuit PC in a diode manner.

[0078] The fourth transistor T4 can be turned on by the initialization gate signal GI of the initialization gate line GIL and electrically connect the third node N3 which is the gate electrode of the first transistor T1 and the first initialization voltage line VIL1. The fourth transistor T4 can be connected in series between the third node N3 and the first initialization voltage line VIL1. For example, the gate electrode of the fourth transistor T4 can be electrically connected with the initialization gate line GIL, the source electrode can be electrically connected with the third node N3, and the drain electrode can be electrically connected with the first initialization voltage line VIL1. The fourth transistor T4 can be a dual gate transistor. The first initialization voltage line VIL1 can transmit the first initialization voltage VI1.

[0079] The fifth transistor T5 can be turned on by the emission control signal EM of the emission control line EML and electrically connect the drive voltage line VDL and the first node N1 which is the source electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be electrically connected with the emission control line EML, the source electrode can be electrically connected with the drive voltage line VDL, and the drain electrode can be electrically connected with the first node N1. The drive voltage line VDL can transmit the drive voltage VD.

[0080] The sixth transistor T6 can be turned on by the emission control signal EM of the emission control line EML and electrically connect the second node N2 which is the drain electrode of the first transistor T1 and the fourth node N4 which is the first electrode of the light emitting element LEL. The gate electrode of the sixth transistor T6 can be electrically connected with the emission control line EML, the source electrode can be electrically connected with the second node N2, and the drain electrode can be electrically connected with the fourth node N4.

[0081] In a case where the fifth transistor T5, the first transistor T1, and the sixth transistor T6 are all turned on, a drive current can be supplied to the light emitting element LEL.

[0082] The seventh transistor T7 can be turned on by the bias gate signal EB of the bias gate line EBL, and electrically connect the fourth node N4 which is the first electrode of the light emitting element LEL and the second initialization voltage line VIL2. The seventh transistor T7 is turned on based on the bias gate signal EB, thereby discharging the first electrode of the light emitting element LEL with the second initialization voltage VI2. The gate electrode of the seventh transistor T7 can be electrically connected with the bias gate line EBL, the source electrode can be electrically connected with the fourth node N4, and the drain electrode can be electrically connected with the second initialization voltage line VIL2. The second initialization voltage line VIL2 can transmit the second initialization voltage VI2.

[0083] The eighth transistor T8 can be turned on by the bias gate signal EB of the bias gate line EBL, and electrically connect the bias voltage line VBL and the first node N1 which is the source electrode of the first transistor T1. The eighth transistor T8 is turned on based on the bias gate signal EB, and can supply the bias voltage VB to the first node N1. The eighth transistor T8 can improve the hysteresis of the first transistor T1 by supplying the bias voltage VB to the source electrode of the first transistor T1. The gate electrode of the eighth transistor T8 can be electrically connected with the bias gate line EBL, the source electrode can be electrically connected with the bias voltage line VBL, and the drain electrode can be electrically connected with the first node N1.

[0084] Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can include a silicon-based active layer. For example, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be a p-type transistor including an active layer composed of low temperature polysilicon (LTPS). The active layer composed of low temperature polysilicon can have high electron mobility and excellent on characteristics. Accordingly, the display device 10 can stably and efficiently drive a plurality of pixels PX by including transistors having excellent on characteristics. Each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 outputs a current flowing into the source electrode to the drain electrode based on a gate low voltage applied to the gate electrode.

[0085] The third transistor T3 and the fourth transistor T4 can be n-type transistors including an oxide-based active layer. The transistor including the oxide-based active layer can have a coplanar structure in which a gate electrode is disposed on an upper portion. The transistor including the oxide-based active layer can output a current flowing into a drain electrode to a source electrode on the basis of a gate high voltage applied to the gate electrode.

[0086] The capacitor Cst can be electrically connected between the third node N3 which is a gate electrode of the first transistor T1 and the drive voltage line VDL. For example, a first electrode of the capacitor Cst can be electrically connected with the third node N3, and a second electrode of the capacitor Cst can be electrically connected with the drive voltage line VDL, so that a potential difference between the drive voltage line VDL and the gate electrode of the first transistor T1 can be maintained.

[0087] Figure 3 is a detailed structure diagram of the gate driving part GD. For example, Figure 3 may be a detailed driving diagram of the control gate signal output part of the gate driving part GD.

[0088] As shown in Figure 3 , the gate driving part GD can include a plurality of stages STG1-STG4.

[0089] Each stage STG1-STG4 can be set according to a gate signal from an upper stage. The set stage can output a clock signal CK from the clock line CLL as a gate signal. For example, the second stage STG2 can be set according to the first gate signal GS1 from the first stage STG1 and then output the clock signal CK from the clock line CLL as the second gate signal GS2. The third stage STG3 can be set according to the second gate signal GS2 from the second stage STG2 and then output the clock signal CK from the clock line CLL as the third gate signal GS3. The fourth stage STG4 can be set according to the third gate signal GS3 from the third stage STG3 and then output the clock signal CK from the clock line CLL as the fourth gate signal GS4.

[0090] The clock line CLL can be configured in a plurality. The plurality of clock lines CLL can transmit a plurality of clock signals CK having different phases from each other.

[0091] In addition, the first stage STG1 can be set by a start signal SP from a start line.

[0092] The plurality of stages STG1-STG4 can be connected to a plurality of gate lines, respectively. For example, the first output electrode OE1 of the first stage STG1 can be connected to a first gate line (e.g., a first control gate line), the second output electrode OE2 of the second stage STG2 can be connected to a second gate line (e.g., a second control gate line), the third output electrode OE3 of the third stage STG3 can be connected to a third gate line (e.g., a third control gate line), and further, the fourth output electrode OE4 of the fourth stage STG4 can be connected to a fourth gate line (e.g., a fourth control gate line).

[0093] At this time, the output electrodes of the stages STG1-STG4 can be further connected to a next stage. For example, the first output electrode OE1 of the first stage STG1 can be connected to the second stage STG2, the second output electrode OE2 of the second stage STG2 can be connected to the third stage STG3, the third output electrode OE3 of the third stage STG3 can be connected to the fourth stage STG4, and further, the fourth output electrode OE4 of the fourth stage STG4 can be connected to a fifth stage.

[0094] The gate signal provided to the gate line can drive the gate line, and the gate signal provided to the next stage can drive the next stage. For example, the gate signal provided to the next stage can set (or enable) the next stage.

[0095] The output electrodes of the stages can be connected to compensation capacitors. For example, the first output electrode OE1 of the first stage STG1 can be connected to a first compensation capacitor Ccp1, the second output electrode OE2 of the second stage STG2 can be connected to a second compensation capacitor Ccp2, the third output electrode OE3 of the third stage STG3 can be connected to a third compensation capacitor Ccp3, and further, the fourth output electrode OE4 of the fourth stage STG4 can be connected to a fourth compensation capacitor Ccp4.

[0096] The compensation capacitors can have different capacitances according to different sub-display regions. For example, a stage for driving a gate line of a first sub-display region SDA1 can be connected to a compensation capacitor having a larger capacitance than a stage for driving a gate line of a second sub-display region SDA2. In other words, a stage for driving a relatively short gate line can be connected to a compensation capacitor having a larger capacitance than a stage for driving a relatively long gate line. For example, when the sub-display region SDA1 is a sub-display region SDA1-1, the stage STG1 can be connected to the compensation capacitor Ccp1 having a larger capacitance than the compensation capacitor Ccp2 connected to the stage STG2. Figure 3The first stage STG1 and the second stage STG2 of the first sub display area SDA1 are connected to the gate lines of the first sub display area SDA1, respectively. Figure 3 When the third stage STG3 and the fourth stage STG4 of the second sub display area SDA2 are connected to the gate lines of the second sub display area SDA2, respectively, the capacity of the first compensation capacitor Ccp1 connected to the first output electrode OE1 of the first stage STG1 can be greater than the capacity of the third compensation capacitor Ccp3 connected to the third output electrode OE3 of the third stage STG3. At this time, the capacity of the second compensation capacitor Ccp2 connected to the second output electrode OE2 of the second stage STG2 can be the same as the capacity of the first compensation capacitor Ccp1, and the capacity of the fourth compensation capacitor Ccp4 connected to the fourth output electrode OE4 of the fourth stage STG4 can be the same as the capacity of the third compensation capacitor Ccp3.

[0097] As described above, since the compensation capacitor connected to the gate line with a smaller number of pixels (e.g., the first gate line) has a greater capacity than the compensation capacitor connected to the gate line with a greater number of pixels (e.g., the second gate line), the load of the stage connected to the first gate line can be substantially the same as the load of the stage connected to the second gate line. For example, the stage connected to a greater number of pixels (e.g., the first stage connected to the first gate line) can have a greater load than the stage connected to a smaller number of pixels (e.g., the second stage connected to the second gate line), as described above, since the compensation capacitor connected to the output electrode of the first stage has a greater capacity than the compensation capacitor connected to the output electrode of the second stage, the first stage and the second stage can have substantially the same load. In other words, the capacities of the compensation capacitor connected to the first stage and the compensation capacitor connected to the second stage can be set to be different so that the loads of the first stage and the second stage connected to different numbers of pixels are the same. Accordingly, the luminance deviation between the first sub display area SDA1 and the second sub display area SDA2 can be reduced, and thus the image quality of the display device can be improved.

[0098] In other words, since the compensation capacitor connected to the gate line with a shorter length has a greater capacity than the compensation capacitor connected to the gate line with a longer length, the load of the stage connected to the shorter gate line can be substantially the same as the load of the stage connected to the longer gate line. Accordingly, the luminance deviation between the first sub display area SDA1 and the second sub display area SDA2 can be reduced, and thus the image quality of the display device can be improved.

[0099] Figure 4 is a detailed configuration diagram of the stage of an embodiment. For example, Figure 4 may be Figure 3 is a detailed configuration diagram of the first stage STG1.

[0100] The first-stage STG1 can include a node control section NC that controls the voltage of the nodes (e.g., the first node N11, the second node N12, the third node N13, and the fourth node N14) and an output section OT connected to the node control section NC.

[0101] The node control section NC can include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a first capacitor Cb1, a second capacitor Cb2, and a third capacitor Cb3.

[0102] The output section OT can include a ninth transistor M9 and a tenth transistor M10.

[0103] The first transistor M1 can include a gate electrode connected to a first clock line CLL1. The first transistor M1 can be connected between a start line STL and the second node N12. In addition, the gate electrode of the first transistor M1 of the stage below the second-stage STG2 can be connected to the output electrode of the upper stage that is not the start line STL. For example, the first transistor M1 of the second-stage STG2 can be connected between the first output electrode OE1 of the first-stage STG1 and the sixth node N16 of the second-stage STG2. A first clock signal CLK1 can be applied to the first clock line CLL1.

[0104] The second transistor M2 can include a gate electrode connected to the second node N12. The second transistor M2 can be connected between the third capacitor Cb3 and a second clock line CLL2. A second clock signal CLK2 can be applied to the second clock line CLL2. The second clock signal CLK2 and the first clock signal CLK1 can have different phases from each other.

[0105] The third transistor M3 can include a gate electrode connected to the first clock line CLL1. The third transistor M3 can be connected between a first power line VGL and the fourth node N14.

[0106] The fourth transistor M4 can include a gate electrode connected to the first power line VGL. The fourth transistor M4 can be connected between the fourth node N14 and the third node N13.

[0107] The fifth transistor M5 can include a gate electrode connected to the second node N12. The fifth transistor M5 can be connected between the first clock line CLL1 and the fourth node N14.

[0108] The sixth transistor M6 may include a gate electrode connected to the third node N13. The sixth transistor M6 may be connected between the seventh transistor M7 and the second clock line CLL2.

[0109] The seventh transistor M7 may include a gate electrode connected to the third node N13. The seventh transistor M7 may be connected between the fifth node N15 and the sixth transistor M6.

[0110] The eighth transistor M8 may include a gate electrode connected to the second clock line CLL2 . The eighth transistor M8 may be connected between the fifth node N15 and the first node N11 .

[0111] The ninth transistor M9 may include a gate electrode connected to the first node N11. The ninth transistor M9 may be connected between the first clock line CLL1 and the first output electrode OE1 of the first stage STG1. The first output electrode OE1 of the first stage STG1 may be connected to the first gate line.

[0112] The tenth transistor M10 may include a gate electrode connected to the second node N12 . The tenth transistor M10 may be connected between the first output electrode OE1 of the first stage STG1 and the first power line VGL.

[0113] The eleventh transistor M11 may include a gate electrode connected to the first power line VGL. The eleventh transistor M11 may be connected between the sixth node N16 and the second node N12.

[0114] The twelfth transistor M12 may include a gate electrode connected to the control line CTL. The twelfth transistor M12 may be connected between the first clock line CLL1 and a sixth node N16.

[0115] The thirteenth transistor M13 may include a gate electrode connected to the control line CTL. The thirteenth transistor M13 may be connected between the first node N11 and the first power line VGL.

[0116] The fourteenth transistor M14 may include a gate electrode connected to the second node N12. The fourteenth transistor M14 may be connected between the first clock line CLL1 and the first node N11.

[0117] The first capacitor Cb1 may be connected between the first clock line CLL1 and the first node N11 .

[0118] The second capacitor Cb2 may be connected between the third node N13 and the fifth node N15.

[0119] The third capacitor Cb3 may be connected between the second node N12 and the second transistor M2.

[0120] The output electrodes at each stage can be connected with compensation capacitors. For example, a first compensation capacitor Ccp1 can be connected between the first output electrode OE1 of the first stage STG1 and the second power line VDDL. A first capacitance electrode of the first compensation capacitor Ccp1 can be connected with the first output electrode OE1 of the first stage STG1, and a second capacitance electrode of the first compensation capacitor Ccp1 is connected with the second power line VDDL.

[0121] The first power line VGL can transmit a first drive voltage VSS, and the second power line VDDL can transmit a second drive voltage VDD.

[0122] The first drive voltage VSS and the second drive voltage VDD can be direct current voltages respectively. The second drive voltage VDD can be greater than the first drive voltage VSS.

[0123] Figure 5 is a diagram showing an array of stages of an embodiment. For example, Figure 5 may be a diagram showing the array of the first stage STG1 related to the foregoing Figure 4 . Figure 6 is a diagram showing only the active layer and the gate electrode layer in Figure 5 , Figure 7 is a diagram showing only the first output electrode OE1 and the first capacitance electrode CE1 in Figure 5 , Figure 8 is a diagram showing only the second power line and the second capacitance electrode CE2 in Figure 5 , and Figure 9 is a cross-sectional view taken along the I-I' line of Figure 5 .

[0124] Figure 9The substrate SUB can be a rigid substrate, or a flexible substrate that can achieve bending, folding, rolling, and the like. The substrate SUB can be composed of an insulating substance such as glass, quartz, a high molecular resin, and the like. As examples of the high molecular substance, polyethersulphone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof can be given. Alternatively, the substrate SUB can also include a substance of a metallic material.

[0125] A barrier layer BR can be provided on the substrate SUB. The barrier layer BR can be provided on the entire surface of the substrate SUB. The barrier layer BR can be a film that protects the transistors T1-T8 of the thin film transistor layer TFTL and the light emitting layer EL of the light emitting element layer EMTL from moisture that permeates through the substrate SUB that is vulnerable to moisture penetration. The barrier layer BR can be composed of a plurality of inorganic films that are alternately layered. For example, the barrier layer BR can be formed of a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately layered.

[0126] A buffer layer BF can be provided on the barrier layer BR. The buffer layer BF can be provided on the entire surface of the substrate SUB including the barrier layer BR. The buffer layer BF can be a film that protects the transistors T1-T8 and the light emitting layer of the light emitting element layer from moisture that permeates through the substrate SUB that is vulnerable to moisture penetration. The buffer layer BF can be composed of a plurality of inorganic films that are alternately layered. For example, the buffer layer BF can be formed of a multilayer film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately layered.

[0127] A first active layer ACT1, a second active layer ACT2, a third active layer ACT3, a fourth active layer ACT4, a fifth active layer ACT5, a sixth active layer ACT6, a seventh active layer ACT7, an eighth active layer ACT8, and a ninth active layer ACT9 may be disposed on the buffer layer BF. Figure 9 As shown, the seventh active layer ACT7 may include: a channel region CH9 of a ninth transistor, a ninth source electrode SE9 of the ninth transistor M9, a ninth drain electrode DE9 of the ninth transistor M9, a channel region CH10 of a tenth transistor M10, a tenth source electrode SE10 of the tenth transistor M10, and a tenth drain electrode DE10 of the tenth transistor M10. Each active layer may be an active layer made of low-temperature polysilicon (LTPS).

[0128] A first gate insulating layer may be disposed on the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, the fourth active layer ACT4, the fifth active layer ACT5, the sixth active layer ACT6, the seventh active layer ACT7, the eighth active layer ACT8, and the ninth active layer ACT9. In this case, the first gate insulating layer GTI1 may be disposed on the entire surface of the substrate SUB including the first active layer ACT1, the second active layer ACT2, the third active layer ACT3, the fourth active layer ACT4, the fifth active layer ACT5, the sixth active layer ACT6, the seventh active layer ACT7, the eighth active layer ACT8, and the ninth active layer ACT9. The first gate insulating layer GTI1 may include at least one of tetraethoxysilane (TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). As an example, the first gate insulating layer GTI1 may have a double-layer film structure in which a silicon nitride film having a thickness of 40 nm and a tetraethoxysilane film having a thickness of 80 nm are sequentially stacked.

[0129] A first gate electrode GE1, a second gate electrode GE2, a third gate electrode GE3, a fourth gate electrode GE4, a fifth gate electrode GE5, a sixth gate electrode GE6, a seventh gate electrode GE7, an eighth gate electrode GE8, a ninth gate electrode GE9, a tenth gate electrode GE10, an eleventh gate electrode GE11, a twelfth gate electrode GE12, a thirteenth gate electrode GE13 and a fourteenth gate electrode GE14 can be configured on the first gate insulating layer GTI1.

[0130] The first gate electrode GE1 and the third gate electrode GE3 may be integrally formed, the first gate electrode GE1 may overlap with the first active layer ACT1, and the third gate electrode GE3 may overlap with the third active layer ACT3.

[0131] The second gate electrode GE2, the fifth gate electrode GE5, and the fourteenth gate electrode GE14 can be integrally formed. The second gate electrode GE2 can overlap the second active layer ACT2, the fifth gate electrode GE5 can overlap the third active layer ACT3, and the fourteenth gate electrode GE14 can overlap the third active layer ACT3.

[0132] The sixth gate electrode GE6 and the seventh gate electrode GE7 can be integrally formed. The sixth gate electrode GE6 can overlap the fifth active layer ACT5, and the seventh gate electrode GE7 can overlap the fifth active layer ACT5.

[0133] The eighth gate electrode GE8 can overlap the sixth active layer ACT6.

[0134] The ninth gate electrode GE9 can overlap the seventh active layer ACT7.

[0135] The tenth gate electrode GE10 can overlap the seventh active layer ACT7.

[0136] The eleventh gate electrode GE11 can overlap the eighth active layer ACT8.

[0137] The twelfth gate electrode GE12 can overlap the eighth active layer ACT8.

[0138] The thirteenth gate electrode GE13 can overlap the ninth active layer ACT9.

[0139] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, the fifth gate electrode GE5, the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8, the ninth gate electrode GE9, the tenth gate electrode GE10, the eleventh gate electrode GE11, the twelfth gate electrode GE12, the thirteenth gate electrode GE13, and the fourteenth gate electrode GE14 can include at least one of molybdenum (Mo), copper (Cu), aluminum, and titanium (Ti), and be composed of a single layer or multiple layers. For example, the first gate electrode GE1 can be composed of a three-layer film including a titanium film, an aluminum film, and a titanium film disposed in this order along the third direction DR3 on the first gate insulating layer GTI1.

[0140] The first transistor M1 can include the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1.

[0141] The second transistor M2 can include the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2.

[0142] The third transistor M3 can include the third gate electrode GE3, the third source electrode SE3, and the third drain electrode DE3.

[0143] The fourth transistor M4 can include a fourth gate electrode GE4, a fourth source electrode SE4, and a fourth drain electrode DE4.

[0144] The fifth transistor M5 can include a fifth gate electrode GE5, a fifth source electrode SE5, and a fifth drain electrode DE5.

[0145] The sixth transistor M6 can include a sixth gate electrode GE6, a sixth source electrode SE6, and a sixth drain electrode DE6.

[0146] The seventh transistor M7 can include a seventh gate electrode GE7, a seventh source electrode SE7, and a seventh drain electrode DE7.

[0147] The eighth transistor M8 can include an eighth gate electrode GE8, an eighth source electrode SE8, and an eighth drain electrode DE8.

[0148] The ninth transistor M9 can include a ninth gate electrode GE9, a ninth source electrode SE9, and a ninth drain electrode DE9.

[0149] The tenth transistor M10 can include a tenth gate electrode GE10, a tenth source electrode SE10, and a tenth drain electrode DE10.

[0150] The eleventh transistor M11 can include an eleventh gate electrode GE11, an eleventh source electrode SE11, and an eleventh drain electrode DE11.

[0151] The twelfth transistor M12 can include a twelfth gate electrode GE12, a first source electrode SE12, and a twelfth drain electrode DE12.

[0152] The thirteenth transistor M13 can include a thirteenth gate electrode GE13, a thirteenth source electrode SE13, and a thirteenth drain electrode DE13.

[0153] The fourteenth transistor M14 can include a fourteenth gate electrode GE14, a fourteenth source electrode SE14, and a fourteenth drain electrode DE14.

[0154] A second gate insulating layer GTI2 can be provided on the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, the fifth gate electrode GE5, the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8, the ninth gate electrode GE9, the tenth gate electrode GE10, the eleventh gate electrode GE11, the twelfth gate electrode GE12, the thirteenth gate electrode GE13, and the fourteenth gate electrode GE14. In this case, the second gate insulating layer GTI2 can be provided on the entire surface of the substrate SUB including the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, the fourth gate electrode GE4, the fifth gate electrode GE5, the sixth gate electrode GE6, the seventh gate electrode GE7, the eighth gate electrode GE8, the ninth gate electrode GE9, the tenth gate electrode GE10, the eleventh gate electrode GE11, the twelfth gate electrode GE12, the thirteenth gate electrode GE13, and the fourteenth gate electrode GE14. The second gate insulating layer GTI2 can include the same substance and structure as the first gate insulating layer GTI1 described above.

[0155] A first capacitor electrode CE1 and a first output electrode OE1 can be provided on the second gate insulating layer GTI2. The first capacitor electrode CE1 and the first output electrode OE1 can be formed integrally. The first capacitor electrode CE1 can be connected to the ninth drain electrode DE9 of the ninth transistor M9 and the tenth source electrode SE10 of the tenth transistor M10 through a contact hole CT that penetrates the second gate insulating layer GTI2 and the first gate insulating layer GTI1. In other words, the first capacitor electrode CE1 and the first output electrode OE1 can connect the contact hole CT to a junction between the ninth drain electrode DE9 and the tenth source electrode SE10. The first capacitor electrode CE1 and the first output electrode OE1 can be composed of the same substance as each of the gate electrodes described above.

[0156] A first interlayer insulating layer ITL1 can be provided on the first capacitor electrode CE1 and the first output electrode OE1. In this case, the first interlayer insulating layer ITL1 can be provided on the entire surface of the substrate SUB including the first capacitor electrode CE1 and the first output electrode OE1. The first interlayer insulating layer ITL1 can include an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Alternatively, the first interlayer insulating layer ITL1 can include a plurality of inorganic films.

[0157] A third gate insulating layer GTI3 can be provided on the first interlayer insulating layer ITL1. The third gate insulating layer GTI3 can be provided on the entire surface of the substrate SUB including the first interlayer insulating layer ITL1. The third gate insulating layer GTI3 can include the same substance and structure as the first gate insulating layer GTI1 described above.

[0158] The second power supply line VDDL and the second capacitor electrode CE2 can be integrally formed. The second capacitor electrode CE2 can overlap the first capacitor electrode CE1. The first compensation capacitor Ccpl can be formed in a region where the second capacitor electrode CE2 and the first capacitor electrode CE1 overlap. The area of the first capacitor electrode CE1 and the area of the second capacitor electrode CE2 can be the same from a planar perspective. The second power supply line VDDL and the second capacitor electrode CE2 can be composed of the same substance as the aforementioned first capacitor electrode CE1 and the first output electrode OE1.

[0159] Figure 10 is a view for explaining the capacitances of the compensation capacitors in the first sub-display region SDA1 and the second sub-display region SDA2.

[0160] As shown in Figure 10 , the first stage STG1 connected to the first gate line GL1 (e.g., the first control gate line GCL1) of the first sub-display region SDA1 can be connected to the first compensation capacitor Ccpl having a relatively large capacitance. In other words, the first compensation capacitor Ccpl connected to the first output electrode OE1 of the first stage STG1 for driving the first gate line GL1 having a short length L1 can have a large capacitance. To this end, the first capacitor electrode CE1 and the second capacitor electrode CE2 of the first compensation capacitor Ccpl can have a long length LL1, respectively.

[0161] On the other hand, as shown in Figure 10 , the third stage STG3 connected to the third gate line GL3 (e.g., the third control gate line GCL3) of the second sub-display region SDA2 can be connected to the third compensation capacitor Ccp3 having a relatively small capacitance. In other words, the third compensation capacitor Ccp3 connected to the third output electrode OE3 of the third stage STG3 for driving the third gate line GL3 having a long length L3 can have a small capacitance. To this end, the first capacitor electrode CE1 and the second capacitor electrode CE2 of the third compensation capacitor Ccp3 can have a short length LL3, respectively. For example, the length LL3 of the first capacitor electrode CE1 (or the second capacitor electrode CE2) connected to the third stage STG3 can be shorter than the length LL1 of the first capacitor electrode CE1 (or the second capacitor electrode CE2) connected to the first stage STG1.

[0162] In addition, as shown in Figure 10, the width of the first capacitor electrode CE1 (or the second capacitor electrode CE2) connected to the first stage STG1 and the width of the first capacitor electrode CE1 (or the second capacitor electrode CE2) connected to the third stage STG3 may be the same. The width refers to the size of the first capacitor electrode CE1 in the first direction DR1.

[0163] Figure 11 This is a diagram for explaining the first auxiliary capacitor electrode ACE1 according to one embodiment.

[0164] like Figure 11 As shown, the area adjacent to the first capacitor electrode CE1 in the non-display area NDA can be further configured with a first capacitor electrode CE1 (hereinafter referred to as a first auxiliary capacitor electrode AC E1). For example, the first auxiliary capacitor area A1 and the second auxiliary capacitor area A2 can be further configured with first auxiliary capacitor electrodes ACE1 and ACE11, respectively. The first auxiliary capacitor electrode ACE1 in the first auxiliary area A1 and the first auxiliary capacitor electrode ACE11 in the second auxiliary area A2 can be configured on the same layer with the same material as the first capacitor electrode CE1. In this case, the first auxiliary capacitor electrode ACE1 in the first auxiliary area A1 and the first auxiliary capacitor electrode ACE11 in the second auxiliary area A2 can be formed integrally with the first capacitor electrode CE1. In this case, the area of ​​at least one of the first auxiliary capacitor electrode AC E1 in the first auxiliary area A1 and the first auxiliary capacitor electrode ACE11 in the second auxiliary area A2 can be different in size depending on the sub-display area.

[0165] Figure 12 FIG. 5 is a diagram for explaining the second auxiliary capacitor electrode ACE2 according to an embodiment.

[0166] like Figure 12 As shown, the area adjacent to the second capacitor electrode CE2 in the non-display area can be additionally configured with a second capacitor electrode CE2 (hereinafter referred to as the second auxiliary capacitor electrode). For example, the third auxiliary area A3 and the fourth auxiliary area A4 can be further configured with second auxiliary capacitor electrodes ACE2 and ACE22, respectively. The second auxiliary capacitor electrode ACE2 in the third auxiliary area A3 and the second auxiliary capacitor electrode ACE22 in the fourth auxiliary area A4 can be configured on the same layer with the same material as the second capacitor electrode CE2. In this case, the second auxiliary capacitor electrode ACE2 in the third auxiliary area A3 and the second auxiliary capacitor electrode ACE22 in the fourth auxiliary area A4 can be formed integrally with at least one of the second capacitor electrode CE2 and the second power line VDDL. In this case, the area of ​​at least one of the second auxiliary capacitor electrode ACE2 in the third auxiliary area A3 and the second auxiliary capacitor electrode ACE22 in the fourth auxiliary area A4 can be different sizes depending on the sub-display area.

[0167] Also, the second auxiliary capacitance electrode ACE2 of the third auxiliary area A3 can overlap the first auxiliary capacitance electrode ACE1 of the first auxiliary area A1, and the second auxiliary capacitance electrode ACE22 of the fourth auxiliary area A4 can overlap the first auxiliary capacitance electrode ACE11 of the second auxiliary area A2.

[0168] Figure 13 is a plan view of a display device of an embodiment.

[0169] Figure 13 The display device of Figure 1 The display device of The display device of

[0170] When a non-display area between the gate driving portion GD in the non-display area NDA and the display area DA is defined as the first sub non-display area AA1, and a non-display area between the light emitting driving portion ED in the non-display area NDA and the display area DA is defined as the second sub non-display area AA2, the aforementioned compensation capacitor's capacitance electrode can be disposed in at least one of the first sub non-display area AA1 and the second sub non-display area AA2.

[0171] Figure 14 is a diagram for explaining a size relationship of a capacitance electrode of an embodiment.

[0172] As shown in the example of Figure 14 The first capacitance electrode CE1 and the second capacitance electrode CE2 that overlap each other can be disposed in the first sub non-display area AA1.

[0173] The first to sixth gate lines GL1-GL6 can be disposed in the first sub display area SDA1, and the seventh and eighth gate lines GL7, GL8 that are longer than the gate lines of the first sub display area SDA1 in length can be disposed in the second sub display area SDA2.

[0174] The first to sixth gate lines GL1-GL6 of the first sub display area SDA1 can be connected to the first to sixth stages STG1-STG6, respectively, and the seventh and eighth gate lines GL7, GL8 of the second sub display area SDA2 can be connected to the seventh and eighth stages STG7, STG8, respectively.

[0175] The first to sixth gate lines GL1-GL6 of the first sub-display region SDA1 and the first to sixth stages STG1-STG6 can be connected to the first to sixth compensation capacitors Ccp1-Ccp6, respectively, and the seventh and eighth gate lines GL7, GL8 of the second sub-display region SDA2 and the seventh and eighth stages STG7, STG8 can be connected to the seventh and eighth compensation capacitors Ccp7, Ccp8, respectively.

[0176] The compensation capacitors Ccp1-Ccp6 connected to the stages of the gate lines GL1-GL6 for driving the first sub-display region SDA can be configured to have smaller capacities farther from the second sub-display region SDA2. In other words, the stages STG1-STG6 connected to the gate lines GL1-GL6 of the first sub-display region SDA are configured farther from the second sub-display region SDA2, the compensation capacitors connected to the stages are configured to have smaller capacities. For example, among the first to sixth compensation capacitors Ccp1-Ccp6, the sixth compensation capacitor Ccp6 can have the largest area of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2), the fifth compensation capacitor Ccp5 can have an area of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2) smaller than that of the sixth compensation capacitor Ccp6, the fourth compensation capacitor Ccp4 can have an area of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2) smaller than that of the fifth compensation capacitor Ccp5, the third compensation capacitor Ccp3 can have an area of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2) smaller than that of the fourth compensation capacitor Ccp4, the second compensation capacitor Ccp2 can have an area of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2) smaller than that of the third compensation capacitor Ccp3, and the first compensation capacitor Ccp1 can have an area of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2) smaller than that of the second compensation capacitor Ccp2. For example, the length (e.g., the size of the capacitor electrodes in the second direction DR2) of the capacitor electrodes (e.g., the first and second capacitor electrodes CE1, CE2) corresponding to the first sub-display region SDA1 can gradually decrease along the second direction DR2. Thus, the capacity of the compensation capacitors corresponding to the first sub-display region SDA1 can gradually decrease along the second direction DR2.

[0177] In addition, when a gate line (e.g., the sixth gate line GL6) of the first sub-display area SDA1 that is closest to the second sub-display area SDA2 is defined as a first closest gate line, a stage (e.g., the sixth stage STG6) connected to the first closest gate line is defined as a first closest stage, a gate line (e.g., the seventh gate line GL7) of the second sub-display area SDA2 that is closest to the first sub-display area SDA1 is defined as a second closest gate line, and a stage (e.g., the seventh stage STG7) connected to the second closest gate line is defined as a second closest stage, a compensation capacitor (e.g., the sixth compensation capacitor Ccp6) connected to the first closest stage can have a larger capacity than a compensation capacitor (e.g., the seventh compensation capacitor Ccp7) connected to the second closest stage, so that a load of the second closest stage and a load of the first closest stage are substantially the same.

[0178] For example, to enable a load of the seventh stage STG7 driving the seventh gate line GL7 to be substantially the same as a load of the sixth stage STG6 driving the sixth gate line GL6, the sixth compensation capacitor Ccp6 connected to the sixth stage STG6 can have a larger capacity than a seventh compensation capacitor connected to the seventh stage STG7, where the seventh gate line GL7 and the sixth gate line GL6 are connected to different numbers of pixels. In other words, to enable a load of the seventh stage STG7 connected to the seventh gate line GL7 of a different length than the sixth gate line GL6 to be substantially the same as a load of the sixth stage STG6, the sixth compensation capacitor Ccp6 connected to the sixth stage STG6 can have a larger capacity than a seventh compensation capacitor connected to the seventh stage STG7.

[0179] With a load of the second closest stage (e.g., STG7) as a reference (e.g., 100%), a load of the first closest stage (e.g., STG6) can be the same 100% as the reference, a stage (hereinafter, an outermost stage; e.g., the first stage STG1) of a gate line (hereinafter, an outermost gate line; e.g., the first gate line GL1) of the gate lines GL1-GL6 of the first sub-display area SDA1 that is configured farthest from the second sub-display area SDA2 can have a load of about 92%. In addition, the stages (e.g., STG2-STG5) between the first closest stage (e.g., STG6) and the outermost stage (e.g., STG1) can have loads gradually decreasing from 100% to 92% along the second direction DR2.

[0180] In order to make the loads of all stages the same, it is preferred that the area of ​​the capacitor electrode of the first sub-display area SDA1 be set to the maximum size (for example, the size of the capacitor electrode in the sixth compensation capacitor Ccp6). However, when the area of ​​the non-display area is not enough to maximize the area of ​​the capacitor electrodes of the compensation capacitors connected to all stages, as described above, Figure 14 In the example shown, in a state where only the load of the first nearest stage and the load of the second nearest stage are kept the same, if the area of ​​the capacitor electrode connected to the stage of the gate line for driving the first sub-display area SDA1 is designed to be gradually reduced, the load deviation between the stages arranged at the boundary between the first sub-display area SDA1 and the second sub-display area SDA2 can be minimized. Moreover, since the load from the boundary to the stage connected to the outermost gate line (for example, the first gate line GL1) gradually decreases, the load deviation between adjacent stages in the first sub-display area SDA1 can be reduced. Therefore, according to Figure 14 In the embodiment, even if the area of ​​the capacitor electrode of the compensation capacitor connected to the stage for driving the first sub-display area SDA1 is not set to the maximum, the image quality degradation (for example, screen spots) caused by the load deviation between the stages can be minimized.

[0181] Figure 15 This is a diagram for explaining the size relationship of capacitor electrodes according to one embodiment.

[0182] Figure 15 The display device and the aforementioned Figure 14 The difference between the display devices is that the width of the capacitor electrode gradually decreases. The following description focuses on this difference.

[0183] like Figure 15 As shown, along the second direction DR2 , the widths of the capacitor electrodes (eg, the first capacitor electrode CE1 and the second capacitor electrode CE2 ) (eg, the size of the capacitor electrodes in the first direction DR1 ) may gradually decrease.

[0184] Figure 16 A diagram for explaining the effects of a display device according to an embodiment.

[0185] Figure 16 1 shows: a first graph G1 showing the degree of speckle generation of the display device of the first embodiment (hereinafter referred to as the first display device) in different grayscale ranges; a second graph G2 showing the degree of speckle generation of the display device of the second embodiment (hereinafter referred to as the second display device) in different grayscale ranges; and a third graph G3 showing the degree of speckle generation of the display device of the third embodiment (hereinafter referred to as the third display device) in different grayscale ranges.

[0186] The first display device is a display device that does not employ a compensation capacitor, and according to the first graph G1, the first display device has a Just Notice Difference (JND) value of more than 1 at a high gray scale (for example, 255 gray scale), an intermediate gray scale (for example, 87 gray scale), and a low gray scale (for example, 11 gray scale). In other words, it can be confirmed that the first display device generates a mura at the high gray scale, the intermediate gray scale, and the low gray scale.

[0187] The second display device is a display device that employs the compensation capacitor of the aforementioned Figure 14 in the stage of the write gate signal output section of the gate drive section GD, and according to the second graph G2, the second display device has a JND value of more than 1 at an intermediate gray scale (for example, 87 gray scale) and a low gray scale (for example, 11 gray scale). In other words, it can be confirmed that the second display device generates a mura at the intermediate gray scale and the low gray scale.

[0188] The third display device is a display device that employs the compensation capacitor of the aforementioned Figure 14 in the stage of the control gate signal output section of the gate drive section GD, and according to the third graph G3, the third display device has a JND value of less than 1 at a high gray scale (for example, 87 gray scale), an intermediate gray scale (for example, 87 gray scale), and a low gray scale (for example, 11 gray scale). In other words, it can be confirmed that the third display device does not generate a mura at the high gray scale, the intermediate gray scale, and the low gray scale.

[0189] Therefore, it can be confirmed that when the compensation capacitor is employed in the stage of the control gate signal output section for controlling Figure 2 the third transistor T3, a considerable improvement in quality is achieved.

[0190] It will be understood by those having ordinary skill in the technical field to which the present specification pertains that the present specification can be implemented in other specific forms without changing the technical idea or essential characteristics of the present specification. Therefore, the above-described embodiments are to be understood in all aspects as illustrative and not restrictive. The scope of the present specification is represented by the scope of the claims described below, and all modifications or variations derived from the meaning, range, and equivalent concept of the appended claims should be interpreted as falling within the scope of the present specification.

[0191] In addition, although specific terms are used in the present specification and appended drawings, they are used only in the general sense and are used only to facilitate the understanding of the present specification, and are not intended to limit the scope of the present specification. It will be obvious to those skilled in the art to which the present specification pertains that other modifications can be made in addition to the embodiments disclosed herein, based on the technical idea of the present specification.

Claims

1. A display device comprising: a display panel, first and second gate lines disposed in the display panel, and a gate driver connected to the first and second gate lines; a number of pixels connected to the first gate line being less than a number of pixels connected to the second gate line, the gate driver comprising: a first stage connected to the first gate line via a first output electrode, and a second stage connected to the second gate line via a second output electrode; a first compensation capacitor connected to the first output electrode, a second compensation capacitor connected to the second output electrode, and a capacitance of the first compensation capacitor being greater than a capacitance of the second compensation capacitor. 2.The display device according to claim 1, wherein a length of the first gate line is greater than a length of the second gate line. 3.The display device according to claim 1, wherein the first and second compensation capacitors are disposed in a non-display region of the display panel. 4.The display device according to claim 3, wherein the first and second compensation capacitors are disposed in a non-display region between the gate driver and a display region of the display panel. 5.The display device according to claim 1, wherein the first compensation capacitor comprises: a first-1 capacitor electrode connected to the first output electrode, and a first-2 capacitor electrode connected to a power supply line and overlapping the first-1 capacitor electrode. 6.The display device according to claim 5, wherein the power supply line transmits a direct current voltage. 7.The display device according to claim 5, wherein the second compensation capacitor comprises: a second-1 capacitor electrode connected to the second output electrode, and a second-2 capacitor electrode connected to the power supply line and overlapping the second-1 capacitor electrode. 8.The display device according to claim 7, wherein the first-1 capacitor electrode of the first compensation capacitor has a greater area than the second-1 capacitor electrode of the second compensation capacitor. 9.The display device according to claim 7, wherein the first-2 capacitor electrode of the first compensation capacitor has a greater area than the second-2 capacitor electrode of the second compensation capacitor. 10.The display device according to claim 1, wherein the capacitance of the first compensation capacitor is greater than the capacitance of the second compensation capacitor so that a load of the first stage connected to the first gate line and a load of the second stage connected to the second gate line are the same. 11.The display device according to claim 1, further comprising a third gate line adjacent to the first gate line, the gate driver further comprising a third stage connected to the third gate line via a third output electrode, and a number of pixels connected to the third gate line being the same as a number of pixels connected to the first gate line. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 12. The display device according to claim 11, wherein a length of the third gate line is the same as a length of the first gate line.

13. The display device according to claim 11, wherein further comprising: a third compensation capacitor connected to the third output electrode.

14. The display device according to claim 13, wherein the first gate line is disposed between the second gate line and the third gate line.

15. The display device according to claim 14, wherein a capacity of the third compensation capacitor is the same as a capacity of the first compensation capacitor.

16. The display device according to claim 14, wherein a capacity of the third compensation capacitor is smaller than a capacity of the first compensation capacitor.

17. The display device according to claim 1, wherein the display panel includes: a display region in which the first gate line and the second gate line are disposed; and a non-display region in which the gate driving portion is disposed.

18. The display device according to claim 17, wherein the display region includes a first sub-display region and a second sub-display region having different sizes.

19. The display device according to claim 18, wherein a length of the first gate line is longer than a length of the second gate line, a length of the first sub-display region is longer than a length of the second sub-display region.

20. The display device according to claim 19, wherein the first gate line is disposed in the first sub-display region, the second gate line is disposed in the second sub-display region.

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