A user-mode memory management method, product, electronic device and storage medium

Abstract

The application discloses a user-mode memory management method and product, an electronic device and a storage medium, and belongs to the technical field of computer systems. In order to solve the technical problems of low memory utilization, low allocation efficiency and influence on system performance, the application provides a memory allocation request sent by a first upper-layer service thread, determines a first target central processor core corresponding to the first upper-layer service thread and a first memory page quantity contained in a memory block corresponding to the memory allocation request; determines a first target order according to the first memory page quantity; determines a first target order sub-cache pool corresponding to the first target order from a local cache pool corresponding to the first target central processor core; and determines a first idle memory block and allocates the first idle memory block to the first upper-layer service thread in the case that there is an idle memory block in the first target order sub-cache pool. In the memory allocation process, the application can improve the memory utilization, the memory allocation efficiency and the system performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer systems, and particularly relates to a user state memory management method, product, electronic device and storage medium. BACKGROUND

[0002] In a computer system, with the wide application of multi-core processors and the continuous improvement of system performance requirements, non-uniform memory access (NUMA) architecture is widely used because it can effectively expand memory capacity and improve system performance. In the related art, when a user state memory management system does not exist in the local cache corresponding to the upper layer business program, the memory block required by the user state memory management system is larger than the requested size, which causes the memory to be wasted. In addition, multiple CPU cores share the entire local cache, which affects the memory allocation efficiency and system performance.

[0003] In addition, the upper limit of the local cache is fixed, and if a large number of memory requests are burst by a thread, the cache is easily exhausted and frequently falls back to the central cache, which destroys the performance stability of the system. SUMMARY

[0004] The present application provides a user state memory management method, product, electronic device and storage medium, which can improve memory utilization, reduce memory waste, improve memory allocation efficiency and system performance during use.

[0005] The present application provides a user state memory management method, comprising:

[0006] According to the memory allocation request sent by the first upper layer business thread, the first target central processor core corresponding to the first upper layer business thread and the first memory page quantity contained in the memory block corresponding to the memory allocation request are determined;

[0007] The first target order is determined according to the first memory page quantity;

[0008] The first target order sub-cache pool corresponding to the first target order is determined from the local cache pool corresponding to the first target central processor core; wherein a local cache pool is allocated to each central processor core on each node, and the local cache pool includes a plurality of sub-cache pools of different orders, the memory page quantity contained in a single memory block in the sub-cache pools of adjacent two orders increases by one page in turn with the increase of the order, and the memory page quantity of each memory block in the sub-cache pool of the same order is the same;

[0009] In the case that there is a free memory block in the first target order sub-cache pool, the first free memory block is determined and allocated to the first upper layer business thread.

[0010] The present application also provides a user state memory management device, comprising:

[0011] The first determining module is configured to determine, according to a memory allocation request sent by the first upper-layer service thread, a first target central processor core corresponding to the first upper-layer service thread and a first memory page quantity contained in a memory block corresponding to the memory allocation request;

[0012] The second determining module is configured to determine a first target order according to the first memory page quantity.

[0013] The third determining module is configured to determine, from a local cache pool corresponding to the first target central processor core, a first target order sub-cache pool corresponding to the first target order; each central processor core is allocated a local cache pool on each node, the local cache pool includes a plurality of order sub-cache pools of different orders, the memory page quantity contained in a single memory block in two adjacent order sub-cache pools increases by one page with the increase of the order, and the memory page quantity of each memory block in the same order sub-cache pool is the same.

[0014] The first allocating module is configured to determine a first idle memory block and allocate the first idle memory block to the first upper-layer service thread in the case that there is an idle memory block in the first target order sub-cache pool.

[0015] The application further provides an electronic device, including a memory for storing a computer program and a processor for executing the computer program to realize the steps of the user-mode memory management method.

[0016] The application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to realize the steps of the user-mode memory management method.

[0017] The application further provides a computer program product, including a computer program, and the computer program is executed by a processor to realize the steps of the user-mode memory management method.

[0018] From the above technical solutions, the application has the following beneficial effects:

[0019] The embodiment of the present application provides a user state memory management method, comprising the following steps: determining a first target central processor core corresponding to a first upper layer service thread and a first memory page quantity contained in a memory block corresponding to a memory allocation request according to the memory allocation request sent by the first upper layer service thread; determining a first target order according to the first memory page quantity; determining a first target order sub-cache pool corresponding to the first target order from a local cache pool corresponding to the first target central processor core; wherein each node is allocated a local cache pool for each central processor core, the local cache pool comprises a plurality of sub-cache pools of different orders, the memory page quantity contained in a single memory block in two adjacent order sub-cache pools is sequentially increased by one page with the increase of the order, and the memory page quantity of each memory block in the same order sub-cache pool is the same; and determining a first idle memory block and allocating the first idle memory block to the first upper layer service thread in the case that there is an idle memory block in the first target order sub-cache pool.

[0020] Therefore, in the present application, each node is allocated a local cache pool for each central processor core of the node, the local cache pool comprises a plurality of sub-cache pools of different orders, the memory page quantity contained in a single memory block in two adjacent order sub-cache pools is sequentially increased by one page with the increase of the order, that is, the memory page quantity contained in a memory block in a current order sub-cache pool is one more than the memory page quantity contained in a memory block in a previous order sub-cache pool. When the system obtains the memory allocation request sent by the first upper layer service thread, the corresponding first target central processor core and the first memory page quantity contained in the memory block to be requested can be determined according to the memory allocation request, the corresponding first target order can be determined according to the first memory page quantity, then the corresponding local cache pool can be determined according to the first target central processor core, then the first target order sub-cache pool corresponding to the first target order can be determined from the local cache pool, and the first idle memory block can be determined and allocated to the first upper layer service thread in the case that there is an idle memory block in the first target order sub-cache pool. Since the memory page quantity in the allocated first idle memory block is consistent with the memory page quantity requested by the memory allocation request, that is, the size of the allocated memory block is consistent with the size of the requested memory block, there is no phenomenon of memory waste, and the memory utilization rate can be improved. In addition, since one CPU core corresponds to one local cache pool, when a plurality of CPU cores are occupied, there is no memory block request conflict, and the memory allocation efficiency can be improved.

[0021] In addition, the present application also provides a corresponding implementation device, electronic equipment and computer readable storage medium for the user state memory management method, so that the method is more practical, and the device, electronic equipment and computer readable storage medium have corresponding advantages. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following embodiments are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0023] Figure 1 A flow chart of a user mode memory management method provided by the embodiments of the present application;

[0024] Figure 2 A correspondence diagram of a central processing unit core and a local cache pool provided by the embodiments of the present application;

[0025] Figure 3 An architecture diagram of a user mode memory management provided by the embodiments of the present application;

[0026] Figure 4 A memory application flow diagram provided by the embodiments of the present application;

[0027] Figure 5 A dynamic adjustment process diagram of a memory block in a local cache pool provided by the embodiments of the present application;

[0028] Figure 6 A structure diagram of a user mode memory management device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the protection scope of the present application.

[0030] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0031] In order to make the skilled in the art better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0032] Embodiments of the present application provide a user-mode memory management method, which is described in detail in combination with a flowchart of the user-mode memory management method as shown in Figure 1 The method comprises the following steps S110-S140.

[0033] S110: According to the memory allocation request sent by the first upper-layer service thread, determine the first target central processor core corresponding to the first upper-layer service thread and the first memory page quantity contained in the memory block corresponding to the memory allocation request.

[0034] It should be noted that there can be multiple central processor cores (i.e. CPU cores or physical cores) on each node (e.g. a NUMA (Non Uniform Memory Access) node), as shown in Figure 2 In the embodiments of the present application, for each node, a local cache pool PagePool is allocated for each CPU core from the local cache pool of the node, and the local cache pool is divided into multiple sub-cache pools, each of which includes multiple memory blocks. The orders of the sub-cache pools are different, and the memory page quantity contained in the memory blocks in the adjacent two orders of sub-cache pools increases by one page in the order from small to large. For example, the orders of the sub-cache pools from small to large are 0th order, 1st order, 2nd order, …, 511th order, etc. The memory page quantity of each memory block in the 0th order sub-cache pool is 1, the memory page quantity of each memory block in the 1st order sub-cache pool is 2, the memory block is composed of two consecutive memory pages, the memory page quantity of each memory block in the 2nd order sub-cache pool is 3, the memory block is composed of three consecutive memory pages, …, and the memory page quantity of each memory block in the 511th order sub-cache pool is 512, the memory block is composed of 512 consecutive memory pages.

[0035] In the user-mode memory management system, when it is detected that there is an upper-layer service thread requesting to allocate memory, the memory allocation request sent by the first upper-layer service thread requesting to allocate memory can be obtained, and according to the first upper-layer service thread, the first target central processor core occupied by the first upper-layer service thread can be determined, and the first memory page quantity corresponding to the memory block requested by the first upper-layer service thread can be determined.

[0036] In actual application, the user-mode memory management system can receive the memory allocation request sent by the first upper-layer application thread by actively calling the API function provided by the application program. The memory allocation request includes the memory page quantity applied, i.e. the memory is applied in page units.

[0037] S120: Determine the first target order according to the first memory page quantity.

[0038] It can be understood that after the first memory page quantity is determined, the first target order corresponding to the first memory page quantity can be determined according to the division rule of each order, for example, if the first memory page quantity is 3, the corresponding first target order is 2 orders.

[0039] S130: determining a first target order sub-cache pool corresponding to the first target order from a local cache pool corresponding to the first target central processor core; wherein each central processor core on each node is allocated a local cache pool, the local cache pool includes a plurality of order sub-cache pools of different orders, and the number of memory pages contained in a single memory block in two adjacent order sub-cache pools increases by one page with the increase of the order, and the number of memory pages of each memory block in the same order sub-cache pool is the same.

[0040] That is, since each CPU core in the node corresponds to a local cache pool PagePool respectively, the first target central processor core can be determined, and the local cache pool corresponding to the first central processor core can be determined according to the first central processor core, wherein the target node where the first target central processor core is located can be determined, and the local cache pool corresponding to the first target central processor core on the target node can be further determined. Since each local cache pool includes a plurality of order sub-cache pools of different orders, the first target order sub-cache pool of the first target order can be further determined from the local cache pool corresponding to the first CPU core according to the determined first target order, for example, if the first target order is 2 orders, the order sub-cache pool of 2 orders is determined from the local cache pool, and the order sub-cache pool is taken as the first target order sub-cache pool.

[0041] S140: in the case that there is a free memory block in the first target order sub-cache pool, determining a first free memory block and allocating it to a first upper-layer service thread.

[0042] It should be noted that in actual application, it can be further determined whether there is a free memory block in the first target sub-cache pool, and if there is a free memory block, a free memory block in the first target sub-cache pool can be determined as a first free memory block and allocated to the first upper-layer service thread. Since the number of memory pages in the allocated first free memory block is consistent with the number of memory pages requested by the memory allocation request, that is, the size of the allocated memory block is consistent with the size of the requested memory block, there is no phenomenon of memory waste, and the memory utilization rate can be improved. In addition, since one CPU core corresponds to one local cache pool, when multiple CPU cores are occupied, there will be no memory block request conflict, and the memory allocation efficiency can be improved. Of course, in the embodiment of the present application, since each CPU core has an independent local cache pool, the memory operations of different CPU cores are isolated from each other, and different applications (such as database and network processing applications) on the same node will not interfere with each other, so the quality of service of each application can be protected.

[0043] In an embodiment, the method can further include:

[0044] In the case that there is no free memory block in the first target sub-cache pool, determining a first memory allocator corresponding to a target node where the first target CPU core is located;

[0045] Determining a first target order memory partition corresponding to the first target order from the first memory allocator; wherein the memory allocator of each node includes a plurality of memory partitions of different orders, and the number of memory pages contained in a single memory block in two adjacent order memory partitions increases by one page with the increase of the order, and the number of memory pages of each memory block in the same order memory partition is the same;

[0046] In the case that there is a free memory block in the first target order memory partition of the first memory allocator, a second free memory block is determined and allocated to the first upper-layer service thread.

[0047] It should be noted that in actual application, the NUMA node can adopt a multi-level cache cooperation architecture of the local cache pool PagePool and the memory allocator Buddy. The memory allocator of each NUMA node also includes a plurality of memory partitions of different orders. In order from small to large, the number of memory pages contained in a single memory block in adjacent memory partitions of two orders increases by one page by one page, and the number of memory pages of each memory block on the same memory partition is the same. For example, the orders of each memory partition are 0, 1, 2, …, 511, and so on from small to large. The number of memory pages of each memory block in the 0-order memory partition is 1, the number of memory pages of each memory block in the 1-order memory partition is 2, the memory block is composed of two continuous memory pages, the number of memory pages of each memory block in the 2-order memory partition is 3, the memory block is composed of three continuous memory pages, and so on. The number of memory pages of each memory block in the 511-order memory partition is 512, and the memory block is composed of 512 continuous memory pages. That is, the order of each memory partition of the memory allocator is one-to-one corresponding to the order of each sub-cache pool in the local cache pool corresponding to each CPU core in the node.

[0048] In the embodiment of the application, after the first target central processor core is determined, the target node where the first target central processor core is located can be further determined. If there is no idle memory block in the first target order sub-cache pool, the first memory allocator of the target node can be further determined, and then the corresponding first target order memory partition can be determined from the first memory allocator according to the first target order. It is further determined whether there is an idle memory block in the first target order memory partition of the first memory allocator. If there is an idle memory block, the corresponding second idle memory block is determined and allocated to the first upper-layer service thread.

[0049] In the embodiment of the application, after the memory allocation request sent by the first upper-layer service thread is obtained, the first target order sub-cache pool consistent with the requested memory block order is found from the local cache pool corresponding to the corresponding first target central processor core, and it is determined whether there is an idle memory block in the first target order sub-cache pool. If there is an idle memory block, the first idle memory block is determined from the first target order sub-cache pool in the local cache and allocated to the first upper-layer service thread. If there is no idle memory block in the first target order sub-cache pool, it is further determined whether there is an idle memory block in the first target order memory partition of the same order in the first memory allocator of the corresponding target node. If there is, the corresponding second memory block is determined from the first target order memory partition of the first memory allocator and allocated to the first upper-layer application thread.

[0050] It can be understood that the allocation method provided in the application can make the local cache pool PagePool become the "exclusive cache" of the memory allocator Buddy, can directly respond to high-frequency small / specific size memory requests, reduce direct calls to the memory allocator Buddy, and reduce lock contention. That is, by corresponding setting of each order sub-cache pool in the local cache pool and each order memory partition in the memory allocator in the application, efficient linkage of the local cache pool and the memory allocator can be achieved.

[0051] In addition, since the local cache pool corresponding to the target central processor belongs to a private PagePool, the private PagePool has extremely low access delay and can quickly meet most memory requests, especially high-frequency small object memory requests. Therefore, in the case of detecting a memory allocation request sent by the first upper application thread, a memory block meeting the requirements is first obtained from the local cache pool corresponding to the first central processor core. In the case that there is no memory block meeting the requirements in the local cache pool, a further obtaining is performed from the memory partition of the corresponding order in the first memory allocator.

[0052] In an implementation, the method can further include:

[0053] In the case that there is no idle memory block in the first target order memory partition of the first memory allocator, a third idle memory block is determined from other order memory partitions of the first memory allocator, which have a higher order than the first target order memory partition.

[0054] The third idle memory block is split to obtain a first memory block corresponding to the order of the first target order memory partition, and the first memory block is put into the first target order memory partition and allocated to the first upper service thread.

[0055] It should be noted that in the case that there is still no idle memory block in the first target order memory partition of the first memory allocator in the application embodiment, a third idle memory block can be determined from other memory partitions having a higher order than the first target order memory partition, and a first memory block of a required order (i.e., the first target order) is obtained by splitting the third idle memory block. Then, the first memory block is put into the first target order memory partition, and the first memory block is allocated to the first upper service thread.

[0056] That is, in the application embodiment, in the case that there is no idle memory block in the memory partition of the corresponding order in the first memory allocator, a memory block of a required order is split from a memory block in a memory partition of a higher order in the first memory allocator, and the memory block is put into the memory partition of the corresponding order and allocated to the corresponding upper service thread.

[0057] For example, when the first upper layer service thread requests a memory block of 3 memory pages, the system first acquires the memory block from the 2nd order of the local cache pool PagePool (because the 2nd order stores memory blocks with 3 continuous memory pages), and when there is no free memory block in the 2nd order, it is indicated that the private local cache pool PagePool cannot meet the allocation requirement, and the memory block needs to be acquired from the 2nd order memory partition of the memory allocator Buddy of the NUMA node to which the CPU core belongs (because each Buddy can manage all the memory of a NUMA node), and when there is also no free memory block in the 2nd order memory partition of the Buddy, it is indicated that the 2nd order memory partition of the Buddy cannot meet the requirement, and at this time, the memory block can be split from the higher order memory partition of the Buddy to obtain a 2nd order memory block for allocation.

[0058] It should be noted that in the embodiment of the application, the high order of the local cache pool PagePool is not split to protect the system performance. In the application, when the memory allocation request is acquired, the memory block is acquired from the corresponding order sub-cache pool of the local cache pool PagePool. Since the local cache pool PagePool can quickly respond, the memory block is directly allocated from the corresponding order sub-cache pool, which can effectively avoid the locking competition and fragmentation traversal of the memory allocator Buddy. The pre-fetch cache mechanism in the embodiment of the application can significantly improve the allocation speed of the memory request of a specific size. Further, when the local cache pool cannot meet the requirement, the memory block is acquired from the corresponding order memory partition of the memory allocator Buddy, and when the corresponding order memory partition of the memory allocator Buddy cannot meet the requirement, the memory block is split from the higher order memory partition of the memory allocator Buddy.

[0059] Further, after the third free memory block is split to obtain the first memory block corresponding to the order of the first target memory partition, the method can further include:

[0060] determining a second memory block obtained by splitting the third free memory block;

[0061] acquiring the number of memory pages in the second memory block, and determining the order corresponding to the second memory block according to the number of memory pages in the second memory block;

[0062] placing the second memory block into the memory partition corresponding to the order in the first memory allocator according to the order corresponding to the second memory block.

[0063] It should be noted that, in the embodiment of the present application, after the third free memory block is split to obtain the first memory block, the remaining memory pages in the third free memory block constitute a second memory block, and the order corresponding to the second memory block can be determined according to the number of memory pages in the second memory block, and then the second memory block is put into the memory partition of the first memory allocator corresponding to the order, so that the orders of the memory blocks in each memory partition can be guaranteed to be the same, and flexible management of the memory blocks in each memory partition of the first memory allocator can be realized.

[0064] In actual application, for each order of the sub-cache pool in the local cache pool Pagepool and each order of the memory partition in the memory allocator Buddy, the number of free memory blocks in the order is counted by a corresponding counter. When there is an upper-layer service thread applying for memory from the Pagepool or the Buddy in a certain order, whether there is a free memory block in the sub-cache pool or the memory partition of the order can be determined by checking whether the counter of the Pagepool or the Buddy corresponding to the order is 0. When a memory block is applied, the counter of the Pagepool or the Buddy corresponding to the order is decremented by 1 based on the current value. When a memory block is filled into the sub-cache pool of the order or released into the memory partition of the order subsequently, the count value of the counter of the order is incremented by 1, so that whether there is a free memory block in a certain order can be quickly identified, and the memory allocation efficiency is improved.

[0065] In an implementation, each node includes a shared local cache pool respectively, and the shared local cache pools constitute a global shared cache pool. Each shared local cache pool includes a plurality of sub-shared cache pools of different orders. The number of memory pages contained in a single memory block in two adjacent orders of sub-shared cache pools is sequentially increased by one page with the increase of the order. The number of memory pages of each memory block in a same order of sub-shared cache pool is the same.

[0066] It should be noted that, in the embodiment of the present application, the cache pool on each NUMA node can also be divided into a part as a shared local cache pool, and the shared local cache pools of each node constitute a global shared cache pool, that is, the global shared cache pool is established according to the shared local cache pools of each NUMA node, and the global shared cache pool can be accessed by each NUMA node. Each shared local cache pool is also divided into a plurality of partitions of different orders, each partition is a sub-shared cache pool, and the orders of each sub-shared cache pool in the shared local cache pool are respectively set corresponding to the orders of each sub-cache pool in the local cache pool and the orders of each memory partition in the memory allocator. That is, the i-th order of sub-cache pool in the local cache pool corresponds to the i-th order of memory partition in the memory allocator and the i-th order of sub-shared cache pool in the shared local cache pool, where i∈[0, 511].

[0067] The method can further include: in the case that there is no third free memory block in other order memory partitions of the first target order in the first memory allocator, determining a first target order sub-shared cache pool corresponding to the first target order from the first shared local cache pool corresponding to the target node according to the first target order; and in the case that there is a free memory block in the first target order sub-shared cache pool, determining a fourth free memory block and allocating the fourth free memory block to the first upper-layer service thread.

[0068] It can be understood that, in the case that there is no third free memory block in higher orders of the first memory allocator for splitting of the memory block, it is indicated that the first memory allocator cannot meet the memory allocation requirement, and at this time, a fourth free memory block can be determined from the global shared cache pool, the first target order sub-shared cache pool of the first target order corresponding to the target node in the first shared local cache pool. Please refer to Figure 3 For core x in node 0, in the case that the corresponding local cache pool x and the memory allocator cannot meet the requirement, a memory block can be obtained from the global shared cache pool, and similarly, core 32 and core 33 in node n can also obtain a memory block from the global shared cache pool in the case that the corresponding local cache pool and the memory allocator cannot meet the requirement.

[0069] For example, when the first upper-layer service thread requests a memory block of 3 memory pages, there is no free memory block in the second order sub-cache pool of the local cache pool PagePool and the second order memory partition of the first memory allocator Buddy, and the higher order memory partitions of Buddy cannot split the memory block, then a memory block can be obtained from the second order sub-shared cache pool in the shared local cache pool of the target node.

[0070] That is, the shared local cache pool in the embodiment of the application can be used as a supplement of the local cache pool PagePool and an emergency channel, in the case that the local cache pool and the memory allocator cannot meet the memory allocation requirement, a memory block can be obtained from the shared local cache pool, dynamic supplement of memory is realized, direct cross-node application is not needed, overhead of cross-node access is avoided, and local memory resources can also be fully utilized. Meanwhile, the shared local cache pool also serves as a coordinator of cross-core resources in the node, and is responsible for balancing memory requirements between different cores.

[0071] In an implementation, the method can further include:

[0072] In the case that there is no free memory block in the first target order sub-shared cache pool, a second shared local cache pool is determined from the global shared cache pool, in which there is a free memory block in the sub-shared cache pool corresponding to the first target order.

[0073] A second target order sub-shared cache pool corresponding to the first target order is determined from the second shared local cache pool, a fifth free memory block is determined, and the fifth free memory block is allocated to the first upper-layer service thread.

[0074] It should be noted that in the case that the first target order sub-shared cache pool in the global shared cache pool still cannot meet the memory allocation requirement, a cross-node application can be performed from the global shared cache pool. For example, a target other node is determined from each other node corresponding sub-shared cache pool in the global shared cache pool, in which the order is the first target order and there is a free memory block, then a shared local cache pool of the target other node is taken as a second shared local cache pool, and a fifth free memory block is determined from a second target order sub-shared cache pool of the first target order in the second shared local cache pool and allocated to the first upper-layer service thread.

[0075] In actual application, in the case that the target other node determined from the global shared cache pool in which the order is the first target order and there is a free memory block is multiple, distances between each target other node and the local target node can be obtained (for example, the NUMA distance file under a specified path in the system can be directly read), then each distance is sorted from small to large, and the target other node with the smallest distance is selected as the final target other node, or in the case that the target other node with the smallest distance is multiple, a node with the largest memory capacity of the sub-shared cache pool corresponding to the first target order is determined from the multiple target other nodes with the smallest distance as the final target other node for memory block allocation.

[0076] On the basis of the above embodiment, as shown in Figure 4 When the first upper-layer service thread requests 3 memory pages of memory blocks, and there is no free memory block in the 2nd order sub-cache pool of the local cache pool PagePool and the 2nd order memory partition of the first memory allocator Buddy, the higher order memory partition of Buddy also cannot perform memory block splitting, and there is also no free memory block in the 2nd order sub-shared cache pool in the shared local cache pool of the target node, so cross-node application can only be performed in the global shared cache pool. Since the global shared cache pool includes shared local cache pools of each node, the global shared cache pool can provide a cross-node path, thereby further meeting the memory application requirement and better meeting the service requirement.

[0077] In an implementation, the method can further include:

[0078] In a case where a memory block release request is detected, determining a memory block to be released and a release target location according to the memory block release request;

[0079] Placing the memory block to be released into the release target location.

[0080] It should be noted that, after a memory block is applied to an upper-layer service thread, a service operation is performed, and then the memory block is released in a case where the memory block is not needed to be used. In actual application, when a second upper-layer application program does not need a previously allocated memory block, the memory block can be released by calling a free interface. In the embodiment of the present application, in order to better manage the memory, the system can determine a memory block to be released and a target location (i.e., a release target location) to which the memory block needs to be released according to information in the memory block release request in a case where a memory block release request is detected, and then place the memory block to be released into the release target location, thereby completing the release of the memory block to be released.

[0081] In an implementation, the process of determining a memory block to be released and a release target location according to a memory block release request in a case where a memory block release request is detected can include:

[0082] Obtaining a memory block release request sent by the second upper-layer service thread;

[0083] Determining a memory block to be released according to the memory block release request;

[0084] Determining a second target order corresponding to the memory block to be released according to a second number of memory pages of the memory block to be released;

[0085] Determining whether the memory block to be released is allocated across nodes in a last allocation, and if yes, determining an original node corresponding to the memory block to be released, and placing the memory block to be released into a sub-shared cache pool corresponding to the second target order in a shared local cache pool of the original node; and if not, determining a target local cache pool corresponding to a second target central processor core corresponding to the second upper-layer service thread, and placing the memory block to be released into a sub-cache pool corresponding to the second target order in the target local cache pool.

[0086] It can be understood that the upper-layer service thread sending the memory block release request in the embodiments of the present application is referred to as a second upper-layer service thread (which can be the same thread as the first upper-layer service thread), and in the case that the system obtains the memory block release request sent by the second upper-layer service thread, the system can determine the to-be-released memory block according to the memory block information in the memory block release request, determine the second number of memory pages in the to-be-released memory block, determine the corresponding second target order according to the second number of memory pages, that is, determine the order (second target order) of the to-be-released memory block. Then, it is further determined whether the to-be-released memory block is cross-node allocation (that is, whether it comes from the shared local cache pool of other nodes in the global shared cache pool) when it is allocated last time, if it is cross-node allocation, the original node where the to-be-released memory block originally locates is further determined, and the shared local cache pool corresponding to the original node and the sub-shared cache pool with the same order as the second target order in the shared local cache pool are determined from the global shared cache pool, and the to-be-released memory block is put into the sub-shared cache pool, thereby completing the release of the memory block.

[0087] Of course, if it is determined that it is not cross-node allocation, the second target central processor core corresponding to the second upper-layer service thread can be further determined, and the target local cache pool corresponding to the second target central processor core is determined, and then the to-be-released memory block is put into the sub-cache pool with the same order as the second target order in the target local cache pool, so as to complete the release of the memory block.

[0088] The allocation method provided in the present application can make the local cache pool PagePool become the "exclusive cache" of the memory allocator Buddy, can directly respond to high-frequency small / specific size memory requests, reduce direct calls to the memory allocator Buddy, reduce lock competition, and also enable batch recycling and accurate preheating of memory blocks through the same order as Buddy, for example, the to-be-released memory block can be directly returned to the local cache pool of the corresponding order without Buddy traversing the fragmented space.

[0089] In an implementation, the process of determining whether the to-be-released memory block is cross-node allocation when it is allocated last time can include:

[0090] According to the second upper-layer service thread, a second target central processor core corresponding to the second upper-layer service thread is determined;

[0091] According to the second target central processor core, a node where the second target central processor core is located is determined;

[0092] According to each memory page in the to-be-released memory block, a node to which the to-be-released memory block belongs is determined;

[0093] In a case where the node where the second target central processor core is located is different from the node to which the to-be-released memory block belongs, it is determined that the to-be-released memory block is cross-node allocated in the last allocation;

[0094] In a case where the node where the second target central processor core is located is the same as the node to which the to-be-released memory block belongs, it is determined that the to-be-released memory block is not cross-node allocated in the last allocation.

[0095] It can be understood that, in the process of determining whether the to-be-released memory block is cross-node allocated in the last allocation, the node where the second target central processor core is located can be determined according to the second target central processor core occupied by the second upper-layer business thread, and then the node to which the to-be-released memory block belongs can be determined according to the specific location information or historical source information of each memory page in the to-be-released memory block, and then it is further judged whether the node to which the to-be-released memory block belongs is the same node as the node where the second target central processor core is located. If it is the same node, it indicates that the to-be-released memory block is not cross-node allocated in the last allocation, and if it is not the same node, it indicates that the to-be-released memory block is cross-node allocated in the last allocation.

[0096] For example, if the second upper-layer business thread releases a memory block including 3 memory pages, it will first judge whether the NUMA node to which the 3 memory pages belong is consistent with the NUMA node to which the CPU core corresponding to the second upper-layer business thread belongs. If it is consistent, it indicates that there is no cross- NUMA application, and the memory block composed of the 3 memory pages needs to be placed on the second-order sub-cache pool of the private local cache pool corresponding to the CPU core. If it is not consistent, the memory block is placed on the second-order of the sub-shared cache pool corresponding to the 3 memory pages in the shared local cache pool of the original node in the global shared cache pool.

[0097] In an embodiment, the method can further include:

[0098] detecting whether there is a second target sub-cache pool with an idle memory block quantity lower than a preset lower limit in each sub-cache pool of a local cache pool corresponding to the first target central processor core;

[0099] If there is, determining a third target order of the second target sub-cache pool;

[0100] determining a second target order memory partition same as the third target order from a first memory allocator corresponding to a target node where the first target central processor core is located, and determining the first preset number of idle memory blocks from the second target order memory partition to fill into the second target sub-cache pool.

[0101] It should be noted that if the capacity of the local cache pool PagePool is fixed, if a core or thread manager manages a burst, large and continuous memory allocation of a certain order, the corresponding local cache pool of the order may be quickly exhausted, resulting in frequent return to Buddy or even shared local cache pool or cross-node application, which may destroy the performance isolation advantage. Of course, if the memory usage of a CPU core is reduced, there are more unused memory blocks in the local cache pool PagePool corresponding to the CPU core, which may cause resource waste, and even cause the Buddy of the entire node to be exhausted too early (memory fragmentation or invalid "hoarding").

[0102] Therefore, in the embodiments of the present application, a plurality of dynamic water lines can be set for each local cache pool, for example, three dynamic water lines are set, which are a low water line (corresponding to a preset lower limit), a high water line (corresponding to a preset upper limit) and a target water line (corresponding to a preset target range). If the number of idle memory blocks in a certain sub-cache pool of the local cache pool is lower than the preset lower limit, it indicates that the idle memory blocks need to be supplemented, if the number of idle memory blocks is higher than the preset upper limit, it indicates that the number of idle memory blocks of the sub-cache pool is high, and a part of it can be safely released back to the upper memory allocator to avoid memory waste. Of course, if the number of idle memory blocks is within the preset target range, it indicates that the number of idle memory blocks is ideal.

[0103] Please refer to Figure 5 In the embodiments of the present application, the Figure 5The scheme is described in detail. In actual application, for each central processor core, the number of idle memory blocks in each order sub-cache pool in the local cache pool corresponding to the central processor core can be monitored in real time. In the embodiment of the application, the first target central processor core is taken as an example for description. By monitoring the number of idle memory blocks in each sub-cache pool of the local cache pool corresponding to the first target central processor core, the third target order (i.e. the order of the second target sub-cache pool) corresponding to the second target sub-cache pool with the number of idle memory blocks lower than the preset lower limit can be determined. Then, the second target order memory partition consistent with the third target order is determined from the first memory allocator corresponding to the target node where the first target central processor core is located, and the first preset number of idle memory blocks are determined from the second target order memory partition and filled into the second target sub-cache pool, so that after the first preset number of idle memory blocks are filled into the second target sub-cache pool in batches, the number of idle memory blocks in the second target sub-cache pool can reach the preset target range, thereby realizing dynamic supplement of memory blocks for the sub-cache pool with less idle memory blocks. It should be noted that in the memory block filling process, the business does not affect the acquisition of memory blocks from the second target sub-cache pool, because the number of memory blocks in the second target sub-cache pool at this time is not 0.

[0104] Further, the process of determining the second target order memory partition consistent with the third target order from the first memory allocator corresponding to the target node where the first target central processor core is located, and determining the first preset number of idle memory blocks from the second target order memory partition and filling them into the second target sub-cache pool can include:

[0105] determining the second target order memory partition consistent with the third target order from the first memory allocator corresponding to the target node where the first target central processor core is located;

[0106] in the case that the first preset number of idle memory blocks exist in the second target order memory partition, directly filling the first preset number of idle memory blocks in the second target order memory partition into the second target sub-cache pool;

[0107] in the case that the first preset number of idle memory blocks do not exist in the second target order memory partition, determining the total number of memory pages corresponding to the first preset number of idle memory blocks;

[0108] determining the third target order memory partition in which the memory blocks satisfy the total number of memory pages from the first memory allocator according to the total number of memory pages;

[0109] splitting the idle memory blocks in the third target order memory partition into the first preset number of idle memory blocks with the third target order;

[0110] fill the first preset number of idle memory blocks obtained after the splitting into the second target sub-cache pool.

[0111] It can be understood that in the process of determining the idle memory blocks filled into the second target sub-cache pool from the first memory allocator, two cases can be considered. One is that there are the first preset number of idle memory blocks in the second target memory partition of the same third target order in the first memory allocator, at which time the first preset number of idle memory blocks can be directly obtained from the second target memory partition to fill into the second target sub-cache pool. The other is that there are not the first preset number of idle memory blocks in the second target memory partition, at which time the second target memory partition can be skipped, and the corresponding order can be determined according to the total number of memory pages of the first preset number of idle memory blocks, and then a third target memory partition that can meet the order is determined from the first memory allocator, wherein the order of the third target memory partition is equal to or greater than the order corresponding to the total number of memory pages. Then the idle memory blocks in the third target memory partition are split into the first preset number of idle memory blocks, and the order of the first preset number of idle memory blocks obtained after the splitting is the third target order, and then the first preset number of idle memory blocks obtained after the splitting are filled into the second target sub-cache pool.

[0112] It should be noted that if the order of the third target memory partition is equal to the order corresponding to the total number of memory pages, after the idle memory blocks in the third target memory partition are split into the first preset number of idle memory blocks with the third target order, there will be no remaining memory pages. If the order of the third target memory partition is greater than the order corresponding to the total number of memory pages, after the idle memory blocks in the third target memory partition are split into the first preset number of idle memory blocks with the third target order, there will be remaining memory pages, at which time the corresponding order can be determined according to the total number of the remaining memory pages, and the memory blocks formed by the remaining memory pages are put into the memory partition of the corresponding order in the first memory allocator. For example, the third target order is 2, the first preset number is 10, and if the idle memory block of the third target memory partition includes 21 memory pages, after the idle memory block is split into 10 memory blocks of 2 pages, there is still one memory page left, which can be put into the 0-order memory partition of the first memory allocator.

[0113] In an implementation, the method can further include:

[0114] detecting whether there is a third target sub-cache pool with an idle memory block number higher than a preset upper limit in each sub-cache pool of a local cache pool corresponding to the first target central processor core;

[0115] if there is, determining a fourth target order of the third target sub-cache pool;

[0116] release the second preset number of free memory blocks in the third target sub-cache pool to a third target order memory partition in the first memory allocator corresponding to the fourth target order.

[0117] It should be noted that in the embodiments of the present application, when it is detected that the number of free memory blocks in the third target sub-cache pool in the local cache pool is higher than the preset upper limit, the fourth target order of the third target sub-cache pool can be further determined, and then the second preset number of free memory blocks in the third target sub-cache pool are released to the third target order memory partition in the first memory allocator corresponding to the fourth target order, so that the excess memory blocks are put into the memory allocator, so that the number of free memory blocks in the adjusted third target sub-cache pool is within the preset target range, thereby realizing dynamic adjustment of the memory blocks in the local cache pool.

[0118] In actual application, the second preset number of free memory blocks are released one by one to the third target order memory partition of the first memory allocator, and the first memory allocator can also merge the released free memory blocks. The first memory allocator can identify the memory pages in the released free memory blocks upon receiving each released free memory block. In the case that the memory pages of the released free memory block are continuous with the memory pages of a certain memory block in the third target order memory partition (for example, the first page of the released memory block is continuous with the last memory page of a certain memory block in the third target order memory partition, or the last memory page of the released memory block is continuous with the first memory page of a certain memory block in the third target order memory partition), the released memory block can be merged with the continuous memory block in the third target order memory partition. The number of memory pages in the merged memory block is doubled. The new order is determined according to the total number of memory pages in the merged memory block, and then the merged memory block is moved to the memory partition corresponding to the new order in the first memory allocator, thereby realizing the merging of the memory blocks.

[0119] In addition, it should be noted that in the embodiments of the present application, the target water level can be adjusted according to historical demand. For example, the allocation frequency of each sub-cache pool at each order of each local cache pool can be monitored. If the allocation frequency is getting higher and higher, the target water level can be slowly adjusted upwards, and the highest water level can be adjusted. If the allocation frequency is getting lower and lower, the water level can be slowly adjusted downwards, and the lowest water level can be adjusted. The low water level and the high water level can be updated according to actual needs.

[0120] It can be understood that each order in the local cache pool in the embodiment of the application corresponds to each order in the system Buddy allocator, so the memory block size in the sub-cache pool of the local cache pool is consistent with the memory block size of the corresponding order in each memory partition managed by Buddy, precise matching is achieved, and therefore batch recycling and preheating without frequent splitting / merging can be achieved, the memory management efficiency is improved. In addition, in the embodiment of the application, the shared cache pool and the Buddy memory are preferentially recycled, the application memory working set of the CPU core is protected, and the memory utilization rate is improved.

[0121] In use, the embodiment of the application not only improves performance, but also improves resource isolation and memory utilization efficiency, and delays cross-node access. Since a local cache pool is allocated for each CPU core, the memory allocation request can quickly obtain a memory block from the bound local cache pool, reduce allocation delay, reduce dependence on the Buddy memory allocator, and avoid lock contention waiting. For example, high-performance database threads can quickly obtain memory blocks and improve response speed. In the embodiment of the application, the low-latency memory resources of the local cache pool are preferentially used, the memory allocation process can be optimized, and the performance loss caused by cache misses can be reduced.

[0122] Since the local cache pool is finely divided according to order in the embodiment of the application, memory requests of different sizes can quickly obtain memory from the corresponding order of the corresponding local cache pool, reducing memory fragmentation. The embodiment of the application can also automatically adjust the number of memory blocks in each sub-cache pool in the local cache pool according to the memory usage, avoiding excessive accumulation or deficiency, and reasonably allocating memory resources.

[0123] The memory management method provided in the embodiment of the application can maximize the use of local cache and improve the overall performance of the system when the local memory resources (private local cache pool, local memory allocator, and local shared local cache pool) can meet the demand without triggering high-latency access across NUMA nodes.

[0124] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software and the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is a better implementation.

[0125] The embodiment of the application also provides a user-mode memory management device, please refer to Figure 6 The user-mode memory management device comprises:

[0126] The first determining module 11 is configured to determine, according to a memory allocation request sent by the first upper-layer service thread, a first target central processor core corresponding to the first upper-layer service thread and a first memory page quantity contained in a memory block corresponding to the memory allocation request.

[0127] The second determining module 12 is configured to determine a first target order according to the first memory page quantity.

[0128] The third determining module 13 is configured to determine, from a local cache pool corresponding to the first target central processor core, a first target order sub-cache pool corresponding to the first target order; wherein each central processor core on each node is allocated a local cache pool, the local cache pool includes a plurality of sub-cache pools of different orders, and the memory page quantity contained in a single memory block in two adjacent order sub-cache pools increases by one page with the increase of the order, and the memory page quantity of each memory block in a same order sub-cache pool is the same.

[0129] The first allocating module 14 is configured to determine a first idle memory block and allocate the first idle memory block to the first upper-layer service thread in a case where there is an idle memory block in the first target order sub-cache pool.

[0130] In an embodiment, the apparatus can further include:

[0131] The fourth determining module is configured to determine a first memory allocator corresponding to a target node where the first target central processor core is located in a case where there is no idle memory block in the first target order.

[0132] The fifth determining module is configured to determine, from the first memory allocator, a first target order memory partition corresponding to the first target order; wherein the memory allocator of each node includes a plurality of memory partitions of different orders, the memory page quantity contained in a single memory block in two adjacent order memory partitions increases by one page with the increase of the order, and the memory page quantity of each memory block in a same order memory partition is the same.

[0133] The sixth determining module is configured to determine a second idle memory block and allocate the second idle memory block to the first upper-layer service thread in a case where there is an idle memory block in the first target order memory partition of the first memory allocator.

[0134] In an embodiment, the apparatus can further include:

[0135] The seventh determining module is configured to determine, from other order memory partitions of the first memory allocator which are higher than the first target order memory partition, a third idle memory block in a case where there is no idle memory block in the first target order memory partition of the first memory allocator.

[0136] The splitting module is configured to split the third free memory block to obtain a first memory block corresponding to a rank of the first target rank memory partition, and put the first memory block into the first target rank memory partition to allocate to the first upper-layer service thread.

[0137] In an embodiment, the apparatus can further include:

[0138] The eighth determining module is configured to determine a second memory block obtained by splitting the third free memory block.

[0139] The ninth determining module is configured to obtain a number of memory pages in the second memory block, and determine a rank corresponding to the second memory block according to the number of memory pages in the second memory block.

[0140] The first putting module is configured to put the second memory block into a memory partition of a corresponding rank in the first memory allocator according to the rank corresponding to the second memory block.

[0141] In an embodiment, each node includes a shared local cache pool, and each shared local cache pool constitutes a global shared cache pool. Each shared local cache pool includes a plurality of sub-shared cache pools of different ranks. The number of memory pages contained in a single memory block in two adjacent sub-shared cache pools of different ranks increases by one page successively with the increase of the rank. The number of memory pages in each memory block in a sub-shared cache pool of the same rank is the same.

[0142] The apparatus can further include:

[0143] The tenth determining module is configured to, in the case that there is no free third free memory block in other rank memory partitions in the first memory allocator which have a rank higher than the first target rank memory partition, determine a first target rank sub-shared cache pool corresponding to the first target rank from a first shared local cache pool corresponding to the target node according to the first target rank.

[0144] The eleventh determining module is configured to, in the case that there is a free memory block in the first target rank sub-shared cache pool, determine a fourth free memory block and allocate the fourth free memory block to the first upper-layer service thread.

[0145] In an embodiment, the apparatus can further include:

[0146] The twelfth determining module is configured to, in the case that there is no free memory block in the first target rank sub-shared cache pool, determine a second shared local cache pool from the global shared cache pool, the second shared local cache pool being located on another node and having a sub-shared cache pool corresponding to the first target rank.

[0147] The second distribution module is configured to determine a second target order sub-shared cache pool corresponding to the first target order from the second shared local cache pool, determine a fifth idle memory block, and distribute the fifth idle memory block to the first upper-layer service thread.

[0148] In an embodiment, the apparatus can further include:

[0149] The thirteenth determination module is configured to, in a case where a memory block release request is detected, determine a to-be-released memory block and a release target position according to the memory block release request.

[0150] The second placing module is configured to place the to-be-released memory block at the release target position.

[0151] In an embodiment, the thirteenth determination module includes:

[0152] The first acquisition unit is configured to acquire a memory block release request sent by the second upper-layer service thread.

[0153] The first determination unit is configured to determine a to-be-released memory block according to the memory block release request.

[0154] The second determination unit is configured to determine a second target order corresponding to the to-be-released memory block according to a second memory page quantity of the to-be-released memory block.

[0155] The first judgment unit is configured to determine whether the to-be-released memory block is allocated across nodes in the last allocation, and if yes, trigger the third determination unit; if not, trigger the fourth determination unit.

[0156] The third determination unit is configured to determine an original node corresponding to the to-be-released memory block, and place the to-be-released memory block in a sub-shared cache pool corresponding to the second target order in a shared local cache pool of the original node.

[0157] The fourth determination unit is configured to determine a target local cache pool corresponding to a second target central processor core corresponding to the second upper-layer service thread, and place the to-be-released memory block in a sub-cache pool corresponding to the second target order in the target local cache pool.

[0158] In an embodiment, the first judgment unit includes:

[0159] The first determination sub-unit is configured to determine a second target central processor core corresponding to the second upper-layer service thread according to the second upper-layer service thread.

[0160] The second determination sub-unit is configured to determine a node in which the second target central processor core is located according to the second target central processor core.

[0161] The third determining subunit is configured to determine a node to which the to-be-released memory block belongs according to each memory page in the to-be-released memory block.

[0162] The fourth determining subunit is configured to determine that the to-be-released memory block is cross-node allocated in the last allocation in a case where the node where the second target central processor core is located is different from the node to which the to-be-released memory block belongs.

[0163] The fifth determining subunit is configured to determine that the to-be-released memory block is not cross-node allocated in the last allocation in a case where the node where the second target central processor core is located is the same as the node to which the to-be-released memory block belongs.

[0164] In an implementation, the apparatus comprises:

[0165] The first judging module is configured to detect whether there is a second target sub-pool with an idle memory block quantity lower than a preset lower limit in each sub-pool of a local cache pool corresponding to the first target central processor core;

[0166] If there is, the thirteenth determining module is triggered;

[0167] The thirteenth determining module is configured to determine a third target order of the second target sub-pool.

[0168] The fourteenth determining module is configured to determine a second target order memory partition same as the third target order from a first memory allocator corresponding to a target node where the first target central processor core is located, and determine the first preset quantity of idle memory blocks from the second target order memory partition to fill into the second target sub-pool.

[0169] In an implementation, the fourteenth determining module comprises:

[0170] The fifth determining unit is configured to determine a second target order memory partition same as the third target order from a first memory allocator corresponding to a target node where the first target central processor core is located.

[0171] The first filling unit is configured to directly fill the first preset quantity of idle memory blocks in the second target order memory partition into the second target sub-pool in a case where the first preset quantity of idle memory blocks exist in the second target order memory partition.

[0172] The sixth determining unit is configured to determine a total memory page quantity corresponding to the first preset quantity of idle memory blocks in a case where the first preset quantity of idle memory blocks do not exist in the second target order memory partition.

[0173] The seventh determining unit is configured to determine, according to the total memory page quantity, a third target order memory partition in which memory blocks satisfy the total memory page quantity from the first memory allocator.

[0174] a splitting unit, configured to split the idle memory block in the third target order memory partition into a first preset number of idle memory blocks with a third target order;

[0175] a second filling unit, configured to fill the first preset number of idle memory blocks obtained after the splitting into the second target sub-cache pool.

[0176] In an embodiment, the apparatus can further include:

[0177] a second judging module, configured to detect whether there is a third target sub-cache pool with a number of idle memory blocks higher than a preset upper limit in each sub-cache pool of a local cache pool corresponding to the first target central processing unit core;

[0178] if there is, triggering a fifteenth determining module;

[0179] the fifteenth determining module, configured to determine a fourth target order of the third target sub-cache pool;

[0180] a releasing module, configured to release a second preset number of idle memory blocks in the third target sub-cache pool into a third target order memory partition corresponding to the fourth target order in the first memory allocator.

[0181] It should be noted that the descriptions of the features in the embodiments of the user state memory management apparatus provided in the present application can refer to the related descriptions of the embodiments of the user state memory management method, which will not be repeated here.

[0182] Embodiments of the present application also provide an electronic device including a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in any of the above-mentioned embodiments of the user state memory management method.

[0183] Embodiments of the present application also provide a computer readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above-mentioned embodiments of the user state memory management method when running.

[0184] In an exemplary embodiment, the above-mentioned computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0185] Embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program realizes the steps in any of the user-mode memory management method embodiments when executed by a processor.

[0186] Embodiments of the present application also provide another computer program product, which comprises a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program realizes the steps in any of the user-mode memory management method embodiments when executed by a processor.

[0187] Those skilled in the art will further appreciate that the steps of the example methods described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various examples have been described generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

[0188] The above provides a user-mode memory management method, product, electronic device and storage medium. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A user-mode memory management method, characterized in that, include: Based on the memory allocation request sent by the first upper-layer business thread, determine the first target central processing unit core corresponding to the first upper-layer business thread and the number of first memory pages contained in the memory block corresponding to the memory allocation request; The first target order is determined based on the number of the first memory pages; A first target order sub-cache pool corresponding to the first target order is determined from the local cache pool corresponding to the first target CPU core; wherein, a local cache pool is allocated to each CPU core on each node, and the local cache pool includes multiple sub-cache pools of different orders. The number of memory pages contained in a single memory block in two adjacent sub-cache pools increases by a single page as the order increases, and the number of memory pages in each memory block in the sub-cache pool of the same order is the same. If there is a free memory block in the first target-level sub-cache pool, the first free memory block is determined and allocated to the first upper-level business thread.

2. The user-mode memory management method according to claim 1, characterized in that, Also includes: If there are no free memory blocks in the first target sub-cache pool, determine the first memory allocator corresponding to the target node where the first target central processing unit core is located; A first target order memory partition corresponding to the first target order is determined from the first memory allocator; wherein, the memory allocator of each node includes multiple memory partitions of different orders, the number of memory pages contained in a single memory block in two adjacent order memory partitions increases sequentially with the order increasing, and the number of memory pages in each memory block in the same order memory partition is the same. If there is a free memory block in the first target-level memory partition of the first memory allocator, a second free memory block is determined and allocated to the first upper-layer business thread.

3. The user-mode memory management method according to claim 2, characterized in that, Also includes: If there is no free memory block in the first target level memory partition of the first memory allocator, a free third free memory block is determined from other level memory partitions in the first memory allocator that have a higher level than the first target level memory partition. The third free memory block is split to obtain a first memory block corresponding to the order of the first target order memory partition, and the first memory block is placed into the first target order memory partition and allocated to the first upper-layer business thread.

4. The user-mode memory management method according to claim 3, characterized in that, After splitting the third free memory block to obtain the first memory block corresponding to the order of the first target order memory partition, the method further includes: Determine the second memory block obtained after splitting the third free memory block; Obtain the number of memory pages in the second memory block, and determine the order of the second memory block based on the number of memory pages in the second memory block; Based on the order of the second memory block, the second memory block is placed into the memory partition of the corresponding order in the first memory allocator.

5. The user-mode memory management method according to claim 3, characterized in that, Each node includes a shared local cache pool, and the shared local cache pools constitute a global shared cache pool. Each shared local cache pool includes multiple sub-shared cache pools of different orders. The number of memory pages contained in a single memory block in two adjacent sub-shared cache pools increases by the number of pages as the order increases. The number of memory pages in each memory block in a sub-shared cache pool of the same order is the same. The method further includes: If there is no free third free memory block in other memory partitions with a higher order than the first target order memory partition in the first memory allocator, the first target order sub-shared cache pool corresponding to the first target order is determined from the first shared local cache pool corresponding to the target node according to the first target order. If there is a free memory block in the first target-level shared cache pool, the fourth free memory block is determined and allocated to the first upper-layer business thread.

6. The user-mode memory management method according to claim 5, characterized in that, Also includes: If there are no free memory blocks in the first target order sub-shared cache pool, determine from the global shared cache pool a second shared local cache pool that is located on other nodes and has free memory blocks in the sub-shared cache pool corresponding to the first target order; The fifth free memory block is determined from the second shared local cache pool, which corresponds to the first target order, and then allocated to the first upper-layer business thread.

7. The user-mode memory management method according to any one of claims 1 to 6, characterized in that, Also includes: Upon detecting a memory block release request, the memory block to be released and the target location for release are determined based on the memory block release request. Place the memory block to be released at the target release location.

8. The user-mode memory management method according to claim 7, characterized in that, The step of determining the memory block to be released and the target location for release based on the memory block release request when a memory block release request is detected includes: Get the memory block release request sent by the second upper-layer business thread; The memory block to be released is determined based on the memory block release request; The second target order corresponding to the memory block to be released is determined based on the number of second memory pages in the memory block to be released; Determine whether the memory block to be released was allocated across nodes in the last allocation. If so, determine the original node corresponding to the memory block to be released and put the memory block to be released into the sub-shared cache pool corresponding to the second target order in the shared local cache pool of the original node. If not, determine the target local cache pool corresponding to the second target CPU core corresponding to the second upper-layer business thread and put the memory block to be released into the sub-cache pool corresponding to the second target order in the target local cache pool.

9. The user-mode memory management method according to claim 8, characterized in that, Determining whether the memory block to be released was allocated across nodes in the last allocation includes: Based on the second upper-layer business thread, determine the second target central processing unit core corresponding to the second upper-layer business thread; Based on the second target CPU core, determine the node where the second target CPU core is located; Based on each memory page in the memory block to be released, determine the node to which the memory block to be released belongs; If the node where the second target central processing unit core is located is different from the node to which the memory block to be released belongs, it is determined that the memory block to be released was allocated across nodes in the last allocation. If the node where the second target central processing unit core is located is the same as the node to which the memory block to be released belongs, it is determined that the memory block to be released was not allocated across nodes in the previous allocation.

10. The user-mode memory management method according to claim 7, characterized in that, Also includes: Detect whether there is a second target sub-cache pool in each sub-cache pool of the local cache pool corresponding to the first target central processing unit core, where the number of free memory blocks is lower than a preset lower limit; If it exists, then determine the third target order of the second target sub-cache pool; From the first memory allocator corresponding to the target node where the first target central processing unit core is located, a second target-level memory partition with the same level as the third target is determined, and a first preset number of free memory blocks are determined from the second target-level memory partition and filled into the second target sub-cache pool.

11. The user-mode memory management method according to claim 10, characterized in that, The step of determining a second target-level memory partition of the same order as the third target from the first memory allocator corresponding to the target node where the first target CPU core is located, and determining a first preset number of free memory blocks from the second target-level memory partition to fill the second target sub-cache pool includes: In the first memory allocator corresponding to the target node where the first target central processing unit core is located, a second target-level memory partition with the same level as the third target is determined; If there are a first preset number of free memory blocks in the second target memory partition, the first preset number of free memory blocks in the second target memory partition are directly filled into the second target sub-cache pool; If there are no first preset number of free memory blocks in the second target memory partition, determine the total number of memory pages corresponding to the first preset number of free memory blocks; Based on the total number of memory pages, a third target-order memory partition is determined from the first memory allocator to satisfy the total number of memory pages; The free memory blocks in the third target order memory partition are split into the first preset number of free memory blocks of the third target order; The first preset number of free memory blocks obtained after splitting are filled into the second target sub-cache pool.

12. The user-mode memory management method according to claim 10, characterized in that, Also includes: Detect whether there is a third target sub-cache pool in each sub-cache pool of the local cache pool corresponding to the first target central processing unit core where the number of free memory blocks exceeds a preset limit; If it exists, then the fourth target order of the third target sub-cache pool is determined; Release a second preset number of free memory blocks from the third target sub-cache pool to the third target level memory partition in the first memory allocator that corresponds to the fourth target level.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the user-mode memory management method as described in any one of claims 1 to 12.

14. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the user-mode memory management method as described in any one of claims 1 to 12 when executing the computer program.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the user-mode memory management method as described in any one of claims 1 to 12.

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