Gate drive circuit, display panel and display device

By introducing pull-up and pull-down modules into the gate drive circuit and using sequentially lagging level control signals, the problem of inconsistent connection duration between the shift register signal output and the clock line is solved, thus improving the output quality of the gate control signal.

CN120853496APending Publication Date: 2025-10-28GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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Patent Information

Application Number
CN202511122868.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-11
Publication Date
2025-10-28

AI Technical Summary

Technical Problem

In the gate drive circuit, the signal output terminals of multiple shift registers are electrically connected to the corresponding clock lines for different durations, which affects the output quality of the gate control signal.

Method used

By introducing pull-up and pull-down modules into the gate drive circuit, and using multiple level control signals with sequentially lagging phases, the electrical connection between the output module of the shift register and the clock line is controlled, reducing the connection duration difference and improving the signal output quality.

Benefits of technology

This effectively reduces the difference in electrical connection duration between the shift register and the clock line, and improves the output quality of the gate control signal.

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Abstract

The invention provides a gate drive circuit, a display panel and a display device, and the gate drive circuit comprises M cascaded shift registers, and pull-down modules in the (M-X + 1) th shift register to the Mth shift register are electrically connected with a control module. A plurality of level control signals with sequentially lagged phases generated by a control module are used as pull-down control signals of the (M-X + 1) th-stage shift register to the Mth-stage shift register, so that electrical connections between output modules in the (M-X + 1) th-stage shift register to the Mth-stage shift register and corresponding clock lines are sequentially disconnected; and the time length difference of electrical connection between the output modules in the (M-X + 1) th-stage shift register to the Mth-stage shift register and the corresponding clock lines is reduced, so that the output quality of the gate control signal is improved.
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