FPGA high-speed dynamic scanning device and method

Abstract

The application relates to the field of integrated circuit design and embedded control system technology, in particular to a FPGA high-speed dynamic scanning device and method. The method comprises the following steps: writing a scan chain in a one-way loop sequence in a FPGA on-chip memory area, wherein the length of the scan chain is equal to the total number of semiconductor test probe array contacts or the total number of LED display array row and column channels; at a preset synchronous scanning clock rising edge, a first pointer register outputs a channel selection signal in a current address, a second pointer register simultaneously locks a resident parameter in the same address and drives a timer to start counting down; when the timer returns to zero, the first pointer register and the second pointer register are simultaneously incremented to point to a next address of the scan chain. Through the double-pointer synchronous beat technology, the application realizes zero drift of a test beat, thereby improving the manufacturing precision of semiconductors and LED lamps.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and embedded control system technology, and in particular to a high-speed dynamic scanning device and method for FPGA. Background Technology

[0002] In the semiconductor and LED manufacturing industry, high-speed dynamic scanning of large-scale arrays (such as semiconductor test probe arrays and LED display arrays) is often required. This involves operations such as orderly switching of multiple channels, precise timing control, and real-time parameter adjustment to achieve efficient testing or production. In existing technologies, the scanning link lacks a stable loop mechanism, which easily leads to missed scans, repeated scans, or loop switching stutters. The consistency of the working and switching timing of each channel is poor, affecting the stability of the test. It is difficult to modify parameters in real time during the scanning process, requiring downtime for adjustment, which is inefficient. Furthermore, the pointer reset at the end of the loop lacks a reliable trigger, which can easily lead to errors in the connection between the beginning and end. Summary of the Invention

[0003] Therefore, it is necessary to provide an FPGA high-speed dynamic scanning device and method to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objectives, a high-speed dynamic scanning method for FPGAs is provided, applicable to the semiconductor and LED manufacturing fields. The FPGA includes a first pointer register and a second pointer register. The method includes the following steps:

[0005] Step S1: Write the scan link in the FPGA on-chip memory area in a unidirectional loop order, wherein the scan link length is equal to the total number of contacts of the semiconductor test probe array or the total number of rows and columns of the LED display array;

[0006] Step S2: At the rising edge of the preset synchronous scan clock, the first pointer register outputs the channel selection signal within the current address, and at the same time, the second pointer register latches the resident parameters within the same address and drives the timer to start counting down;

[0007] Step S3: When the timer returns to zero, the first pointer register and the second pointer register increment simultaneously, pointing to the next address of the scan link;

[0008] Step S4: During the period when the channel selection signal is valid, write the correction information to the current address to replace the original resident parameters or channel identifier; when the cycle flag bit of the end address of the scan link is valid and read, the two-level pointer registers are reset to the starting address in the same clock cycle.

[0009] Preferably, the preset rising edge formation operation of the synchronous scan clock in step S2 includes:

[0010] Read the start and end addresses of the scan link, swap the corresponding bits, and send them to the pulse width register;

[0011] The highest two bits of the pulse width register are used as the upper limit of the count. The one-bit ring counter starts to increment from 0 and is immediately cleared after reaching the upper limit. A single pulse is output the instant the counter is cleared.

[0012] After a single pulse passes through a two-stage series rising edge sharpening link, it replaces the original clock signal and is connected to the FPGA global clock network.

[0013] Preferably, in step S2, the first pointer register outputs the channel selection signal within the current address as follows:

[0014] Circularly shift the current address value one bit to the right to obtain a shifted copy;

[0015] The shifted copy is bitwise ORed with the channel selection signal, and the result is written to the high byte of the FPGA's on-chip I / O bit selection area.

[0016] The result of the operation is shifted left by one bit within the same clock cycle and then XORed with itself bitwise. The resulting check code is written to the low byte of the I / O bit selection area.

[0017] Preferably, step S2, in which the second pointer register latches the resident parameters at the same address and drives the timer, includes:

[0018] Latch the high seven bits of the resident parameter into the second pointer register, invert the low one bit and write it to the lower half byte of the same address;

[0019] The inverse code is added bit by bit to the resident parameter, discarding the carry, and the result is written to the timer check register;

[0020] When the check register is zero, the timer initial value register loads the resident parameters and begins to count down.

[0021] Preferably, in step S3, when the timer is reset to zero, both the first pointer register and the second pointer register increment simultaneously as follows:

[0022] The timer reset pulse is fed into an on-chip delay line formed by four inverters connected in series.

[0023] The outputs of each tap of the delay line are combined by an AND gate array to form the trigger edge;

[0024] The trigger edge is applied to both the first pointer register and the second pointer register simultaneously within the same clock cycle.

[0025] Preferably, writing the correction information to the current address in step S4 includes:

[0026] The correction information is circularly shifted left by one bit by the current address, and then a bit rotation operation is performed.

[0027] The round-robin result overrides the residency parameters of the current address;

[0028] The overwritten dwell parameter is shifted left by one bit again within the same clock cycle and bitwise ORed with itself, and the result is written back to the channel identifier field.

[0029] Preferably, the steps following writing the correction information to the current address in step S4 include:

[0030] The current address content is bitwise XORed with the first pointer register, and the result is temporarily stored in the second pointer register;

[0031] The contents of the second pointer register are XORed again with the one's complement of the resident parameter, and the result is written back to the high half byte of the current address.

[0032] After the write-back is completed, the read and write ports for the current address remain open.

[0033] Preferably, the operation of scanning the loop flag bit at the end address of the link to trigger the reset of the two-level pointer register in step S4 includes:

[0034] Perform a bitwise XOR operation between the last address and the first address. If the result of the bitwise XOR operation is all 1, latch the cycle flag bit.

[0035] The circular flag bit is connected to the synchronous reset terminal of the two-level pointer register;

[0036] The reset pin clears the pointer and points to the starting address within the same clock cycle.

[0037] Preferably, the operation after resetting the two-level pointer registers in step S4 is as follows:

[0038] The reset pulse trigger delay counter is loaded with a fixed value of 1;

[0039] The delay counter overflows in the next clock cycle and outputs an enable signal;

[0040] External correction information is enabled by the enable signal and written into the window, while remaining there until the next zeroing pulse.

[0041] This specification also provides an FPGA high-speed dynamic scanning apparatus, including a control system for executing the FPGA high-speed dynamic scanning method described above, the control system comprising:

[0042] The link writing module is used to write the scan link in a unidirectional loop sequence to the on-chip memory area of ​​the FPGA. The length of the scan link is equal to the total number of contacts of the semiconductor test probe array or the total number of rows and columns of the LED display array.

[0043] The dual-pointer drive module is used to output the channel selection signal within the current address in the first pointer register at the rising edge of the preset synchronous scan clock, while the second pointer register latches the resident parameters within the same address and drives the timer to start counting down.

[0044] The synchronous increment module is used to increment both the first pointer register and the second pointer register simultaneously when the timer returns to zero, pointing to the next address of the scan link;

[0045] The online write-back module is used to write correction information to the current address during the period when the channel selection signal is valid, replacing the original resident parameters or channel identifier; when the cycle flag bit of the end address of the scan link is valid and read, the two-level pointer registers are reset to the starting address in the same clock cycle.

[0046] The beneficial effects of this invention are as follows:

[0047] During wafer-level electrical testing, the end address of the linked list automatically returns to the beginning address, and the two pointers increment simultaneously. The channel switching cycle is locked to a fixed clock period and does not drift due to the increase in the number of probes, ensuring that the setup / hold time window of each contact is strictly consistent.

[0048] During scanning, ATE or brightness feedback data can directly replace the resident parameters in the current address via the online write-back channel; a write operation is completed within the valid window of the channel selection signal, and the write action and the scan read action share the same clock edge, achieving zero-wait update of the cycle time, and the scan flow can be updated without interruption during production line changeover or process compensation.

[0049] The cycle flag bit and the reset terminal are hard-wired, and a clear pulse is output immediately after the last address is read; the reset delay is fixed to one clock cycle, eliminating the cumulative jitter caused by traditional software polling, so that the wafer test sequence and the LED aging sequence remain strictly aligned after multiple cycles.

[0050] Each linked list cell simultaneously stores the main value, high-order mirror image, low-order mirror image, and check word. During the scanning process, the main value and mirror image value are cross-checked in real time. Any single bit flip can be immediately located by the check word. Data consistency is maintained even when the array size is expanded without the need for additional redundant channels. Attached Figure Description

[0051] Figure 1 This is a flowchart illustrating the steps of a high-speed dynamic scanning method for FPGA.

[0052] Figure 2 This is a picture of the actual FPGA development board;

[0053] Figure 3 This is a signal timing diagram in an embodiment of the present invention;

[0054] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0055] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0056] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0057] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0058] To achieve the above objectives, please refer to Figures 1 to 3 A high-speed dynamic scanning method for FPGAs, applied in the semiconductor and LED manufacturing fields, wherein the FPGA includes a first pointer register and a second pointer register, and the method includes the following steps:

[0059] Preferably, step S1: write the scan link in the FPGA on-chip memory area in a unidirectional loop order, wherein the scan link length is equal to the total number of contacts of the semiconductor test probe array or the total number of rows and columns of the LED display array.

[0060] Of particular importance, the step S1 of writing the scan link in the FPGA on-chip memory area in a unidirectional loopback order includes:

[0061] The address space 0~N-1 is divided into N cells with the total number of contacts or row and column channels N as the period, and each cell reserves a high-order mirror slot and a low-order mirror slot;

[0062] Write the serial number i into the main slot of cell i in ascending order, immediately shift i three positions to the left and write it into the high-order mirror slot of cell i, and shift i three positions to the right and write it into the low-order mirror slot, forming a three-dimensional interleaved backup.

[0063] When i equals N-1, the address value of cell 0 is written to the loop pointer slot of cell N-1, and the address value of cell N-1 is written back to the loop pointer slot of cell 0, forming a double-locked loop with mutual pointers at the beginning and end.

[0064] During the writing process, after each cell is completed, the main slot value and the high and low mirror slot values ​​are immediately swapped and accumulated. The accumulated result is written as the check word into the check slot of that cell.

[0065] After all cells have been written, the check word sequence is joined end to end to form a looped list with embedded check.

[0066] It should be noted that the relevant hardware devices and settings are not limited in this embodiment.

[0067] In this embodiment, a Xilinx Artix-7XC7A100T FPGA is selected, with an on-chip BlockRAM capacity of 4.9 Mbit. The clock is generated as a 100 MHz system master clock via a PLL. The number of row and column bus channels N is 256 (16×16 contact matrix), corresponding to the address space 0x0000–0x00FF. 16 pairs each of JTAG debug port and LVDS differential I / O are used for row and column driving, and 16 x 512MB DDR3 memory is used as data cache.

[0068] Allocate 256 consecutive 128-bit cells within BlockRAM, with each cell arranged in little-endian order:

[0069] [127:120] Loop pointer slot;

[0070] [119:96] Verification slot;

[0071] [95:64] High-level mirror slot;

[0072] [63:32] Low-position mirror slot;

[0073] [31:0] Main slot;

[0074] Initialization steps: After reset, the on-chip state machine sequentially accesses cells starting from i=0.

[0075] For cell i: 1) Write the 32-bit unsigned number i to the main slot; 2) Immediately shift the bits of i cyclically left by 3 bits and write them to the high-order mirror slot; 3) Simultaneously shift the same i cyclically right by 3 bits and write it to the low-order mirror slot.

[0076] When i=255: 1) Write the physical address 0x0000 of cell 0 to the loop pointer slot of cell 255; 2) Write the address 0x00FF of cell 255 back to the loop pointer slot of cell 0, forming a double-locked loop with mutual pointers at the beginning and end.

[0077] Checksum generation: After each cell is written to all three slots, the state machine immediately performs a bit swap: the bit order of the high-order mirror slot is reversed, the bit order of the low-order mirror slot is reversed, and then XORed with the main slot value. The resulting 32-bit result is written to the checksum slot; simultaneously, it is accumulated in the global checksum register. After all cells have been written, the checksum returns to zero, indicating that the linked list is complete.

[0078] Scanning Operation: After initialization, the scan clock drops to 25MHz. On each clock edge: the current cell's main slot value is retrieved, decoded, and used to drive the corresponding row and column channels; the check slot is compared with the real-time checksum. If the XOR is non-zero, the FPGA immediately pulls the ERROR pin high and freezes the scan, waiting for external JTAG to read the fault information.

[0079] Of particular importance, step S1 also includes:

[0080] After the cell is written, the cell number and the check word are rotated and concatenated to generate a rotated concatenation code;

[0081] The rotated splicing code is bit-swapped with the main slot value, and the swap result is written to the hidden slot of the cell;

[0082] The hidden slots remain unchanged after the loop list is formed, and are used for address uniqueness verification in the subsequent step S4.

[0083] In one embodiment, 256 160-bit cells are allocated in the FPGA's on-chip Block RAM: main slot, mirror slot, parity slot, hidden slot, and loopback pointer slot arranged sequentially. During initialization, the index i is written to the main slot in the order of 0 to 255, and immediately i is circularly shifted left by 3 bits to write to the high-order mirror slot and circularly shifted right by 3 bits to write to the low-order mirror slot; the parity slot is written with the XOR value of the main slot and the two mirror slots after swapping bits. When i=255, the address of cell 0 is written to the loopback pointer slot of cell 255, and the address of cell 255 is written back to cell 0, forming a double-locked loop.

[0084] In another embodiment, the cell number and the check slot value are concatenated into 64-bit data, cyclically shifted 11 bits to the right to obtain the rotated concatenation code, which is then bit-swapped with the main slot value and written into the hidden slot and latched. At a scanning clock of 25 MHz, the hidden slot and the real-time rotated concatenation code are compared in each round of traversal. If they match, scanning continues; otherwise, an error is immediately reported and scanning stops.

[0085] Preferably, in step S2: at the rising edge of the preset synchronous scan clock, the first pointer register outputs the channel selection signal within the current address, while the second pointer register latches the resident parameters within the same address and drives the timer to start counting down;

[0086] Optionally, the preset operation for forming the rising edge of the synchronous scan clock in step S2 includes:

[0087] Read the start and end addresses of the scan link, swap the corresponding bits, and send them to the pulse width register;

[0088] The highest two bits of the pulse width register are used as the upper limit of the count. The one-bit ring counter starts to increment from 0 and is immediately cleared after reaching the upper limit. A single pulse is output the instant the counter is cleared.

[0089] After a single pulse passes through a two-stage series rising edge sharpening link, it replaces the original clock signal and is connected to the FPGA global clock network.

[0090] In one embodiment, after the FPGA is powered on and the scan link initialization is completed, the starting address HEAD and the ending address TAIL are read out via AXI-Lite. A dedicated switching module swaps the 16-bit bit vectors of HEAD and TAIL bit by bit, and the resulting swap code is latched into a 16-bit pulse width register PWM.

[0091] In another embodiment, the two highest bits of the PWM are then used as the 2-bit count limit MAX; a 1-bit ring counter increments from 0 under the original 50 MHz clock, immediately resets to zero upon reaching MAX, and outputs a single-cycle pulse at the moment of reset. This pulse is first compressed at the edge by a two-stage differential inverter chain, then sharpened into a narrow pulse with a 300 ps rising edge by BUFIO→BUFG, and finally directly connected to the global clock network through BUFG, replacing the original 50 MHz clock and achieving high-speed scanning with four variable frequency levels from 12.5 to 50 MHz.

[0092] Optionally, in step S2, the first pointer register outputs the channel selection signal within the current address as follows:

[0093] Circularly shift the current address value one bit to the right to obtain a shifted copy;

[0094] The shifted copy is bitwise ORed with the channel selection signal, and the result is written to the high byte of the FPGA's on-chip I / O bit selection area.

[0095] The result of the operation is shifted left by one bit within the same clock cycle and then XORed with itself bitwise. The resulting check code is written to the low byte of the I / O bit selection area.

[0096] In one embodiment, after the FPGA's on-chip Block RAM completes the initialization of the loop-linked list, the scan state machine performs a cyclic right shift of 1 bit on the current cell address addr[15:0] every cycle to obtain a shifted copy shift_addr. Simultaneously, the row and column decoder outputs a 6-bit channel selection signal ch_sel[5:0]. The shifted copy and ch_sel are bitwise ORed on a 16-bit wide OR gate array, and the result is latched into the high byte IO_HIGH[15:0] of the I / O bit selection area.

[0097] It should be noted that within the same clock cycle, IO_HIGH is immediately shifted left by 1 bit to obtain shift_high, which is then XORed with IO_HIGH itself in a 32-bit XOR tree. The resulting 16-bit checksum IO_LOW[15:0] is written to the low byte of the I / O bit selection area at the end of the same clock cycle. IO_HIGH and IO_LOW together constitute a 32-bit parallel output, directly driving the external row and column drivers to achieve bit selection and checksum output within a single cycle.

[0098] Optionally, in step S2, the second pointer register latches the resident parameters at the same address and drives the timer, including:

[0099] Latch the high seven bits of the resident parameter into the second pointer register, invert the low one bit and write it to the lower half byte of the same address;

[0100] The inverse code is added bit by bit to the resident parameter, discarding the carry, and the result is written to the timer check register;

[0101] When the check register is zero, the timer initial value register loads the resident parameters and begins to count down.

[0102] In one embodiment, after the FPGA is powered on, the scan control logic first reads the current resident parameter (8-bit unsigned value) into the on-chip register via the AXI-Lite bus. Subsequently, the dedicated bit field splitting module directly latches the high 7 bits of the parameter into the second pointer register PTR[6:0]; the lowest bit D0 is inverted by a first-stage inverter and immediately written to the low half-byte BIT[3] at the same address to maintain byte alignment.

[0103] In another embodiment, the inverse bit and the complete resident parameter are added in parallel within an 8-bit adder. The carry is forcibly discarded, and only the lower 8 bits of the result are retained and written to a timer check register named CHK_REG. The state machine then continuously polls CHK_REG: once its value is detected as 0, the original value of the resident parameter is immediately written to the TMR_INIT timer initial value register, and simultaneously an 8-bit decrement counter is triggered to decrease downwards from TMR_INIT.

[0104] It should be noted that when the counter reaches zero, the hardware automatically outputs a single-cycle SCAN_END pulse to indicate the end of the current dwell period and the start of the next period. The entire process is completed within a single clock domain, without the need for cross-clock handshakes, ensuring zero-latency switching under a 25MHz scan clock.

[0105] Preferably, in step S3: when the timer is reset to zero, the first pointer register and the second pointer register are incremented simultaneously, pointing to the next address of the scan link;

[0106] Optionally, in step S3, when the timer is reset to zero, both the first pointer register and the second pointer register increment simultaneously as follows:

[0107] The timer reset pulse is fed into an on-chip delay line formed by four inverters connected in series.

[0108] The outputs of each tap of the delay line are combined by an AND gate array to form the trigger edge;

[0109] The trigger edge is applied to both the first pointer register and the second pointer register simultaneously within the same clock cycle.

[0110] In one embodiment, within the FPGA chip, a scan timer outputs a zero-reset pulse once it reaches zero. This pulse is first fed into an on-chip delay line consisting of four inverters connected in series: each inverter stage has a delay of approximately 75 ps, for a total delay of 300 ps. The delay line has a tap at the output of each of the second, third, and fourth inverter stages, and the three tap signals, along with the original pulse, are connected to a 4-input AND gate array.

[0111] It should be noted that the AND gate output generates a sharp trigger edge of approximately 150 ps only when all four signals are high simultaneously. This trigger edge is applied to the clock terminals of the first and second pointer registers simultaneously via a dedicated signal line within the same clock cycle, achieving zero-latency parallel updates.

[0112] Preferably, in step S4: during the period when the channel selection signal is valid, the correction information is written to the current address to replace the original resident parameters or channel identifier; when the cycle flag bit of the end address of the scan link is valid and read, the two-level pointer registers are reset to the starting address in the same clock cycle.

[0113] Optionally, writing the correction information to the current address in step S4 includes:

[0114] The correction information is circularly shifted left by one bit by the current address, and then a bit rotation operation is performed.

[0115] The round-robin result overrides the residency parameters of the current address;

[0116] The overwritten dwell parameter is shifted left by one bit again within the same clock cycle and bitwise ORed with itself, and the result is written back to the channel identifier field.

[0117] In this embodiment, when the rising edge of the clock arrives, the sixteen-bit correction value in the correction register is first XORed bit by bit with the current address to obtain the corrected address. Then, the sixteen bits are shifted one bit to the left, with the highest bit shifted to the lowest bit and the remaining bits shifted one bit to the front to obtain the rotated address. Within the same clock cycle, the rotation result is written into the resident parameter register using the global write enable signal, overwriting the original content. Then, the value of the resident parameter register is immediately shifted one bit to the left again, and then bitwise ORed with the original value. The result is written back to the channel identifier field within the same clock cycle.

[0118] Optionally, the steps following writing the correction information to the current address in step S4 include:

[0119] The current address content is bitwise XORed with the first pointer register, and the result is temporarily stored in the second pointer register;

[0120] The contents of the second pointer register are XORed again with the one's complement of the resident parameter, and the result is written back to the high half byte of the current address.

[0121] After the write-back is completed, the read and write ports for the current address remain open.

[0122] In one embodiment, after the clock edge arrives, all sixteen-bit signals output by the current address register are connected to one end of the first group of XOR gates, and the sixteen-bit signals output by the first pointer register are connected to the other end of the same group of XOR gates. The sixteen XOR gates complete the bitwise XOR in the same clock cycle to form a sixteen-bit XOR result, which is latched into the second pointer register in the same clock cycle through a sixteen-bit parallel line.

[0123] In another embodiment, the sixteen-bit output of the second pointer register and the sixteen-bit inverted code signal output from the resident parameter register—each bit is inverted by an inverter—are simultaneously connected to the second set of XOR gates, and the bitwise XOR is performed again in the same clock cycle to obtain the sixteen-bit final result.

[0124] It should be noted that the high four bits of the result are extracted and written directly back to the high nibble of the current address register via a dedicated high four bit line. The write operation is completed within the same clock cycle by the write enable pulse. After the write pulse ends, the read / write port of the current address register remains enabled, and the sixteen-bit address bus remains directly connected to the register, allowing subsequent cycles to continue reading and writing.

[0125] Optionally, the operation of triggering a two-level pointer register reset by scanning the loop flag bit at the end address of the link in step S4 includes:

[0126] Perform a bitwise XOR operation between the last address and the first address. If the result of the bitwise XOR operation is all 1, latch the cycle flag bit.

[0127] The circular flag bit is connected to the synchronous reset terminal of the two-level pointer register;

[0128] The reset pin clears the pointer and points to the starting address within the same clock cycle.

[0129] In one embodiment, when triggered by the rising edge of the clock, the sixteen-bit end address signal lines stored in the end address register and the sixteen-bit start address signal lines stored in the start address register are connected one-to-one to sixteen XOR gates; each XOR gate outputs one bit, generating a total of sixteen XOR results. All sixteen XOR results are connected to a sixteen-input AND gate; a high-level output from the AND gate indicates that all sixteen bits are equal.

[0130] In another embodiment, the output of the AND gate is directly connected to the data input of the cyclic tag latch. During the clock high level, if the output of the AND gate is high, the cyclic tag latch latches logic 1 and holds it until the next update.

[0131] For example, the output of the cyclic tag latch is simultaneously connected to the synchronous reset terminals of both the first-level and second-level pointer registers. The reset terminals of both pointer registers are active low; when the cyclic tag latch outputs a high level, the reset terminals are pulled low. Within the same clock cycle, the two pointer registers complete their reset operation: all sixteen internal pointers are set to zero. Subsequently, the address selection logic directly loads the sixteen-bit value from the starting address register into the output of the two pointer registers, causing the pointers to point to the starting address within the same clock cycle.

[0132] Optionally, the operation after resetting the two-level pointer registers in step S4 is as follows:

[0133] The reset pulse trigger delay counter is loaded with a fixed value of 1;

[0134] The delay counter overflows in the next clock cycle and outputs an enable signal;

[0135] External correction information is enabled by the enable signal and written into the window, while remaining there until the next zeroing pulse.

[0136] In one embodiment, the reset pulse signal is sent to the asynchronous reset terminal of the delay counter when the rising edge of the clock arrives. The delay counter is immediately forced to zero, and its preset enable terminal is set in the same clock cycle. The fixed value 1 on the preset port is synchronously loaded into the delay counter. At the beginning of the next clock cycle, the delay counter starts counting upward from the stored value 1. The count value reaches 2 at the moment the clock edge arrives and a carry is generated. The carry signal is directly output as an enable pulse.

[0137] It should be noted that the enable pulse lasts for a full clock cycle. During this period, the external correction information bus is opened through a tri-state gate, and the 16-bit data of the external correction information is written to the window register. The writing operation is completed during the high-level phase of the enable pulse. After the enable pulse ends, the latch-holding terminal of the window register is set, and the window register maintains the written 16-bit external correction information until the next clear pulse triggers the delay counter again.

[0138] Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0139] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A high-speed dynamic scanning method for FPGA, characterized in that, Applied to the semiconductor and LED manufacturing fields, the FPGA includes a first pointer register and a second pointer register. The method includes the following steps: Step S1: Write the scan link in the FPGA on-chip memory area in a unidirectional loop order, wherein the scan link length is equal to the total number of contacts of the semiconductor test probe array or the total number of rows and columns of the LED display array; Step S2: At the rising edge of the preset synchronous scan clock, the first pointer register outputs the channel selection signal within the current address, and at the same time, the second pointer register latches the resident parameters within the same address and drives the timer to start counting down; Step S3: When the timer returns to zero, the first pointer register and the second pointer register increment simultaneously, pointing to the next address of the scan link; Step S4: During the period when the channel selection signal is valid, write the correction information to the current address to replace the original resident parameters or channel identifier; when the cycle flag bit of the end address of the scan link is valid and read, the two-level pointer registers are reset to the starting address in the same clock cycle.

2. The FPGA high-speed dynamic scanning method according to claim 1, characterized in that, The preset synchronous scan clock rising edge generation operation in step S2 includes: Read the start and end addresses of the scan link, swap the corresponding bits, and send them to the pulse width register; The highest two bits of the pulse width register are used as the upper limit of the count. The one-bit ring counter starts to increment from 0 and is immediately cleared after reaching the upper limit. A single pulse is output the instant the counter is cleared. After a single pulse passes through a two-stage series rising edge sharpening link, it replaces the original clock signal and is connected to the FPGA global clock network.

3. The FPGA high-speed dynamic scanning method according to claim 1, characterized in that, In step S2, the first pointer register outputs the channel selection signal within the current address as follows: Circularly shift the current address value one bit to the right to obtain a shifted copy; The shifted copy is bitwise ORed with the channel selection signal, and the result is written to the high byte of the FPGA's on-chip I / O bit selection area. The result of the operation is shifted left by one bit within the same clock cycle and then XORed with itself bitwise. The resulting check code is written to the low byte of the I / O bit selection area.

4. The FPGA high-speed dynamic scanning method according to claim 1, characterized in that, Step S2, in which the second pointer register latches the resident parameters at the same address and drives the timer, includes: Latch the high seven bits of the resident parameter into the second pointer register, invert the low one bit and write it to the lower half byte of the same address; The inverse code is added bit by bit to the resident parameter, discarding the carry, and the result is written to the timer check register; When the check register is zero, the timer initial value register loads the resident parameters and begins to count down.

5. The FPGA high-speed dynamic scanning method according to claim 4, characterized in that, In step S3, when the timer is reset to zero, both the first pointer register and the second pointer register increment simultaneously as follows: The timer reset pulse is fed into an on-chip delay line formed by four inverters connected in series. The outputs of each tap of the delay line are combined by an AND gate array to form the trigger edge; The trigger edge is applied to both the first pointer register and the second pointer register simultaneously within the same clock cycle.

6. The FPGA high-speed dynamic scanning method according to claim 1, characterized in that, Step S4, which involves writing the correction information to the current address, includes: The correction information is circularly shifted left by one bit by the current address, and then a bit rotation operation is performed. The round-robin result overrides the residency parameters of the current address; The overwritten dwell parameter is shifted left by one bit again within the same clock cycle and bitwise ORed with itself, and the result is written back to the channel identifier field.

7. The FPGA high-speed dynamic scanning method according to claim 1, characterized in that, Step S4, following the writing of correction information to the current address, includes the following steps: The current address content is bitwise XORed with the first pointer register, and the result is temporarily stored in the second pointer register; The contents of the second pointer register are XORed again with the one's complement of the resident parameter, and the result is written back to the high half byte of the current address. After the write-back is completed, the read and write ports for the current address remain open.

8. The FPGA high-speed dynamic scanning method according to claim 1, characterized in that, Step S4, which involves scanning the loop flag bit at the end of the link address to trigger a reset of the two-level pointer register, includes: Perform a bitwise XOR operation between the last address and the first address. If the result of the bitwise XOR operation is all 1, latch the cycle flag bit. The circular flag bit is connected to the synchronous reset terminal of the two-level pointer register; The reset pin clears the pointer and points to the starting address within the same clock cycle.

9. The FPGA high-speed dynamic scanning method according to claim 2, characterized in that, The specific operation after resetting the two-level pointer registers in step S4 is as follows: The reset pulse trigger delay counter is loaded with a fixed value of 1; The delay counter overflows in the next clock cycle and outputs an enable signal; External correction information is enabled by the enable signal and written into the window, while remaining there until the next zeroing pulse.

10. A high-speed dynamic scanning device for FPGA, characterized in that, Includes a control system for performing the FPGA high-speed dynamic scanning method as described in claim 1, the control system comprising: The link writing module is used to write the scan link in a unidirectional loop sequence to the on-chip memory area of ​​the FPGA. The length of the scan link is equal to the total number of contacts of the semiconductor test probe array or the total number of rows and columns of the LED display array. The dual-pointer drive module is used to output the channel selection signal within the current address in the first pointer register at the rising edge of the preset synchronous scan clock, while the second pointer register latches the resident parameters within the same address and drives the timer to start counting down. The synchronous increment module is used to increment both the first pointer register and the second pointer register simultaneously when the timer returns to zero, pointing to the next address of the scan link; The online write-back module is used to write correction information to the current address during the period when the channel selection signal is valid, replacing the original resident parameters or channel identifier; when the cycle flag bit of the end address of the scan link is valid and read, the two-level pointer registers are reset to the starting address in the same clock cycle.

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