Preparation method of power device
By forming a metal layer at high temperature in the back-end process of superjunction MOSFETs and increasing the heat transfer distance during the cooling process, the problem of insufficient tensile stress in the metal layer is solved, thereby improving the electron mobility and drive current performance of the device.
Patent Information
- Application Number
- CN202511050295.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-11
AI Technical Summary
In the back-end process of superjunction MOSFETs, traditional fabrication processes result in insufficient tensile stress or loss of the metal layer, affecting the Vdson performance of the device.
A metal layer is formed using PVD technology at an temperature of 400℃ to 440℃. During the cooling process, tensile stress is retained by increasing the heat transfer distance. Inert gas is used for cooling, and the semiconductor structure is raised from the first height to the second height for slow cooling.
It significantly accelerated electron mobility, increased device drive current, and improved the device's Delta Vdson performance.
Smart Images
Figure CN120936059A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power device manufacturing technology, and specifically to a method for preparing a power device. Background Technology
[0002] Superjunction MOSFET (Metal-Oxide-Semiconductor Transistor) is a novel power device with a superjunction structure design. This design allows the low-doped epitaxial layer to ensure the breakdown voltage when turned off, while forming a highly doped N+ region as a current path when turned on, thereby achieving high blocking voltage and low on-resistance.
[0003] Among them, Vdson (source-drain on-state voltage) is one of the important performance indicators of superjunction MOSFET devices. How to improve Delta Vdson (ΔVdson) under different conditions is an important research direction in the metal layer (e.g., aluminum layer) fabrication process in the back-end process of superjunction MOSFETs. According to SMT (Surface Mount Technology) theory, stress can affect the channel, and tensile stress can significantly accelerate the electron mobility of MOS devices (e.g., NMOS devices), thereby increasing the drive current of NMOS devices.
[0004] Currently, in the traditional back-end flow (BEOL flow) of superjunction MOSFETs, macroscopic warpage characterization and high-temperature stress show that the tensile stress of thicker hot metal layers (such as aluminum layers) is insufficient or lost. Therefore, thicker hot metal layers (such as aluminum layers) are a significant site affecting Vdson. Summary of the Invention
[0005] This application provides a method for fabricating power devices, which can solve the problem that the metal layer obtained by traditional fabrication processes affects the Vdson of the device due to insufficient tensile stress / loss in the back-end process of superjunction MOSFET devices.
[0006] This application provides a method for fabricating a power device, including:
[0007] A substrate is provided in which a plurality of first conductivity type pillars and a plurality of second conductivity type pillars are formed, the first conductivity type pillars and the first conductivity type pillars are arranged at intervals, and a gate structure is formed on the substrate, the gate structure being located on the first conductivity type pillars;
[0008] An interlayer dielectric layer is formed, which covers the surface of the second conductivity type pillar in the substrate and the gate structure;
[0009] The interlayer dielectric layer is etched and stopped at the surface of the second type of conductive pillar to form multiple vias;
[0010] A barrier layer is formed, which covers the sidewall and bottom wall of the through-hole and the interlayer dielectric layer;
[0011] A metal layer is formed using a PVD process at an temperature of 400℃ to 440℃, the metal layer filling the vias and covering the barrier layer.
[0012] The semiconductor structure after the metal layer is formed is transferred to the cooling stage of the cooling process chamber. An inert gas is introduced into the cooling process chamber, and the semiconductor structure after the metal layer is formed is raised from a first height to a second height relative to the cooling stage for cooling.
[0013] Optionally, in the method for fabricating the power device, a circulating water cooling system is provided at the bottom of the cooling workbench. The circulating water cooling system includes at least a cooling source and cooling pipes, wherein a portion of the cooling pipes are laid inside the cooling workbench, and the remaining cooling pipes are located inside the workbench support at the bottom of the cooling workbench. The cooling source is located at the bottom of the workbench support.
[0014] Optionally, in the method for fabricating the power device, after the semiconductor structure after forming the metal layer rises from a first height to a second height relative to the cooling stage, the distance between the semiconductor structure after forming the metal layer and the coolant in the cooling pipe increases, the heat conduction path increases, so as to slow down the cooling rate of the semiconductor structure after forming the metal layer.
[0015] Optionally, in the method for fabricating the power device, the semiconductor structure after the metal layer is formed is transferred to the cooling stage of the cooling process chamber, an inert gas is introduced into the cooling process chamber, and the semiconductor structure after the metal layer is formed is raised from a first height to a second height relative to the cooling stage for cooling. During the cooling process, the gas flow rate of the inert gas is 3 Torr; the cooling process lasts for 120 seconds.
[0016] Optionally, in the fabrication method of the power device, a metal layer is formed using a PVD process at an environment of 420°C.
[0017] Optionally, in the method for fabricating the power device, the metal layer is an aluminum layer.
[0018] Optionally, in the fabrication method of the power device, the thickness of the metal layer located on the upper surface of the interlayer dielectric layer is 4 μm to 5 μm.
[0019] Optionally, in the method for fabricating the power device, after forming the barrier layer and before forming the metal layer, the method further includes performing a degassing process on the semiconductor structure after forming the barrier layer, wherein the process temperature of the degassing process chamber is 380°C to 420°C.
[0020] Optionally, in the method for fabricating the power device, after cooling the semiconductor structure following the formation of the metal layer, the method further includes:
[0021] The metal layer and the barrier layer are etched and stopped on the surface of the interlayer dielectric layer to form a trench located on the interlayer dielectric layer away from all the vias.
[0022] Optionally, in the method for fabricating the power device, the barrier layer comprises a titanium layer and a titanium nitride layer, wherein the titanium layer covers the sidewall and bottom wall of the via and the interlayer dielectric layer, and the titanium nitride layer covers the titanium layer.
[0023] The technical solution of this application has at least the following advantages:
[0024] This application provides a method for fabricating a power device. After forming a barrier layer on the surface of the interlayer dielectric layer and on the sidewalls and bottom walls of vias in the subsequent process flow, a metal layer is formed using a PVD process at an environment of 400°C to 440°C. The semiconductor structure after metal layer formation is then transferred to a cooling stage in a cooling process chamber. An inert gas is introduced into the cooling process chamber, and the semiconductor structure after metal layer formation is raised from a first height to a second height relative to the cooling stage for cooling. This application utilizes the 400°C to 440°C environment to generate more tensile stress. By raising the semiconductor structure after metal layer formation from the first height to the second height, the heat transfer distance increases, and the heat transfer efficiency decreases. This transforms the semiconductor structure from traditional rapid cooling to slow cooling, allowing more tensile stress to be retained and applied to the preceding layer of the metal layer, significantly accelerating the electron mobility of the device, increasing the device drive current, and thus improving the device's Delta Vdson performance. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0026] Figure 1This is a flowchart of a method for fabricating a power device according to an embodiment of the present invention;
[0027] Figures 2-5 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of the power device according to an embodiment of the present invention;
[0028] Figure 6 This is a schematic diagram of the process chamber for cooling treatment according to an embodiment of this application;
[0029] The reference numerals in the attached figures are explained as follows:
[0030] 10-Substrate, 11-Pillar of first conductivity type, 12-Pillar of second conductivity type, 13-Heavily doped region, 21-Gate oxide layer, 22-Gate gate, 30-Interlayer dielectric layer, 31-Through hole, 40-Barrier layer, 50-Metal layer, 60-Semiconductor structure after forming the metal layer;
[0031] 1-Cooling process chamber, 2-Cooling workbench, 3-Workbench support, 4-Cooling source, 5-Cooling pipeline, 6-Ejector pin. Detailed Implementation
[0032] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0035] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0036] This application provides a method for fabricating a power device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a power device according to an embodiment of the present invention. The method for fabricating the power device includes:
[0037] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after the formation of an interlayer dielectric layer according to an embodiment of this application. A substrate 10 is provided, in which a plurality of first conductivity type pillars 11 and a plurality of second conductivity type pillars 12 are formed. The first conductivity type pillars 11 and the first conductivity type pillars 12 are arranged at intervals. A gate structure is formed on the substrate 10, and the gate structure is located on the first conductivity type pillars 11.
[0038] Specifically, the gate structure includes a gate oxide layer 21 and a gate 22, wherein the gate oxide layer 21 at least covers each of the first conductivity type pillars 11, and the gate 22 covers the gate oxide layer 21. A heavily doped region 13 is further formed in the region near the surface of each of the first conductivity type pillars 11.
[0039] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
[0040] In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.
[0041] Then, proceed to step S2: Continue to refer to Figure 2 An interlayer dielectric layer 30 is formed, which covers the surface of the second conductivity type pillar 12 in the substrate 10 and the gate structure.
[0042] In this embodiment, the interlayer dielectric layer 30 includes at least a silicon oxide layer.
[0043] Next, proceed to step S3: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of vias in an embodiment of this application. The interlayer dielectric layer 30 is etched and stopped on the surface of the second conductivity type pillar 12 to form a plurality of vias 31.
[0044] Further, proceed to step S4: (Refer to...) Figure 4 , Figure 4This is a schematic diagram of the semiconductor structure after the formation of the barrier layer according to an embodiment of this application. The barrier layer 40 is formed, and the barrier layer 40 covers the sidewall and bottom wall of the via 31 and the interlayer dielectric layer 30.
[0045] Preferably, the barrier layer 40 includes a titanium layer and a titanium nitride layer (not shown), wherein the titanium layer covers the sidewall and bottom wall of the via 31 and the interlayer dielectric layer 30, and the titanium nitride layer covers the titanium layer.
[0046] Preferably, after forming the barrier layer 40 and before forming the metal layer 50, the method for fabricating the power device may further include: processing the semiconductor structure after forming the barrier layer 40 ( Figure 4 The semiconductor structure shown performs a degassing process, wherein the process temperature of the degassing process chamber is 380℃~420℃.
[0047] In this embodiment, the semiconductor structure after the formation of the barrier layer 40 ( Figure 4 During the degassing process of the semiconductor structure shown, the process temperature of the degassing process chamber is 400°C.
[0048] The above-mentioned degassing process is used to remove impurity gases from the surface or interior of the semiconductor structure after the formation of the barrier layer 40, so as to ensure the quality and stability of subsequent processes.
[0049] Next, proceed to step S5: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the metal layer in an embodiment of this application. The metal layer 50 is formed by PVD process in an environment of 400°C to 440°C. The metal layer 50 fills the via 31 and covers the barrier layer 40.
[0050] In this embodiment, the metal layer 50 is formed using a PVD process at an environment of 420°C.
[0051] Preferably, the metal layer 50 is an aluminum layer.
[0052] Preferably, the thickness of the metal layer 50 located on the upper surface of the interlayer dielectric layer 30 (or the upper surface of the barrier layer 40) is 4 μm to 5 μm.
[0053] Finally, proceed to step S6: (Refer to...) Figure 6 , Figure 6This is a schematic diagram of a process chamber for cooling according to an embodiment of this application. The semiconductor structure 60 after the metal layer is formed is transferred to the cooling stage 2 of the cooling process chamber 1. An inert gas is introduced into the cooling process chamber 1, and the semiconductor structure 60 after the metal layer is formed is raised from a first height to a second height relative to the cooling stage 2 for cooling.
[0054] Specifically, the cooling worktable 2 is equipped with multiple liftable pins 6, which are used to support and lift the semiconductor structure 60 formed with the metal layer on the cooling worktable 2, so that the semiconductor structure 60 formed with the metal layer can rise from a first height to a second height.
[0055] Preferably, the first height and the second height both refer to the straight-line distance between the upper surface of the cooling worktable 2 and the back surface of the semiconductor structure 60 after the metal layer is formed, when the ejector pin 6 is ejected from the cooling worktable 2 at different heights.
[0056] In this embodiment, the difference between the second height and the first height is 35mm to 45mm. That is, compared with the working height of the wafer on the cooling stage in the conventional fabrication process, the working height of the wafer (the semiconductor structure 60 after the metal layer) on the cooling stage 2 in the fabrication method provided in this application is increased by 35mm to 45mm.
[0057] In this embodiment, the inert gas introduced into the cooling process chamber 1 can be argon.
[0058] Preferably, the bottom of the cooling workbench 2 is provided with a circulating water cooling system, which includes at least a cooling source 5 and cooling pipes 4. Part of the cooling pipes 4 are laid inside the cooling workbench 2 and near its upper surface, while the remaining cooling pipes 4 are located inside the workbench support 3 at the bottom of the cooling workbench 2. The cooling source 5 is located at the bottom of the workbench support 3. The cooling source 5 provides coolant, which flows through the cooling pipes 4 according to... Figure 6 The arrows indicate the direction of flow.
[0059] When the cooling workbench 2 rises from the first height to the second height, the distance between the semiconductor structure 60 after the metal layer is formed and the coolant in the cooling pipe 4 increases, the heat conduction distance increases, and the heat transfer efficiency decreases, thereby slowing down the cooling rate of the semiconductor structure 60 after the metal layer is formed.
[0060] Preferably, the semiconductor structure 60 after the metal layer is formed is transferred to the cooling stage 2 of the cooling process chamber 1, argon gas is introduced into the cooling process chamber 1, and the semiconductor structure 60 after the metal layer is formed is raised from a first height to a second height relative to the cooling stage 2 (coolant in the cooling pipe 4) for cooling. During the cooling process, the argon gas flow rate is 3 Torr; the cooling process lasts for 120 seconds.
[0061] In this application, depositing a metal layer at an environment of 400°C to 440°C can generate more tensile stress. Subsequently, by raising the semiconductor structure after the formation of the metal layer from a first height to a second height relative to the cooling stage, the heat conduction distance increases and the heat transfer efficiency decreases. This transforms the semiconductor structure from traditional rapid cooling to slow cooling, allowing more tensile stress to be retained. The retained tensile stress can act on all the preceding layers of the metal layer, significantly accelerating the electron mobility of the device, increasing the device drive current, and thus improving the device Delta Vdson performance.
[0062] Furthermore, after cooling the semiconductor structure 60 formed with the metal layer, the fabrication method of the power device may further include: etching the metal layer 50 and the barrier layer 40 and stopping at the surface of the interlayer dielectric layer 30 to form a trench (not shown), the trench being located on the interlayer dielectric layer 30 away from all the vias 31. In this embodiment, the trench is located on the right side of the interlayer dielectric layer 30 away from all the vias 31.
[0063] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a power device, characterized in that, include: A substrate is provided in which a plurality of first conductivity type pillars and a plurality of second conductivity type pillars are formed, the first conductivity type pillars and the first conductivity type pillars are arranged at intervals, and a gate structure is formed on the substrate, the gate structure being located on the first conductivity type pillars; An interlayer dielectric layer is formed, which covers the surface of the second conductivity type pillar in the substrate and the gate structure; The interlayer dielectric layer is etched and stopped at the surface of the second type of conductive pillar to form multiple vias; A barrier layer is formed, which covers the sidewall and bottom wall of the through-hole and the interlayer dielectric layer; A metal layer is formed using a PVD process at an temperature of 400℃ to 440℃, the metal layer filling the vias and covering the barrier layer. The semiconductor structure after the metal layer is formed is transferred to the cooling stage of the cooling process chamber. An inert gas is introduced into the cooling process chamber, and the semiconductor structure after the metal layer is formed is raised from a first height to a second height relative to the cooling stage for cooling.
2. The method for fabricating the power device according to claim 1, characterized in that, The bottom of the cooling workbench is equipped with a circulating water cooling system, which includes at least a cooling source and cooling pipes. Some of the cooling pipes are laid inside the cooling workbench, and the remaining cooling pipes are located inside the workbench support at the bottom of the cooling workbench. The cooling source is located at the bottom of the workbench support.
3. The method for fabricating the power device according to claim 2, characterized in that, After the semiconductor structure with the metal layer formed rises from a first height to a second height relative to the cooling stage, the distance between the semiconductor structure with the metal layer formed and the coolant in the cooling pipe increases, thereby slowing down the cooling rate of the semiconductor structure with the metal layer formed.
4. The method for fabricating a power device according to claim 1, characterized in that, The semiconductor structure after the metal layer is formed is transferred to the cooling stage of the cooling process chamber. Inert gas is introduced into the cooling process chamber, and the semiconductor structure after the metal layer is formed is raised from a first height to a second height relative to the cooling stage for cooling. During the cooling process, the gas flow rate of the inert gas is 3 Torr; the cooling process lasts for 120 seconds.
5. The method for fabricating a power device according to claim 1, characterized in that, A metal layer is formed using PVD technology at an temperature of 420℃.
6. The method for fabricating a power device according to claim 1, characterized in that, The metal layer is an aluminum layer.
7. The method for fabricating a power device according to claim 1, characterized in that, The thickness of the metal layer located on the upper surface of the interlayer dielectric layer is 4 μm to 5 μm.
8. The method for fabricating a power device according to claim 1, characterized in that, After forming the barrier layer and before forming the metal layer, the method for fabricating the power device further includes performing a degassing process on the semiconductor structure after forming the barrier layer, wherein the process temperature of the degassing process chamber is 380°C to 420°C.
9. The method for fabricating a power device according to claim 1, characterized in that, After cooling the semiconductor structure following the formation of the metal layer, the method for fabricating the power device further includes: The metal layer and the barrier layer are etched and stopped on the surface of the interlayer dielectric layer to form a trench located on the interlayer dielectric layer away from all the vias.
10. The method for fabricating a power device according to claim 1, characterized in that, The barrier layer comprises a titanium layer and a titanium nitride layer, wherein the titanium layer covers the sidewall and bottom wall of the via and the interlayer dielectric layer, and the titanium nitride layer covers the titanium layer.