Pixel for display device and display device

Abstract

A pixel for a display device and a display device are provided. The pixel for a display device includes: a light emitting element; a first transistor including a first electrode electrically connected to the first node and controlling the driving current; a second transistor electrically connected between the data line and the first node and turned on in response to a first scan signal supplied through the first scan line; a third transistor electrically connected between the second node and a third node electrically connected to the second electrode of the first transistor, and turned on in response to a first scan signal; and a fourth transistor turned on in response to a second scan signal supplied through the second scan line, and applying a bias voltage to the first transistor. The fourth transistor is turned on at a first frequency. The second transistor and the third transistor are turned on at a second frequency different from the first frequency.

Description

[0001] This application is a divisional application of application No. 202010878943.X, entitled "Pixels for a Display Device and Display Device", filed with the State Intellectual Property Office on August 27, 2020. Technical Field

[0002] The embodiments relate to a display device, and to a pixel and a display device including the pixel. Background Technology

[0003] The display device may include pixels. Each pixel may include a transistor, a light-emitting element electrically connected to or electrically linked to the transistor, and a capacitor. The transistor may be turned on in response to a corresponding signal provided via a line, and a predetermined drive current may be generated by the turned-on transistor. The light-emitting element may emit light in response to the drive current.

[0004] Recently, methods for driving display devices at low frequencies have been developed to improve driving efficiency and minimize power consumption. Therefore, when driving display devices at low frequencies, methods to improve display quality are needed.

[0005] It will be understood that this background in the technical section is partly intended to provide useful context for understanding the technology. However, this background in the technical section may also include ideas, concepts, or knowledge that were not known or realized by a person skilled in the art prior to the corresponding valid application date of the subject matter disclosed herein. Summary of the Invention

[0006] The embodiments relate to a pixel that can periodically apply a bias voltage to a driving transistor during low-frequency driving.

[0007] The embodiments relate to a display device having the aforementioned pixels and driven at various driving frequencies.

[0008] However, the purpose of disclosure is not limited to the aforementioned purposes, and can be extended in various forms without departing from the spirit and scope of disclosure.

[0009] An embodiment may provide a pixel for a display device. The pixel may include: a light-emitting element; a first transistor, which may include a first electrode electrically connected to a first node electrically connected to a first power supply and controls a drive current based on a voltage at a second node; a second transistor, which may be electrically connected between a data line and the first node and can be turned on in response to a first scan signal supplied via a first scan line; a third transistor, which may be electrically connected between the second node and the third node and can be turned on in response to the first scan signal, the third node being electrically connected to a second electrode of the first transistor; and a fourth transistor, which can be turned on in response to a second scan signal supplied via a second scan line and can supply a bias voltage to the first transistor. The fourth transistor may be turned on at a first frequency, and the second and third transistors may be turned on at a second frequency different from the first frequency.

[0010] The second frequency can be lower than the first frequency.

[0011] In an embodiment, the second frequency may be equal to the image refresh rate and may be an equal part of the first frequency.

[0012] In an embodiment, the pixel may further include: a fifth transistor electrically connected between a first power source and a first node, and capable of being turned off in response to an emission control signal supplied via an emission control line; a sixth transistor electrically connected between a third node and a fourth node, and capable of being turned off in response to an emission control signal, the fourth node being electrically connected to a first electrode of the light-emitting element; a seventh transistor electrically connected between the fourth node and a first initialization power source, and capable of being turned on in response to a second scan signal; an eighth transistor electrically connected between a second node and a second initialization power source, and capable of being turned on in response to a third scan signal supplied via a third scan line; and a storage capacitor electrically connected between the first power source and the second node.

[0013] In one embodiment, the fifth to seventh transistors can be turned on at a first frequency, and the eighth transistor can be turned on at a second frequency.

[0014] In one embodiment, the fourth transistor may be electrically connected between the transmit control line and the third node, and may apply the transmit control signal as a bias voltage to the third node in response to the second scan signal.

[0015] In one embodiment, the fourth transistor may be electrically connected between the transmit control line and the first node, and may apply the transmit control signal as a bias voltage to the third node in response to the second scan signal.

[0016] In an embodiment, the fourth transistor may be electrically connected between the bias power supply and the third node or between the bias power supply and the first node, and may apply the voltage of the bias power supply as a bias voltage to the third node or the first node in response to the second scan signal.

[0017] An embodiment may provide a pixel for a display device. The pixel may include: a light-emitting element; a first transistor, which may include a first electrode electrically connected to a first node electrically connected to a first power supply and controls a drive current based on a voltage at a second node; a second transistor, which may be electrically connected between a data line and the first node and can be turned on in response to a first scan signal supplied via a first scan line; a third transistor, which may be electrically connected between the second node and the third node and can be turned on in response to a second scan signal supplied via a second scan line, the third node being electrically connected to a second electrode of the first transistor; and a fourth transistor, which can be turned on in response to a third scan signal supplied via a third scan line and can apply a bias voltage to the first transistor. The fourth transistor may be turned on at a first frequency, the second and third transistors may be turned on at a second frequency lower than the first frequency, and the lengths of the on-time of the second transistor and the on-time of the third transistor may be different from each other.

[0018] In an embodiment, the second frequency may be equal to the image refresh rate and correspond to an equal portion of the first frequency.

[0019] The pixel may further include: a fifth transistor electrically connected between a first power source and a first node, and turned off in response to an emission control signal supplied via a first emission control line; a sixth transistor electrically connected between a third node and a fourth node, and turned off in response to an emission control signal supplied via a second emission control line, the fourth node being electrically connected to a first electrode of the light-emitting element; a seventh transistor electrically connected between the fourth node and an initialization power source, and turned on in response to a third scan signal supplied via a fourth scan line; and a storage capacitor electrically connected between the first power source and a second node.

[0020] In one embodiment, the fifth and sixth transistors may be turned on at a first frequency.

[0021] In one embodiment, a portion of the off period of the fifth transistor may overlap with a portion of the on period of the sixth transistor, and the third and seventh transistors may be controlled simultaneously.

[0022] In an embodiment, the conduction period of the fourth transistor may not overlap with the conduction periods of the third transistor and the seventh transistor.

[0023] In an embodiment, the fourth transistor may be electrically connected between the first transmit control line and the third node or between the first transmit control line and the first node, and may apply the transmit control signal as a bias voltage to the third node or the first node in response to the third scan signal.

[0024] The fourth transistor can be electrically connected between the bias power supply and the third node or between the bias power supply and the first node, and can apply the voltage of the bias power supply as a bias voltage to the third node or the first node in response to the third scan signal.

[0025] An embodiment may provide a display device. The display device may include: a pixel electrically connected to a first scan line, a second scan line, an emission control line, and a data line; a scan driver capable of supplying a second scan signal to the second scan line at a first frequency and supplying a first scan signal to the first scan line at a second frequency corresponding to the pixel's image refresh rate; an emission driver capable of supplying an emission control signal to the emission control line at the first frequency; a data driver capable of supplying a data signal to the corresponding data line at a second frequency; and a timing controller capable of controlling the driving of the scan driver, the emission driver, and the data driver. Among the pixels, a pixel that can be located in the i-th horizontal row (where "i" is a natural number) may include: a light-emitting element; a first transistor, which may include a first electrode electrically connected to a first node electrically connected to a first power supply, and controls a drive current based on the voltage of a second node; a second transistor, which may be electrically connected between a data line and the first node, and can be turned on in response to a first scan signal supplied through the i-th first scan line; a third transistor, which may be electrically connected between the second node and the third node, and can be turned on in response to the first scan signal supplied through the i-th first scan line, the third node being electrically connected to a second electrode of the first transistor; and a fourth transistor, which can be turned on in response to a second scan signal supplied through the i-th second scan line, and can apply a bias voltage to the first transistor. The second frequency may be an equal part of the first frequency.

[0026] In an embodiment, the scan driver may include: a first scan driver capable of supplying a first scan signal to each of the first scan lines at a second frequency; and a second scan driver capable of supplying a second scan signal to each of the second scan lines at a first frequency.

[0027] In an embodiment, a first scan driver may supply a first scan signal during a display scan period of one frame period and may not supply a first scan signal during a self-scan period of one frame period; a second scan driver may supply a second scan signal during both the display scan period and the self-scan period; a transmit driver may supply a transmit control signal during both the display scan period and the self-scan period; and a data signal may be written to a pixel during the display scan period.

[0028] In an embodiment, the pixel disposed in the i-th horizontal row may further include: a fifth transistor electrically connected between a first power supply and a first node, and capable of being turned off in response to an emission control signal supplied via the i-th emission control line; a sixth transistor electrically connected between a third node and a fourth node, and capable of being turned off in response to an emission control signal supplied via the i-th emission control line, the fourth node being electrically connected to a first electrode of the light-emitting element; a seventh transistor electrically connected between the fourth node and a first initialization power supply, and capable of being turned on in response to a second scan signal supplied via the i-th second scan line; an eighth transistor electrically connected between a second node and a second initialization power supply, and capable of being turned on in response to a first scan signal supplied via the (i-1)-th first scan line; and a storage capacitor electrically connected between the first power supply and the second node.

[0029] In one embodiment, the fourth transistor may be electrically connected between the i-th emitter control line and the third node. Attached Figure Description

[0030] The above and other features will become more apparent from the further detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0032] Figure 2A This is an equivalent circuit diagram showing the pixels according to an embodiment.

[0033] Figure 2B It is shown Figure 2A The equivalent circuit diagram of the pixel variant.

[0034] Figure 3A It is shown Figure 2A A timing diagram of an example of pixel-driven operation.

[0035] Figure 3B It is shown Figure 2A A timing diagram of an example of pixel-driven operation.

[0036] Figures 4A to 4DThis is a timing diagram illustrating an example of the start pulses supplied to the transmit driver and scan driver included in the display device according to the image refresh rate.

[0037] Figure 5 This is a diagram illustrating an example of a method for driving a display device according to an image refresh rate.

[0038] Figure 6 and Figure 7 It is shown that it includes Figure 1 An example of an equivalent circuit diagram of pixels in a display device.

[0039] Figure 8 It is shown Figure 1 A block diagram of an example display device.

[0040] Figure 9 It is shown that it includes Figure 8 An example of an equivalent circuit diagram of pixels in a display device.

[0041] Figure 10 It is shown Figure 9 A timing diagram of an example of pixel-driven operation.

[0042] Figure 11 It is shown that it includes Figure 8 An example of an equivalent circuit diagram of pixels in a display device.

[0043] Figure 12A It is shown Figure 11 A timing diagram of an example of pixel-driven operation.

[0044] Figure 12B It is shown Figure 11 A timing diagram of an example of pixel-driven operation.

[0045] Figures 13 to 15 It is shown Figure 11 The equivalent circuit diagram of the pixel variant.

[0046] Figures 16 to 19 It is shown Figure 11 The equivalent circuit diagram of the pixel variant. Detailed Implementation

[0047] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] In order to describe the disclosed embodiments, some parts that are not related to the description may be omitted, and the same reference numerals denote the same elements throughout the specification.

[0049] When a layer, membrane, region, substrate, or area is referred to as being "on" another layer, membrane, region, substrate, or area, it may be directly on said other layer, membrane, region, substrate, or area, or there may be intermediate layers, intermediate membranes, intermediate regions, intermediate substrates, or intermediate areas between them. Conversely, when a layer, membrane, region, substrate, or area is referred to as being "directly on" another layer, membrane, region, substrate, or area, there may be no intermediate layers, intermediate membranes, intermediate regions, intermediate substrates, or intermediate areas between them. Furthermore, when a layer, membrane, region, substrate, or area is referred to as being "below" another layer, membrane, region, substrate, or area, it may be directly below said other layer, membrane, region, substrate, or area, or there may be intermediate layers, intermediate membranes, intermediate regions, intermediate substrates, or intermediate areas between them. Conversely, when a layer, membrane, region, substrate, or area is referred to as being "directly below" another layer, membrane, region, substrate, or area, there may be no intermediate layers, intermediate membranes, intermediate regions, intermediate substrates, or intermediate areas between them. Furthermore, "above" or "on" can include being positioned on or below a target, and does not necessarily imply a direction based on gravity.

[0050] For ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those depicted in the drawings. For example, in the case where the device shown in the drawings is flipped, a device positioned “below” or “below” another device may be placed “above” said other device. Therefore, the descriptive term “below” can include both a below position and an above position. The device may also be oriented in other directions; thus, spatial relative terms can be interpreted differently depending on the orientation.

[0051] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to said other element, or “electrically connected” to said other element in the presence of one or more intermediate elements. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combinations thereof.

[0052] In the accompanying drawings, the dimensions and thicknesses of the elements may be enlarged for better understanding, clarity, and ease of description. However, the disclosure is not limited to the dimensions and thicknesses shown. In the accompanying drawings, the thicknesses of layers, films, panels, areas, and other elements may be exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and areas may be exaggerated for better understanding and ease of description.

[0053] Furthermore, in the instruction manual, the phrase "in a plan view" refers to the view of the target portion from above, while the phrase "in a schematic sectional view" refers to the view of the target portion as a schematic cross-section taken by vertically cutting it from the side.

[0054] Additionally, the terms "overlay" or "surround" indicate that the first target may be above, below, or to one side of the second target, or vice versa. Furthermore, the term "overlay" may include layer, stack, face or facing, "extend over," cover or partially cover, or any other suitable term that will be understood and appreciated by those skilled in the art. The terms "face" and "facing" indicate that the first element may be directly or indirectly opposite the second element. In the case where a third element is located between the first and second elements, although they still face each other, the first and second elements may be understood as indirectly opposite each other. When an element is described as "not" overlaying another element or "not to" be "overlayed" with another element, this may include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable term that will be understood and appreciated by those skilled in the art.

[0055] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0056] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a combined or separate sense and can be understood to be equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0057] It will be understood that although the terms “first,” “second,” etc., may be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be named the second element without departing from the publicly stated teaching. Similarly, the second element may also be named the first element.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Furthermore, it will be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an ideal or overly formal sense unless expressly defined herein.

[0059] In the following description, the disclosed embodiments will be illustrated with reference to the accompanying drawings.

[0060] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0061] Reference Figure 1 The display device 1000 may include a pixel unit 100, scan drivers 200 and 300, a transmit driver 400, a data driver 500, and a timing controller 600.

[0062] Scan drivers 200 and 300 can be classified as a first scan driver 200 and a second scan driver 300 based on their construction and operation. However, the classification of scan drivers 200 and 300 is for ease of description, and at least some of scan drivers 200 and 300 and transmit driver 400 can be integrated into a single drive circuit, module, etc., according to design.

[0063] The display device 1000 can display one or more images at various image refresh rates (i.e., refresh rate, drive frequency, or screen display rate) depending on the driving conditions. The image refresh rate can be the frequency at which the drive transistor actually writes data signals to each pixel PX. For example, the image refresh rate can also be referred to as the scan rate or screen display frequency, and can represent the frequency at which the displayed image is reproduced or refreshed per second.

[0064] In this embodiment, the image refresh rate can be the output frequency of the data driver 500 and / or the first scan driver 200, which can output written scan signals. For example, the refresh rate for video driving can be a frequency of about 60 Hz or higher (e.g., about 120 Hz). Here, the scan signal output from the first scan driver 200 can be supplied to each horizontal line (pixel line) 60 times per second.

[0065] In an embodiment, the display device 1000 can adjust the output frequencies of the first scan driver 200 and the second scan driver 300, as well as the output frequency of their corresponding data driver 500, according to driving conditions. For example, the display device 1000 can display one or more images according to various image refresh rates in the range of about 1 Hz to about 120 Hz. However, this is only exemplary, and the display device 1000 can also display one or more images at an image refresh rate of about 120 Hz or higher (e.g., about 240 Hz or about 480 Hz).

[0066] The timing controller 600 can receive input image data IRGB and timing signals Vsync, Hsync, DE and CLK from a host system (such as an application processor (AP)) via a predetermined interface.

[0067] The timing controller 600 can generate a data drive control signal DCS based on the input image data IRGB and timing signals (such as the vertical sync signal Vsync, the horizontal sync signal Hsync, the data enable signal DE, and the clock signal CLK). The data drive control signal DCS can be supplied to the data driver 500. The timing controller 600 can rearrange the input image data IRGB and can provide the rearranged data to the data driver 500.

[0068] The timing controller 600 can supply gate start pulses GSP1 and GSP2 and clock signal CLK to the first scan driver 200 and the second scan driver 300 based on timing signals.

[0069] The timing controller 600 can supply the transmit start pulse ESP and the clock signal CLK to the transmit driver 400 based on the timing signals. The transmit start pulse ESP controls the first timing of the transmit control signals. The clock signal CLK can be used to shift the transmit start pulse ESP.

[0070] The first gate start pulse GSP1 can control the first timing of the scan signal (e.g., the first scan signal) supplied from the first scan driver 200. The clock signal CLK can be used to shift the first gate start pulse GSP1.

[0071] The second gate start pulse GSP2 can control the first timing of the scan signal (e.g., the second scan signal) supplied from the second scan driver 300. The clock signal CLK can be used to shift the second gate start pulse GSP2.

[0072] In this embodiment, the pulse widths of the first gate start pulse GSP1 and the second gate start pulse GSP2 can be different from each other. Therefore, the widths of the scan signals corresponding to each gate start pulse can also be different from each other.

[0073] The data driver 500 can convert rearranged image data (RGB) into analog data signals. The data driver 500 can supply data signals to data line D in response to the data drive control signal DCS. The data signals supplied via data line D can be supplied to pixels PX selected by the scan signal.

[0074] The data driver 500 can supply data signals to the data line D during one frame period according to the image refresh rate. For example, the data driver 500 can supply data signals to the data line D at the same frequency as the image refresh rate. Here, the data signal supplied through the data line D can be synchronized with the scan signal supplied through the first scan line S1.

[0075] The first scan driver 200 supplies scan signals to the first scan line S1 in response to the first gate start pulse GSP1. For example, the first scan driver 200 can sequentially supply scan signals to the first scan line S1. Here, each scan signal can be set to a gate on-voltage (e.g., logic low voltage) such that the transistor included in the corresponding pixel PX can be turned on.

[0076] In an embodiment, a data signal may be supplied to pixel PX in response to a first scan signal supplied via the first scan line S1.

[0077] The first scan driver 200 can supply scan signals to the first scan line S1 at the same frequency as the image refresh rate of the display device 1000 (e.g., a second frequency). In an embodiment, the second frequency may correspond to the output frequency of the first gate start pulse GSP1 that can be supplied from the timing controller 600 to the first scan driver 200.

[0078] The second frequency can be set to an equal portion of the first frequency that drives the transmitter driver 400. For example, the first frequency can be an integer multiple of the second frequency.

[0079] The first scan driver 200 can supply scan signals to the first scan line S1 during a display scan period of one frame. For example, the first scan driver 200 can supply at least one scan signal to each of the first scan lines S1 during the display scan period.

[0080] The second scan driver 300 can supply scan signals to the second scan line S2 in response to the second gate start pulse GSP2. For example, the second scan driver 300 can sequentially supply second scan signals to the second scan line S2. Here, each scan signal supplied from the second scan driver 300 can be set to a gate on-voltage (e.g., logic low voltage) such that the transistor included in the corresponding pixel PX can be turned on.

[0081] In an embodiment, a bias voltage for applying a bias to the driving transistor of pixel PX can be supplied in response to a second scan signal supplied via the second scan line S2. For example, when the second scan signal is supplied to the corresponding pixel PX, a predetermined bias voltage can be applied to the source and / or drain electrodes of the driving transistor of pixel PX, and the driving transistor can be biased and turned on.

[0082] The second scan driver 300 can supply a scan signal to the second scan line S2 at a first frequency, which can always be constant and is independent of the image refresh rate. Here, the first frequency can correspond to the output frequency of the second gate start pulse GSP2 that can be supplied from the timing controller 600 to the second scan driver 300.

[0083] The second scan driver 300 can supply scan signals at a first frequency that is higher than the image refresh rate. In an embodiment, the image refresh rate frequency (and the second frequency) can be set as equal parts of the first frequency. For example, the first frequency can be set to approximately twice the maximum refresh rate of the display device 1000 (i.e., the maximum driving frequency set in the display device 1000). When the maximum refresh rate of the display device 1000 is approximately 120Hz, the first frequency can be set to approximately 240Hz (i.e., the second frequency is half of the first frequency). Therefore, during one frame period, the scanning operation of sequentially outputting scan signals to the second scan line S2 can be repeated periodically at predetermined intervals several times.

[0084] For example, at all driving frequencies that can drive the display device 1000, the second scan driver 300 can perform one scan during the display scan period and at least one scan during the self-scan period according to the image refresh rate. For example, during the display scan period, the scan signal can be sequentially output to the corresponding second scan line S2 once, and during the self-scan period, the scan signal can be sequentially output to the corresponding second scan line S2 once or more.

[0085] When the image refresh rate decreases, the number of repetitions of the operation in which the second scan driver 300 supplies scan signals to the corresponding second scan line S2 during a frame period can be increased.

[0086] The transmit driver 400 can supply transmit control signals to the transmit control line E in response to the transmit start pulse ESP. For example, the transmit driver 400 can sequentially supply transmit control signals to the transmit control line E. When transmit control signals are sequentially supplied via the transmit control line E, the pixel PX can be non-transmitting based on horizontal alignment. For this operation, each transmit control signal can be set to a gate cutoff voltage (e.g., a logic high voltage) such that some transistors (e.g., P-type transistors) included in the pixel PX can be turned off.

[0087] In an embodiment, similar to the second scan driver 300, the transmit driver 400 can supply transmit control signals to the transmit control line E at a first frequency. Therefore, during a frame period, the transmit control signals supplied via the respective transmit control line E can be repeatedly supplied at predetermined intervals.

[0088] Therefore, when the image refresh rate decreases, the number of repetitions of the operation supplying the transmit control signal during a frame period can be increased.

[0089] Each of the first scan driver 200, the second scan driver 300, and the emitter driver 400 can be individually mounted on a substrate using a thin-film process. Each of the first scan driver 200 and the second scan driver 300 can be located on or disposed on either side of the pixel unit 100. The emitter driver 400 can also be located on or disposed on either side of the pixel unit 100. However, the disclosure is not limited thereto.

[0090] Pixel unit 100 may include pixel PX, which may be positioned or configured to be electrically coupled or connected to data line D, scan lines S1 and S2, and transmit control line E. Pixel PX may be supplied with a first power supply VDD, a second power supply VSS, and an initialization power supply Vint from an external device.

[0091] In an embodiment, the scan lines S1 and S2, the emission control line E, and the data line D electrically connected to each pixel PX can be configured in various forms according to the circuit structure of the pixel PX.

[0092] Pixel PX located or disposed on the current horizontal row (or current pixel row) may be additionally electrically coupled or connected to scan lines located or disposed on the previous horizontal row (or previous pixel row) and / or located or disposed on the next horizontal row (or next pixel row) depending on the circuit structure of pixel PX. For this operation, dummy scan lines and / or dummy emission control lines (not shown) may be additionally formed in pixel unit 100.

[0093] Figure 2A This is an equivalent circuit diagram showing the pixels according to an embodiment.

[0094] exist Figure 2A In the diagram, for ease of description, pixels that can be located or set on the i-th horizontal row (where "i" is a natural number) and can be electrically coupled or electrically connected to the j-th data line Dj (where "j" is a natural number) are shown.

[0095] Reference Figure 2A Pixel 10 may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0096] The first electrode (anode or cathode) of the light-emitting element LD can be electrically coupled or connected to the fourth node N4, and its second electrode (cathode or anode) can be electrically coupled or connected to the second power supply VSS. The light-emitting element LD can generate light with a predetermined brightness according to the amount of current supplied from the first transistor M1.

[0097] In one embodiment, the light-emitting element LD may be an organic light-emitting diode including an organic light-emitting layer. Alternatively, the light-emitting element LD may be an inorganic light-emitting element formed of an inorganic material. The light-emitting element LD may have a form or structure in which the inorganic light-emitting elements can be connected in parallel and / or in series electrically coupled or electrically connected between the second power supply VSS and the fourth node N4.

[0098] The first electrode of the first transistor M1 (or driving transistor) can be electrically connected or electrically coupled to the first node N1, and its second electrode can be electrically connected or electrically coupled to the third node N3. The gate electrode of the first transistor M1 can be electrically connected or electrically coupled to the second node N2. The first transistor M1 can control the amount of current flowing from the first power supply VDD through the light-emitting element LD into the second power supply VSS according to the voltage of the second node N2. For this operation, the voltage of the first power supply VDD can be set to a higher voltage than the voltage of the second power supply VSS.

[0099] The second transistor M2 can be electrically connected or electrically coupled between the data line Dj and the first node N1. The gate electrode of the second transistor M2 can be electrically connected or electrically coupled to the i-th first scan line S1i. The second transistor M2 can be turned on when a scan signal (e.g., a first scan signal) can be supplied through the i-th first scan line S1i, and then the data line Dj can be electrically connected or electrically coupled to the first node N1.

[0100] The third transistor M3 can be electrically coupled or connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the second node N2. The gate electrode of the third transistor M3 can be electrically coupled or connected to the i-th first scan line S1i. When a scan signal is supplied through the i-th first scan line S1i, the third transistor M3 can be turned on, and then the second electrode of the first transistor M1 can be electrically coupled or connected to the second node N2. For example, the second transistor M2 and the third transistor M3 can be controlled simultaneously. When the third transistor M3 is turned on, the first transistor M1 can be electrically coupled or connected in a diode configuration. Therefore, writing data to the first transistor M1 and threshold voltage compensation can be performed together.

[0101] The fourth transistor M4 can be electrically coupled or connected between the third node N3 and the i-th emitter control line Ei. The gate electrode of the fourth transistor M4 can be electrically coupled or connected to the i-th second scan line S2i. The fourth transistor M4 can be turned on when a scan signal (e.g., a second scan signal) is supplied through the i-th second scan line S2i, and then the voltage of the i-th emitter control line Ei can be supplied to the third node N3. Here, an emitter control signal (e.g., a gate cutoff voltage or a logic high voltage) can be supplied through the i-th emitter control line Ei. For example, the gate cutoff voltage (i.e., the emitter control signal) can be in the range of about 5V to about 7V.

[0102] Therefore, a predetermined high voltage can be applied as a bias voltage to the drain electrode (and source electrode) of the first transistor M1 by turning on the fourth transistor M4, and the first transistor M1 can have a biased state (i.e., biased on).

[0103] The fifth transistor M5 can be electrically connected or electrically coupled between the first power supply VDD and the first node N1. The gate electrode of the fifth transistor M5 can be electrically connected or electrically coupled to the i-th emitter control line Ei. The fifth transistor M5 can be turned off when an emitter control signal is supplied through the i-th emitter control line Ei, and can be turned on in other cases.

[0104] The sixth transistor M6 can be electrically coupled or connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be electrically coupled or connected to the i-th emission control line Ei. The sixth transistor M6 can be turned off when an emission control signal is supplied through the i-th emission control line Ei, and can be turned on otherwise. Therefore, the fifth transistor M5 and the sixth transistor M6 can be controlled simultaneously.

[0105] The seventh transistor M7 can be electrically coupled or connected between the first electrode (i.e., the fourth node N4) of the light-emitting element LD and the first initialization power supply Vint1. The gate electrode of the seventh transistor M7 can be electrically coupled or connected to the i-th second scan line S2i. The seventh transistor M7 can be turned on when a scan signal is supplied through the i-th second scan line S2i, and then the voltage of the first initialization power supply Vint1 can be supplied to the first electrode (i.e., the fourth node N4) of the light-emitting element LD.

[0106] When the voltage of the first initialization power supply Vint1 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can be discharged. When the residual voltage charged in the parasitic capacitor is discharged (eliminated), unintended fine light emission can be prevented. Therefore, the black level performance of pixel 10 can be improved.

[0107] The eighth transistor M8 can be electrically coupled or connected between the second node N2 and the second initialization power supply Vint2. The gate electrode of the eighth transistor M8 can be electrically coupled or connected to the third scan line (or the (i-1)th first scan line S1i-1). The eighth transistor M8 can be turned on when a scan signal (e.g., a first scan signal) is supplied through the (i-1)th first scan line S1i-1, and then the voltage of the second initialization power supply Vint2 can be supplied to the second node N2 (i.e., the gate electrode of the first transistor M1). Therefore, the gate voltage of the first transistor M1 can be initialized.

[0108] In this embodiment, the first initialization power supply Vint1 and the second initialization power supply Vint2 can generate different voltages. For example, the voltage used to initialize the second node N2 and the voltage used to initialize the fourth node N4 can be set to different voltages.

[0109] When the voltage of the second initialization power supply Vint2, which is to be supplied to the second node N2, is too low during low-frequency driving with an increasing frame period length, the hysteresis variation of the first transistor M1 in the corresponding frame period may worsen. Such hysteresis may cause flickering during low-frequency driving. Therefore, in a display device driven at low frequencies, it may be necessary for the voltage of the second initialization power supply Vint2 to be higher than the voltage of the second power supply VSS.

[0110] During this low-frequency drive, when a conduction bias is applied to the first transistor M1 using a signal supplied via data line Dj through the conduction operation of the second transistor M2 (i.e., when the first transistor M1 is biased and turned on), a severe deviation due to hysteresis caused by the difference in grayscale values ​​between adjacent pixels may occur. Therefore, a difference arises between the offsets of the threshold voltages of the driving transistors in adjacent pixels, and thus motion blur (i.e., ghosting) caused by such a difference can be perceived.

[0111] To solve this problem, according to the embodiment, pixel 10 and display device having pixel 10 (e.g., Figure 1 The first transistor M1 (1000) can use a fourth transistor M4 to periodically apply a bias as a constant voltage to the drain electrode (and / or source electrode) of the first transistor M1. Therefore, hysteresis bias attributable to grayscale differences between adjacent pixels can be removed, and thus image blur attributable to hysteresis bias can be reduced (or eliminated).

[0112] In an embodiment, the first transistors M1 through M8 may be formed of polysilicon semiconductor transistors. For example, each of the first transistors M1 through M8 may include a polysilicon semiconductor layer (as an active layer (channel)) formed by a low-temperature polysilicon (LTPS) process. However, this is merely exemplary, and within the spirit and scope of the disclosure, at least one of the first transistors M1 through M8 may be replaced by an oxide semiconductor transistor or the like.

[0113] Figure 2B It is shown Figure 2A The equivalent circuit diagram of the pixel variant.

[0114] Because, apart from the bonding relationship of the fourth transistor M4, Figure 2B The 10' pixel can be with Figure 2A Since the pixels 10 are the same or similar, the same reference numerals are used to denote the same or corresponding components, and therefore their repeated descriptions will be omitted.

[0115] Reference Figure 2B Pixel 10' may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0116] The first electrode of the fourth transistor M4 can be electrically coupled or connected to the i-th emitter control line Ei. The second electrode of the fourth transistor M4 can be electrically coupled or connected to the first node N1 (i.e., the source electrode of the first transistor M1). When the fourth transistor M4 is turned on, a logic high voltage can be supplied to the i-th emitter control line Ei. Therefore, when the fourth transistor M4 is turned on, the logic high voltage can be supplied as a bias voltage to the source electrode of the first transistor M1, and the first transistor M1 can have a biased state.

[0117] like Figure 2A and Figure 2B As shown, when one electrode of the fourth transistor M4 is electrically coupled or connected to either the source electrode or the drain electrode of the first transistor M1, the first transistor M1 can be biased and turned on for a predetermined period of time.

[0118] Figure 3AIt is shown Figure 2A A timing diagram of an example of pixel-driven operation.

[0119] Reference Figure 2A and Figure 3A During the display scan period, pixel 10 can be supplied with signals for displaying an image. The display scan period may include a period during which a data signal DVi corresponding to the output image can be written.

[0120] For ease of description, the following description can be made: the i-th transmit control line Ei can be used as the transmit control line Ei, the i-th first scan line S1i can be used as the first scan line S1i, the i-th second scan line S2i can be used as the second scan line S2i, and the (i-1)-th first scan line S1i-1 can be used as the previous first scan line S1i-1.

[0121] In an embodiment, the first scan signal supplied via the first scan lines S1i-1 and S1i can have a pulse width of one horizontal time period (1H) or less. The first and second scan signals supplied via the second scan line S2i can be defined as logic low voltages, and the transmit control signal used to turn off the fifth transistor M5 and the sixth transistor M6 can be defined as a logic high voltage. However, this is merely exemplary, and therefore the pulse widths and logic levels of the scan signals and transmit control signals are not limited thereto, and can be varied according to the pixel structure, transistor type, etc., within the spirit and scope of the disclosure.

[0122] Transmission control signals can be supplied via the transmission control line Ei. These signals can be maintained from the first time period P1 to the third time period P3.

[0123] During the first time period P1, a transmit control signal can be supplied via the transmit control line Ei, and a first scan signal can be supplied via the preceding first scan line S1i-1. The fifth transistor M5 and the sixth transistor M6 can be turned off in response to the transmit control signal. The eighth transistor M8 can be turned on in response to the first scan signal supplied via the preceding first scan line S1i-1.

[0124] During the first time period P1, the drive current supply to the light-emitting element LD can be stopped. Since the eighth transistor M8 is turned on, the voltage of the second initialization power supply Vint2 can be supplied to the gate electrode of the first transistor M1 (i.e., the second node N2). Therefore, the gate voltage of the first transistor M1 can be initialized during the first time period P1.

[0125] During the second time period P2, the first scan signal can be supplied through the first scan line S1i (or the current first scan line). Therefore, the second transistor M2 and the third transistor M3 can be turned on. The second transistor M2 can be turned on, so that the i-th data signal DVi can be supplied to the first node N1 through the data line Dj.

[0126] Since the second transistor M2 and the third transistor M3 can be turned on together, the first transistor M1 can be electrically coupled or connected in a diode configuration. For example, the second time period P2 can be the data writing and threshold voltage compensation period.

[0127] During the third time period P3, the second scan signal can be supplied through the second scan line S2i. Therefore, the fourth transistor M4 and the seventh transistor M7 can be turned on.

[0128] When the seventh transistor M7 is turned on, the voltage of the first initialization power supply Vint1 can be supplied to the fourth node N4. Therefore, the voltage of the first electrode (e.g., the anode electrode) of the light-emitting element LD can be initialized, and the voltage of the parasitic capacitor formed in the light-emitting element LD can be discharged (or removed).

[0129] When the fourth transistor M4 is turned on, the gate cutoff voltage (e.g., logic high voltage) of the transmit control signal can be supplied to the third node N3. The transmit control signal (i.e., the logic high voltage of the transmit control signal) can be in the range of about 5V to about 7V, and the first transistor M1 can be biased and turned on during the third time period P3. In an embodiment, the second scan signal can have a pulse width of about 4 horizontal time periods (4H) or greater. Therefore, for a sufficient time period, the logic high voltage of the transmit control signal can be supplied to the first transistor M1.

[0130] Furthermore, during the third time period P3, the first transistor M1, which arranges or sets all pixels in the i-th pixel row, can be biased and turned on in response to the emission control signal, thus eliminating the difference between bias voltages. Therefore, the hysteresis deviation between pixels can be eliminated (or reduced).

[0131] For example, the conduction periods of the third transistor M3 and the fourth transistor M4 may not overlap. For example, the initialization / compensation period and the bias period of the first transistor M1 may be separate.

[0132] Subsequently, during the fourth time period P4, the supply of the transmit control signal can be stopped, and the fifth transistor M5 and the sixth transistor M6 can be turned on. When the fifth transistor M5 and the sixth transistor M6 are turned on, the drive current generated based on the data signal DVi can be supplied to the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the drive current. For example, the fourth time period P4 can be the transmit period.

[0133] For example, the display scan period may include an initialization period (e.g., a first period P1), a write and compensation period (e.g., a second period P2), a bias period (e.g., a third period P3), and an emission period (e.g., a fourth period P4). In this case, the first period P1 to the third period P3 may correspond to the non-emission period of pixel 10.

[0134] The operation corresponding to the display scan period can be implemented in response to the scan signal supplied through the first scan lines S1i-1 and S1i, and can be synchronized with a frequency that can drive the first scan driver 200 (e.g., the frequency can be described as a second frequency).

[0135] Figure 2B Pixel 10' can also perform the same operation as described above during the display scan period.

[0136] Although for the sake of ease of description Figure 3A The diagram illustrates that a single first scan signal can be supplied through each of the first scan lines S1i-1 and S1i during the first time period P1 and the second time period P2, but the disclosure is not limited thereto. For example, multiple first scan signals can be supplied through each of the first scan lines S1i-1 and S1i. Even in this case, the actual operation process can be... Figure 3A The operation process is the same, so their detailed descriptions will be omitted.

[0137] Figure 3B It is shown Figure 2A A timing diagram of an example of pixel-driven operation.

[0138] Reference Figure 2A and Figure 3B In order to maintain the brightness of the image that can be output during the display scan period, an emission control signal can be applied to one electrode of the first transistor M1 (e.g., the drain electrode or the third node N3) during the self-scan period.

[0139] A single frame may include at least one self-scanning period, depending on the image frame rate. The self-scanning period may include a bias period (e.g., a third period P3) and a transmission period (e.g., a fourth period P4). In embodiments, the operation corresponding to the self-scanning period may be substantially the same as the operation of the display scanning period, except that a first scan signal may not be supplied.

[0140] In this embodiment, during the self-scan period, the scan signal may not be supplied to the second transistor M2 and the third transistor M3. The scan signal may not be supplied to the eighth transistor M8. For example, during the self-scan period, the first scan signal supplied through the first scan lines S1i-1 and S1i may have a gate cutoff voltage (e.g., a logic high voltage).

[0141] Therefore, the self-scanning period may not include the initialization period (e.g., Figure 3A The first period P1) and the write and compensation periods (e.g., Figure 3A The second period (P2).

[0142] Since the second transistor M2, the third transistor M3 and the eighth transistor M8 remain off, the gate voltage of the first transistor M1 (i.e., the voltage of the second node N2) is not affected by the drive during the self-scan period.

[0143] In other words, transistors M4 through M7 can be turned on at a first frequency, and transistors M2, M3, and M8 can be turned on at a second frequency, which can be different from the first frequency. For example, the second frequency can be lower than the first frequency.

[0144] During the non-emission period, during the third period P3, the second scan signal can be supplied through the second scan line S2i. The fourth transistor M4 can be turned on in response to the second scan signal. When the fourth transistor M4 is turned on, the logic high voltage of the transmit control signal can be supplied to the third node N3. Therefore, because the on-bias can be applied to the first transistor M1 during the third period P3, flickering during low-frequency driving can be improved.

[0145] The second scan signal and the transmit control signal can be supplied at a first frequency, regardless of the image refresh rate. Therefore, even when the image refresh rate may change, the application of the conduction bias during the third time period P3 can always be performed periodically. Thus, flicker can be improved depending on various image refresh rates (e.g., in low-frequency drive).

[0146] Subsequently, during the fourth time period P4, the fourth transistor M4 can be turned off, and the fifth transistor M5 and the sixth transistor M6 can be turned on. Therefore, during the fourth time period P4, pixel 10 can emit light based on the data signal DVi supplied during the previous display scan period.

[0147] In this embodiment, during the self-scanning period, the data driver 500 may not supply the data signal DVi to the pixel unit 100. Therefore, power consumption can be further reduced.

[0148] Despite Figures 2A to 3B In this design, P-type transistors are described as being included in pixels 10 and 10', but the disclosure is not limited thereto, and at least one of the first transistors M1 to the eighth transistor M8 may be an N-type transistor. The waveforms of the scan signals or transmit control signals supplied to the respective transistors may vary depending on the type of transistor.

[0149] Figures 4A to 4D This is a timing diagram illustrating an example of the start pulses supplied to the transmit driver and scan driver included in the display device according to the image refresh rate. Figure 5 This is a diagram illustrating an example of a method for driving a display device according to an image refresh rate.

[0150] Reference Figure 1 , Figure 2A , Figures 4A to 4D and Figure 5 The output frequency of the first gate start pulse GSP1 can vary according to the image refresh rate RR.

[0151] In an embodiment, the pulse width of the transmit start pulse ESP can be greater than the pulse width of the first gate start pulse GSP1 and the second gate start pulse GSP2.

[0152] In this embodiment, regardless of the driving frequency, the timing controller 600 can output the transmit start pulse ESP and the second gate start pulse GSP2 at a predetermined frequency (e.g., a first frequency). For example, the output frequency of the transmit start pulse ESP and the second gate start pulse GSP2 can be set to approximately twice the maximum refresh rate of the display device 1000.

[0153] The timing controller 600 can output a first gate start pulse GSP1 at the same frequency as the image refresh rate RR (e.g., a second frequency). A frame period of the display device 1000 can be determined by the output period of the first gate start pulse GSP1. For example, a frame period of the display device 1000 can be determined based on the frequency supplied to the pixels (e.g., ...). Figure 2A The second, third, and eighth transistors (i.e., 10) Figure 2A The time period of the scan signals (M2, M3, and M8) is used to determine the time.

[0154] In an embodiment, during the display scan period DSP, all transmit start pulses ESP, the first gate start pulse GSP1, and the second gate start pulse GSP2 can be output. For example, during the display scan period DSP, each of the pixels PX can perform... Figure 3A The drive. During the display scan period of the DSP, each pixel PX can store a data signal corresponding to the image to be displayed.

[0155] In an embodiment, during the self-scanning period SSP, an emit start pulse ESP and a second gate start pulse GSP2 can be output. For example, during the self-scanning period SSP, each of the pixels PX can perform... Figure 3B The drive. During the self-scanning period (SSP), a predetermined high voltage for applying bias can be supplied to each pixel (e.g., Figure 2A The first transistor in (e.g., 10) Figure 2A The first electrode and / or the second electrode of M1).

[0156] In this embodiment, the length of a single display scan period (DSP) can be substantially the same as the length of a single self-scanning period (SSP). However, the number of self-scanning periods (SSPs) included in one frame cycle can be determined based on the image refresh rate (RR).

[0157] like Figure 4A and Figure 5 As shown, when the display device 1000 is driven at an image refresh rate RR of approximately 120 Hz, the number of first gate start pulses GSP1 supplied during one frame period can be approximately half the number of second gate start pulses GSP2. Therefore, at an image refresh rate RR of approximately 120 Hz, one frame period can include a single display scan period DSP and a single self-scan period SSP.

[0158] The transmit start pulse ESP can be supplied at the same frequency as the second gate start pulse GSP2. When the display device 1000 is driven at an image refresh rate RR of approximately 120Hz, the pixel PX can alternately repeat transmit and non-transmit twice during the frame period.

[0159] like Figure 4B and Figure 5As shown, when the display device 1000 is driven at an image refresh rate RR of approximately 80Hz, the number of first gate start pulses GSP1 supplied during one frame period can be approximately 1 / 3 of the number of second gate start pulses GSP2. Therefore, when the display device 1000 is driven at an image refresh rate RR of approximately 80Hz, one frame period can include one display scan period DSP and two consecutive self-scan periods SSP. Here, the pixel PX can alternately repeat emission and non-emission three times.

[0160] like Figure 4C and Figure 5 As shown, when the display device 1000 is driven at an image refresh rate RR of approximately 60Hz, the number of first gate start pulses GSP1 supplied during one frame period can be approximately 1 / 4 of the number of second gate start pulses GSP2. Therefore, when the display device 1000 is driven at an image refresh rate RR of approximately 60Hz, one frame period can include one display scan period DSP and three consecutive self-scan periods SSP. Here, the pixel PX can alternately repeat emission and non-emission four times.

[0161] like Figure 4D and Figure 5 As shown, when the display device 1000 is driven at an image refresh rate RR of approximately 48Hz, the number of first gate start pulses GSP1 supplied during one frame period can be approximately 1 / 5 of the number of second gate start pulses GSP2. Therefore, when the display device 1000 is driven at an image refresh rate RR of approximately 48Hz, one frame period can include one display scan period DSP and four consecutive self-scan periods SSP. Here, the pixel PX can alternately repeat emission and non-emission five times.

[0162] like Figure 5 As shown, the light wave LW detected from pixel unit 100 through experiments can be output at the same time period as the second gate start pulse GSP2.

[0163] Similar to the method described above, the display device 1000 can be driven at various driving frequencies of approximately 60Hz, approximately 30Hz, approximately 24Hz, approximately 12Hz, approximately 8Hz, approximately 6Hz, approximately 5Hz, approximately 4Hz, approximately 3Hz, approximately 2Hz, and approximately 1Hz by adjusting the number of self-scanning periods (SSPs) included in one frame cycle. In other words, the display device 1000 can support various image refresh rates (RR) having frequencies corresponding to equal parts of the first frequency.

[0164] As the driving frequency decreases, the number of self-scanning periods (SSPs) increases, thus a predetermined conduction bias can be periodically applied to each of the first transistors (M1) included in the pixel unit 100. Therefore, brightness reduction, flickering, or image blurring that occurs during low-frequency driving can be improved.

[0165] Figure 6 and Figure 7 It is shown that it includes Figure 1 An example of an equivalent circuit diagram of pixels in a display device.

[0166] Because, apart from the construction of the fourth transistor M4, Figure 6 and Figure 7 Pixels 11 and 11' can be with Figure 2A Since the pixels 10 are the same or similar, the same reference numerals are used to indicate the same or corresponding components, and therefore their repeated descriptions will be omitted.

[0167] Reference Figure 6 and Figure 7 Each of pixels 11 and 11' may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0168] like Figure 6 As shown, the fourth transistor M4 can be electrically coupled or connected between a predetermined bias power supply VEH and the third node N3 (i.e., the drain electrode of the first transistor M1). The fourth transistor M4 can be turned on in response to a second scan signal supplied through the second scan line S2i.

[0169] The bias power supply VEH can have a voltage level in the range of approximately 5V to approximately 8V. The voltage level of the bias power supply VEH can be easily controlled according to the driving conditions of the display device 1000. The bias power supply VEH can be implemented as a DC voltage source, and therefore the bias difference between the first transistors M1 can be further reduced.

[0170] like Figure 7 As shown, the fourth transistor M4 can also be electrically coupled or connected between a predetermined bias power supply VEH and the first node N1 (i.e., the source electrode of the first transistor M1). When one electrode of the fourth transistor M4 is electrically coupled or connected to either the source electrode or the drain electrode of the first transistor M1, the first transistor M1 can be biased and turned on for a predetermined period of time.

[0171] In an embodiment, Figure 6 and Figure 7 Pixels 11 and 11' can be connected with Figure 3A and Figure 3B The timing diagram uses the same driver to display one or more images.

[0172] Figure 8 It is shown Figure 1 A block diagram of an example display device.

[0173] Because, apart from the construction of the third scan driver 350, Figure 8 The display device can be with Figure 1 Since the display devices are the same or similar, the same reference numerals are used to indicate the same or corresponding components, and therefore repeated descriptions of them will be omitted.

[0174] Reference Figure 8 The display device 1001 may include a pixel unit 100, a first scan driver 200, a second scan driver 300, a third scan driver 350, a transmission driver 400, a data driver 500, and a timing controller 600.

[0175] The timing controller 600 can supply gate start pulses GSP1, GSP2, and GSP3, as well as clock signal CLK, to the first scan driver 200, the second scan driver 300, and the third scan driver 350 based on timing signals Vsync, Hsync, DE, and CLK.

[0176] The first gate start pulse GSP1 can control the first timing of the scan signal (e.g., the first scan signal) output from the first scan driver 200. The second gate start pulse GSP2 can control the first timing of the scan signal (e.g., the second scan signal) output from the second scan driver 300.

[0177] The third gate start pulse GSP3 can control the first timing of the scan signal (e.g., the third scan signal) output from the third scan driver 350.

[0178] In an embodiment, the pulse width of at least one of the first gate start pulses GSP1 to the third gate start pulses GSP3 may be different from the pulse widths of the other gate start pulses. Therefore, the width of the scan signal corresponding to the respective gate start pulse may also vary.

[0179] The data driver 500 can supply data signals to the data line D in response to the data drive control signal DCS. The data signals supplied through the data line D can be supplied to the pixel PX selected by the scan signal.

[0180] The first scan driver 200 can supply a scan signal to the first scan line S1 in response to a first gate start pulse GSP1. The first scan driver 200 can supply the scan signal to the first scan line S1 at a second frequency corresponding to the image refresh rate. The first scan driver 200 can output the scan signal only during the display scan period.

[0181] The second scan driver 300 can supply a scan signal to the second scan line S2 in response to the second gate start pulse GSP2. In an embodiment, the second scan driver 300 can supply the scan signal to the second scan line S2 at a first frequency independent of the image refresh rate. For example, the second scan driver 300 can output the scan signal during the display scan period and the self-scan period.

[0182] The third scan driver 350 can supply a scan signal to the third scan line S3 in response to the third gate start pulse GSP3. The third scan driver 350 can supply a scan signal to the third scan line S3 at a second frequency.

[0183] The transmit driver 400 can supply a transmit control signal to the transmit control line E in response to the transmit start pulse ESP. The transmit driver 400 can supply the transmit control signal to the transmit control line E at a first frequency. For example, the transmit driver 400 can output the transmit control signal during the display scan period and the self-scan period.

[0184] However, since this is merely an example, some of the first scan driver 200, the second scan driver 300, and the third scan driver 350 may be driven at a first frequency, and the remaining scan drivers may be driven at a second frequency depending on the structure of the pixel PX. Scan drivers may be reduced or increased depending on the structure of the pixel PX.

[0185] Figure 9 It is shown that it includes Figure 8 An example of an equivalent circuit diagram of pixels in a display device. Figure 10 It is shown Figure 9 A timing diagram of an example of pixel-driven operation.

[0186] Because, apart from some of the components of the third transistor M3, Figure 9 The pixels can be with Figure 2A Since the pixels 10 are the same or similar, the same reference numerals are used to indicate the same or corresponding components, and therefore their repeated descriptions will be omitted. This is because, apart from the width of the signal supplied via the third scan line S3i, Figure 10 The timing diagram can be combined with Figure 3A Since the timing diagrams are the same or similar, their repeated descriptions will be omitted.

[0187] Reference Figure 9 and Figure 10 Pixel 12 may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a storage capacitor Cst.

[0188] In an embodiment, the third transistor M3 and the second transistor M2 can be controlled in response to different scan signals. For example, the gate electrode of the third transistor M3 can be electrically coupled or electrically connected to the third scan line S3i, and the third transistor M3 can be turned on in response to a third scan signal supplied through the third scan line S3i.

[0189] During the display scan period, pixel 12 can perform operations corresponding to the first time period P1 to the fourth time period P4. In an embodiment, the third scan signal supplied via the third scan line S3i can overlap with the first scan signal supplied via the first scan line S1i. The pulse width of the third scan signal can be greater than the pulse width of the first scan signal, and the length of the second time period P2 during which data writing and threshold voltage compensation are performed can be increased.

[0190] For example, as the on-time of the third transistor M3 increases, the time required for threshold voltage compensation can be increased. The difference between the gate and source voltages of the first transistor M1 can be reduced before data is written. Therefore, image quality can be further improved.

[0191] Figure 11 It is shown that it includes Figure 8 An example of an equivalent circuit diagram of pixels in a display device.

[0192] Reference Figure 11 Pixel 13 may include a light-emitting element LD, a first transistor M1 to a seventh transistor M7, and a storage capacitor Cst.

[0193] Because the light-emitting element LD, the first transistor M1, and the second transistor M2 can be constructed in conjunction with... Figure 2A The construction of pixels 10 is basically the same, so repeated descriptions of them will be omitted.

[0194] The third transistor M3 can be electrically coupled or connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the second node N2. The gate electrode of the third transistor M3 can be electrically coupled or connected to the i-th second scan line S2i. When a scan signal is supplied through the i-th second scan line S2i, the third transistor M3 can be turned on, and then the second electrode of the first transistor M1 can be electrically coupled or connected to the second node N2. Therefore, when the third transistor M3 is turned on, the first transistor M1 can be electrically coupled or connected in a diode configuration.

[0195] In one embodiment, with the second transistor M2 off and the third transistor M3 on, the voltage of the initialization power supply Vint can be supplied to the gate electrode of the first transistor M1.

[0196] The fourth transistor M4 can be electrically coupled or connected between the third node N3 and the i-th emitter control line Ei. The gate electrode of the fourth transistor M4 can be electrically coupled or connected to the (i+q)-th third scan line S3i+q. The fourth transistor M4 can be turned on when a scan signal (e.g., a third scan signal) is supplied through the (i+q)-th third scan line S3i+q (where q is a natural number), and then the voltage of the i-th emitter control line Ei can be supplied to the third node N3. For example, the gate electrode of the fourth transistor M4 can be electrically coupled or connected to the (i+5)-th third scan line S3i+5. The third scan signal supplied through the (i+5)-th third scan line S3i+5 can be a signal obtained by delaying the third scan signal that can be supplied through the i-th third scan line S3i by 5 horizontal time intervals (5H). However, this is only exemplary, and the third scan line S3i+q electrically coupled or connected to the gate electrode of the fourth transistor M4 is not limited to this.

[0197] Here, the gate cutoff voltage (or logic high voltage) can be supplied via the i-th emit control line Ei. For example, the gate cutoff voltage can be in the range of about 5V to about 7V.

[0198] Therefore, a predetermined high voltage can be applied to the drain electrode (and source electrode) of the first transistor M1 by turning on the fourth transistor M4, and the first transistor M1 can have a conduction bias state.

[0199] The fifth transistor M5 can be electrically connected or electrically coupled between the first power supply VDD and the first node N1. The gate electrode of the fifth transistor M5 can be electrically connected or electrically coupled to the i-th emitter control line Ei. The fifth transistor M5 can be turned off when the emitter control signal can be supplied through the i-th emitter control line Ei, and can be turned on in other cases.

[0200] The sixth transistor M6 can be electrically coupled or connected between the second electrode (i.e., the third node N3) of the first transistor M1 and the first electrode (i.e., the fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be electrically coupled or connected to the (i+p)th emitter control line Ei+p (where p is a natural number). The sixth transistor M6 can be turned off when an emitter control signal can be supplied through the (i+p)th emitter control line Ei+p, and can be turned on otherwise. Therefore, the conduction periods of the fifth transistor M5 and the sixth transistor M6 can only partially overlap.

[0201] For example, the gate electrode of the sixth transistor M6 can be electrically coupled or connected to the (i+4)th emitter control line Ei+4. The emitter control signal supplied via the (i+4)th emitter control line Ei+4 can be a signal obtained by delaying the emitter control signal supplied via the (i)th emitter control line Ei by four horizontal time intervals (4H). However, this is merely exemplary, and the emitter control line Ei+p electrically coupled or connected to the gate electrode of the sixth transistor M6 is not limited to this.

[0202] The seventh transistor M7 can be electrically coupled or connected between the first electrode (i.e., the fourth node N4) of the light-emitting element LD and the initialization power supply Vint. The gate electrode of the seventh transistor M7 can be electrically coupled or connected to the i-th third scan line S3i. The seventh transistor M7 can be turned on when a scan signal is supplied through the i-th third scan line S3i, and then the voltage of the initialization power supply Vint can be supplied to the first electrode and the fourth node N4 of the light-emitting element LD.

[0203] In this embodiment, the conduction periods of the seventh transistor M7 and the sixth transistor M6 may not overlap.

[0204] In this embodiment, transistors M4 through M7 can be turned on at a first frequency, and transistors M2 and M3 can be turned on at a second frequency, which is different from the first frequency. For example, the second frequency can be lower than the first frequency. For example, the second frequency can be an equal part of the first frequency (the first frequency can be divided into equal parts by the second frequency).

[0205] because Figure 11 The 13 pixels include more than Figure 2A With fewer transistors per 10 pixels, the pixel layout can be simplified, which is beneficial for achieving high resolution.

[0206] Figure 12A It is shown Figure 11 A timing diagram of an example of pixel-driven operation.

[0207] Reference Figure 11 and Figure 12A The signal for displaying the image can be supplied to pixel 13 during the display scan period. The display scan period may include a period during which a data signal DVi corresponding to the output image can be written.

[0208] For ease of description, the following description can be made: the i-th transmit control line Ei can be used as the transmit control line Ei, the (i+p)-th transmit control line Ei+p can be used as the subsequent transmit control line Ei+p, the i-th first scan line S1i can be used as the first scan line S1i, the i-th second scan line S2i can be used as the second scan line S2i, the i-th third scan line S3i can be used as the third scan line S3i, and the (i+q)-th third scan line S3i+q can be used as the subsequent third scan line S3i+q.

[0209] During the first time period P1, the transmit control signal can be supplied via the transmit control line Ei, the second scan signal via the second scan line S2i, and the third scan signal via the third scan line S3i. The fifth transistor M5 can be turned off in response to the transmit control signal. Since the second scan signal can be supplied via the second scan line S2i and the third scan signal via the third scan line S3i, the third transistor M3 and the seventh transistor M7 can be turned on. Since the transmit control signal can be supplied without the subsequent transmit control line Ei+p, the sixth transistor M6 can remain on.

[0210] During the first time period P1, the drive current supply to the light-emitting element LD can be stopped. When the seventh transistor M7 is turned on, the voltage of the initialization power supply Vint can be supplied to the fourth node N4. For example, the voltage of the initialization power supply Vint can be supplied to the gate electrode of the first transistor M1 (i.e., the second node N2) through the third transistor M3 and the sixth transistor M6, which can be turned on.

[0211] Therefore, during the first time period P1, the voltage initialization (i.e., the discharge of the parasitic capacitor) of the first electrode of the light-emitting element LD can be performed, and the gate voltage initialization of the first transistor M1 can also be performed. For example, the first time period P1 can be an initialization period.

[0212] After the first time period P1, a transmit control signal is supplied to the subsequent transmit control line Ei+p, and the sixth transistor M6 can be turned off. During the first time period P1, the fifth transistor M5 can be turned off, and the sixth transistor M6 can be turned on. For example, the length of the first time period P1 can be approximately four horizontal time periods (4H) or longer.

[0213] Subsequently, during the second time period P2, the first scan signal can be supplied via the first scan line S1i. The second transistor M2 can be turned on, allowing the i-th data signal DVi to be supplied to the first node N1 via the data line Dj. Since the third transistor M3 can be turned on, the first transistor M1 can be electrically coupled or connected in a diode configuration. For example, the second time period P2 can be a data writing and threshold voltage compensation period.

[0214] Subsequently, the supply of the second scan signal to the second scan line S2i can be stopped, and the supply of the third scan signal to the third scan line S3i can also be stopped. Therefore, the third transistor M3 and the seventh transistor M7 can be turned off. In this embodiment, the third transistor M3 and the seventh transistor M7 can be controlled simultaneously.

[0215] During the third time period P3, the third scan signal can be supplied via the subsequent third scan line S3i+q. The fourth transistor M4 can be turned on in response to the third scan signal. When the fourth transistor M4 is turned on, the gate cutoff voltage (e.g., logic high voltage) of the transmit control signal can be supplied to the third node N3. During the third time period P3, the first transistor M1 can be biased and turned on. In this embodiment, the third scan signal can have a pulse width of approximately four horizontal time periods (4H) or longer. Therefore, for a sufficient period of time, the logic high voltage of the transmit control signal can be supplied to the first transistor M1.

[0216] Furthermore, the conduction periods of the third transistor M3 and the fourth transistor M4 can be non-overlapping. For example, the initialization / compensation period and the bias period of the first transistor M1 can be separate. The conduction periods of the fourth transistor M4 and the seventh transistor M7 can also be non-overlapping.

[0217] Subsequently, the supply of transmission control signals to the transmission control line Ei and the subsequent transmission control line Ei+p can be sequentially stopped, and the fifth transistor M5 and the sixth transistor M6 can be sequentially turned on. When the fifth transistor M5 and the sixth transistor M6 are turned on, the drive current generated based on the data signal DVi can be supplied to the light-emitting element LD, and the light-emitting element LD can emit light with a brightness corresponding to the drive current. The fourth time period P4 during which both the fifth transistor M5 and the sixth transistor M6 can be turned on can be the transmission period.

[0218] The operation corresponding to the display scan period can be implemented based on the frequency of the scan signal supplied to the first scan line S1i. For example, the display scan period can be represented by the second frequency described above.

[0219] Figure 12B It is shown Figure 11 A timing diagram of an example of pixel-driven operation.

[0220] Reference Figure 11 and Figure 12B In order to maintain the brightness of the image that can be output during the display scan period, an emission control signal can be applied to one electrode of the first transistor M1 (e.g., the drain electrode or the third node N3) during the self-scan period.

[0221] The self-scanning period may include a bias period (e.g., a third period P3) and a transmission period (e.g., a fourth period P4). In embodiments, the operation corresponding to the self-scanning period may be substantially the same as the operation of the display scanning period, except that the first and second scan signals may not be supplied.

[0222] During the self-scan period, the scan signal may not be supplied to the second transistor M2 and the third transistor M3. For example, during the self-scan period, the first scan signal supplied through the first scan line S1i may have a gate cutoff voltage (e.g., a logic high voltage).

[0223] Since the second transistor M2 and the third transistor M3 remain off, the gate voltage of the first transistor M1 is unaffected by the drive during the self-scan period.

[0224] For example, transistors M4 through M7 can be turned on at a first frequency, and transistors M2 and M3 can be turned on at a second frequency, which can be different from the first frequency. For example, the second frequency can be lower than the first frequency.

[0225] During the third period P3 of the self-scanning phase, the third scan signal can be supplied through the third scan line S3i. The fourth transistor M4 can be turned on in response to the third scan signal. When the fourth transistor M4 is turned on, the logic high voltage of the transmit control signal can be supplied to the third node N3. Therefore, because the on-bias can be applied to the first transistor M1 during the third period P3, flickering that occurs during low-frequency driving can be improved.

[0226] Subsequently, during the fourth time period P4, the fifth transistor M5 and the sixth transistor M6 can be turned on. Therefore, during the fourth time period P4, pixel 13 can emit light based on the data signal DVi supplied during the previous display scan period.

[0227] Figures 13 to 15 It is shown Figure 11 The equivalent circuit diagram of the pixel variant.

[0228] Because, apart from the construction of the fourth transistor M4, Figures 13 to 15 Pixels 13', 14' and 14' can be with Figure 2A Since the pixels 10 are the same or similar, the same reference numerals are used to indicate the same or corresponding components, and therefore their repeated descriptions will be omitted.

[0229] Reference Figures 13 to 15 Each of pixels 13', 14' and 14' may include a light-emitting element LD, a first transistor M1 to a seventh transistor M7, and a storage capacitor Cst.

[0230] like Figure 13 As shown, pixel 13' may include a fourth transistor M4 electrically coupled or connected between the i-th emitter control line Ei and the first node N1. When the fourth transistor M4 is turned on, a logic high voltage may be supplied as a bias voltage to the source electrode of the first transistor M1, and the first transistor M1 may have a conduction bias state.

[0231] like Figure 14 As shown, the fourth transistor M4 of pixel 14 can be electrically coupled or connected between the bias power supply VEH and the third node N3 (i.e., the drain electrode of the first transistor M1). The fourth transistor M4 can be turned on in response to the third scan signal supplied through the i+q third scan line S3i+q.

[0232] When the fourth transistor M4 is turned on, the voltage of the bias power supply VEH can be supplied to the drain electrode of the first transistor M1 as a bias voltage, and the first transistor M1 can have a conducting bias state.

[0233] like Figure 15 As shown, the fourth transistor M4 of pixel 14' can be electrically coupled or connected between the bias power supply VEH and the first node N1 (i.e., the source electrode of the first transistor M1). The fourth transistor M4 can be turned on in response to the third scan signal supplied through the i+q third scan line S3i+q.

[0234] Figures 13 to 15 Pixels 13', 14' and 14' can be accessed via Figure 12A and Figure 12B The driver is used to display one or more images.

[0235] Figures 16 to 19 It is shown Figure 11 The equivalent circuit diagram of the pixel variant.

[0236] Because, apart from the connection between the third transistor M3 and the seventh transistor M7 Figures 16 to 19 Pixels 15, 15', 16, and 16' can be respectively connected to Figure 11 , Figure 13 , Figure 14 and Figure 15 Since the pixels are the same, the same reference numerals are used to indicate the same or corresponding components, and their repeated descriptions will be omitted.

[0237] Reference Figures 16 to 19 Each of pixels 15, 15', 16 and 16' may include a light-emitting element LD, a first transistor M1 to a seventh transistor M7 and a storage capacitor Cst.

[0238] In this embodiment, the gate electrodes of the third transistor M3 and the seventh transistor M7 can be electrically coupled or connected to the second scan line S2i. Therefore, the third transistor M3 and the seventh transistor M7 can be jointly controlled. Since the second scan signal supplied through the second scan line S2i can be driven at a second frequency corresponding to the image frame rate, the third transistor M3 and the seventh transistor M7 can be turned on at the second frequency.

[0239] The gate electrode of the fourth transistor M4 can be electrically coupled or connected to the i+qth third scan line S3i+q used to supply the third scan signal. The fourth transistor M4 can be turned on at a first frequency in a manner similar to that of the fifth transistor M5 and the sixth transistor M6. For example, a conduction bias can be supplied to the first transistor M1 at the first frequency.

[0240] In other words, the seventh transistor M7 can be turned on at a second frequency, while the fourth transistor M4 can be turned on at a first frequency to supply a bias voltage during both the display scan period and the self-scan period. For example, a third scan signal can be supplied at the first frequency, and a second scan signal can be supplied at a second frequency lower than the first frequency. For example, the second frequency can be different from the first frequency.

[0241] In an embodiment, the third scan signal may have the same waveform as the second scan signal, and the third scan signal supplied via the (i+q)th third scan line S3i+q may correspond to a signal obtained by delaying the second scan signal supplied via the (i)th second scan line S2i by q horizontal time intervals (qH). However, this is merely exemplary, and the pulse widths of the third scan signal and the second scan signal may differ from each other. For example, the second scan signal may be supplied for approximately 5 horizontal time intervals (5H), and the third scan signal may be supplied for 6H.

[0242] like Figure 16 As shown, the fourth transistor M4 of pixel 15 can supply the transmit control signal as a bias voltage to the third node N3 (i.e., the drain electrode of the first transistor M1).

[0243] like Figure 17 As shown, the fourth transistor M4 of pixel 15' can supply the transmit control signal as a bias voltage to the first node N1 (i.e., the source electrode of the first transistor M1).

[0244] like Figure 18 As shown, the fourth transistor M4 of pixel 16 can supply the voltage of the bias power supply VEH as a bias voltage to the third node N3 (i.e., the drain electrode of the first transistor M1).

[0245] like Figure 19As shown, the fourth transistor M4 of pixel 16' can supply the voltage of the bias power supply VEH as a bias voltage to the first node N1 (i.e., the source electrode of the first transistor M1).

[0246] As described above, the pixels and display device having pixels according to the embodiments can support displaying images at various driving frequencies by allowing a display scan period and at least one self-scanning period to be included in a frame. For example, as the driving frequency decreases, the number of self-scanning periods can be increased, and thus the perception of brightness reduction and flicker that occur at low-frequency driving can be improved.

[0247] Hysteresis (i.e., the difference between threshold voltage shifts) attributable to the conduction bias difference (and grayscale difference) between adjacent pixels can be overcome by periodically applying a constant bias voltage used to bias the first transistor via a fourth transistor to the first transistor, independent of the data signal and image grayscale level. Therefore, motion blur (i.e., ghosting) attributable to hysteresis bias can be improved (or removed).

[0248] However, the advantages of openness are not limited to those mentioned above, and can be extended in various forms without departing from the spirit and scope of openness.

Claims

1. A pixel for a display device, the pixel comprising: Light-emitting elements; The first transistor includes a first electrode electrically connected to a first node, a gate electrode directly connected to a second node, and a second electrode electrically connected to a third node, wherein the first node is electrically connected to a first power supply, and the third node is electrically connected to the light-emitting element; The second transistor is electrically connected between the data line and the first node, and the second transistor includes a gate electrode electrically connected to the first scan line; A third transistor, electrically connected between the gate electrode of the first transistor and the third node, the third transistor including a gate electrode electrically connected to a third scan line; and A fourth transistor includes a gate electrode electrically connected to a second scan line to apply a bias voltage to either the first or second electrode of the first transistor. The fourth transistor is turned on at a first frequency, and The second transistor is turned on at a second frequency, which is different from the first frequency.

2. The pixel according to claim 1, wherein, The first transistor is configured to control the drive current of the light-emitting element based on the voltage of the second node.

3. The pixel according to claim 1, wherein, The third transistor is turned on at the second frequency.

4. The pixel according to claim 3, wherein, The length of the conduction period of the second transistor and the length of the conduction period of the third transistor are different from each other.

5. The pixel according to claim 3, wherein, The first signal is supplied through the first scan line. The second signal is supplied through the third scan line. The second transistor turns on in response to the first signal that is enabled in the first time period. The third transistor turns on in response to the second signal that is enabled in the second time period, and The second time period overlaps with the first time period.

6. The pixel according to claim 5, wherein, The second time period is longer than the first time period.

7. The pixel according to claim 1, wherein the pixel further comprises: The fifth transistor is electrically connected between the first power source and the first node; The sixth transistor is electrically connected between the third node and the fourth node, and the fourth node is electrically connected to the first electrode of the light-emitting element; The seventh transistor is electrically connected between the fourth node and the first initialization power supply; as well as The eighth transistor is electrically connected between the second node and the second initialization power supply.

8. The pixel according to claim 7, wherein, The fifth transistor includes a gate electrode electrically connected to the emitter control line.

9. The pixel according to claim 7, wherein, The sixth transistor includes a gate electrode electrically connected to the emitter control line.

10. The pixel according to claim 7, wherein, The seventh transistor includes a gate electrode electrically connected to the second scan line.

11. The pixel according to claim 7, wherein, The eighth transistor includes a gate electrode electrically connected to the preceding first scan line.

12. The pixel according to claim 7, wherein, The storage capacitor is electrically connected between the first power source and the second node.

13. The pixel according to claim 7, wherein, The fifth to seventh transistors are turned off at the first frequency, and The eighth transistor is turned on at the second frequency.

14. The pixel according to claim 1, wherein, The fourth transistor is electrically connected between the transmit control line and the third node, and is configured to apply the voltage of the transmit control line as the bias voltage to the third node in response to a signal from the second scan line.

15. The pixel according to claim 1, wherein, The fourth transistor is electrically connected between the transmit control line and the first node, and is configured to apply the voltage of the transmit control line as the bias voltage to the first node in response to a signal from the second scan line.

16. The pixel according to claim 1, wherein, The fourth transistor is electrically connected between the bias power supply and the third node or between the bias power supply and the first node, and is configured to apply the voltage of the bias power supply as the bias voltage to the third node or the first node in response to a signal from the second scan line.

17. The pixel according to claim 1, wherein, The second frequency is lower than the first frequency.

18. The pixel according to claim 1, wherein, The second frequency is equal to the image refresh rate and corresponds to an equal portion of the first frequency.

19. The pixel according to claim 1, wherein, The length of the conduction period of the second transistor and the length of the conduction period of the third transistor are different from each other.

Images