Display device

Abstract

The display device includes a pixel including a light emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixels are connected to a first scan line, a second scan line, a third scan line, a fourth scan line, a fifth scan line, an emission control line, and a data line. The display device further includes an emission driver configured to supply an emission control signal to the emission control line, a scan driver configured to supply first to fifth scan signals to the first to fifth scan lines, respectively, in a period in which the emission control signal is supplied, and a data driver configured to supply first to fifth scan signals to the first to fifth scan lines, respectively, in a period in which the emission control signal is supplied. And a data line configured to supply a data signal to the data line. The first scan signal controls a timing in which the second node and a first electrode of the light emitting element are connected to each other.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0063893, filed on May 16, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of this disclosure relate to display devices. Background Technology

[0004] Enhancing the driving efficiency of a display device can be achieved by reducing power consumption. For example, power consumption can be reduced by lowering the driving frequency (or data write frequency). Furthermore, the display device can operate at different frame rates (or driving frequencies) to display images under various conditions. Summary of the Invention

[0005] Embodiments of this application provide a display device that supplies data voltages corresponding to each of a plurality of sub-pixels.

[0006] According to an embodiment of this application, a display device includes: a pixel, including a light-emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, a fifth scan line, an emission control line, and a data line. The display device further includes: an emission driver configured to supply an emission control signal to the emission control line; a scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to the first scan line, the second scan line, the third scan line, the fourth scan line, and the fifth scan line, respectively, during a period of supplying the emission control signal; and a data driver configured to supply a data signal to the data line. The first scan signal controls the timing of the connection between the second node and the first electrode of the light-emitting element.

[0007] In an embodiment, the pixel further includes: a second transistor connected between the data line and the first node, the second transistor being turned on in response to a second scan signal; a third transistor connected between the second node and a third node to which the gate electrode of the first transistor is connected, the third transistor being turned on in response to a third scan signal; a fourth transistor connected between the first node and a first power line providing a voltage from a first power source, the fourth transistor being turned on in response to a fourth scan signal; a fifth transistor connected between the second power line providing a voltage from a driving power source and the first node, the fifth transistor being turned off in response to an emission control signal; a sixth transistor connected between the second node and the first electrode of the light-emitting element, the sixth transistor being turned off in response to an emission control signal; and a seventh transistor connected between the second node and the first electrode of the light-emitting element, the seventh transistor being turned on in response to a first scan signal.

[0008] In one embodiment, after the scan driver supplies the fourth scan signal to the fourth scan line, the scan driver supplies the first scan signal to the first scan line.

[0009] In one embodiment, the pixel further includes an eighth transistor connected between the third node and a third power line providing the voltage of the second power source, the eighth transistor being turned on in response to a fifth scan signal.

[0010] In one embodiment, the pixel further includes a ninth transistor connected between the first electrode of the light-emitting element and a fourth power line providing a voltage from a third power source, the ninth transistor being turned on in response to a fourth scan signal.

[0011] In an embodiment, a frame period includes multiple non-transmission periods divided by a transmit control signal, the scan driver supplies a fourth scan signal in the multiple non-transmission periods, and the scan driver supplies a first scan signal, a second scan signal, a third scan signal, and a fifth scan signal only in a first non-transmission period among the multiple non-transmission periods.

[0012] In an embodiment, the first non-emission cycle includes a first cycle and a second cycle following the first cycle, and the scan driver is further configured to: supply a fourth scan signal to a fourth scan line during the first cycle; and supply a first scan signal to a first scan line during the second cycle.

[0013] In an embodiment, the first non-emission cycle further includes a third cycle, a fourth cycle following the third cycle, and a fifth cycle following the fourth cycle. The scan driver is further configured to: supply a fifth scan signal to a fifth scan line during the third cycle; supply a third scan signal to a third scan line during the fourth cycle; and supply a second scan signal to a second scan line and a third scan signal to a third scan line during the fifth cycle. The fifth cycle ends earlier than the first cycle begins.

[0014] According to embodiments of this disclosure, a display device includes: a pixel, including a light-emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emission control line, and a data line. The display device further includes: an emission driver configured to supply an emission control signal to the emission control line; a scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan line, the second scan line, the third scan line, and the fourth scan line, respectively, during a period of supplying the emission control signal; and a data driver configured to supply a data signal to the data line. The first scan signal controls the timing of the connection between the second node and the first electrode of the light-emitting element.

[0015] In an embodiment, the pixel further includes: a second transistor connected between the data line and the first node, the second transistor being turned on in response to a second scan signal; a third transistor connected between the second node and a third node to which the gate electrode of the first transistor is connected, the third transistor being turned on in response to a third scan signal; a fourth transistor connected between the first node and a first power line providing a voltage from a first power source, the fourth transistor being turned on in response to a first scan signal; a fifth transistor connected between the second power line providing a voltage from a driving power source and the first node, the fifth transistor being turned off in response to an emission control signal; a sixth transistor connected between the second node and a first electrode of the light-emitting element, the sixth transistor being turned off in response to an emission control signal; and a seventh transistor connected between the second node and the first electrode of the light-emitting element, the seventh transistor including a gate electrode connected to the first node.

[0016] In one embodiment, the pixel further includes an eighth transistor connected between the first electrode of the light-emitting element and a third power line providing the voltage of the second power source, the eighth transistor being turned on in response to a first scan signal.

[0017] In one embodiment, the pixel further includes a capacitor connected between the first node and the gate electrode of the eighth transistor.

[0018] In one embodiment, the pixel further includes a ninth transistor connected between the third node and a fourth power line providing a voltage from a third power source, the ninth transistor being turned on in response to a fourth scan signal.

[0019] In an embodiment, a frame period includes a plurality of non-transmission periods divided by a transmit control signal. The scan driver supplies a first scan signal during the plurality of non-transmission periods, and the scan driver supplies a second, third, and fourth scan signal only during the first non-transmission period of the plurality of non-transmission periods.

[0020] In an embodiment, the pixel further includes: a second transistor connected between the data line and the first node, the second transistor being turned on in response to a second scan signal; a third transistor connected between the second node and a third node to which the gate electrode of the first transistor is connected, the third transistor being turned on in response to a third scan signal; a fourth transistor connected between the first node and a first power line providing a voltage from a first power source, the fourth transistor being turned on in response to a first scan signal; a fifth transistor connected between the second power line providing a voltage from a driving power source and the first node, the fifth transistor being turned off in response to an emission control signal; a sixth transistor connected between the second node and the first electrode of the light-emitting element, the sixth transistor being turned off in response to an emission control signal; a seventh transistor connected between the first electrode of the light-emitting element and the third power line providing a voltage from a second power source, the seventh transistor being turned on in response to a first scan signal; and an eighth transistor connected between the second node and the first electrode of the light-emitting element, the eighth transistor including a gate electrode connected to the gate electrode of the seventh transistor.

[0021] In one embodiment, the pixel further includes a ninth transistor connected between the third node and a fourth power line providing a voltage from a third power source, the ninth transistor being turned on in response to a fourth scan signal.

[0022] According to embodiments of this disclosure, a display device includes: a pixel, including a light-emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emission control line, and a data line. The display device further includes: an emission driver configured to supply an emission control signal to the emission control line; a scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan line, the second scan line, the third scan line, and the fourth scan line, respectively, during a period of supplying the emission control signal; and a data driver configured to supply a data signal to the data line. Before pausing the supply of the emission control signal, a voltage comprising multiple pulses is provided to a first electrode of the light-emitting element.

[0023] In an embodiment, the pixel further includes: a second transistor connected between the data line and the first node, the second transistor being turned on in response to a first scan signal; a third transistor connected between the second node and a third node to which the gate electrode of the first transistor is connected, the third transistor being turned on in response to a second scan signal; a fourth transistor connected between the first node and a first power line providing a voltage from a first power source, the fourth transistor being turned on in response to a third scan signal; a fifth transistor connected between the second power line providing a voltage from a driving power source and the first node, the fifth transistor being turned off in response to an emission control signal; a sixth transistor connected between the second node and the first electrode of the light-emitting element, the sixth transistor being turned off in response to an emission control signal; and a seventh transistor connected between the first electrode of the light-emitting element and the third power line providing a voltage from a second power source, the seventh transistor being turned on in response to a third scan signal.

[0024] In one embodiment, the pixel further includes an eighth transistor connected between the third node and a fourth power line providing a voltage from a third power source, the eighth transistor being turned on in response to a fourth scan signal.

[0025] In this embodiment, the voltage of the second power source includes multiple pulses.

[0026] According to an embodiment of this application, an electronic device includes: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device includes: a pixel, including a light-emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, a fifth scan line, an emission control line, and a data line. The display device further includes: an emission driver configured to supply an emission control signal to the emission control line; a scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to the first scan line, the second scan line, the third scan line, the fourth scan line, and the fifth scan line, respectively, during a period of supplying the emission control signal; and a data driver configured to supply a data signal to the data line. The first scan signal controls the timing of the connection between the second node and the first electrode of the light-emitting element. Attached Figure Description

[0027] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 It is shown Figure 1The diagram shows an example of a scan driver included in a display device.

[0030] Figure 3 It is shown Figure 1 The circuit diagram shown is an example of the pixels included in the display device.

[0031] Figure 4 It shows the supply to Figure 3 The timing diagram shows an example of the signal of the pixel.

[0032] Figure 5 It shows the supply to during a frame period Figure 3 The timing diagram shows an example of the signal of the pixel.

[0033] Figure 6 It is shown Figure 1 The circuit diagram shown is an example of the pixels included in the display device.

[0034] Figure 7 It is shown Figure 1 The circuit diagram shown is an example of the pixels included in the display device.

[0035] Figure 8 It is shown Figure 1 The circuit diagram shown is an example of the pixels included in the display device.

[0036] Figure 9 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0037] Figure 10 It is shown Figure 9 A schematic diagram illustrating an example of an electronic device implemented as a smartphone.

[0038] Figure 11 It is shown Figure 9 The electronic device is a schematic diagram of an example of a tablet computer. Detailed Implementation

[0039] In the following description, embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0040] It will be understood that when a component “includes” an element, unless there is another description to the contrary, it should be understood that the component does not exclude another element, but may also include another element. It will be understood that, for the purposes of this disclosure, “at least one of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more items of X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0041] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed below may also be referred to as the “second” element.

[0042] It should be understood that, unless the context clearly indicates otherwise, the description of features or aspects within each embodiment should generally be considered in relation to other similar features or aspects that may be used in other embodiments.

[0043] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are intended to include the plural forms as used herein.

[0044] It will be understood that when a component is referred to as being "on" another component, "connected to" another component, "coupled to" another component, or "adjacent to" another component, the component can be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or there may be intermediary components. It will also be understood that when a component is referred to as being "between" two components, the component can be the only component between the two components, or there may be one or more intermediary components. Other terms used to describe relationships between components should be interpreted in the same manner.

[0045] Given the measurements discussed and the errors associated with the measurement of specific quantities (e.g., limitations of the measurement system), the term "about" as used herein includes stated values ​​and means within an acceptable range of deviation for a specific value as determined by those skilled in the art. For example, as understood by those skilled in the art, "about" may mean within one or more standard deviations. Furthermore, it should be understood that although a parameter may be described herein as having "about" a certain value, according to embodiments, as will be understood by those skilled in the art, a parameter may be an exact or approximate value within the measurement error.

[0046] At low drive frequencies, drive current leakage may occur in pixels, which can lead to noticeable image flicker. Furthermore, changes in frame rate or frame response speed can cause image distortion. As further described below, embodiments of this application address these problems.

[0047] Figure 1 This is a diagram illustrating a display device 1000 according to an embodiment of the present disclosure.

[0048] Reference Figure 1The display device 1000 may include a pixel unit 100 (also called a display panel), a scan driver 200 (also called a scan driver circuit), a transmit driver 300 (also called a transmit driver circuit), a data driver 400 (also called a data driver circuit), and a timing controller 500 (also called a timing controller circuit).

[0049] The display device 1000 can display images at various frame rates (e.g., refresh rate, drive frequency, or screen refresh rate) depending on the driving conditions. Frame rate is the frequency at which data voltage is substantially written to the driving transistors of pixels PX within one second. For example, frame rate can also be called screen scan rate or screen refresh rate, and can represent the frequency at which the displayed image is reproduced within one second.

[0050] In an embodiment, the output frequency of the data driver 400 and / or the third scan signal supplied to the third scan line S3i to supply data signals can be varied in accordance with the frame rate. For example, the frame rate used to drive moving images (e.g., video) can be a frequency of about 60 Hz or higher (e.g., about 120 Hz). When the frame rate is about 60 Hz, the third scan signal can be supplied to each horizontal line (pixel row) 60 times per second.

[0051] In an embodiment, the display device 1000 can adjust the output frequencies of the scan driver 200 and the transmit driver 300, as well as the output frequency of the data driver 400 corresponding to the output frequencies of the scan driver 200 and the transmit driver 300, according to driving conditions. For example, the display device 1000 can display images corresponding to various frame rates from about 1 Hz to about 120 Hz. However, this disclosure is not limited thereto. For example, according to an embodiment, the display device 1000 can display images at a frame rate of about 120 Hz or higher (e.g., about 240 Hz or about 480 Hz).

[0052] Pixel unit 100 may include scan lines S11 to S1n, S21 to S2n, S31 to S3n, S41 to S4n and S51 to S5n, emission control lines E1 to En, and data lines D1 to Dm, and includes pixels PX connected to scan lines S11 to S1n, S21 to S2n, S31 to S3n, S41 to S4n and S51 to S5n, emission control lines E1 to En, and data lines D1 to Dm (where m and n are each an integer of 1 or greater). Each of the plurality of pixels PX may include a driving transistor and a plurality of switching transistors.

[0053] The timing controller 500 can be supplied with input image data IRGB and control signals (synchronization signal Sync and data enable signal DE) from a host system (such as an application processor (AP)) via a predetermined interface.

[0054] The timing controller 500 can generate a first control signal SCS, a second control signal ECS, and a third control signal DCS based on input image data IRGB, a synchronization signal Sync (e.g., vertical synchronization signal and horizontal synchronization signal), a data enable signal DE, and a clock signal. The first control signal SCS can be supplied to the scan driver 200, the second control signal ECS can be supplied to the transmit driver 300, and the third control signal DCS can be supplied to the data driver 400. The timing controller 500 can rearrange the input image data IRGB and supply the rearranged input image data to the data driver 400.

[0055] The scan driver 200 can receive a first control signal SCS from the timing controller 500, and based on the first control signal SCS, supply the first scan signal, the second scan signal, the third scan signal, the fourth scan signal, and the fifth scan signal to the first scan lines S11 to S1n, the second scan lines S21 to S2n, the third scan lines S31 to S3n, the fourth scan lines S41 to S4n, and the fifth scan lines S51 to S5n, respectively.

[0056] Each of the first to fifth scan signals can be set to a gate on-voltage corresponding to the type of transistor supplied by the corresponding scan signal.

[0057] The transistor receiving the scan signal can be configured to be on when the scan signal is supplied. For example, the gate on-state voltage of the scan signal supplied to a P-channel metal-oxide-semiconductor (PMOS) transistor can be logic low, and the gate on-state voltage of the scan signal supplied to an N-channel metal-oxide-semiconductor (NMOS) transistor can be logic high. In the following text, the phrase "scan signal supplied" can be understood to mean that the scan signal is supplied at a logic level that enables the transistor controlled by the scan signal to turn on.

[0058] In this embodiment, the scan driver 200 can supply some of the first to fifth scan signals multiple times during non-emission cycles. Therefore, the bias state of the driving transistors included in the pixel PX can be controlled.

[0059] The transmit driver 300 can supply transmit control signals to transmit control lines E1 to En based on the second control signal ECS. For example, the transmit control signals can be supplied sequentially to transmit control lines E1 to En.

[0060] The transmit control signal can be set to a gate cutoff voltage (e.g., a high voltage). The transistor receiving the transmit control signal can be turned off when the transmit control signal is supplied, and can be set to be on under other conditions. In the following text, the phrase "the transmit control signal is supplied" can be understood to mean that the transmit control signal is supplied at a logic level at which the transistor controlled by the transmit control signal is turned off.

[0061] exist Figure 1 In this illustration, for ease of description, each of the scan driver 200 and the transmit driver 300 is shown as a single component. However, this disclosure is not limited thereto. For example, according to an embodiment, depending on specific design requirements, the scan driver 200 may include a plurality of scan drivers that respectively supply at least one of the first to fifth scan signals. Furthermore, at least a portion of the scan driver 200 and the transmit driver 300 may be integrated into a single drive circuit or a single module, etc.

[0062] The data driver 400 can receive a third control signal DCS and image data RGB from the timing controller 500. The data driver 400 can convert the digital image data RGB into an analog data signal (data voltage). The data driver 400 can supply data signals to data lines D1 to Dm in response to the third control signal DCS. The data signals supplied to data lines D1 to Dm can be synchronized with the third scan signals supplied to the third scan lines S31 to S3n.

[0063] In an embodiment, the display device 1000 may further include a power supply. The power supply may supply the voltages of a first driving power source VDD, a second driving power source VSS, a first power source Vbs (or a bias power source), a second power source Vint1 (or a first initialization power source Vint1), and a third power source Vint2 (or a second initialization power source Vint2) to the pixel unit 100.

[0064] The display device 1000 can operate at various frame rates. In the case of low-frequency driving, image malfunctions such as flickering may occur due to current leakage in the pixels. Furthermore, as a result of driving at various frame rates, afterimages (such as blurring) may occur due to changes in response speed caused by changes in the bias state of the driving transistors or threshold voltage shifts based on hysteresis characteristics.

[0065] According to an embodiment, depending on the frame rate, one frame period of pixel PX may include one display scan period and at least one offset scan period. As a result, image quality can be improved. (Refer to...) Figure 4 and Figure 5 The operation of displaying the scan cycle and offset scan cycle is described in detail.

[0066] Figure 2 It is shown Figure 1 The figure shows an example of a scan driver 200 included in a display device 1000.

[0067] Reference Figure 1 and Figure 2 The scan driver 200 may include a first scan driver 210 (also referred to as a first scan driver circuit), a second scan driver 220 (also referred to as a second scan driver circuit), a third scan driver 230 (also referred to as a third scan driver circuit), a fourth scan driver 240 (also referred to as a fourth scan driver circuit), and a fifth scan driver 250 (also referred to as a fifth scan driver circuit).

[0068] The first control signal SCS may include the first scan start signal FLM1 to the fifth scan start signal FLM5. The first scan start signal FLM1 to the fifth scan start signal FLM5 may be supplied to the first scan driver 210, the second scan driver 220, the third scan driver 230, the fourth scan driver 240 and the fifth scan driver 250 respectively.

[0069] The width and supply timing of each of the first scan start signals FLM1 to the fifth scan start signals FLM5 can be determined based on the driving conditions of the pixel PX and the frame rate. The first scan signals to the fifth scan signals can be output based on the first scan start signals FLM1 to the fifth scan start signals FLM5 respectively. For example, the signal width of at least one of the first scan signals to the fifth scan signals can be different from the signal width of the other scan signals.

[0070] The first scan driver 210 can sequentially supply a first scan signal to the first scan lines S11 to S1n in response to a first scan start signal FLM1. The second scan driver 220 can sequentially supply a second scan signal to the second scan lines S21 to S2n in response to a second scan start signal FLM2. The third scan driver 230 can sequentially supply a third scan signal to the third scan lines S31 to S3n in response to a third scan start signal FLM3. The fourth scan driver 240 can sequentially supply a fourth scan signal to the fourth scan lines S41 to S4n in response to a fourth scan start signal FLM4. The fifth scan driver 250 can sequentially supply a fifth scan signal to the fifth scan lines S51 to S5n in response to a fifth scan start signal FLM5.

[0071] Figure 3 It is shown Figure 1 The circuit diagram shown is an example of a pixel PX included in the display device 1000.

[0072] exist Figure 3 In the diagram, for ease of description, the pixel PXij located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj will be shown (i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m).

[0073] Reference Figure 1 and Figure 3 The pixel PXij may include a light-emitting element LD, a first transistor M1 to a ninth transistor M9, and a first capacitor C1.

[0074] The first electrode (anode or cathode) of the light-emitting element LD can be connected to the sixth transistor M6, and the second electrode (cathode or anode) of the light-emitting element LD can be connected to the electrode that provides the second driving power source VSS. The light-emitting element LD can generate light with a predetermined brightness in accordance with the amount of current supplied from the first transistor M1.

[0075] In one embodiment, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting element LD can be an inorganic light-emitting element formed of inorganic materials. In yet another embodiment, the light-emitting element LD can be a light-emitting element configured with a combination of inorganic and organic materials. Alternatively, the light-emitting element LD can be in the form where a plurality of inorganic light-emitting elements are connected in parallel and / or in series between the second driving power source VSS and the sixth transistor M6.

[0076] The first electrode of the first transistor M1 (or driving transistor M1) can be connected to the first node N1, and the second electrode of the first transistor M1 can be connected to the second node N2. The gate electrode of the first transistor M1 can be connected to the third node N3. The first transistor M1 can control the amount of current flowing from the first driving power source VDD through the light-emitting element LD to the second driving power source VSS in accordance with the voltage of the third node N3. For this purpose, the voltage of the first driving power source VDD can be set to be higher than the voltage of the second driving power source VSS.

[0077] The second transistor M2 can be connected between the j-th data line Dj (hereinafter referred to as data line Dj) and the first node N1. The gate electrode of the second transistor M2 can be connected to the third scan line S3i. The second transistor M2 can be turned on when the third scan signal is supplied to the third scan line S3i to electrically connect the data line Dj and the first node N1 to each other.

[0078] The third transistor M3 can be connected between the second electrode (e.g., the second node N2) and the third node N3 of the first transistor M1. The gate electrode of the third transistor M3 can be connected to the second scan line S2i. The third transistor M3 can be turned on when the second scan signal is supplied to the second scan line S2i to electrically connect the second electrode of the first transistor M1 and the third node N3 to each other. That is, the timing of the connection between the second electrode (e.g., the drain electrode) and the gate electrode of the first transistor M1 can be controlled. When the third transistor M3 is turned on, the first transistor M1 can be connected in a diode manner.

[0079] A fourth transistor M4 can be connected between the first node N1 and the second power line PL2, which provides the voltage of the first power source Vbs. The fourth transistor M4 can be turned on in response to a fourth scan signal supplied to the fourth scan line S4i, and supply the voltage of the first power source Vbs to the first node N1. The timing of the supply of the voltage of the first power source Vbs to the first node N1 can be controlled by the fourth scan signal.

[0080] In this embodiment, the voltage of the first power source Vbs can be lower than the voltage of the first drive power source VDD and higher than the voltage of the second drive power source VSS.

[0081] Therefore, when the fourth transistor M4 is turned on (e.g., when the fourth transistor M4 is in the on state), a predetermined voltage can be applied to the first electrode (e.g., the source electrode) of the first transistor M1. When the third transistor M3 is in the off state, the first transistor M1 can have a conduction bias state (where the first transistor M1 is able to conduct) (e.g., conduction bias).

[0082] The fifth transistor M5 can be connected between the first power line PL1, which provides the voltage of the first drive power source VDD, and the first node N1. The gate electrode of the fifth transistor M5 can be connected to the i-th emitter control line Ei (hereinafter referred to as emitter control line Ei). The fifth transistor M5 can be turned off when the emitter control signal is supplied to the emitter control line Ei and turned on under other conditions.

[0083] The sixth transistor M6 can be connected between the second electrode (e.g., the second node N2) of the first transistor M1 and the first electrode (e.g., the fourth node N4) of the light-emitting element LD. The gate electrode of the sixth transistor M6 can be connected to the emission control line Ei. The sixth transistor M6 can be controlled in substantially the same way as the fifth transistor M5.

[0084] The seventh transistor M7 can be connected between the third node N3 and the third power line PL3, which provides the voltage of the second power source Vint1 (hereinafter referred to as the first initialization power source Vint1). The gate electrode of the seventh transistor M7 can be connected to the first scan line S1i.

[0085] The seventh transistor M7 can be turned on when the first scan signal is supplied to the first scan line S1i, so as to supply the voltage of the first initialization power source Vint1 to the third node N3. The voltage of the first initialization power source Vint1 can be set to a voltage lower than the optimal level of the data signal supplied to the data line Dj.

[0086] Therefore, when the seventh transistor M7 is turned on (e.g., when the seventh transistor M7 is in the on state), the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power source Vint1.

[0087] The eighth transistor M8 can be connected between the first electrode of the light-emitting element LD (e.g., the fourth node N4) and the fourth power line PL4, which provides the voltage of the third power source Vint2 (hereinafter referred to as the second initialization power source Vint2). In an embodiment, the gate electrode of the eighth transistor M8 can be connected to the fourth scan line S4i.

[0088] The eighth transistor M8 can be turned on when the fourth scan signal is supplied to the fourth scan line S4i, so as to supply the voltage of the second initialization power source Vint2 to the first electrode of the light-emitting element LD.

[0089] The ninth transistor M9 can be connected between the second electrode (e.g., the second node N2) of the first transistor M1 and the first electrode (e.g., the fourth node N4) of the light-emitting element LD. In an embodiment, the gate electrode of the ninth transistor M9 can be connected to the fifth scan line S5i.

[0090] The ninth transistor M9 can be turned on when the fifth scan signal is supplied to the fifth scan line S5i to connect the second node N2 and the fourth node N4 to each other.

[0091] In low-frequency driving where one frame period is longer, flickering may occur when the light-emitting element (LD) emits light when a voltage difference exists between the second node N2 and the fourth node N4. Reducing the voltage difference between the second node N2 and the fourth node N4 in the low-frequency driving of the display device can reduce or eliminate this flickering.

[0092] Before the light-emitting element LD emits light, the voltage difference between the second node N2 and the fourth node N4 can be reduced as the ninth transistor M9 is turned on. Therefore, flickering caused by the voltage difference between the second node N2 and the fourth node N4 can be prevented or reduced.

[0093] When the voltage of the second initialization power source Vint2 is supplied to the first electrode of the light-emitting element LD, the parasitic capacitance of the light-emitting element LD can be discharged. Since the residual voltage charged in the parasitic capacitance is discharged (removed), unintended minute emissions can be prevented or reduced. Therefore, the black level performance of pixel PXij can be improved.

[0094] The first initial power source Vint1 and the second initial power source Vint2 can generate different voltages. That is, the voltage initialized to the third node N3 and the voltage initialized to the fourth node N4 can be set to be different from each other.

[0095] A first capacitor C1 can be connected between the first electric field line PL1 and the third node N3. The first capacitor C1 can store the voltage applied to the third node N3. In this document, the expression "stores...voltage / voltage difference" regarding a capacitor means that the capacitor stores the charge corresponding to said voltage / voltage difference.

[0096] In this embodiment, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be implemented using polysilicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can comprise a polysilicon semiconductor layer formed as an active layer (channel) using a low-temperature polysilicon (LTPS) process.

[0097] Furthermore, the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can be implemented using P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage of the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 can have a logic low level.

[0098] Due to the high response speed of polysilicon semiconductor transistors, they can be used in switching elements that perform fast switching.

[0099] The third transistor M3, the seventh transistor M7, and the ninth transistor M9 can be formed using oxide semiconductor transistors. For example, the third transistor M3, the seventh transistor M7, and the ninth transistor M9 can be implemented using N-type oxide semiconductor transistors (e.g., NMOS transistors) and include an oxide semiconductor layer as the active layer. Therefore, the gate on-state voltage of the third transistor M3, the seventh transistor M7, and the ninth transistor M9 can have a logic high level.

[0100] However, this disclosure is not limited thereto, and according to embodiments, the first transistor M1 to the ninth transistor M9 can be formed of various types of transistors.

[0101] Figure 4 It shows the supply to Figure 3 The timing diagram shows an example of the signal of pixel PXij. Figure 5 It shows the supply to during a frame period Figure 3 The timing diagram shows an example of the signal of pixel PXij.

[0102] Reference Figure 3 , Figure 4 and Figure 5 In a frequency converter drive used to control the frame rate, a frame period FP may include a display scan period DSP and at least one bias scan period BSP.

[0103] The display scan cycle DSP may include a first non-emission cycle NEP1 and a first transmission cycle EP1. The bias scan cycle BSP may include a second non-emission cycle NEP2 and a second transmission cycle EP2. Figure 4 The non-emission periodic NEP and emission periodic EP shown can be respectively compared with... Figure 5 The first non-emission cycle NEP1 and the first transmission cycle EP1 shown correspond to each other.

[0104] The display scan cycle DSP can include the cycle in which data signals corresponding to the actual output image are written. For example, when displaying a still image by driving it at a low frequency, data signals can be written to the DSP for each display scan cycle.

[0105] like Figure 5As shown, during the first non-emission cycle NEP1, which is the non-emission cycle of the display scan cycle DSP, the first scan signal to the fifth scan signal can be supplied to the pixel PXij. In an embodiment, the first scan signal can control the timing of the voltage of the second power source Vint1 being supplied to the third node N3. The second scan signal can control the timing of the connection (e.g., diode connection) between the second electrode (drain electrode) and the gate electrode of the first transistor M1. The third scan signal can control the timing of the data signal being supplied to the first node N1. The fourth scan signal can control the timing of the voltage of the first power source Vbs being supplied to the first node N1 and the timing of the voltage of the third power source Vint2 being supplied to the fourth node N4. The fifth scan signal can control the timing of the connection between the second node N2 and the fourth node N4.

[0106] In an embodiment, a frame period FP may consist only of the display scan period DSP. That is, the bias scan period BSP can be omitted in a frame period FP.

[0107] like Figure 5 As shown, the fourth scan signal can be supplied to the fourth scan line S4i during the second non-emission period NEP2, which is the non-emission period of the bias scan period BSP. Therefore, the voltage of the first power source Vbs can be supplied to the source electrode of the first transistor M1 during the second non-emission period NEP2. Thus, the brightness change of the first transistor M1 during the low-frequency driven frame period FP can be minimized or reduced.

[0108] The period during which the transmit control signal has a logic low level can be the transmit period EP, the first transmit period EP1, and the second transmit period EP2. In addition to the transmit period EP, the first transmit period EP1, and the second transmit period EP2, the period can be the non-transmit period NEP, the first non-transmit period NEP1, and the second non-transmit period NEP2.

[0109] The gate on-state voltages of the second, first, and fifth scan signals supplied to the third transistor M3, the seventh transistor M7, and the ninth transistor M9 (each of which is an N-type transistor) can be logic high. The gate on-state voltages of the third and fourth scan signals supplied to the second transistor M2, the fourth transistor M4, and the eighth transistor M8 (each of which is a P-type transistor) can be logic low.

[0110] In the following text, reference will be made to Figure 4 Also refer to Figure 3The scan signal supplied in the DSP during the display scan cycle and the operation of pixel PXij are described in detail.

[0111] During the non-emit cycle (NEP), the transmit control signal can be supplied to the transmit control line Ei. Therefore, during the non-emit cycle (NEP), the fifth transistor M5 and the sixth transistor M6 can be turned off. The non-emit cycle (NEP) can include the first cycle P1 to the fifth cycle P5.

[0112] In the first cycle P1, the scan driver 200 can supply a first scan signal to the first scan line S1i. When the first scan signal is supplied, the seventh transistor M7 can be turned on, and the voltage of the first initialization power source Vint1 can be supplied to the third node N3. Therefore, the gate voltage of the first transistor M1 can be initialized to the voltage of the first initialization power source Vint1.

[0113] In the second cycle P2, the scan driver 200 can supply a second scan signal to the second scan line S2i. When the second scan signal is supplied, the third transistor M3 can be turned on. The first transistor M1 can be connected in a diode manner when the third transistor M3 is turned on (e.g., when the third transistor M3 is in the on state), and the magnitude of the gate-source voltage of the first transistor M1 can be reduced to a level corresponding to the absolute value of the threshold voltage of the first transistor M1.

[0114] In the third cycle P3, the scan driver 200 can supply the second scan signal to the second scan line S2i and the third scan signal to the third scan line S3i. Furthermore, the second transistor M2 and the third transistor M3 can be turned on. Therefore, since the data signal supplied to the data line Dj is supplied to the first node N1 and the first transistor M1 is connected in a diode manner, data writing and threshold voltage compensation of the first transistor M1 can be performed.

[0115] In the fourth cycle P4, the scan driver 200 can supply the fourth scan signal to the fourth scan line S4i. Because the fourth scan signal is supplied, the fourth transistor M4 and the eighth transistor M8 can be turned on.

[0116] When the fourth transistor M4 is turned on (e.g., when the fourth transistor M4 is in the on state), the voltage of the first power source Vbs can be supplied to the first node N1. When the eighth transistor M8 is turned on (e.g., when the eighth transistor M8 is in the on state), the voltage of the third power source Vint2 can be supplied to the fourth node N4.

[0117] By compensating for the threshold voltage in the third cycle P3, the voltage difference between the gate and source voltages of the first transistor M1 can be significantly reduced. Then, the characteristics of the first transistor M1 may be altered again, and the drive current in the emitter cycle EP may increase, or black grayscale excitation may be observed.

[0118] To prevent this characteristic change, the fourth transistor M4 can be turned on in the fourth cycle P4. Therefore, in the fourth cycle P4, the voltage of the first power source Vbs is supplied to the source electrode of the first transistor M1, so that the first transistor M1 can be set to the on-biased state.

[0119] In the fifth cycle P5, the scan driver 200 can supply the fifth scan signal to the fifth scan line S5i. When the fifth scan signal is supplied, the ninth transistor M9 can be turned on. Therefore, the second node N2 and the fourth node N4 are connected to each other, which makes it possible to reduce the voltage difference between the second node N2 and the fourth node N4.

[0120] In one embodiment, the ninth transistor M9 can be turned on before the emit cycle EP, after the voltage of the third power source Vint2 is last applied to the fourth node N4 in the fourth cycle P4.

[0121] Subsequently, the transmit driver 300 can pause supplying the transmit control signal to the transmit control line Ei during the transmit cycle EP. Therefore, the fifth transistor M5 and the sixth transistor M6 can be turned on, and the drive current based on the data signal can be supplied to the light-emitting element LD through the first transistor M1. The light-emitting element LD can then emit light with a brightness corresponding to the drive current.

[0122] As described above, before the transmit cycle EP, the ninth transistor M9 is turned on, which reduces the voltage difference between the second node N2 and the fourth node N4. Therefore, flickering that may occur during the transmit cycle EP can be prevented or reduced.

[0123] Although it has been referenced Figure 5 The supply of first to fifth scan signals to the first to fifth cycles P1 has been described, but this disclosure is not limited thereto. For example, in some embodiments, the pulse width of each of the first to fifth scan signals may be varied. Furthermore, the sequential supply of the first to fifth scan signals has been described. However, this disclosure is not limited thereto. For example, in some embodiments, the order in which the first to fifth scan signals are supplied during the non-transmit cycle NEP may be changed.

[0124] Figure 6 It is shown Figure 1The circuit diagram shown is an example of a pixel PX included in the display device 1000.

[0125] Reference Figure 6 The ninth transistor M9 can be turned on based on the fourth scan signal.

[0126] exist Figure 6 In the diagram, for ease of description, the pixel PXij located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj will be shown (i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m).

[0127] Pixel PXij may include a light-emitting element LD, a first transistor M1 to a ninth transistor M9, a first capacitor C1, and a second capacitor C2. Figure 6 The light-emitting element LD, the first transistor M1 to the ninth transistor M9, and the first capacitor C1 shown are similar to Figure 3 The light-emitting element LD, the first transistor M1 to the ninth transistor M9 and the first capacitor C1 are shown in the figure, and therefore, for ease of explanation, further description of these components and related technical aspects will be omitted.

[0128] The ninth transistor M9 can be connected between the second electrode of the first transistor M1 (e.g., the second node N2) and the first electrode of the light-emitting element LD (e.g., the fourth node N4). In an embodiment, the gate electrode of the ninth transistor M9 can be connected to the first node N1.

[0129] The second capacitor C2 can be connected between the first node N1 and the fourth scan line S4i. Therefore, the fourth scan signal can be supplied to the gate electrode of the ninth transistor M9 through the fourth scan line S4i and the second capacitor C2.

[0130] Reference Figure 4 During the fourth cycle P4, based on the fourth scan signal provided to the fourth scan line S4i, the eighth transistor M8 can be turned on and the ninth transistor M9 can be turned off.

[0131] In other words, before the transmit cycle EP, as the ninth transistor M9 is turned on, the voltage difference between the second node N2 and the fourth node N4 can be reduced. Therefore, flickering caused by the voltage difference between the second node N2 and the fourth node N4 can be prevented or reduced.

[0132] Figure 7 It is shown Figure 1 The circuit diagram shown is an example of a pixel PX included in the display device 1000.

[0133] Reference Figure 7 The ninth transistor M9 can be turned on based on the fourth scan signal.

[0134] exist Figure 7 In the diagram, for ease of description, the pixel PXij located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj will be shown (i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m).

[0135] Pixel PXij may include a light-emitting element LD, a first transistor M1 to a ninth transistor M9, and a first capacitor C1. Figure 7 The light-emitting element LD, the first transistor M1 to the ninth transistor M9, and the first capacitor C1 shown are similar to Figure 3 The light-emitting element LD, the first transistor M1 to the ninth transistor M9 and the first capacitor C1 are shown in the figure, and therefore, for ease of explanation, further description of these components and related technical aspects will be omitted.

[0136] The ninth transistor M9 can be connected between the second electrode (e.g., the second node N2) of the first transistor M1 and the first electrode (e.g., the fourth node N4) of the light-emitting element LD. In an embodiment, the gate electrode of the ninth transistor M9 can be connected to the fourth scan line S4i.

[0137] Reference Figure 4 During the fourth cycle P4, based on the fourth scan signal provided to the fourth scan line S4i, the eighth transistor M8 can be turned on and the ninth transistor M9 can be turned off. During the fifth cycle P5, based on the fourth scan signal provided to the fourth scan line S4i, the eighth transistor M8 can be turned off and the ninth transistor M9 can be turned on.

[0138] In other words, before the transmit cycle EP, as the ninth transistor M9 is turned on, the voltage difference between the second node N2 and the fourth node N4 can be reduced. Therefore, flickering caused by the voltage difference between the second node N2 and the fourth node N4 can be prevented or reduced.

[0139] Figure 8 It is shown Figure 1 The circuit diagram shown is an example of a pixel PX included in the display device 1000.

[0140] Reference Figure 8 The pixel PXij may include a light-emitting element LD, a first transistor M1 to an eighth transistor M8, and a first capacitor C1.

[0141] exist Figure 8 In the diagram, for ease of description, the pixel PXij located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj will be shown (i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m).

[0142] Figure 8 The light-emitting element LD, the first transistor M1 to the eighth transistor M8, and the first capacitor C1 shown are similar to Figure 3 The light-emitting element LD, the first transistor M1 to the eighth transistor M8 and the first capacitor C1 are shown in the figure, and therefore, for ease of explanation, further description of these components and related technical aspects will be omitted.

[0143] The voltage of the third power source Vint2 can be a voltage comprising multiple pulses. In an embodiment, the voltage of the third power source Vint2 can be a voltage comprising multiple step pulses, each of which increases by a constant step voltage.

[0144] Therefore, the voltage of the fourth node N4 provided by the fourth scan signal can be increased based on the voltage of the third power source Vint2. In other words, since the voltage of the fourth node N4 increases to a level similar to that of the second node N2, the voltage difference between the second node N2 and the fourth node N4 can be reduced. Therefore, flickering caused by the voltage difference between the second node N2 and the fourth node N4 can be prevented or reduced.

[0145] In the display device according to an embodiment of the present disclosure, before the emission cycle, the voltage difference between one electrode of the driving transistor M1 and one electrode of the light-emitting element LD is reduced. As a result, flickering can be prevented or reduced.

[0146] Figure 9 This is a block diagram illustrating an electronic device 2000 according to an embodiment of the present disclosure. Figure 10 It is shown Figure 9 The diagram shows an example of an electronic device 2000 implemented as a smartphone. Figure 11 It is shown Figure 9 The electronic device 2000 is a schematic diagram of an example of a tablet computer.

[0147] Reference Figures 9 to 11 The electronic device 2000 may include a processor 2010, a memory device 2020, a storage device 2030, an input / output (I / O) device 2040, a power supply 2050, and a display device 2060. The display device 2060 may be... Figure 1 The display device 1000. The electronic device 2000 may also include various ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, or other systems. In embodiments, such as Figure 10 As shown, the electronic device 2000 can be implemented as a smartphone. In an embodiment, as... Figure 11As shown, the electronic device 2000 can be implemented as a tablet computer. However, the above examples are illustrative, and the electronic device 2000 is not limited to the examples described above. For example, the electronic device 2000 can be implemented as a cellular phone, a video phone, a smart tablet, a smartwatch, a navigation device for a vehicle, a computer monitor, a laptop computer, and a head-mounted display device, etc.

[0148] Processor 2010 can perform specific calculations or tasks. In embodiments, processor 2010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller. Processor 2010 can be connected to other components via address buses, control buses, and data buses. In embodiments, processor 2010 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In embodiments, processor 2010 can provide input image data to display device 2060. Therefore, display device 2060 can display images based on the input image data provided from processor 2010.

[0149] The memory device 2020 can store data required for performing operations of the electronic device 2000. The memory device 2020 can be used as working memory and / or buffer memory for the processor 2010. For example, the memory device 2020 may include one or more volatile memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, and mobile DRAM devices.

[0150] Storage device 2030 can respond to control signals or data storage from processor 2010. Storage device 2030 may include one or more non-volatile memories to retain data even when electronic device 2000 is powered off. In some embodiments, storage device 2030 may include a solid-state drive (SSD), hard disk drive (HDD), or optical disc read-only memory (CD-ROM), etc.

[0151] I / O device 2040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In an embodiment, display device 2060 may be integrated with I / O device 2040.

[0152] Power supply 2050 can supply the power required to operate electronic device 2000. For example, power supply 2050 may include a power management integrated circuit (PMIC). In an embodiment, power supply 2050 can supply power to display device 2060.

[0153] Display device 2060 can display images in response to image data signals and / or control signals from processor 2010. Display device 2060 can be connected to other components via a bus or other communication link.

[0154] As is customary in the art of this disclosure, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) that can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar elements, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions.

[0155] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: A pixel includes a light-emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, a fifth scan line, an emission control line, and a data line; A transmit driver configured to supply transmit control signals to the transmit control line; A scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a fifth scan signal to a first scan line, a second scan line, a third scan line, a fourth scan line, and a fifth scan line, respectively, during a period of supplying the transmit control signal; and A data driver, configured to supply data signals to the data line, The first scanning signal controls the timing of the connection between the second node and the first electrode of the light-emitting element.

2. The display device according to claim 1, wherein, The pixels also include: A second transistor is connected between the data line and the first node. The second transistor is turned on in response to the second scan signal; A third transistor is connected between the second node and the third node to which the gate electrode of the first transistor is connected. The third transistor is turned on in response to the third scan signal; A fourth transistor is connected between the first node and the first power line providing the voltage of the first power source. The fourth transistor is turned on in response to the fourth scan signal; The fifth transistor is connected between the second power line providing the driving power source voltage and the first node. The fifth transistor is turned off in response to the transmit control signal; A sixth transistor is connected between the second node and the first electrode of the light-emitting element. Wherein, the sixth transistor is turned off in response to the transmit control signal; and The seventh transistor is connected between the second node and the first electrode of the light-emitting element. The seventh transistor is turned on in response to the first scan signal.

3. The display device according to claim 2, wherein, After the scan driver supplies the fourth scan signal to the fourth scan line, the scan driver supplies the first scan signal to the first scan line.

4. The display device according to claim 2, wherein, The pixels also include: The eighth transistor is connected between the third node and the third power line providing the voltage of the second power source. The eighth transistor is turned on in response to the fifth scan signal.

5. The display device according to claim 4, wherein, The pixels also include: The ninth transistor is connected between the first electrode of the light-emitting element and the fourth electric field line that provides the voltage of the third power source. The ninth transistor is turned on in response to the fourth scan signal.

6. The display device according to claim 5, wherein, A frame period comprises multiple non-transmission periods divided by the transmit control signal. The scan driver supplies the fourth scan signal during the plurality of non-emission cycles, and The scan driver supplies the first scan signal, the second scan signal, the third scan signal, and the fifth scan signal only in the first non-emission cycle among the plurality of non-emission cycles.

7. The display device according to claim 6, wherein, The first non-emission cycle includes a first cycle and a second cycle following the first cycle, and The scan driver is further configured as follows: The fourth scan signal is supplied to the fourth scan line during the first cycle; and In the second cycle, the first scan signal is supplied to the first scan line.

8. The display device according to claim 7, wherein, The first non-emission cycle also includes a third cycle, a fourth cycle following the third cycle, and a fifth cycle following the fourth cycle. The scan driver is further configured as follows: The fifth scan signal is supplied to the fifth scan line during the third cycle; The third scan signal is supplied to the third scan line during the fourth cycle; and In the fifth cycle, the second scan signal is supplied to the second scan line and the third scan signal is supplied to the third scan line, and The fifth cycle ends earlier than the first cycle begins.

9. A display device, wherein, The display device includes: A pixel includes a light-emitting element and a first transistor connected between a first node and a second node. The first transistor is configured to generate a drive current. The pixel is connected to a first scan line, a second scan line, a third scan line, a fourth scan line, an emission control line, and a data line; A transmit driver configured to supply transmit control signals to the transmit control line; A scan driver configured to supply a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to a first scan line, a second scan line, a third scan line, and a fourth scan line, respectively, during a period of supplying the transmit control signal; and A data driver, configured to supply data signals to the data line, The first scanning signal controls the timing of the connection between the second node and the first electrode of the light-emitting element.

10. The display device according to claim 9, wherein, The pixels also include: A second transistor is connected between the data line and the first node. The second transistor is turned on in response to the second scan signal; A third transistor is connected between the second node and the third node to which the gate electrode of the first transistor is connected. The third transistor is turned on in response to the third scan signal; A fourth transistor is connected between the first node and the first power line providing the voltage of the first power source. The fourth transistor is turned on in response to the first scan signal; The fifth transistor is connected between the second power line providing the driving power source voltage and the first node. The fifth transistor is turned off in response to the transmit control signal; A sixth transistor is connected between the second node and the first electrode of the light-emitting element. Wherein, the sixth transistor is turned off in response to the transmit control signal; and The seventh transistor is connected between the second node and the first electrode of the light-emitting element. The seventh transistor includes a gate electrode connected to the first node.

Images