MicroLED display chip and manufacturing method thereof

Abstract

The invention discloses a MicroLED display chip which comprises the components of a substrate; the LED semiconductor layer is arranged on the substrate, the LED semiconductor layer comprises a plurality of LED units arranged in an array, the adjacent LED units can be independently driven, the LED units comprise a first light-emitting unit, a second light-emitting unit and a third light-emitting unit, and the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are arranged on the substrate. The first light-emitting unit, the second light-emitting unit and the third unit are stacked in the thickness direction of the substrate, the second unit and the third unit are located on the upper portion of the first unit, and the third light-emitting unit is located on the side portion of the second light-emitting unit. According to the MicroLED display chip provided by the embodiment of the invention, a two-color stacked structure is adopted, and the other color is arranged in parallel, so that on one hand, the problem of defocusing is reduced due to the fact that the vertical distance between the light-emitting layers is reduced; and on the other hand, after the two-color stacked structure is adopted, the size of the red unit can be amplified, so that the size effect of the whole device is reduced, and the working efficiency of the whole device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of light emitting, in particular to a MicroLED display chip. BACKGROUND

[0002] At present, "artificial intelligence" and "meta universe" have become the most advanced technologies in the field of frontier information technology. Micro display is the visual portal of the "meta universe" related artificial intelligence glasses and other advanced technologies. However, the mainstream technology of micro display is currently silicon-based liquid crystal (LCOS) and silicon-based Micro-OLED. For example, the technical solution adopted by Apple Vision Pro is Sony's silicon-based Micro-OLED micro display. Due to the low brightness of Micro-OLED, it cannot adopt light waveguides such as diffraction light waveguides, and therefore cannot meet the needs of multiple scenarios and lightweight. The development market of AR in the "meta universe" is expanding and gradually becoming dominant. Due to the higher requirements of AR equipment for lightweight and high brightness of Micro chips, the current mainstream micro display such as silicon-based liquid crystal (LCOS) and silicon-based Micro-OLED cannot meet this demand well. At present, MicroLED micro display chips are the only ones with high stability and high brightness, and are recognized as the most suitable micro display chip for AR applications. However, the existing MicroLED micro display chips generally use the X-Cube scheme (i.e., using red, green, and blue single-color Micro screens to cooperate with light machines to synthesize colors) and the technology scheme of blue light emitting epitaxial unit plus quantum dot color conversion to complete color display. However, the above X-Cube scheme has the problems of high production cost, large volume and heavy weight due to the use of three screens to synthesize, and it is difficult to meet the lightweight and other production needs. The technology scheme of blue light emitting epitaxial unit plus quantum dot color conversion to complete color display also has the disadvantage that brightness and quantum dot reliability cannot be considered. There are also schemes in related colorization technologies that stack three color light emitting units, but the stacked structure has a high thickness and cannot be applied to AR micro display of human intelligent glasses that require ultra-high PPI. In addition, the distance from the light emitting layer of different light emitting units to the light receiving structure is quite different, especially in the field of near-eye display artificial intelligence AR glasses, the distance from the glasses to the human eye is short, and there is a significant "defocus" problem after light convergence. SUMMARY

[0003] In view of the above technical problems, the present application aims to provide a full-color MicroLED stacked chip to overcome the shortcomings of the prior art.

[0004] To achieve the above-mentioned application purposes, the technical solutions adopted by the present application include:

[0005] The MicroLED display chip provided by the present application comprises:

[0006] Substrate;

[0007] An LED semiconductor layer is disposed on the substrate. The LED semiconductor layer includes multiple LED units arranged in an array. Adjacent LED units can be driven independently. Each LED unit includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit that emit different colors of light. The first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are stacked in the thickness direction of the substrate. The second light-emitting unit and the third light-emitting unit are located above the first light-emitting unit, or the second light-emitting unit and the third light-emitting unit are located below the first light-emitting unit, and the third light-emitting unit is located on the side of the second light-emitting unit.

[0008] In some embodiments, the first light-emitting unit is a red light-emitting unit.

[0009] In some embodiments, the second light-emitting unit is a blue light-emitting unit, and the third light-emitting unit is a green light-emitting unit.

[0010] In some embodiments, each of the three light-emitting units includes a P-type semiconductor layer, an epitaxial light-emitting layer, and an N-type semiconductor layer stacked sequentially, wherein the thickness of the P-type semiconductor layer is 0.05 μm-0.5 μm, and the thickness of the N-type semiconductor layer is 1 μm-5 μm.

[0011] In some embodiments, the size ratio of the second light-emitting unit and the third light-emitting unit along the length of the substrate is N:1, where N ranges from 0.5 to 2.

[0012] In some embodiments, the P-type semiconductor layers of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are disposed opposite to each other.

[0013] In some embodiments, the substrate is provided with a common anode driving electrode and three cathode driving electrodes. The common anode driving electrode is electrically connected to the P-type semiconductor layer of the three light-emitting units, and the three cathode driving electrodes are respectively electrically connected to the N-type semiconductor layer of the three light-emitting units.

[0014] In some embodiments, when the second light-emitting unit and the third light-emitting unit are located above the first light-emitting unit, a transmissive layer is provided between the first light-emitting unit and the second light-emitting unit, and between the first light-emitting unit and the third light-emitting unit. The transmissive layer is used to reflect the light emitted by the second light-emitting unit and the third light-emitting unit, and to transmit the light emitted by the first light-emitting unit.

[0015] In some embodiments, when the second light-emitting unit and the third light-emitting unit are located below the first light-emitting unit, a transmissive layer is provided between the first light-emitting unit and the second light-emitting unit, and between the first light-emitting unit and the third light-emitting unit. The transmissive layer is used to transmit the light emitted by the second light-emitting unit and the third light-emitting unit, and to reflect the light emitted by the first light-emitting unit.

[0016] In some embodiments, a current spreading layer is provided on the P-type semiconductor of each of the three light-emitting units, and the common anode driving electrode is electrically connected to the P-type semiconductor layer through the current spreading layer.

[0017] The full-color MicroLED stacked chip proposed in this invention has the following technical effects:

[0018] The MicroLED display chip provided in this embodiment of the invention adopts a two-color stacked structure, with another color arranged in parallel. On the one hand, by reducing the vertical distance between the light-emitting layers, the "defocusing" problem is reduced, improving the working effect of the device. On the other hand, by adopting a two-color stacked structure, the size of the light-emitting unit emitting red light can be maximized, and the size of the red light-emitting unit, green light-emitting unit, and blue light-emitting unit can all be adjusted individually. The size ratio can be infinitely adapted to its luminous efficiency, thereby reducing the size effect of the entire device and maximizing the working efficiency of the entire device. Attached Figure Description

[0019] The preferred embodiments will now be described in a clear and easy-to-understand manner, in conjunction with the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of the present invention.

[0020] Figure 1 This is a schematic diagram of the structure after redistribution of a CMOS substrate in a typical embodiment of the present invention;

[0021] Figure 2 is a schematic diagram of the epitaxial wafer structure and processing in a typical embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the structure of the first light-emitting unit after bonding in a typical embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the structure after the substrate is peeled off following the bonding of the first light-emitting unit in a typical embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the structure of the bottom light-emitting unit of the stacked pixels in a typical embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of the filling medium opening structure in a typical embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of the structure after metal filling and fabrication of the first connecting electrode in a typical embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of the device structure after the transparent reflective functional layer has been fabricated in a typical embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram of the device structure after the dielectric layer is fabricated in a typical embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram of the structure of the driving electrode after metal filling in a typical embodiment of the present invention;

[0030] Figure 11 This is a schematic diagram of the structure after bonding the second light-emitting unit in a typical embodiment of the present invention;

[0031] Figure 12 This is a schematic diagram of the structure of the second light-emitting unit after substrate peeling in a typical embodiment of the present invention;

[0032] Figure 13 This is a schematic diagram of a typical embodiment of the present invention, in which the N-type semiconductor layer of the second light-emitting unit is isolated to form a second isolation structure;

[0033] Figure 14 This is a schematic diagram of the process structure for forming the second light-emitting unit in a typical embodiment of the present invention;

[0034] Figure 15 This is a schematic diagram of the process structure of the third light-emitting unit after bonding in a typical embodiment of the present invention;

[0035] Figure 16a yes Figure 22 Schematic diagram of the AA' section structure;

[0036] Figure 16b yes Figure 23 Schematic diagram of the cross-section structure of BB';

[0037] Figure 17a yes Figure 22 Schematic diagram of the structure after filling the dielectric layer at section AA';

[0038] Figure 17b yes Figure 23 Schematic diagram of the structure after filling the medium layer at the BB' section;

[0039] Figure 18a yes Figure 22 A schematic diagram of the driving electrode structure exposed after etching the dielectric layer at section AA'.

[0040] Figure 18byes Figure 23 A schematic diagram of the driving electrode structure exposed after etching the dielectric layer at the BB' section;

[0041] Figure 19a yes Figure 22 Schematic diagram of the structure after filling the AA' section with conductive metal;

[0042] Figure 19b yes Figure 23 Schematic diagram of the structure after filling the BB' section with conductive metal;

[0043] Figure 20 This is a schematic diagram of the device structure after the second electrode and the third electrode are connected in a typical embodiment of the present invention.

[0044] Figure 21 This is a schematic diagram of the complete device structure after the passivation protective layer is fabricated in a typical embodiment of the present invention;

[0045] Figure 22 This is a top view of the cross-sectional area of ​​the device array driving via in a typical embodiment of the present invention;

[0046] Figure 23 This is a top view of the cross-sectional position of the anode interconnect electrode of the device array in a typical embodiment of the present invention. Detailed Implementation

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0048] As used in this embodiment of the invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A single layer may comprise multiple layers. For example, a semiconductor layer may comprise one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0049] The term MicroLED, as used in the embodiments of this invention, refers to a descriptive size of certain devices or structures according to embodiments of the invention, intended to indicate a scale from 0.1 to 100 μm. However, it should be understood that embodiments of the invention are not necessarily limited thereto, and certain aspects of the embodiments can be applied to larger and possibly smaller size scales.

[0050] Figure 21 A top view of an illustrative MicroLED chip structure according to some embodiments of the present invention is shown. Figure 22 This is a top view of the device array in a typical embodiment of the present invention.

[0051] Please see Figure 21 and Figure 22 The MicroLED chip structure disclosed in this embodiment of the invention includes a substrate 1 and an LED semiconductor layer formed on the substrate 1. The LED semiconductor layer includes a plurality of LED units arranged in an array. The LED units are electrically isolated from each other by a partition structure, so that each LED unit can be controlled independently.

[0052] In this embodiment, substrate 1 can be formed from semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, and indium phosphide, or from non-conductive materials such as glass, plastic, or sapphire. Substrate 1 can be a CMOS backplane or a TFT glass substrate, etc., and is not limited thereto. Substrate 1 includes a driving circuit, which can be fabricated according to specific requirements, and is used to provide electrical signals to the LED units to control brightness. The driving circuit can include an active matrix driving circuit, with each individual LED unit having its own independent driver. In some embodiments, the driving circuit can also include a passive matrix driving circuit.

[0053] Taking one LED pixel unit as an example, the LED unit includes a first light-emitting unit 20 and a second light-emitting unit 21 and a third light-emitting unit 22 stacked together. The first light-emitting unit 20 is closer to or further away from the substrate 1 than the second light-emitting unit 21 and the third light-emitting unit 22; this is not limited. The second light-emitting unit 21 is located above the first light-emitting unit 20, and the third light-emitting unit 22 is also located above the first light-emitting unit, and is arranged parallel to the second unit on its side. Alternatively, the second light-emitting unit 21 is located below the first light-emitting unit 20, and the third light-emitting unit 22 is also located below the first light-emitting unit.

[0054] It is understood that "parallel" in this embodiment refers to two light-emitting units arranged in one direction. For example, if the third light-emitting unit 22 and the second light-emitting unit 21 are arranged in parallel, it means that the third light-emitting unit 22 and the second light-emitting unit 21 are arranged along the first direction. It should be noted that the first direction is along the length of the substrate 1.

[0055] In this embodiment, the first light-emitting unit 20 can be a red light-emitting unit, or the second light-emitting unit 21 or the third unit 22 can be a red light-emitting unit. This embodiment does not specifically limit the position of the red light-emitting unit. Due to the size effect of MicroLED devices, when the size in the first direction of the device is about 20µm, the device efficiency decreases sharply as the device size decreases, with the size effect being most pronounced in red light. In this embodiment, the first light-emitting unit 20 and the second light-emitting unit 21, and the first light-emitting unit 20 and the third light-emitting unit 22 are stacked in the thickness direction of the substrate 1, with one of them capable of emitting red light. Thus, without increasing the size in the first direction of the device, the size of the red light-emitting unit can be enlarged, thereby reducing the overall size effect of the device and improving the overall operating efficiency.

[0056] In this embodiment, the first light-emitting unit 20 is a red light-emitting unit. Due to the size effect of MicroLED devices, when the size in the first direction of the device is about 20 μm, the device efficiency decreases sharply as the device size decreases, with the size effect of red light being the most obvious. In this embodiment, the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22 are stacked in the thickness direction of the substrate 1. The first light-emitting unit 20 is set as a red light-emitting unit, so that the size of the first light-emitting unit 20 is the sum of the sizes of the second light-emitting unit 21 and the third light-emitting unit 22, which is the same as the pixel size. In this way, without increasing the size of the device in the first direction, the size of the red light-emitting unit can be maximized, thereby reducing the size effect of the entire device and maximizing the working efficiency of the entire device.

[0057] In this embodiment, the third light-emitting unit 22 is either a green light-emitting unit or a blue light-emitting unit. As an example, the third light-emitting unit 22 is a green light-emitting unit, and the area of ​​the third light-emitting unit 22 is smaller than that of the second light-emitting unit 21. The area ratio of the second light-emitting unit 21 to the third light-emitting unit 22 is M:1, where M ranges from 1 to 5. Under the same intensity conditions, the human eye generally perceives green light as brighter than other colors, meaning the human eye is more sensitive to green light and relatively less sensitive to blue and red light. To maintain a balanced lifespan for the display units, the area of ​​the blue light-emitting unit can be set larger than that of the green light-emitting unit. In this embodiment, the first-direction dimension of the blue light-emitting unit is approximately 3µm, and the first-direction dimension of the green light-emitting unit is approximately 1.5µm. Compared to a typical horizontal red, green, and blue light-emitting structure, the stacked structure occupies less horizontal dimension, thus allowing the display to have a higher PPI (pixel density), which is more suitable for the high PPI requirements of AI AR (augmented reality) glasses. Furthermore, by designing the third light-emitting unit 22 as a green light-emitting unit, the size of the third light-emitting unit 22 in the first direction can be reduced, and the size of the blue light display unit can be increased accordingly, so that the entire device can achieve maximum operating efficiency at the same PPI.

[0058] When the first light-emitting unit is closer to the substrate 1, based on the fact that the third light-emitting unit 22 is a green light-emitting unit, the first light-emitting unit 20 can be a red light-emitting unit, and the second light-emitting unit 21 can be a blue light-emitting unit. The transflective layer is configured to reflect blue-green light while transmitting red light. In this way, the red light-emitting unit can emit upwards through the transflective layer and pass through the blue and green light-emitting units. After the blue and green light-emitting units are driven, the blue and green light will not be transmitted towards the red light-emitting unit, which can prevent the red light-emitting unit from absorbing blue and green light energy and re-emitting red light, thus ensuring the color quality of the entire device.

[0059] In this embodiment, the substrate 1 further includes an anode driving via 104, and a first cathode driving via 101, a second cathode driving via 102, and a third cathode driving via 103 corresponding to the positions of the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22, respectively. The anode driving via 104 and the cathode driving via penetrate the substrate 1, and conductive electrodes are present on their surfaces to form an anode metal electrode and a cathode metal electrode. The anode metal electrode is electrically connected to a constant voltage source, and the cathode metal electrode is electrically connected to the source / drain of the driving circuit. The anode metal electrode and the cathode metal electrode can be made of metal or metal alloy, such as one or more materials including Cu, Al, Au, Pt, Ti, Cr, Ag, Ta, Ni, etc., and are not limited thereto.

[0060] In this embodiment, the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22 each include a P-type semiconductor layer 24, an epitaxial light-emitting layer, and an N-type semiconductor layer 23 stacked sequentially. The difference between the above light-emitting units is that the colors of the light emitted by the epitaxial light-emitting layer are different. For example, the epitaxial light-emitting layer of the first light-emitting unit 20 can emit red light, the epitaxial light-emitting layer of the second light-emitting unit 21 can emit blue light, and the epitaxial light-emitting layer of the third light-emitting unit 22 can emit green light.

[0061] In this embodiment, the thickness of the epitaxial light-emitting layer is 0.05µm-0.5µm, preferably 0.1µm. The epitaxial light-emitting layer is disposed between the P-type semiconductor layer 24 and the N-type semiconductor layer 23, and is used to recombine the holes and electrons provided from the P-type semiconductor layer 24 and the N-type semiconductor layer 23 respectively, and output light of a specific wavelength. The epitaxial light-emitting layer may have a single quantum well structure, a multi-quantum well structure, or an alternating stacked structure of well layers and barrier layers.

[0062] Because the P-type layer has poor conductivity and uneven current distribution, a current spreading layer 4 is provided on the P-type semiconductor layer 24 in this embodiment to enhance its conductivity. The current spreading layer includes an ohmic contact layer and a current transport layer. The ohmic contact layer is preferably made of ITO material, which can form a good ohmic contact with the first P-type semiconductor layer 24. It is understood that the current transport layer can be made of ITO, or it can be made of metals with good conductivity such as Al or Ag, and is not limited to these. If it is made of metal, it requires high transparency so that it will not block the light emitted upwards from the epitaxial light-emitting layer of the bottom first light-emitting unit 20 during operation. To achieve a balance between conductivity and transparency, the current transport layer at the center of the pixel can be made of ITO conductive layer, with the outer periphery made of metal.

[0063] In this embodiment, the P-type semiconductor layer 24 and the N-type semiconductor layer 23 may be formed of one or more layers of II-VI materials (such as ZnSe or ZnO) or III-V nitride materials (such as GaN, AlN, InN, InGaN, GaP, AlInGaP, AlGaAs and their alloys).

[0064] In this embodiment, the thickness of the P-type semiconductor layer 24 is 0.05 μm-0.5 μm, preferably 0.2 μm-0.35 μm. The P-type semiconductor layer 24 can be P-type GaN, for example, a P-type semiconductor layer 24 formed by doping GaN with elements such as magnesium or boron. In other embodiments, the P-type semiconductor layer 24 can also be P-type InGaN or P-type AlInGaP, etc., and no specific limitation is made here.

[0065] In this embodiment, the thickness of the N-type semiconductor layer 23 is 1 μm-5 μm, preferably 1.5 μm-3 μm. The N-type semiconductor layer 23 can be N-type GaN, for example, an N-type semiconductor layer 23 formed by doping GaN with elements such as phosphorus and arsenic. In other embodiments, the N-type semiconductor layer 23 can also be N-type GaN, N-type InGaN, N-type AlInGaP, etc., and no specific limitation is made here.

[0066] In this embodiment, the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22 are electrically connected to the anode metal electrode and the cathode metal electrode independently, thereby achieving the purpose of independently controlling the epitaxial light-emitting layer of the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22.

[0067] In this embodiment, the P-type semiconductor layer 24 is electrically connected to the anode metal electrode. As an example, a common anode driving electrode 304 is electrically connected to the anode metal electrode. The common anode driving electrode 304 is electrically connected to the first connecting electrode 11 through a filler metal. One end of the first connecting electrode 11 is located on the upper part of the common anode driving electrode 304, and the other end is partially located on the surface of the current extension layer 4 of the first light-emitting unit 20. The first connecting electrode 11 is electrically connected to a bonding interconnect electrode 7, which is electrically connected to the current extension layer 4 of the second light-emitting unit 21. An anode interconnect electrode 18 is provided between the second light-emitting unit 21 and the third light-emitting unit 22. The two ends of the anode interconnect electrode 18 are electrically connected to the current extension layer 4 of the second light-emitting unit 21 and the current extension layer 4 of the third light-emitting unit 22, respectively.

[0068] In this embodiment, the N-type semiconductor layers 23 of the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22 are electrically connected to the cathode metal electrodes. As an example, the cathode metal electrodes include a first cathode metal electrode, a second cathode metal electrode, and a third cathode metal electrode. A redistribution metal layer 2 is connected to each of the first, second, and third cathode metal electrodes. The three redistribution metal layers 2 are electrically connected to a first cathode driving electrode 301, a second cathode driving electrode 302, and a third cathode driving electrode 303, respectively. The first cathode driving electrode 301 is electrically connected to the N-type semiconductor layer 23 of the first light-emitting unit 20. The second cathode driving electrode 302 and the third driving cathode 303 are electrically connected to the N-type semiconductor layers 23 of the second light-emitting unit 21 and the third light-emitting unit 22, respectively, through a second connecting electrode 16 and a third connecting electrode 17. It should be noted that the redistribution metal layers 2 can be designed to accommodate the MicroLED chip according to the required application scenario. For example, in the field of MicroLED chips for AR applications, the required pixel positions can be rearranged. It is understandable that in other implementation cases, the redistribution metal layer 2 can be omitted, and the cathode metal electrode can be directly physically connected to the cathode drive electrode.

[0069] The common anode driving electrode 304 and the cathode driving electrode can be made of transparent conductive materials. For example, the cathode driving electrode can be made of conductive metal oxides such as ITO and ZnO, or conductive metal materials such as Cr, Ti, Pt, Au, Al, Cu, Ge or Ni. No specific restrictions are imposed here.

[0070] In this embodiment, a transflective layer 12 can be disposed on the surface of the P-type semiconductor layer 24 of the first light-emitting unit 20. The transflective layer 12 allows light emitted by the first light-emitting unit 20 to pass through, reflecting the light emitted by the second light-emitting unit 21 and the third light-emitting unit 22, and transmitting the light emitted by the first light-emitting unit 20. This ensures that the light emitted by the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 23 are all emitted outward, thereby improving the luminous efficiency of the device. Specifically, it is a DBR functional layer with a structure of 19nm TiO2 / (89nm SiO2 / 52nm TiO2 for 7 periods) / 63nm SiO2 / 66nm TiO2 / (73nm SiO2 / 42.5nm TiO2 for 8 periods) / 154nm SiO2. It can achieve a red light transmission and blue light reflection rate of over 90%, resulting in excellent performance in both efficiency and color gamut for the entire device.

[0071] In the epitaxial structure of LEDs, the thickness of the N-type semiconductor layer 23 is generally around 1.5 μm, the thickness of the P-type layer is around 0.3 μm, and the thickness of the epitaxial light-emitting layer is generally less than 0.11 μm. Therefore, if a stacked structure of three-color light-emitting units is used, the distance from the quantum well layer of different light-emitting units to the light-receiving structure varies significantly. This is especially problematic in the field of near-eye display AI AR glasses, where the distance between the glasses and the human eye is close, resulting in a noticeable "defocus" problem after the light converges, which reduces display quality and affects the user experience. In this embodiment, the P-type semiconductor layers 24 of the first light-emitting unit 20 and the second light-emitting unit 21 are positioned opposite each other and close to each other. The P-type semiconductor layer 24 and the epitaxial light-emitting layer of the third light-emitting unit 22 are basically at the same horizontal level as the corresponding functional layer of the second light-emitting unit 21, making the epitaxial light-emitting layers of the three colors closer together and effectively solving the "defocus" problem of the device.

[0072] In this embodiment, the N-type semiconductor located in the pixel edge region (i.e., the N-type semiconductor corresponding to the portion connected to the second connection electrode 16 and the third connection electrode 17) is partially thinned. The thinning thickness is approximately 1 / 5 to 2 / 3 of the N-type semiconductor thickness. Preferably, after filling the second and third connection electrodes, the height of the connection electrodes is the same as the thickness of the unthinned N-type semiconductor. This reduces the thickness of the POC adhesive used in the subsequent cover plate bonding process, which is more conducive to the chip's portability and improved light output efficiency. The ohmic contact layer in the current extension layer 4 below the corresponding position of the anode interconnect electrode is etched away, allowing the anode interconnect electrode to be directly connected to the current transport layer in the current extension layer. Since the current transport layer has better conductivity than the ohmic contact layer, it can improve the driving capability of the driving substrate for the device, thereby comprehensively improving the overall operating efficiency of the device.

[0073] In this embodiment, the cathode driving electrode is connected to the sidewall of each light-emitting unit and the N-type semiconductor layer 23 of the adjacent pixel through an insulating material to avoid short circuit between the P-type semiconductor and the N-type semiconductor, which would affect the function of the epitaxial layer in the pixel or even cause the pixel to fail, and also avoid the impact on adjacent pixels.

[0074] In this embodiment, a passivation layer 19 is provided on the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22. The passivation layer 19 is used to protect and isolate the LED units. The material of the passivation layer 19 can be SiO2, Al2O3, polyimide, photoresist, etc., and no specific limitation is made here. Finally, the cover glass is bonded with POC adhesive to protect the entire surface of the microdisplay chip. The above-mentioned MicroLED device chip can be used in the display field, especially in the microdisplay field. When the epitaxial layer is a functional layer with photoelectric conversion performance, it can also be used to form a camera chip for the field of camera technology.

[0075] Figures 1 to 21 A cross-sectional view of an illustrative MicroLED chip structure during the manufacturing process is shown, according to some embodiments of the present invention. Please refer to... Figures 1 to 21 The method for fabricating a MicroLED chip structure provided in this embodiment of the invention includes the following steps:

[0076] Step 1:

[0077] Please see Figure 1 A substrate 1 is provided, and a driving circuit is included inside the substrate 1. The driving circuit is connected to an anode driving via 104, a first cathode driving via 101, a second cathode driving via 102, and a third cathode driving via 103. The driving vias penetrate the substrate upward in the thickness direction of the substrate 1. A dielectric layer is deposited on the surface of the substrate 1, and after etching to remove the dielectric layer at the location of the driving vias, conductive electrodes are deposited.

[0078] Substrate 1 can be formed from semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, and indium phosphide. Alternatively, substrate 1 can be made from non-conductive materials such as glass, plastic, or sapphire wafers. In this embodiment, substrate 1 can be a CMOS backplane or a TFT glass substrate, etc. The driving circuit provides electrical signals to the LED units to control brightness. The driving circuit can include an active matrix driving circuit, where each individual LED unit is equivalent to an independent driver. In other embodiments, the driving circuit can also include a passive matrix driving circuit.

[0079] The dielectric layer can be made of silicon oxide, nitride, carbide, carbonitride, aluminum oxide, or other dielectric materials, with SiO2 being preferred. The thickness of the dielectric layer can be approximately 1 μm. The method for creating openings in the substrate 1 and the dielectric layer can be achieved through standard photolithography, etching processes, or other methods known to those skilled in the art.

[0080] The conductive electrode can be made of one or more materials such as Cu, Al, Au, Pt, Ti, Cr, Ag, Ta, and Ni, preferably a TiN / Ti / Al / Ti / TiN composite layer with thicknesses of approximately 6 / 20 / 260 / 10 / 4 nm. Ti and Al are commonly used materials in the semiconductor industry. Among them, Ti has better adhesion to substrate 1, while Al combines excellent conductivity with cost advantages.

[0081] After depositing the conductive electrode, a thinning operation can be performed to remove a portion of the conductive electrode. The thinning operation can include dry etching or wet etching operations, such as chemical mechanical polishing (CMP), etc. The thickness of the conductive electrode after the thinning process is approximately 500 nm, and the flatness is approximately 10 nm.

[0082] Step 2:

[0083] A metal layer with a thickness of 0.2-1 μm is deposited on the surface of the conductive electrode to form an anode metal electrode layer and a cathode metal electrode layer. The metal electrode layer is preferably a TiN / Ti / Al / Ti / TiN composite layer with a thickness of approximately 6 / 20 / 260 / 10 / 4 nm, respectively. Subsequently, a redistribution metal layer 2 is formed on the surface of the metal electrode layer by standard photolithography and etching processes.

[0084] Step 3: A photoresist layer is fabricated on the surface of the redistribution metal layer 2 using photolithography. Holes are made in the photoresist layer at the positions corresponding to the driving electrodes. A metal material with a thickness of 0.2-1.5 μm, preferably Cu, is deposited at the holes. After metal deposition, the photoresist layer is removed, and the metal on the photoresist surface is stripped off, thereby forming a cathode driving electrode (including a first cathode driving electrode 301, a second cathode driving electrode 302, and a third cathode driving electrode 303) and a common anode driving electrode 304 on the surface of the redistribution metal layer 2. The removal of the photoresist layer and surface metal can be achieved by direct stripping or other methods known to those skilled in the art.

[0085] Step 4:

[0086] A dielectric layer is deposited on the surface of substrate 1 until it extends approximately 0.2-3 μm above the cathode driving electrode.

[0087] Step 5:

[0088] After depositing the dielectric layer, a thinning operation can be performed to remove a portion of the dielectric layer, exposing the cathode driving electrode and the common anode driving electrode 304. The thinning operation can be performed using chemical mechanical polishing (CMP), achieving a flatness of approximately 2 nm.

[0089] Step 6:

[0090] Please see Figure 2a-1 An epitaxial substrate is provided, and an epitaxial structure on the surface of the epitaxial substrate is sequentially formed as an N-type semiconductor layer 23, a first epitaxial light-emitting layer 201, and a P-type semiconductor layer 24 to form a first light-emitting unit 20.

[0091] In this embodiment, the epitaxial substrate can be made of semiconductor materials such as silicon, sapphire, silicon carbide, gallium nitride, germanium, gallium arsenide, and indium phosphide. The P-type semiconductor layer 24 can be P-type GaN, for example, a P-type semiconductor layer 24 formed by doping GaN with elements such as magnesium and boron. In other embodiments, the P-type semiconductor layer 24 can also be P-type InGaN or P-type AlInGaP. The thickness of the first epitaxial light-emitting layer 201 is 0.05 μm to 0.5 μm, preferably 0.1 μm, and can have a single quantum well structure, a multi-quantum well structure, or an alternating stacked structure of well layers and barrier layers. The thickness of the N-type semiconductor layer 23 is 1 μm to 5 μm, preferably 1.5 μm to 3 μm. The N-type semiconductor layer 23 can be N-type GaN, for example, an N-type semiconductor layer 23 formed by doping GaN with elements such as phosphorus and arsenic. In other embodiments, the N-type semiconductor layer 23 can also be N-type GaN, N-type InGaN, N-type AlInGaP, etc.

[0092] Please see Figure 2a-2 A current spreading layer 4 is deposited on the surface of the P-type semiconductor layer 24. The current spreading layer 4 can be formed using ITO alone as both the ohmic contact layer and the current transport layer, or it can be formed using a composite layer, with each layer serving as both. The ohmic contact layer can be made of Ni / ITO, and the current transport layer can be made of metals such as Al / Ag / Au / Cu / Ta / Ti. The ohmic contact layer can be prepared by sputtering 0.01-1 μm of ITO followed by depositing 0.1-0.5 μm of Al as the current transport layer to form the current spreading layer 4. The thickness of the ohmic contact layer is approximately 0.1 μm, and the thickness of the current spreading layer 4 is approximately 0.3 μm.

[0093] A temporary bonding layer 5 with a thickness of 1-5 μm is spin-coated on the surface of the current spreading layer 4. The material of the temporary bonding layer 5 can be polyimide (PI), polydimethylsiloxane (PDMS), silsesquioxane (HSQ), divinylsiloxane-bis-benzocyclobutene (DVS-BCB), paraffin, etc., preferably polyimide (PI), with a thickness of about 3 μm.

[0094] Please see Figure 2a-3 A temporary substrate 8 is temporarily bonded to the first light-emitting unit 20 through a temporary bonding layer 5. The temporary substrate 8 can be made of materials such as Si, sapphire, SiC, GaN, or glass, with Si being preferred, as it is compatible with standard semiconductor processes.

[0095] Please see Figure 2a-4 The epitaxial substrate is removed using a wet etching process. Based on the designed product requirements, the N-type semiconductor layer 23 is isolated at appropriate locations to form the first isolation structure 9. The isolation can be achieved using a standard semiconductor ion implantation process, including H+ implantation. +He + N + O + F + Mg + Si + Or Ar + The properties of the N-type semiconductor layer 23 can be altered by ions, and a method of etching followed by filling with a dielectric layer can also be used. In this embodiment, the method of Ar+ ion implantation modification is preferred.

[0096] Please see Figure 2a-5 A dielectric layer 6 and bonding interconnect electrodes 7 are fabricated on the surface of the N-type semiconductor layer 23 using standard photolithography, CVD, PVD, and etching processes. The dielectric layer 6 can be made of materials such as SiCN, SiO2, or SiN, with a thickness of 10-1500 nm, preferably 100 nm SiCN. The interconnect electrodes 7 can be made of conductive metals such as Cu, Al, Ag, Au, Ti, Ta, or Ni, preferably Cu, with a thickness of 10-1500 nm, preferably 80 nm. After the dielectric layer 6 and bonding interconnect electrodes 7 are fabricated, they can be planarized using CMP processes, with the flatness controlled within 2 nm. It is understood that before depositing the dielectric layer 6 and bonding interconnect electrodes 7, the N-type semiconductor layer 23 can be thinned to 0.3-1 μm, preferably 0.7 μm, using CMP or etching processes.

[0097] Step 7:

[0098] Please see Figure 3 The substrate 1 and the temporary substrate 8 are bonded using a hybrid bonding process. Before bonding, the first cathode driving electrode 301 and the bonding interconnect electrode 7 need to be aligned. The size of the first cathode driving electrode 301 is selected based on the size of the first light-emitting unit 20. In this embodiment, the size of the first light-emitting unit 20 is 3 μm, and the size of the first cathode driving electrode 301 is approximately 0.5~2.5 μm, preferably 1.5 μm. The size of the bonding interconnect electrode 7 is slightly smaller than the size of the first cathode driving electrode 301.

[0099] Step 8:

[0100] Please see Figure 4 The temporary substrate 8 is removed by debonding through a debonding process.

[0101] Step 9:

[0102] Please see Figure 5 The functional layer outside the first light-emitting unit 20 is etched away by semiconductor standard photolithography and etching processes, and the functional layer of the corresponding first light-emitting unit on the surface of the common anode driving electrode 304 is etched simultaneously.

[0103] Step 10:

[0104] Please see Figure 6 The dielectric is filled using CVD technology to make it roughly flush with the current extension layer 4 of the first light-emitting unit 20. The surfaces of the first cathode driving electrode 301, the second cathode driving electrode 302, the third cathode driving electrode 303, and the common anode driving electrode 304 are etched using standard semiconductor photolithography and etching processes to expose the corresponding electrodes, and a portion of dielectric is reserved around the etched areas.

[0105] Step 11:

[0106] Please see Figure 7 Conductive metal is deposited at the etched locations using standard semiconductor processes such as PVD, etching, photolithography, and CMP to form a metal filling layer, and a first connecting electrode 11 is deposited at the corresponding location of the common anode driving electrode 304. The metal filling layer can be one or more of Cu, Al, Ag, Au, Ti, Ta, and Ni, preferably a TiN / Ti / Al composite layer, with thicknesses of approximately 6 / 20 / 3000 nm. The first connecting electrode 11 is preferably a TiN / Ti / Al / Ti / TiN composite layer with thicknesses of approximately 6 / 20 / 260 / 10 / 4 nm. Thus, the common anode driving electrode 304 and the first cathode driving electrode 301 are electrically connected to the P-type semiconductor layer 24 and the N-type semiconductor layer of the first light-emitting unit 20, respectively.

[0107] Step 12:

[0108] Please see Figure 8 A transflective functional layer 12 is deposited on the surface of the current extension layer 4 of the first light-emitting unit 20 using a PVD process. In this embodiment, the transflective functional layer 12 can specifically be a DBR functional layer, with a specific structure of 19nm TiO2 / (89nm SiO2 / 52nm TiO2 for 7 periods) / 63nm SiO2 / 66nm TiO2 / (73nm SiO2 / 42.5nm TiO2 for 8 periods) / 154nm SiO2. This achieves a red light transmission and blue light reflection rate exceeding 90%, resulting in excellent performance in both efficiency and color gamut for the entire device.

[0109] Step 13:

[0110] Please see Figure 9 A 0.1-0.5µm dielectric layer is deposited on the entire device surface using CVD technology and then planarized as the device bonding layer.

[0111] Step 14:

[0112] Please see Figure 10Conductive metal is deposited at the positions of the first cathode driving electrode 301, the second cathode driving electrode 302, the third cathode driving electrode 303, and the common anode driving electrode 304 through semiconductor standard photolithography, PVD, and etching processes until it is flush with the dielectric layer. The material of the conductive metal can be one or more of Cu, Al, Ag, Au, Ti, Ta, and Ni, with Cu being preferred.

[0113] Step 15:

[0114] Please see Figure 2b Another epitaxial substrate is provided, on which an N-type semiconductor layer 23, a second epitaxial light-emitting layer 211, and a P-type semiconductor layer 24 are sequentially deposited to form a second light-emitting unit 21. The manufacturing process of the second light-emitting unit 21 is similar to that of the first light-emitting unit 20. A current spreading layer 4 is deposited on the surface of the P-type semiconductor layer 24 of the second light-emitting unit 21. The current spreading layer 4 can be made of ITO alone as the ohmic contact layer and the current transport layer, or a composite layer can be used as the ohmic contact layer and the current transport layer respectively. The ohmic contact layer can be made of Ni / ITO material, and the transport layer 4 can be made of metals such as Al / Ag / Au / Cu / Ta / Ti. The ohmic contact layer can be prepared by sputtering 0.01-1 μm ITO and then depositing 0.1-0.5 μm Al as the current transport layer to jointly form the current spreading layer 4. The thickness of the ohmic contact layer is about 0.1 μm, and the thickness of the current transport layer is about 0.3 μm.

[0115] A dielectric layer 6 and bonding interconnect electrodes 7 are fabricated on the surface of the current spreading layer 4 using standard photolithography, CVD, PVD, and etching processes, respectively. Subsequently, a CMP process is used for planarization, with the flatness controlled within 2 nm. The dielectric layer 6 has a thickness of 10-1500 nm, and the interconnect electrodes can be made of one or more of Cu, Al, Ag, Au, Ti, Ta, and Ni, preferably Cu, with a thickness of 10-1500 nm, preferably 80 nm.

[0116] Please see Figure 11 The epitaxial substrate of the second light-emitting unit 21 is aligned and mixed-bonded with the substrate 1 in step 15, so that the bonding interconnect electrode 7 on the surface of the second light-emitting unit 21 is interconnected with the metal Cu deposited in step 15. At this point, the common anode driving electrode 304 is electrically connected to the P-type semiconductor layer 24 of the first light-emitting unit 20 and the second light-emitting unit 21.

[0117] Please see Figure 12 The epitaxial substrate of the second light-emitting unit 21 is removed. The method for removing the epitaxial substrate of the second light-emitting unit 21 can be achieved by direct peeling or other methods known to those skilled in the art.

[0118] Step 16:

[0119] Please see Figure 13 Based on the designed product requirements, the N-type semiconductor layer 23 of the second light-emitting unit 21 is isolated at the appropriate location to form a second isolation structure 14. The isolation can be achieved using a standard semiconductor ion implantation process, including H+ implantation. + He + N + O + F + Mg + Si + Or Ar + Ions and other substances can alter the properties of the original red epitaxial N-type semiconductor layer 23. Alternatively, a method of etching followed by filling with a dielectric layer can be employed, with Ar being the preferred choice. + Methods of ion implantation modification.

[0120] Step 17:

[0121] Please see Figure 14 The functional layer outside the second light-emitting unit 21 and the dielectric layer 6 on the surface of the second light-emitting unit 21 are etched away using semiconductor standard photolithography and etching processes.

[0122] Step 18:

[0123] Referring to Figure c-1, another epitaxial substrate is provided. An N-type semiconductor layer 23, a third epitaxial light-emitting layer 221, and a P-type semiconductor layer 24 are sequentially deposited on the surface of this substrate to form a third light-emitting unit 22. The fabrication process of the third light-emitting unit 22 is similar to that of the first light-emitting unit. A current spreading layer 4 is deposited on the surface of the P-type semiconductor layer 24 of the third light-emitting unit 22. The current spreading layer 4 can be made of ITO alone as both the ohmic contact layer and the current transport layer, or a composite layer can be used as both the ohmic contact layer and the current spreading layer. The ohmic contact layer can be made of Ni / ITO material, and the current transport layer can be made of metals such as Al / Ag / Au / Cu / Ta / Ti. The ohmic contact layer can be prepared by sputtering 0.01-1 μm ITO and then depositing 0.1-0.5 μm Al as the current transport layer to jointly form the current spreading layer 4. The thickness of the ohmic contact layer is approximately 0.1 μm, and the thickness of the current spreading layer 4 is approximately 0.3 μm.

[0124] A dielectric layer is fabricated on the surface of the current spreading layer 4 using CVD technology, followed by planarization using CMP technology, with flatness controlled within 2 nm. The thickness of the dielectric layer is 10-1500 nm, preferably 100 nm.

[0125] Please refer to Figure c-2. The functional layer in the area outside the third light-emitting unit 22, as well as the dielectric layer on the surface of the third light-emitting unit 22, are etched away using standard semiconductor photolithography and etching processes. Please refer to...Figure 15 The third light-emitting unit 22, which has undergone the above processing, is aligned and bonded to the substrate 1 in step 17.

[0126] Step 19:

[0127] Please see Figure 16a The epitaxial substrate of the third light-emitting unit 22 is peeled off using a substrate 1 peeling process. (See also...) Figure 16b The light-emitting functional layer on the surface of the adjacent region (0.05-1µm range at the edge) of the second light-emitting unit 21 and the third light-emitting unit 22 is etched away using standard semiconductor photolithography and etching processes. It is understood that before etching, the N-type semiconductor layer 23 can be thinned to 0.3-1µm, preferably 0.7µm, using CMP or etching processes.

[0128] Step 20:

[0129] Please see Figure 17a and Figure 17b The etched portions of steps 18 and 19 are filled with dielectric material by depositing a dielectric material using a CVD process. The dielectric material can be one or more of SiCN, SiO2, and SiN, with SiO2 being preferred. Then, the material is planarized using a CMP process, and the flatness is controlled within 2nm.

[0130] Step 21:

[0131] Please see Figure 18a and 18b The surfaces of the first cathode driving electrode 301, the second cathode driving electrode 302, the third cathode driving electrode 303, and the common anode driving electrode 304 are etched using standard semiconductor photolithography and etching processes to expose the corresponding driving electrodes. The dielectric material filled in step 21 is then etched to expose the current spreading layer 4 on the surfaces of the corresponding second light-emitting unit 21 and third light-emitting unit 22. It should be noted that a portion of the dielectric layer is reserved around the etched areas.

[0132] Step 22:

[0133] Please see Figure 19a and 19b The etched portion in step 21 is filled with metal. The metal can be one or more of Cu, Al, Ag, Au, Ti, Ta, and Ni. The filling height is approximately flush with the height of the N-type semiconductor layer 23 of the second light-emitting unit 21. Subsequently, planarization is performed using a CMP process, with the flatness controlled within 2 nm. Filling with metal enables the current spreading layer 4 of the third light-emitting unit 22 to be electrically connected to the current spreading layer 4 of the second light-emitting unit 21. The common anode driving electrode 304 can be electrically connected to the P-type semiconductor layer 24 of the third light-emitting unit 22 through the current spreading layer 4 of the second light-emitting unit 21.

[0134] Step 23:

[0135] Please see Figure 20 Metal is deposited at corresponding positions of the second cathode driving electrode 302 and the third cathode driving electrode 303 using standard semiconductor processes such as PVD, etching, and photolithography to form the second connecting electrode 16 and the third connecting electrode 17. The second connecting electrode 16 connects the second cathode driving electrode 302 and the N-type semiconductor layer 23 of the second light-emitting unit 21, and the third connecting electrode 17 connects the third cathode driving electrode 303 and the N-type semiconductor layer 23 of the third light-emitting unit 22. The second connecting electrode 16 and the third connecting electrode 17 are preferably TiN / Ti / Al / Ti / TiN composite layers with thicknesses of approximately 6 / 20 / 260 / 10 / 4 nm, respectively.

[0136] Step 24:

[0137] Please see Figure 21 A passivation layer 19 is formed on the N-type semiconductor layer 23 of the first light-emitting unit 20, the second light-emitting unit 21, and the third light-emitting unit 22 using a CVD process. The material of the passivation layer 19 can be SiO2, Al2O3, polyimide, photoresist, etc., with SiO2 being preferred, and the thickness is 0.2-1µm, preferably 0.5µm. After the passivation layer 19 is formed, it can be planarized using a CMP process, with the flatness controlled within 2nm. Finally, a cover glass is bonded to the entire surface of the microdisplay chip using POC adhesive to protect it. Alternatively, a microlens array can be fabricated on the surface of the passivation layer before bonding the cover glass to improve light output efficiency and color mixing uniformity. Microlens arrays are existing technology and will not be described in detail here.

[0138] The above-described process steps complete the fabrication of the stacked full-color Micro-LED device. It can be used in the display field, especially in micro-displays; when the epitaxial layer is a functional layer with photoelectric conversion properties, it can form a camera chip.

[0139] The MicroLED display chip provided in this embodiment of the invention adopts a two-color stacked structure. With the two-color stacked structure, another color is arranged in parallel. On the one hand, by reducing the vertical distance between the light-emitting layers, the "defocusing" problem is reduced, and the working effect of the device is improved. On the other hand, by adopting a two-color stacked structure, the size of the light-emitting unit that emits red light can be enlarged, thereby reducing the size effect of the entire device and improving the working efficiency of the entire device.

[0140] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A MicroLED display chip, characterized in that, include: Substrate; An LED semiconductor layer is disposed on the substrate. The LED semiconductor layer includes multiple LED units arranged in an array. Adjacent LED units can be driven independently. Each LED unit includes a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit that emit different colors of light. The first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are stacked in the thickness direction of the substrate. The second light-emitting unit and the third light-emitting unit are located above the first light-emitting unit, or the second light-emitting unit and the third light-emitting unit are located below the first light-emitting unit. The third light-emitting unit is located on the side of the second light-emitting unit.

2. The MicroLED display chip according to claim 1, characterized in that: The first light-emitting unit is closer to the substrate than the second light-emitting unit, and the third light-emitting unit is arranged in parallel with the second light-emitting unit.

3. The MicroLED display chip according to claim 2, characterized in that: The third light-emitting unit is a green light-emitting unit, and the first light-emitting unit is a red light-emitting unit.

4. The MicroLED display chip according to claim 1, characterized in that: Each of the three light-emitting units includes a P-type semiconductor layer, an epitaxial light-emitting layer, and an N-type semiconductor layer stacked sequentially. The thickness of the P-type semiconductor layer is 0.05μm-0.5μm, and the thickness of the N-type semiconductor layer is 1μm-5μm.

5. The MicroLED display chip according to claim 1, characterized in that: The size ratio of the second light-emitting unit and the third light-emitting unit along the length of the substrate is N:1, and the value of N ranges from 0.5 to 2.

6. The MicroLED display chip according to claim 4, characterized in that: The P-type semiconductor layers of the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are arranged opposite to each other.

7. The MicroLED display chip according to claim 1, characterized in that: The substrate is provided with a common anode driving electrode and three cathode driving electrodes. The common anode driving electrode is electrically connected to the P-type semiconductor layer of the three light-emitting units, and the three cathode driving electrodes are respectively electrically connected to the N-type semiconductor layer of the three light-emitting units.

8. The MicroLED display chip according to claim 1, characterized in that: A transflective layer is provided between the first light-emitting unit and the second light-emitting unit, and between the first light-emitting unit and the third light-emitting unit. The transflective layer is used to reflect the light emitted by the second light-emitting unit and the third light-emitting unit, and to transmit the light emitted by the first light-emitting unit.

9. The MicroLED display chip according to claim 7, characterized in that: Each of the three light-emitting units has a current spreading layer on its P-type semiconductor, and the common anode driving electrode is electrically connected to the P-type semiconductor layer through the current spreading layer.

10. A method for fabricating a MicroLED display chip, characterized in that: A substrate is provided, and a driving circuit is included inside the substrate. The driving circuit is connected to an anode driving via, a first cathode driving via, a second cathode driving via, and a third cathode driving via. The driving vias penetrate the substrate upward in the thickness direction. A first light-emitting unit is fabricated on the surface of the substrate using standard semiconductor processes. A second light-emitting unit and a third light-emitting unit are fabricated on the surface of the first light-emitting unit. The sum of the areas of the second light-emitting unit and the third light-emitting unit is equivalent to the area of ​​the first light-emitting unit.

Images