output circuit

Abstract

The present application relates to an output circuit. The present invention can suppress power consumption, does not cause adverse effects on gate drive, and quickly turns off the output transistor of the p-channel. The present invention includes: an output transistor (MP1) of the p-channel, whose drain is connected to an output terminal; a gate drive circuit (A1) that drives the gate voltage of the output transistor; and a pull-up transistor (NAT) of the n-channel, which is connected to the gate of the output transistor (MP1) and turns on to pull up the gate voltage when the output transistor turns off. The output transistor (MP1) is an enhancement type with a relatively high threshold voltage for turning on, and the pull-up transistor (NAT) is a natural type with a relatively low threshold voltage for turning on.

Description

Technical Field

[0001] This invention relates to an output circuit utilizing a p-channel output transistor. Background Technology

[0002] Output circuits that supply the output current from the output transistor to the load to drive the load are widely used. In this case, a p-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is sometimes used as the output transistor, supplying the output of the gate drive circuit to its gate.

[0003] When the source of a p-channel MOSFET is connected to a high-voltage power supply, disconnecting the p-channel MOSFET is generally achieved by pulling up its gate through a resistor or another p-channel MOSFET.

[0004] Figure 1 This diagram illustrates the configuration of a conventional output circuit. The output of the gate drive circuit A1 is supplied to the gate of the p-channel output transistor MP1. The source of the output transistor MP1 is connected to the power supply Vhv, and the drain of the output transistor MP1 is grounded through the load resistor RL, serving as the output terminal for the output voltage Vout. Furthermore, the gate of the output transistor MP1 is connected to the power supply Vhv through the pull-up resistor R1. Therefore, when the output transistor MP1 is turned off, if the output of the gate drive circuit A1 becomes high impedance, the gate of the output transistor MP1 will be pulled up by the pull-up resistor R1, thereby turning off the output transistor MP1. Summary of the Invention

[0005] [The problem the invention aims to solve]

[0006] When using pull-up resistor R1, if the resistance value of R1 is small, it will affect the circuit characteristics driving the gate of output transistor MP1. On the other hand, if the resistance value of pull-up resistor R1 is large, the turn-off time of output transistor MP1 will be longer.

[0007] Furthermore, if a pull-up resistor R1 is not used, but another p-channel transistor is used for pull-up, a voltage clamping circuit is required to protect the gate of the transistor. To achieve voltage clamping, current needs to flow through the resistor to generate a clamping voltage, which will cause drawbacks in any of the following aspects: operating characteristics, turn-off speed, and current consumption during turn-off.

[0008] [Technical means to solve the problem]

[0009] The output circuit of this invention includes:

[0010] The output transistor of the p-channel has its drain connected to the output terminal;

[0011] A gate driving circuit drives the gate voltage of the output transistor; and

[0012] The n-channel pull-up transistor is connected to the gate of the output transistor, and is turned on when the output transistor is off to pull up the gate voltage; and

[0013] The output transistor is an enhancement-type transistor connected to a relatively high general-purpose threshold voltage.

[0014] The pull-up transistor is a natural type connected to a general threshold voltage that is relatively low.

[0015] [The effects of the invention]

[0016] The output circuit according to the present invention can suppress power consumption, avoid adverse effects on gate drive, and quickly disconnect the output transistor of the p-channel. Attached Figure Description

[0017] Figure 1 This is a circuit diagram showing the configuration of a conventional output circuit.

[0018] Figure 2 This is a circuit diagram showing the configuration of the output circuit in the implementation method.

[0019] Figure 3 This is an explanation Figure 2 The timing diagram of the circuit operation. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, the embodiments shown below do not limit the present invention, and configurations selectively combined from multiple examples are also included in the present invention.

[0021] Circuit Structure

[0022] Figure 2 This is a circuit diagram showing the configuration of the output circuit in the implementation method.

[0023] Output transistor MP1 supplies drive current to the load resistor RL. MP1 is a p-channel MOSFET with its source connected to the high-voltage power supply Vhv and its drain grounded via the load resistor RL. The drain of MP1 is the output terminal for the output voltage Vout.

[0024] The gate of the output transistor MP1 is connected to the output terminal of the gate drive circuit A1. For example, the gate drive circuit A1 is composed of an operational amplifier, etc., and performs feedback control of the gate drive voltage to make the output voltage Vout the target voltage. Furthermore, the gate drive circuit A1 starts or stops operating via the signal EN. When the gate drive circuit A1 is off, its output terminal becomes a high-impedance state.

[0025] The gate of the output transistor MP1 is connected to the source of the n-channel pull-up transistor NAT, whose drain is connected to the high-voltage power supply Vhv. Here, the pull-up transistor NAT is a natural n-channel MOSFET with a threshold voltage of -0.3V to +0.1V. In addition, the threshold voltage of a typical enhancement-mode MOSFET is 0.5V to 1.0V.

[0026] Additionally, one end of resistor R3 is connected to the high-voltage power supply Vhv, and the other end is grounded via the n-channel transistor MN2. The gate of transistor MN2 is supplied with the signal EN. When the signal EN is high (EN = H), transistor MN2 is turned on; when the signal EN is low (EN = L), transistor MN2 is turned off. Furthermore, regarding the current source for the current Ibias, only transistor MN2 is shown in the figure; transistor MN2 can be considered as the transistor carrying the final segment of the current source.

[0027] The source of the pull-up transistor NAT is connected to the gate of the n-channel protection transistor MN1. The drain of the protection transistor MN1 is connected to the high-voltage power supply Vhv, and the source is connected to the junction of resistor R3 and transistor MN2. Therefore, when the protection transistor MN1 is on, the voltage difference between the gate of the output transistor MP1 and the gate of the pull-up transistor NAT is maintained at the threshold voltage Vth of the protection transistor MN1.

[0028] Furthermore, the connection point between resistor R3 and transistor MN2 is connected to the gate of pull-up transistor NAT. Therefore, when transistor MN2 is on, the current flowing through transistor MN2 flows to resistor R3, applying a voltage that has been stepped down by resistor R3 from the high-voltage power supply Vhv to the gate of pull-up transistor NAT. On the other hand, when transistor MN2 is off, the gate of pull-up transistor NAT becomes the voltage of the high-voltage power supply Vhv via resistor R3.

[0029] In addition, the output transistors MP1, MN1, and MN2, other than the pull-up transistor NAT, are enhancement MOSFETs.

[0030] "Circuit operation"

[0031] Figure 3 This is an explanation Figure 2 The timing diagram of the circuit operation.

[0032] Transistor MN2 and gate drive circuit A1 are switched on or off in conjunction with the high level (EN=H) or low level (EN=L) of signal EN.

[0033] When EN = H, transistor MN2 is turned on, and current Ibias flows. Therefore, the gate voltage of pull-up transistor NAT becomes a voltage lower than the voltage drop across resistor R3 by the high-voltage supply Vhv. The source voltage of pull-up transistor NAT is only slightly higher than the gate-source voltage Vgs of protection transistor MN1. Therefore, the gate-source voltage Vgs_NAT of pull-up transistor NAT becomes a specified negative voltage (e.g., -0.8V), and pull-up transistor NAT is turned off.

[0034] The gate (MP1_gate) of the output transistor MP1 is controlled by the gate drive circuit A1 to set the output voltage Vout of the output transistor MP1 to a specified value (e.g., 5V) that is lower than the high voltage power supply Vhv.

[0035] Moreover, the output voltage Vout, as described above, is the target voltage (e.g., 5V) determined by the gate drive circuit A1.

[0036] Here, the voltage drop across resistor R3 can be adjusted by changing the current Ibias of transistor MN2. In one example, a maximum voltage of 8V is generated across resistor R3. Because of the protection transistor MN1, the gate voltage of pull-up transistor NAT is maintained at a level lower than the gate voltage of output transistor MP1 by the gate-source voltage Vgs of protection transistor MN1. That is, the voltage relationship becomes NAT_gate = MP1_gate - Vgs, and NAT_gate is clamped to prevent it from dropping too low by the protection transistor MN1. Furthermore, the gate-source voltage Vgs of protection transistor MN1 in the ON state is equal to its threshold voltage Vth.

[0037] Secondly, when EN = L, the output of the gate drive circuit A1 becomes high impedance. Additionally, the current Ibias of transistor MN2 is disconnected. Therefore, resistor R3 no longer reduces the voltage, and the gate of pull-up transistor NAT, NAT_gate, quickly rises to the high-voltage supply voltage Vhv. Consequently, the gate-source voltage Vgs of pull-up transistor NAT becomes 0V to 0.1V.

[0038] The threshold voltage of the pull-up transistor NAT is -0.3V to +0.1V. When the pull-up transistor NAT is turned on, the gate of the output transistor MP1 is pulled up to the voltage of the high-voltage power supply Vhv (e.g., 15V), and the gate-source voltage Vgs of the output transistor MP1 becomes 0V to 0.1V. The output transistor MP1 is then quickly turned off. Therefore, the output voltage Vout also becomes 0V.

[0039] As described above, in this embodiment, the output transistor MP1 can be turned off without consuming current from the high-voltage power supply Vhv. Furthermore, during the turn-off process, the pull-up transistor NAT operates as a source follower, thus enabling the output transistor MP1 to be turned off very quickly.

[0040] When EN = H and the circuit operates in its normal state, the gate of the output transistor MP1 is driven to a minimum of (Vhv - |max.Vgs|). |max.Vgs| is the maximum permissible gate-source voltage of the output transistor MP1.

[0041] Furthermore, the values ​​of current Ibias and R3 are determined such that Ibias × R3 is slightly larger than |max.Vgs_p|, thereby ensuring that the gate voltage of the pull-up transistor NAT is always smaller than the gate voltage of the output transistor MP1. Furthermore, in Figure 2 In the circuit, the gate voltage of the pull-up transistor NAT is prevented from dropping too low and being damaged by the protection transistor MN1.

[0042] When the output transistor MP1, which is a p-channel MOSFET, is turned off using the circuit of this embodiment, the following three items can be achieved.

[0043] (1) Make the current consumption of the output transistor MP1 in the off state zero.

[0044] (2) Quickly disconnect the output transistor MP1.

[0045] (3) When the output transistor MP1 is driven in a normal manner, the circuit used to pull up the output transistor MP1 will not have an adverse effect on the gate drive of the output transistor MP1.

[0046] [Explanation of Symbols]

[0047] A1: Gate drive circuit

[0048] MN1: Protective transistor

[0049] MP1: Output transistor

[0050] NAT: Pull-up transistor

[0051] R1: Pull-up resistor

[0052] Vhv: High voltage power supply.

Claims

1. An output circuit comprising: The output transistor of the p-channel has its drain connected to the output terminal; A gate driving circuit that drives the gate voltage of the output transistor; and An n-channel pull-up transistor is connected to the gate of the output transistor and is turned on when the output transistor is off to pull up the gate voltage. The output transistor is an enhanced type with a relatively high threshold voltage for turn-on. The pull-up transistor is a natural type with a relatively low threshold voltage for turn-on.

2. The output circuit according to claim 1, wherein... The drain of the pull-up transistor is connected to a high-voltage power supply, the source of the pull-up transistor is connected to the gate of the output transistor, and the gate of the pull-up transistor is connected to the junction of a resistor and a current source connected to the high-voltage power supply.

3. The output circuit according to claim 2, further comprising: An n-channel enhancement-mode protection transistor, wherein the gate of the n-channel enhancement-mode protection transistor is connected to the gate of the output transistor, its drain is connected to the high-voltage power supply, and its source is connected to the junction of the resistor and the current source.

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