Circuits and methods for combining multiple clock sources to improve phase noise
By combining multiple clock sources and optimizing the signal-to-noise gain ratio, the problem of insufficient noise performance of traditional clock sources is solved, thereby improving the clock signal-to-noise ratio and phase noise, making it suitable for radar, communication, and high-speed data conversion systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- JOYWELL SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2025-08-19
- Publication Date
- 2026-06-12
AI Technical Summary
Traditional clock sources have poor in-band and out-of-band phase noise performance that fails to meet the requirements of high-performance systems, and existing methods are costly and limited in size.
By combining multiple clock sources, multiple clock sources with essentially the same frequency, amplitude, and phase are generated and connected to the load circuit through a matching network. The signal-to-noise ratio performance of the clock is improved by optimizing the signal-to-noise ratio using a phase-locked loop and a matching network.
It significantly improves the phase noise performance of the clock and enhances the overall performance of the system. Theoretically, it can improve the performance by 10×log(N)dB, and actual tests have verified its effectiveness.
Smart Images
Figure CN121012494B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a circuit and method for improving phase noise by combining multiple clock sources. Background Technology
[0002] In systems such as radar, communication, and high-speed data conversion, the phase noise performance of the clock source directly affects the overall system performance. For example, in next-generation gigabit sampling rate analog-to-digital converters (Gsps ADCs), clock jitter noise significantly reduces the effective number of bits (ENOB) and signal-to-noise ratio (SNR) of the analog-to-digital conversion, thus limiting system performance. There is an endless pursuit of improving the phase noise performance of clock and local oscillator clock sources in critical radar and communication systems.
[0003] Traditional clock sources typically employ frequency synthesizers or phase-locked loops (PLLs) to generate the desired frequency. However, the in-band and out-of-band phase noise performance of a single clock source often falls short of the requirements of high-performance systems. Common approaches to improve noise characteristics include refining crystal or resonant cavity designs to reduce phase noise and thus improve the clock source's quality factor (Q), but these methods are costly and size-constrained. Therefore, this invention proposes a circuit structure that combines multiple clock sources to significantly improve phase noise performance. Summary of the Invention
[0004] The purpose of this application is to provide a circuit and method for improving phase noise by combining multiple clock sources. By combining multiple clock sources, the phase noise of the clock is improved, thereby improving the overall performance of the system.
[0005] In a first aspect, this application provides a circuit for improving phase noise by combining multiple clock sources, comprising:
[0006] Reference clock source for phase-locked loop;
[0007] A clock generator that generates multiple clock sources with substantially the same frequency, amplitude, and phase based on the reference clock source;
[0008] Multiple phase-locked loops, each receiving a clock source, each phase-locked loop having R Source The output impedance; and
[0009] The matching network includes multiple first resistors matched one-to-one with the plurality of phase-locked loops and a second resistor matched with the load, the load having R Load impedance;
[0010] Among them, according to Calculate the resistance value of the first resistor, and according to Calculate the resistance value of the second resistor; where R1 represents the resistance value of the first resistor, R2 represents the resistance value of the second resistor, and N represents the number of the plurality of clock sources.
[0011] In a preferred embodiment, the clock generator employs a clock driver or a clock power divider.
[0012] In a preferred embodiment, the phase-locked loop and the load have equal impedances, and a... Calculate the resistance values of the first resistor and the second resistor.
[0013] In a preferred embodiment, if the reference clock source or clock source is a differential signal, the circuit further includes a converter for converting one or more of the reference clock source or multiple clock sources into a single-ended signal, the converter being disposed between the reference clock source and the clock generator, between the clock generator and the phase-locked loop, between the phase-locked loop and the matching network, or between the matching network and the load.
[0014] In a preferred embodiment, if the reference clock source or multiple clock sources are differential signals, one end of the differential signal is connected to the various components of the circuit, and the other end is grounded through a matching resistor, so as to convert the differential signal into a single-ended signal.
[0015] In a preferred embodiment, the plurality of phase-locked loops have the same circuit structure and function.
[0016] In a preferred embodiment, each phase-locked loop includes a delay adjustment circuit for adjusting the phase of the clock source to align the clock source output by the phase-locked loop with the rising edge of the received clock source.
[0017] In a preferred embodiment, each phase-locked loop includes an amplitude adjustment circuit for adjusting the amplitude of the clock source to match the amplitude of the clock source output by the phase-locked loop with the amplitude of the received clock source.
[0018] In a preferred embodiment, the value of N ranges from 2 to 10.
[0019] In a second aspect, this application provides a circuit for improving phase noise by combining multiple clock sources, comprising:
[0020] A reference clock source is used for the phase-locked loop, and multiple clock sources with essentially the same frequency, amplitude, and phase as the reference clock source are generated.
[0021] Each of the plurality of clock sources is provided to one of a plurality of phase-locked loops, wherein the plurality of phase-locked loops have the same circuit structure and function;
[0022] The outputs of the plurality of phase-locked loops are connected to the load via a matching network; and
[0023] The resistance value of the matching resistor in the matching network is calculated based on the output impedance of the phase-locked loop, the impedance of the load, and the number of the plurality of clock sources.
[0024] In a preferred embodiment, the matching network includes a plurality of first resistors matched one-to-one with the plurality of phase-locked loops and a second resistor matched with the load, wherein according to Calculate the resistance value of the first resistor, and according to Calculate the resistance value of the second resistor; where R1 represents the resistance value of the first resistor, R2 represents the resistance value of the second resistor, N represents the number of the plurality of clock sources, R Source R represents the impedance of the phase-locked loop. Load This represents the impedance of the load.
[0025] In a preferred embodiment, the plurality of clock sources are generated based on the reference clock source by a clock driver or a clock power divider.
[0026] Compared with the prior art, this application has at least the following beneficial effects:
[0027] This application improves the phase-locked loop (PLL) performance by replicating the reference clock provided to the PLL into multiple identical clock sources and supplying them to PLLs with the same structure and function, connecting them to the load circuit via a matching network. Combining multiple clock sources results in a signal enhancement that is greater than the noise increase, leading to a net improvement in the clock's signal-to-noise ratio (SNR) and thus its phase noise performance.
[0028] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description
[0029] Figure 1 This is the theoretical total power and phase difference relationship between two clock signals with equal amplitude but a phase difference, according to one embodiment of this application.
[0030] Figure 2 A schematic diagram of a circuit that combines multiple clock sources to improve phase noise is shown in one embodiment of this application.
[0031] Figure 3 It shows Figure 2 A schematic diagram of the matching network structure of the circuit for improving phase noise.
[0032] Figure 4 A schematic diagram of a circuit that combines two clock sources to improve phase noise is shown in one embodiment of this application.
[0033] Figure 5 The test results for the phase noise of the PLL with two clock sources and the circuit with the two clock sources combined are shown.
[0034] Figure 6 A flowchart illustrating a method for improving phase noise by combining multiple clock sources according to one embodiment of this application is shown. Detailed Implementation
[0035] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0036] The following is a brief summary of some of the innovative aspects of the embodiments of this application:
[0037] This application generates multiple clock sources with essentially the same frequency, amplitude, and phase based on a single reference clock. These sources drive multiple phase-locked loops (PLLs) respectively, and the outputs are then synthesized through a matching network. This ensures that the signal amplitude gain exceeds the noise increase, thereby improving the clock signal-to-noise ratio (SNR) and reducing phase noise. Theoretically, the improvement reaches 10 × log(N) dB, and the effectiveness of this invention has been verified through actual testing.
[0038] Furthermore, a matching network consisting of multiple first resistors and one second resistor was designed, and a precise calculation formula based on the phase-locked loop impedance, load impedance, and number of clock sources was proposed. This matching network ensures input / output impedance matching after signal synthesis, reduces reflection and loss, and enhances system stability.
[0039] Each phase-locked loop (PLL) has the same structure and function, and integrates delay and amplitude adjustment circuits to ensure phase and amplitude consistency of the multiple output signals, thus solving the problem of superposition distortion caused by phase / amplitude inconsistency in traditional multi-channel synthesis schemes. Furthermore, for the differential reference clock, it can be converted to a single-ended signal via a balun or directly taken as a single-ended signal and grounded through a matching resistor, thereby improving system compatibility and facilitating integration on various hardware platforms.
[0040] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0041] One embodiment of this application relates to a circuit for improving phase noise by combining multiple clock sources, the structure of which is shown in the figure. The structure includes a reference clock source for a phase-locked loop (PLL), a clock generator, multiple PLLs, and a matching network. The reference clock source is coupled to the clock generator, which generates multiple clock sources with substantially the same frequency, amplitude, and phase based on the reference clock source. The clock generator is coupled to each PLL, and each PLL receives one clock source. Each PLL has an Rn. Source The output impedance is [not specified]. Multiple phase-locked loops (PLLs) are coupled to a matching network, which includes multiple first resistors matched one-to-one with each PLL and a second resistor matched to the load, which has an R [not specified]. Load The impedance. In a preferred embodiment, the value of N ranges from 2 to 10, for example, preferably from 2 to 5.
[0042] It should be noted that multiple phase-locked loops (PLLs) share the same structure and function. Each PLL includes a delay adjustment circuit to regulate the phase of the clock source, aligning the PLL output clock source with the rising edge of the received clock source. Each PLL also includes an amplitude adjustment circuit to regulate the amplitude of the clock source, ensuring it matches the amplitude of the received clock source. Through delay and amplitude adjustment, multiple clock sources can maintain as consistent a phase and amplitude as possible after passing through their respective PLLs.
[0043] In this application, the reference clock source can be a single-ended signal or a differential signal. If it is a single-ended signal, the circuit structure does not need to be adjusted. If the reference clock source or multiple clock sources are differential signals, the circuit for improving phase noise further includes a converter, which is used to convert one or more of the reference clock source or multiple clock sources into a single-ended signal. The converter is located between the reference clock source and the clock generator, between the clock generator and the phase-locked loop, between the phase-locked loop and the matching network, or between the matching network and the load, and can be configured according to the actual situation of the circuit. In one embodiment, the converter can use a balun conversion method for conversion.
[0044] In other embodiments, such as when the reference clock source or multiple clock sources are differential signals, one end of the differential signal is connected to the various components of the circuit, and the other end is grounded through a matching resistor. That is, instead of converting the differential signal to a single-ended signal through a converter, only one signal of the differential signal is used, while the other signal is grounded through a matching resistor (e.g., a 50Ω matching resistor). This method is equivalent to converting the differential signal to a single-ended signal.
[0045] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.
[0046] First, consider the scenario of combining only two clock sources. Since the signals are correlated, they have equal amplitude and phase. This will boost the signal by 6dB. Since the noise is random and uncorrelated, there are random amplitude and phase differences between the two clock source noise signals. The combined incoherent noise increases by an average of 3dB. Overall, the signal-to-noise ratio (SNR) performance is improved by a net 3dB. Therefore, combining N clock sources together can theoretically yield a gain of 10×log(N).
[0047] Even if the phases of the two clock source signals in the combination are not perfectly synchronized, most of the phase noise advantage can still be achieved. Two signals with the same amplitude and frequency but a phase error of θ have an output power of 10×log[2+2×cos(θ)]. The output power reaches its maximum when θ is zero degrees. Even if θ deviates from a very small value, the increase in output power is still close to the maximum benefit.
[0048] Figure 1 The relationship between the theoretical total power and phase difference when combining two clock signals with a phase difference is shown. The ideal phase noise amplitude loss is only 0.3 dB when the phase error reaches 30 degrees. Combiners may have losses, but these apply to both the signal and the noise and therefore do not affect the phase noise. Since jitter is proportional to the square root of the phase noise, this means that combining two combiners can reduce jitter. This is equivalent to a reduction of approximately 30%.
[0049] Figure 2 This demonstrates a general approach to combining multiple clock sources to achieve better phase noise. It assumes that a clean reference clock with phase noise lower than that of the clock sources and clock drivers is available from the outset. Starting from this reference source, it is necessary to distribute this reference source as input to multiple clock sources and combine these multiple clock sources into a single output to the load.
[0050] This reference source can be assigned to the input of multiple clock sources using a clock driver, which is a device that completes one clock input and multiple clock outputs. However, the multiple clock outputs have different delays, resulting in phase differences. Typically, this delay difference is on the picosecond level and is adjustable and controllable throughout the entire link.
[0051] This reference source can also be assigned to the input of multiple clock sources using a resistive power divider, which is a circuit structure consisting only of passive components such as resistors. This structure can provide smaller delay differences and does not increase noise, but one drawback is that if too many clock sources are to be driven, the slew rate will be reduced, thereby degrading the noise of the phase-locked loop.
[0052] Phase-locked loop (PLL) clock sources are recommended to support zero input / output delay (or adjustable output delay) and adjustable output signal amplitude, so as to fine-tune the delay and amplitude of the two clock source outputs to obtain the best signal-to-noise ratio.
[0053] In most cases, combining or separating single-ended signals is much easier than combining differential signals. If it is a differential signal, a balun can be used for conversion, or only one end can be used, with the other end undergoing appropriate matching.
[0054] Figure 3 This is a general circuit diagram using a resistor matching network. Among them, according to... Calculate the resistance of a resistor, and based on... Calculate the resistance value of the second resistor. Where R1 represents the resistance value of the first resistor, R2 represents the resistance value of the second resistor, and N represents the number of clock sources (i.e., the number of phase-locked loops). Furthermore, when the output impedance of the phase-locked loop is equal to the impedance of the load, the following is used: Calculate the resistance values of the first resistor and the second resistor.
[0055] The following section presents a test of the phase noise of the circuit after merging two clock sources. The test configuration is as follows:
[0056] 1. The reference clock frequency is 100MHz.
[0057] 2. The clock source phase-locked loop chip is LMX2594.
[0058] 3. The output frequency is 9GHz.
[0059] Table 1 and Figure 5 The test results for the phase noise of the PLL with two clock sources and the circuit after merging the two clock sources are shown. It can be seen that the phase noise at different frequencies of the merged circuit is improved, and the jitter performance is also improved.
[0060] Table 1 Phase noise test results
[0061]
[0062]
[0063] This application also provides a method for improving phase noise in its embodiments. A flowchart of this method is shown below. Figure 6 As shown, it includes the following steps:
[0064] Step 101: Provide a reference clock source for the phase-locked loop and generate multiple clock sources with substantially the same generation frequency, amplitude, and phase as the reference clock source.
[0065] Step 102: Provide multiple clock sources to one of multiple phase-locked loops, wherein the multiple phase-locked loops have the same structure and function.
[0066] Step 103: Connect the outputs of multiple phase-locked loops to the load through a matching network.
[0067] Step 104: Calculate the resistance value of the matching resistor in the matching network based on the output impedance of the phase-locked loop, the impedance of the load, and the number of multiple clock sources.
[0068] Specifically, the matching network includes multiple first resistors that are matched one-to-one with multiple phase-locked loops and a second resistor that is matched with the load. Wherein, according to... Calculate the resistance value of the first resistor, and according to... Calculate the resistance value of the second resistor. Where R1 represents the resistance value of the first resistor, R2 represents the resistance value of the second resistor, N represents the number of clock signal sources, and R... Source R represents the impedance of the phase-locked loop. Load This represents the impedance of the load.
[0069] In summary, this application replicates the reference clock provided to the phase-locked loop (PLL) into multiple identical clock sources, each of which is provided to a structurally identical PLL. These multiple PLLs are connected to the load circuit via a matching network. Combining multiple clock sources results in a signal enhancement that is greater than the noise increase, leading to a net improvement in the overall signal-to-noise ratio (SNR) of the clock and thus improving its phase noise performance.
[0070] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.
[0071] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.
[0072] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.
[0073] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.
Claims
1. A circuit for improving phase noise by combining multiple clock sources, characterized in that, include: Reference clock source for phase-locked loop; A clock generator that generates multiple clock sources with substantially the same frequency, amplitude, and phase based on the reference clock source; a plurality of phase-locked loops, each phase-locked loop receiving a clock source, each phase-locked loop having an output impedance, wherein the clock source output by each phase-locked loop is adjusted to align with a rising edge of the received clock source, and the amplitude of the clock source output by each phase-locked loop is adjusted to conform to the amplitude of the received clock source; and a matching network comprising a plurality of first resistors matched one-to-one with the plurality of phase-locked loops and a second resistor matched with a load, the load having an impedance; Among them, according to Calculate the resistance value of the first resistor, and according to Calculate the resistance value of the second resistor; where, This indicates the resistance value of the first resistor. The value of the second resistor is represented by , and N represents the number of the plurality of clock sources.
2. The circuit as described in claim 1, characterized in that, The clock generator employs a clock driver or a clock power divider.
3. The circuit as described in claim 1, characterized in that, The phase-locked loop and the load have equal impedances, and adopt... Calculate the resistance values of the first resistor and the second resistor.
4. The circuit as described in claim 1, characterized in that, If the reference clock source or clock source is a differential signal, the circuit further includes: a converter, the converter being used to convert one or more of the reference clock source or multiple clock sources into a single-ended signal, the converter being disposed between the reference clock source and the clock generator, between the clock generator and the phase-locked loop, between the phase-locked loop and the matching network, or between the matching network and the load.
5. The circuit as described in claim 1, characterized in that, If the reference clock source or multiple clock sources are differential signals, one end of the differential signal is connected to each component of the circuit, and the other end is grounded through a matching resistor, so as to convert the differential signal into a single-ended signal.
6. The circuit as described in claim 1, characterized in that, The multiple phase-locked loops have the same circuit structure and function.
7. The circuit as described in claim 1, characterized in that, Each phase-locked loop includes a delay adjustment circuit that adjusts the phase of the clock source to align the clock source output by the phase-locked loop with the rising edge of the received clock source.
8. The circuit as described in claim 1, characterized in that, Each phase-locked loop includes an amplitude adjustment circuit for adjusting the amplitude of the clock source to match the amplitude of the clock source output by the phase-locked loop with the amplitude of the received clock source.
9. A method for improving phase noise by combining multiple clock sources, characterized in that, include: Provide a reference clock source for the phase-locked loop, and generate multiple clock sources that have substantially the same generation frequency, amplitude, and phase as the reference clock source; Each of the plurality of clock sources is provided to one of a plurality of phase-locked loops, wherein the plurality of phase-locked loops have the same circuit structure and function; The outputs of the plurality of phase-locked loops are connected to the load via a matching network, wherein the clock source of each phase-locked loop output is adjusted to align with the rising edge of the received clock source, and the amplitude of the clock source of each phase-locked loop output is adjusted to match the amplitude of the received clock source; and The resistance value of the matching resistor in the matching network is calculated based on the output impedance of the phase-locked loop, the impedance of the load, and the number of the plurality of clock sources; The matching network includes multiple first resistors that are matched one-to-one with the plurality of phase-locked loops and a second resistor that is matched with the load, wherein according to Calculate the resistance value of the first resistor, and according to Calculate the resistance value of the second resistor; where, This indicates the resistance value of the first resistor. This represents the resistance value of the second resistor, and N represents the number of the plurality of clock sources. This represents the impedance of the phase-locked loop. This represents the impedance of the load.