Phase-locked loop, imaging device, and electronic circuit

Abstract

The present invention enables reduction of jitter while suppressing an increase in the circuit scale of a phase-locked loop.　This phase-locked loop comprises: a sample-and-hold circuit that subsamples an input signal on the basis of a reference signal; a voltage-to-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-to-digital converter that detects the time difference converted by the voltage-to-time converter; a first selector that switches between input of the time difference converted by the voltage-to-time converter and input of the reference signal and the input signal into the time-to-digital converter; and an offset correction unit that corrects, on the basis of the output of the time-to-digital converter, an offset based on the switching by the first selector.

Description

Phase synchronization circuit, imaging device, and electronic circuit 【0001】 The present technology relates to a phase synchronization circuit, an imaging device, and an electronic circuit. Specifically, the present technology relates to a phase synchronization circuit, an imaging device, and an electronic circuit in which an AD PLL (All Digital PLL) is used. 【0002】 In an AD PLL, the phase difference (time difference) between a reference clock and the output signal of a DCO (Digitally Control Oscillator) is detected in the time domain by a TDC (Time to Digital Converter). For example, a digital PLL circuit provided with a sample-and-hold circuit that samples the phase difference between the output signal of the DCO and the reference signal as a voltage has been proposed (see, for example, Patent Document 1). 【0003】 Japanese Patent Application Laid-Open No. 2016-140021 【0004】 However, in the above-described conventional technology, in order to reduce jitter, subsampling using an ADC (Analog to Digital Converter) is performed. Therefore, in the above-described conventional technology, there is a risk of an increase in circuit scale and power consumption. 【0005】 The present technology has been created in view of such a situation, and an object thereof is to be able to reduce jitter while suppressing an increase in the circuit scale of the phase synchronization circuit. 【0006】This technology was developed to solve the aforementioned problems, and its first aspect is a phase-locking circuit comprising: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal to the time-digital converter; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter. This achieves both an expansion of the lock range of the phase-locking circuit and an improvement in the time resolution, while setting the time resolution of the input signal based on the voltage resolution of the input signal and reducing the phase error based on switching between normal mode and subsampling mode. 【0007】 Furthermore, in the first aspect, the offset correction unit may include a holding unit that holds the output of the time digital converter as the offset, a second selector that switches between the offset and 0 and outputs it, a first arithmetic unit that subtracts the output of the second selector from the output of the time digital converter, and a third selector that switches between the output of the first arithmetic unit and 0 and outputs it. This results in the effect that the offset based on the switching between normal mode and subsampling mode is corrected based on the output of the time digital converter. 【0008】Furthermore, in the first aspect, the system may include a digital control oscillator that generates the input signal, an accumulator that sets a count-up value for each period of the reference signal based on an FCW (Frequency Command Word), a counter that counts up for each period of the input signal, a second arithmetic unit that subtracts the output of the counter and the output of the third selector from the output of the accumulator, and a loop filter that band-limits the input to the digital control oscillator. This results in the configuration of a phase-locked loop using a time-domain ADC while adjusting the frequency of the input signal based on the control of a digital code input to the digital control oscillator voltage. 【0009】 Furthermore, in the first aspect, the sample-and-hold circuit, the voltage-time converter, and the time-digital converter may constitute a time-domain ADC (Analog to Digital Converter). This results in the time resolution of the input signal being set based on the AD conversion. 【0010】 Furthermore, in the first aspect, the time resolution of the time-domain ADC may be higher than the time resolution of the time-digital converter. This has the effect of reducing jitter caused by the limitations of the time resolution of the time-digital converter. 【0011】 Furthermore, in the first aspect, the system may further include a frequency divider that divides the input signal generated by the digital control oscillator. This results in the divided input signal being input to the time-domain ADC. 【0012】 Furthermore, in the first aspect, the system may further include a digital time converter that delays the reference signal. This results in the adjustment of fractional phase shifts in the fractional PLL (Phase Locked Loop). 【0013】Furthermore, in the first aspect, the first selector may input the time difference converted by the voltage-time converter to the time-digital converter when the subsampling mode is specified, and input the reference signal and the input signal to the time-digital converter when the normal mode is specified. This results in the effect of switching between the subsampling mode and the normal mode. 【0014】 Furthermore, in the first aspect, the normal mode may be operated intermittently while the subsampling mode is in operation. This has the effect of improving the temporal resolution while stabilizing the phase synchronization. 【0015】 Furthermore, in the first aspect, the offset correction unit may correct the offset by selecting 0 with the third selector when switching between the normal mode and the subsampling mode. This reduces the phase error based on switching between the normal mode and the subsampling mode while responding to fluctuations in the offset of the time digital converter. 【0016】 Furthermore, in the first aspect, the second selector may select the offset, the first arithmetic unit may subtract the offset held in the holding unit from the output of the time digital converter, and the offset correction unit may correct the offset by selecting the output of the first arithmetic unit with the third selector when switching between the normal mode and the subsampling mode. This has the effect of reducing the phase error based on switching between the normal mode and the subsampling mode. 【0017】 Furthermore, in the first aspect, calibration of the phase-locked loop may be performed. This has the effect of improving the stability of the phase lock. 【0018】The second aspect is an imaging device comprising an imaging unit provided with a plurality of pixels, and a phase-locking circuit that generates a clock signal for setting the operating timing of the imaging unit, wherein the phase-locking circuit comprises a sample-and-hold circuit that subsamples an input signal based on a reference signal, a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference, a time-digital converter that detects the time difference converted by the voltage-time converter, a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal to the time-digital converter, and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter. This results in the time resolution of the clock signal being set based on the voltage resolution of the clock signal used in the imaging device, and the phase error based on switching between normal mode and subsampling mode being reduced. 【0019】 The third aspect is an electronic circuit comprising a circuit section that operates based on a clock signal, and a phase-synchronization circuit that generates a clock signal to set the operating timing of the circuit section, wherein the phase-synchronization circuit comprises a sample-and-hold circuit that subsamples an input signal based on a reference signal, a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference, a time-digital converter that detects the time difference converted by the voltage-time converter, a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal to the time-digital converter, and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter. This results in the time resolution of the clock signal being set based on the voltage resolution of the clock signal used in the electronic circuit, and the phase error based on switching between normal mode and subsampling mode being reduced. 【0020】This is a block diagram showing an example configuration of a phase-synchronous circuit according to the first embodiment. This is a timing chart showing the waveforms of each part of the phase-synchronous circuit according to the first embodiment. This is a timing chart showing the relationship between the clock signal and the reference clock of the phase-synchronous circuit according to the first embodiment. This is a diagram showing a first example of the relationship between the offset frequency and phase noise of the phase-synchronous circuit according to the first embodiment. This is a diagram showing a second example of the relationship between the offset frequency and phase noise of the phase-synchronous circuit according to the first embodiment. This is a diagram showing an example configuration of a time-digital converter according to the first embodiment. This is a diagram showing an example configuration of a digital time converter according to the first embodiment. This is a diagram showing an example configuration of a digital time converter according to the first embodiment. This is a flowchart showing the subsampling operation of the phase-synchronous circuit according to the first embodiment. This is a timing chart showing frequency fluctuations based on switching between normal operation and subsampling operation according to the first embodiment. This is a timing chart showing phase errors based on switching between normal operation and subsampling operation according to the first embodiment. This is a flowchart showing an example of the offset correction operation of the phase-synchronous circuit according to the first embodiment. This is a timing chart showing an example of the offset correction operation of the phase-synchronous circuit according to the first embodiment. This is a flowchart showing other examples of the offset correction operation of the phase-synchronous circuit according to the first embodiment. This is a timing chart showing another example of the offset correction operation of the phase-synchronous circuit according to the first embodiment. This is a block diagram showing an example of the configuration of the phase-synchronous circuit according to the second embodiment. This is a block diagram showing an example of the configuration of the phase-synchronous circuit according to the third embodiment. This is a block diagram showing an example of the configuration of an imaging device to which the phase-synchronous circuit according to the fourth embodiment is applied. This is a block diagram showing an example of the configuration of a solid-state imaging device according to the fourth embodiment. This is a perspective view showing an example of the stacking of the pixel array according to the fifth embodiment. This is a block diagram showing a schematic example of the configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the imaging unit. 【0021】The following describes the embodiments for implementing this technology (hereinafter referred to as "embodiments"). The description will proceed in the following order: 1. First Embodiment (An example in which the voltage of a clock signal subsampled by a sample-and-hold circuit is converted into a time difference by a voltage-time converter, the time difference is detected by a time-digital converter, and the offset based on switching between normal operation and subsampling operation is corrected) 2. Second Embodiment (An example in which a reference clock is input to a selector without the intervention of a digital time converter, and the offset based on switching between normal operation and subsampling operation is corrected) 3. Third Embodiment (An example in which the offset based on switching between normal operation, which divides the frequency of a clock signal output from a digital control oscillator, and subsampling operation is corrected) 4. Fourth Embodiment (An example in which a phase-locking circuit is applied to an imaging device) 5. Fifth Embodiment (An example in which pixel arrays are stacked) 6. Application Examples to Mobile Devices 【0022】 <1. First Embodiment> Figure 1 is a block diagram showing an example of the configuration of a phase-locked circuit according to the first embodiment. 【0023】 In the figure, an ADPLL 200 is provided as a phase-locked circuit. The ADPLL 200 forms a feedback loop based on phase locking and outputs a clock signal CLK. The frequency of the clock signal CLK can be determined based on an FCW (Frequency Command Word). The FCW can specify the ratio of the frequency of the clock signal CLK to the frequency of the reference clock RCK. The FCW can include an integer int and a decimal number frc. The FCW can be provided from outside the ADPLL 200. The ADPLL 200 includes an accumulator 201, an arithmetic unit 202, a loop filter 203, a digitally controlled oscillator 204, a counter 206, a time-domain ADC 207, a digital time converter 208, and a control unit 209. The ADPLL 200 also includes an offset correction unit 219. 【0024】The digitally controlled oscillator 204 generates a clock signal CLK based on its oscillation operation. The digitally controlled oscillator 204 can change its oscillation frequency based on the oscillator tuning word. The digitally controlled oscillator 204 may be a ring oscillator or an LC oscillator. 【0025】 The counter 206 counts up with each clock cycle of the clock signal CLK and outputs the count value to the arithmetic unit 202. At this time, the counter 206 can detect the phase of the clock signal CLK in units of one period. 【0026】 The accumulator 201 sets a count-up value for each period of the reference clock RCK based on the FCW and outputs it to the arithmetic unit 202. At this time, the FCW is input to the accumulator 201. The accumulator 201 can then output the integer int specified by the FCW to the arithmetic unit 202 and the decimal number frc specified by the FCW to the digital-to-time converter (DTC) 208. 【0027】 The arithmetic unit 202 subtracts the output of the counter 206 and the output of the offset correction unit 219 from the output of the accumulator 201 and outputs the result to the loop filter 203. The output of the arithmetic unit 202 can indicate the phase error between the reference clock RCK and the clock signal CLK. At this time, the ADPLL 200 can operate the phase-synchronous loop so that the phase error approaches zero. 【0028】 The loop filter 203 band-limits the input to the digitally controlled oscillator 204, reducing the effects of quantization errors. The gain of the loop filter 203 can be adjusted based on the calibration of the ADPLL 200. 【0029】The digital time converter 208 delays the reference clock RCK and outputs it to the sample-and-hold circuit 211 and the operating mode selector 213. In a fractional PLL, a fractional phase shift occurs each time the clock signal CLK is subsampled based on the reference clock RCK. Since the value of this phase shift is known, the digital time converter 208 can be set to a delay time that corrects this phase shift. By correcting the phase shift in the digital time converter 208, it becomes unnecessary to expand the range of the digital time converter 214 to accommodate this phase shift. Therefore, the digital time converter 214 only needs to handle a relatively narrow range that includes a margin to accommodate the resolution of the digital time converter 208, the jitter of the digital control oscillator 204, and other errors. Note that in an integer PLL, the digital time converter 208 is not required. 【0030】 The time-domain ADC 207 performs A / D conversion in the time domain. The time resolution of the time-domain ADC 207 can be higher than the time resolution of the time-digital converter 214. The time-domain ADC 207 comprises a sample-and-hold circuit 211, a voltage-time converter 212, an operating mode selector 213, and a time-digital converter 214. 【0031】 The sample-and-hold circuit 211 subsamples the clock signal CLK based on the reference clock RCK. The sample-and-hold circuit 211 then holds the subsampled sample-and-hold value SH and outputs it to the voltage-to-time converter (VTC) 212. 【0032】 The voltage-time converter 212 converts the voltage of the subsampled clock signal CLK in the sample-and-hold circuit 211 into a time difference. At this time, the voltage-time converter 212 can set the rise time difference of the output voltages VP and VN based on the sample-and-hold value SH held in the sample-and-hold circuit 211. 【0033】The operation mode selector 213 switches between inputting the time difference converted by the voltage-time converter 212 to the time-digital converter 214, and inputting the reference clock RCK and the clock signal CLK. Here, the operation mode selector 213 can set the operation mode based on the mode setting signal MOD1. The operation mode can be selected from subsampling mode and normal mode. In this case, in subsampling mode, the operation mode selector 213 inputs the time difference converted by the voltage-time converter 212 to the time-digital converter 214. In normal mode, the operation mode selector 213 inputs the reference clock RCK and the clock signal CLK to the time-digital converter 214. 【0034】 In subsampling mode, the time-to-digital converter (TDC) 214 detects the time difference converted by the voltage-to-time converter 212, digitizes it, and outputs it to the offset correction unit 219. In subsampling mode, the time difference detected by the time-to-digital converter 214 is amplified and input. In normal mode, the time-to-digital converter 214 detects the time difference between the reference clock RCK and the clock signal CLK, digitizes it, and outputs it to the offset correction unit 219. The time-to-digital converter 214 may also be a delay line TDC. 【0035】 The time difference detected by the time-digital converter 214 is amplified based on the gain from the input of the sample-and-hold circuit 211 to the input of the time-digital converter 214. The gain from the input of the sample-and-hold circuit 211 to the input of the time-digital converter 214 can be given as follows. 【0036】 If the clock signal CLK is a sine wave with amplitude Vck [V] and frequency fck [Hz], the slope near the zero crossing is 2π・fck・Vck. Therefore, the voltage gain with respect to the time delay Δtck of the clock signal CLK is 2π・fck・Vck・Δtck. Also, the gain TG of the voltage-time converter 212 is a design value, and for example, with a 100mV input, a gain of 200 [psec] can be achieved. 【0037】Assuming standard values ​​of Vck = 1 [V] and fck = 2 [GHz], the gain from the time difference Δtck at the input of the sample-and-hold circuit 211 to the time difference Δtvo at the output of the voltage-time converter 212 can be given by the following equation. 【0038】 Δtvo=2π・fck・Vck・Δtck[V / sec]・TG[sec / V] =2π・2・10 ９ ・Δtck・200p / 100m Δtvo / Δtck=25.1 【0039】 In other words, by interposing a sample-and-hold circuit 211 and a voltage-time converter 212 before the time-digital converter 214, the time shift of the clock signal CLK near its zero-crossing, which has gain in the time domain, is magnified by 25.1 times and input to the time-digital converter 214. When the time resolution is converted to the input, if the TDC time resolution is 20 psec, the input-converted time resolution becomes approximately 0.8 psec, effectively improving the time resolution. 【0040】 The offset correction unit 219 corrects the offset based on the switching between normal operation and subsampling operation, based on the output of the time-digital converter 214. In normal operation, the path from the digital control oscillator 204 to the time-digital converter 214 is set via the operation mode selector 213. In subsampling operation, the path from the digital control oscillator 204 to the time-digital converter 214 is set via the operation mode selector 213, through the sample-and-hold circuit 211 and the voltage-time converter 212. As a result, a phase error occurs when switching between normal operation and subsampling operation due to the amount of delay from each path, causing jitter. At this time, the offset correction unit 219 can reduce the phase error caused by the amount of delay from each path by correcting the offset according to the phase error when switching between normal operation and subsampling operation. The offset correction unit 219 includes a flip-flop 215, an operation mode selection selector 216, an arithmetic unit 217, and a freeze mode selection selector 218. 【0041】The flip-flop 215 holds the output of the time digital converter 214 as an offset based on the reference clock RCK. A register may be provided instead of the flip-flop 215. Note that the flip-flop 215 is an example of the holding unit described in the claims. 【0042】 The operation mode selection selector 216 switches between the offset held in the flip-flop 215 and 0 based on the mode setting signal MOD2 and outputs the result to the arithmetic unit 217. The mode setting signal MOD2 can set the operation selection mode. 【0043】 The arithmetic unit 217 subtracts the output of the operation mode selection selector 216 from the output of the time digital converter 214 and outputs the result to the freeze mode selection selector 218. 【0044】 The freeze mode selection selector 218 switches between the output of the arithmetic unit 217 and 0 based on the mode setting signal MOD3 and outputs the result to the arithmetic unit 202. The mode setting signal MOD3 can set the freeze mode. 【0045】 In offset correction, after startup in the normal mode, when switching to the subsampling operation via the operation mode selector 213, the input to the loop filter 203 is stopped, and 0 is input to the arithmetic unit 202 via the freeze mode selection selector 218. At this time, the flip-flop 215 holds the output value of the time digital converter 214 as an offset. Then, at the timing of restarting the integration of the loop filter, the output of the arithmetic unit 217 is input to the arithmetic unit 202 via the freeze mode selection selector 218, and an offset is added to the output of the arithmetic unit 202, thereby making it possible to reduce the phase error at the time of switching the subsampling operation. 【0046】 When switching from the subsampling operation to the normal mode via the operation mode selector 213, the integration of the loop filter is stopped and the state of the time digital converter 214 is held, thereby making it possible to reduce the phase error and achieve both low jitter operation and robust operation. <​The control unit 209 comprehensively controls the AD PLL 200. For example, the control unit 209 can control the operation sequence of the AD PLL 200, supply an enable signal when the AD PLL 200 is started up, perform mode switching of the AD PLL 200, and set the coefficients of the loop filter 203. At this time, the control unit 209 can switch the operation mode, operation selection mode, and freeze mode of the AD PLL 200. 【0048】 FIG. 2 is a timing chart showing waveforms of each part of the phase-locked loop circuit according to the first embodiment. 【0049】 In the figure, when the reference clock RCK rises (t1), the sample-and-hold circuit 211 subsamples the clock signal CLK and holds the sample-and-hold value SH. 【0050】 Then, the voltage-to-time converter 212 raises the output voltage VN based on the sample-and-hold value SH held by the sample-and-hold circuit 211 (t2). Next, after the elapse of the time difference DT corresponding to the sample-and-hold value SH, the voltage-to-time converter 212 raises the output voltage VP (t3). The time difference DT may be proportional to the sample-and-hold value SH. 【0051】 FIG. 3 is a timing chart showing the relationship between the clock signal and the reference clock of the phase-locked loop circuit according to the first embodiment. Note that a in the figure shows an operation example in the normal mode. b in the figure shows an operation example in the subsampling mode. 【0052】 In a in the figure, in the normal mode, the time-to-digital converter 214 detects the time difference between the reference clock RCK and the clock signal CLK. As the TDC time resolution at this time, for example, a value of 20 psec can be obtained. 【0053】 In the normal mode, the time difference between the reference clock RCK and the clock signal CLK is directly detected. Therefore, in the normal mode, the time difference between the reference clock RCK and the clock signal CLK is not affected by the period of the clock signal CLK, and a wide lock range LR1 can be ensured. 【0054】 In figure b, in subsampling mode, the voltage-time converter 212 converts the voltage VD of the subsampled clock signal CLK in the sample-and-hold circuit 211 into a time difference. For example, a time resolution of 0.8 psec can be obtained. For example, suppose the gain TG of the voltage-time converter 212 is 200 psec / 100 mV. In this case, the voltage resolution of the voltage-time converter 212 is TDC time resolution / TG = 10 mV. If the clock signal CLK is a sine wave, a time resolution of 10 mV / 2πf [V / sec] = 0.8 psec can be obtained for the time domain ADC 207. 【0055】 In subsampling mode, the voltage VD of the clock signal CLK is converted into a time difference. Therefore, in subsampling, the time difference between the reference clock RCK and the clock signal CLK is affected by the period of the clock signal CLK, resulting in a narrower lock range LR2. This lock range LR2 is limited to within ±π / 4rad. 【0056】 Therefore, to achieve both an expanded lock range and improved temporal resolution of the phase-locked circuit, it is effective to switch between subsampling mode and normal mode. For example, normal mode may be operated intermittently while operating in subsampling mode. 【0057】 Figure 4 shows a first example of the relationship between the offset frequency and phase noise of a phase-locked circuit according to the first embodiment. In this figure, the relationship between the offset frequency and phase noise in normal mode is shown. L1 represents the phase noise of the OL-DCO, L2 represents the phase noise of the TDC, L3 represents the phase noise of the DCO, and L4 represents the total phase noise. 【0058】 In the figure, when the TDC time resolution is 20 psec, the quantization noise of the time-digital converter 214 contributes significantly to the jitter of the ADPLL 200, resulting in a jitter of 1.8 psec. 【0059】Figure 5 shows a second example of the relationship between the offset frequency and phase noise of a phase-locked circuit according to the first embodiment. In this figure, the relationship between the offset frequency and phase noise is shown in subsampling mode. 【0060】 In the figure, if the TDC time resolution is assumed to be 0.8 psec, the quantization noise of the time-digital converter 214 becomes approximately 10 dB or more smaller than other noises and ceases to be a dominant term. As a result, the jitter of the ADPLL 200 is reduced to 0.6 psec. 【0061】 The normal mode has a wide lock range LR1 and is robust, so various calibrations immediately after startup can be performed in normal mode, and then switching to subsampling mode allows for safe startup. Although the normal mode has more jitter than the subsampling mode, it is robust and low power consumption, allowing for the selection of the appropriate mode depending on the application. Furthermore, by inserting normal mode between subsampling modes, cycle slip during subsampling operation can be prevented, achieving both an expanded lock range and improved temporal resolution. 【0062】 Figure 6 shows an example of the configuration of a time-digital converter according to the first embodiment. In this figure, the time-digital converter 214 is shown as a delay line TDC. 【0063】 In the figure, the time-to-digital converter 214 includes delay buffers 311 to 313 and flip-flops 321 to 323. The reference clock RCK is input via buffer 301, delayed by an integer multiple of the buffer delay τ in delay buffers 311 to 313, and input to the D terminals of flip-flops 321 to 323, respectively. 【0064】The CK terminal of each flip-flop 321 to 323 receives the clock signal CLK via the buffer 302. At this time, each flip-flop 321 to 323 captures the state of the reference clock RCK on the delay line at the rising edge of the clock signal CLK. This makes it possible to measure how many buffer delay stages the time interval until the rising edge of the clock signal CLK corresponds to, and to convert time into a digital value. In this configuration, the buffer delay τ on the path of the reference clock RCK becomes the minimum time resolution. 【0065】 Figure 7 shows an example configuration of a digital time converter according to the first embodiment. In the figure, a represents the first example of the digital time converter 208, b represents the second example of the digital time converter 208, and c represents the third example of the digital time converter 208. 【0066】 In figure a, the first example of the digital time converter 208 comprises inverters 401 and 402, capacitors 411 to 413, and field-effect transistors 421 to 423. Inverters 401 and 402 are connected in series with each other. Each capacitor 411 to 413 is connected in series with each field-effect transistor 421 to 423. The series circuits of each capacitor 411 to 413 and each field-effect transistor 421 to 423 are connected in parallel between inverters 401 and 402. The series circuits of each capacitor 411 to 413 and each field-effect transistor 421 to 423 can be operated as a variable capacitance. 【0067】 In figure b, a second example of the digital time converter 208 comprises inverters 431 to 433, capacitors 441 to 443, and a selector 403. Capacitors 441 to 443 are connected in parallel to the output of each inverter 431 to 433. The parallel circuits of each inverter 431 to 433 and each capacitor 441 to 443 can have different delay amounts. The selector 403 can select any of the outputs of the inverters 431 to 433. 【0068】In figure c, a third example of the digital time converter 208 comprises wiring 451 to 454 and a selector 404. Wiring 451 to 454 may have different propagation delays. The selector 404 can select any of wiring 451 to 454. 【0069】 Figure 8 shows an example of the configuration of a digital time converter according to the first embodiment. 【0070】 In the figure, the digital time converter 208 includes switches 511, 521, 515, 525, inverters 512, 522, capacitors 513, 523, and current sources 514, 524. Switch 511 is connected in series with inverter 512. Switch 521 is connected in series with inverter 522. Current source 514 is connected in series with switch 515. Current source 524 is connected in series with switch 525. The series circuit of capacitor 513 and current source 514 and switch 515 is connected in parallel between switch 511 and inverter 512. The series circuit of capacitor 523 and current source 524 and switch 525 is connected in parallel between switch 521 and inverter 522. Each switch 511, 521 is turned on / off based on clock CL. Each switch 515, 525 is turned on / off based on inverting clock CB. Inverting clock CB is a signal obtained by inverting clock CL. At this time, each input PIN and NIN are input via switches 511 and 521, respectively, and each output POT and NOT are output via inverters 512 and 522, respectively. 【0071】 Figure 9 is a flowchart showing the subsampling operation of the phase-locked circuit according to the first embodiment. 【0072】 In the figure, when the power to the ADPLL200 is turned on (S101), the initial setup of the ADPLL200 is performed (S102). 【0073】Next, the calibration and phase pull-in of the ADPLL200 begins (S103). During calibration, in order to maintain a constant loop gain when switching between the normal path and the subsampling path, prevent malfunctions, and maintain low jitter, the gains of the normal path and the subsampling path are detected and reflected in the loop filter. The following methods can be used to detect each gain. 【0074】 In estimating the gain of the digital time converter 208, the error can be detected by using the correlation value between the output of the time digital converter 214 and the input of the digital time converter 208, thereby determining the delay amount (time) with respect to the input code of the digital time converter 208. The method disclosed in the following document may also be used to estimate the gain of the digital time converter 208: "Y. -H. Liu et al., "An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and MOD1ulator for IoT Applications in 40 nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 5, pp. 1094-1105, May 2017, doi: 10.1109 / TCSI.2016.2625462." 【0075】 The gain of the normal path can be determined by shifting the DTC input code and comparing the amount of the shift with the amount of change in the TDC output code to find the DTC input code for the TDC1 code. Since the relationship between the DTC input code and time is known, the time corresponding to the TDC1 code can be determined. 【0076】 The gain of the subsampling path can be determined in the same way as the gain of the normal path by combining the sample-and-hold circuit 211, the voltage-time converter 212, and the time-digital converter 214 to find the time corresponding to the TDC1 code. 【0077】Next, ADPLL200 determines whether a subsampling mode is specified (S104). If a subsampling mode is not specified, ADPLL200 continues to operate in normal mode (S105). On the other hand, if a subsampling mode is specified, ADPLL200 sets the subsampling mode (S106). 【0078】 By switching between normal mode and subsampling mode, the low robustness of subsampling mode can be compensated for. In normal mode, even if the phase of the clock signal CLK shifts significantly due to unexpected movements or disturbances, the phase shift can be measured within the detection range of the time-digital converter 214, and normal operation can be restored. For example, during calibration immediately after startup, the phase may shift more than expected because it is unknown how much the frequency of the digital control oscillator 204 will move in relation to the adjustment amount. Even in such cases, proper control is possible by designing a wide detection range for the time-digital converter 214. A similar effect can be obtained against unexpected disturbances. 【0079】 On the other hand, in subsampling mode, the phase is detected based on the slope of the sine wave. Therefore, if the phase deviates by more than ±90 degrees relative to the clock signal CLK, the slope reverses, making it uncontrollable. To address this, the system operates in normal mode during startup, and the ADPLL200 performs calibration, enabling safe startup. Subsequently, low-jitter operation is performed in subsampling mode, achieving both robustness and low-jitter operation. 【0080】 Even during subsampling mode operation, intermittent operation in normal mode ensures robustness against problems where disturbances may cause cycle slip in response to the input, thanks to the wide-range phase detection provided by normal mode. 【0081】Next, the ADPLL200 performs phase pull-in and locking (S107) and continues operation (S108). At this point, the ADPLL200 returns to S104 during continued operation to determine whether a subsampling mode has been specified. 【0082】 Figure 10 is a timing chart showing frequency fluctuations based on switching between normal operation and subsampling operation according to the first embodiment, and Figure 11 is a timing chart showing phase errors based on switching between normal operation and subsampling operation according to the first embodiment. 【0083】 In Figure 10, without offset correction, a frequency fluctuation KS2 of the clock signal CLK occurs based on the switch from normal operation to subsampling operation. Also, without offset correction, a frequency fluctuation KN2 of the clock signal CLK occurs based on the switch from subsampling operation to normal operation. 【0084】 Furthermore, in Figure 11, if there is no offset correction, a phase error PS2 occurs at the output of the time-digital converter 214 based on the switch from normal operation to subsampling operation. Also, if there is no offset correction, a phase error PN2 occurs at the output of the time-digital converter 214 based on the switch from subsampling operation to normal operation. 【0085】 On the other hand, in Figure 10, when offset correction is present, the frequency fluctuation KS1 of the clock signal CLK is suppressed when switching from normal operation to subsampling operation, and the target frequency Ft is maintained. Also, when offset correction is present, the frequency fluctuation KN1 of the clock signal CLK is suppressed when switching from subsampling operation to normal operation, and the target frequency Ft is maintained. 【0086】 Furthermore, in Figure 11, when offset correction is applied, the phase error PS1 of the output of the time-digital converter 214 is suppressed based on the switch from normal operation to subsampling operation. Also, when offset correction is applied, the phase error PN1 of the output of the time-digital converter 214 is suppressed based on the switch from subsampling operation to normal operation. 【0087】Figure 12 is a flowchart showing an example of the offset correction operation of a phase-locked circuit according to the first embodiment. 【0088】 In the same figure, when the power to the ADPLL200 is turned on (S201), the initial setup of the ADPLL200 is performed (S202). 【0089】 Next, the calibration and phase pull-in of the ADPLL200 begins (S203). 【0090】 Next, ADPLL200 determines whether to switch the operating mode (S204). If subsampling mode is not specified in the operating mode, ADPLL200 continues to operate in normal mode (S205). On the other hand, if subsampling mode is specified in the operating mode, ADPLL200 determines whether to switch the selection of the operating mode (S208). In the operating mode selection switch, either switching from normal mode to subsampling mode or switching from subsampling mode to normal mode is selected. 【0091】 Next, the ADPLL200 performs phase pull-in and locking (S206) and continues operation (S207). At this point, the ADPLL200 returns to S204 during operation to determine whether a subsampling mode has been specified. 【0092】 On the other hand, in S208, when switching from normal mode to subsampling mode is selected, the state hold of the time digital converter 214 is set to "on" (S209), and the subsampling mode is started (S210). 【0093】 Next, offset correction is performed, the state hold of the time digital converter 214 is set to none (S211), and the process proceeds to S206. 【0094】 On the other hand, in S208, if switching from subsampling mode to normal mode is selected, the state hold of the time digital converter 214 is set to none (S212), and normal mode is started (S213). 【0095】Next, the state hold of the time digital converter 214 is set to none (S214), and the process proceeds to S206. 【0096】 Figure 13 is a timing chart showing an example of the offset correction operation of the phase-locked circuit according to the first embodiment. Note that initial setup and calibration are omitted in this figure. 【0097】 In the figure, when the power is turned on, the nth cycle (where n is a positive integer) begins. Here, the normal mode is selected by the operation mode selector 213, the offset correction is set to "no" by the operation mode selection selector 216, and the state hold of the time digital converter 214 is set to "no". At this time, the output of the time digital converter 214 is set to ~0, the output of the flip-flop 215 is set to ~0, the output of the arithmetic unit 217 is set to ~0, and ~0 is output from the freeze mode selection selector 218. Note that ~ indicates nearly equal. Here, the operation mode selection selector 216 selects 0 when the mode setting signal MOD2 = 0, and selects the output of the flip-flop 215 when the mode setting signal MOD2 = 1. The freeze mode selection selector 218 selects 0 when the mode setting signal MOD3 = 1, and selects the output of the arithmetic unit 217 when the mode setting signal MOD3 = 0. When switching operation modes, the output of the arithmetic unit 217 is set to ~0. 【0098】 Next, in the (n+1)th cycle, the operation mode is set to subsampling mode using the operation mode selector 213, and the state hold of the time digital converter 214 is set to "on". At this time, the output of the time digital converter 214 is set to offset OF, the output of the arithmetic unit 217 is set to offset OF, and 0 is output from the freeze mode selection selector 218. Offset OF is a value corresponding to the phase error of the time digital converter 214 based on the switching between normal mode and subsampling mode. 【0099】Next, in the (n+2)th cycle, the operation mode selection mode is set to "Offset Correction On" using the operation mode selection selector 216, and the state hold of the time digital converter 214 is set to "Off". At this time, the output of the time digital converter 214 is set to offset ~ OF, the output of the flip-flop 215 is set to offset ~ OF, the output of the arithmetic unit 217 is set to ~ 0, and ~ 0 is output from the freeze mode selection selector 218. 【0100】 Next, in the m-th cycle (where m is an integer greater than or equal to n+3), the output of the time-digital converter 214 is set to offset OF, and the output of the flip-flop 215 is set to offset OF. Figure 13 shows an example in which the output of the time-digital converter 214 fluctuates from the n+2th cycle to the mth cycle due to changes over time. 【0101】 Next, in the m+1 cycle, the normal mode is selected in the operation mode selector 213, and the state hold of the time digital converter 214 is set to "on". At this time, the output of the time digital converter 214 is set to offset OF2, the output of the arithmetic unit 217 is set to OF2-OF, and 0 is output from the freeze mode selection selector 218. Offset OF2 is a value corresponding to the phase error of the time digital converter 214 based on the switching between subsampling mode and normal mode. 【0102】 Next, in the m+2 cycle, the state hold of the time digital converter 214 is set to none. At this time, the output of the flip-flop 215 is set to offset OF2, the output of the arithmetic unit 217 is set to ~0, and ~0 is output from the freeze mode selection selector 218. 【0103】 Figure 14 is a flowchart showing another example of the offset correction operation of the phase-locked circuit according to the first embodiment. 【0104】 In the same figure, this offset correction operation includes S313 and S314 instead of S212 to S214 in Figure 12. The other processing of this offset correction operation is the same as the processing of the offset correction operation in Figure 12. 【0105】In S208, if switching from subsampling mode to normal mode is selected, normal mode is started (S313), the state hold of the time digital converter 214 is set to none (S314), and the process proceeds to S206. 【0106】 Figure 15 is a timing chart showing another example of the offset correction operation of the phase-locked circuit according to the first embodiment. Note that initial setup and calibration are omitted in this figure. 【0107】 In this figure, the processing up to the (n+2)th cycle is the same as the processing in Figure 13. Note that this figure shows an example where the output of the time-digital converter 214 does not fluctuate from the (n+2)th cycle to the mth cycle. 【0108】 Next, in the mth cycle, the output of the time digital converter 214 is set to offset to OFF, and the output of the flip-flop 215 is set to offset to OFF. 【0109】 Next, in the m+1 cycle, the operating mode is set to normal mode using the operating mode selector 213, and the state hold of the time digital converter 214 is set to none. At this time, the output of the time digital converter 214 is set to ~0. 【0110】 Next, in the m+2 cycle, the output of the flip-flop 215 is set to ~0. 【0111】As described above, in the first embodiment, the voltage of the clock signal CLK, which has been subsampled by the sample-and-hold circuit 211, is converted into a time difference by the voltage-time converter 212, and this time difference is detected by the time-digital converter TDC. This makes it possible to set the time resolution of the clock signal CLK based on the voltage resolution of the clock signal CLK. At this time, by converting the voltage of the clock signal CLK into a time difference, the time difference detected by the time-digital converter 214 can be increased. Therefore, the time resolution of the ADPLL 200 can be improved while addressing the constraints of the TDC time resolution. At this time, by providing the sample-and-hold circuit 211 and the voltage-time converter 212 in the time-domain ADC 207, subsampling using the ADC to increase the time difference detected by the time-digital converter 214 can be eliminated. Therefore, jitter can be reduced while suppressing an increase in the circuit size and power consumption of the ADPLL 200. 【0112】 Furthermore, by making it possible to switch between normal mode and subsampling mode, robustness can be ensured in normal mode while reducing jitter in subsampling mode. 【0113】 Furthermore, the offset correction unit 219 corrects the offset resulting from the switching between normal operation and subsampling operation based on the output of the time digital converter 214. This allows for both an expansion of the lock range and improvement of the time resolution of the ADPLL 200, while setting the time resolution of the clock signal CLK based on the voltage resolution of the clock signal CLK, and reducing the phase error resulting from the switching between normal operation and subsampling operation. 【0114】 <2. Second Embodiment> In the first embodiment described above, the reference clock RCK was input to the operation mode selector 213 via the digital time converter 208. In this second embodiment, the reference clock RCK is input to the operation mode selector 213 without the use of the digital time converter 208. 【0115】Figure 16 is a block diagram showing an example configuration of a phase-locked circuit according to the second embodiment. 【0116】 In the figure, ADPLL 700 operates as an integer PLL. ADPLL 700 is provided with a time-domain ADC 707 instead of the time-domain ADC 207 of the first embodiment described above. The other configurations of ADPLL 700 in the second embodiment are the same as those of ADPLL 200 in the first embodiment described above. 【0117】 In the time-domain ADC 707, the reference clock RCK is input to the operating mode selector 213 without the intervention of the digital time converter 208. The other configurations of the time-domain ADC 707 in the second embodiment are the same as those of the time-domain ADC 207 in the first embodiment described above. 【0118】 Thus, in the second embodiment described above, the reference clock RCK can be directly input to the operation mode selector 213 by inputting the reference clock RCK to the operation mode selector 213 without the need for the digital time converter 208. 【0119】 <3. Third Embodiment> In the first embodiment described above, the clock signal CLK output from the digital control oscillator 204 was input to the time-domain ADC 207. In this third embodiment, the clock signal CLK output from the digital control oscillator 204 is divided before being input to the time-domain ADC 207. 【0120】 Figure 17 is a block diagram showing an example configuration of a phase-locked circuit according to the third embodiment. 【0121】 In the figure, the ADPLL 800 has a frequency divider 205 added to the ADPLL 800 of the first embodiment described above. The other configurations of the ADPLL 800 of the third embodiment are the same as those of the ADPLL 200 of the first embodiment described above. 【0122】The frequency divider 205 is connected downstream of the digital control oscillator 204. At this time, the frequency divider 205 divides the clock signal CLK generated by the digital control oscillator 204 and outputs it to the counter 206, the sample-and-hold circuit 211, and the operating mode selector 213. 【0123】 Thus, in the third embodiment described above, a frequency divider 205 is connected downstream of the digital control oscillator 204. This makes it possible to reduce the operating frequencies of the counter 206 and the time-domain ADC 207, thereby reducing power consumption. 【0124】 In the above embodiment, an example was shown in which a counter 206 was provided in the ADPLL for initial frequency adjustment, but it does not necessarily have to be a counter 206. For example, a driver and a PFD (Phase Frequency Detector) may be provided instead of the counter 206. 【0125】 <4. Fourth Embodiment> In the first embodiment described above, the voltage of the clock signal CLK, which was subsampled by the sample-and-hold circuit 211, was converted into a time difference by the voltage-time converter 212, and this time difference was detected by the time-digital converter TDC. In this fourth embodiment, a phase-locked circuit is applied to the imaging device. 【0126】 Figure 18 is a block diagram showing an example configuration of an imaging device according to the fourth embodiment. 【0127】 In the figure, the imaging device comprises an optical system 11, a solid-state imaging device 12, a controller 13, an optical system drive unit 14, and an LCD (Liquid Crystal Display) 15. The imaging device also comprises a storage medium 16, flash memory 17, SDRAM (Synchronous Dynamic Random Access Memory) 18, and an operation unit 19. The imaging device may be used as a standalone unit, incorporated into a mobile terminal such as a smartphone, incorporated into an authentication device or monitoring device, or incorporated into an EV (Electric Vehicle) or a drone. 【0128】The optical system 11 forms an optical image on the imaging surface of the solid-state imager 12. The optical system 11 includes a focus lens 21, a zoom lens 22, and an aperture 23. The focus lens 21 adjusts the focus position on the imaging surface of the solid-state imager 12. The zoom lens 22 adjusts the magnification of the subject image formed on the imaging surface. The aperture 23 adjusts the amount of light incident on the imaging surface of the solid-state imager 12. 【0129】 The solid-state imaging device 12 detects the optical image formed on the imaging surface pixel by pixel, converts it into an electrical signal, and outputs a digitized pixel signal corresponding to the light intensity of the optical image. The solid-state imaging device 12 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. In addition, any of the phase-locking circuits of the first to third embodiments described above can be used to generate a clock signal to set the operating timing of the solid-state imaging device 12. 【0130】 The controller 13 comprehensively controls the entire imaging device. The controller 13 may include a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The processor may be a single-core processor or a multi-core processor. The controller 13 may also include hardware circuits such as accelerators that perform part of the processing (for example, an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit)). In addition, any of the phase-locking circuits of the first to third embodiments described above can be used to generate the clock signal that operates the controller 13. 【0131】The controller 13 includes an image processing unit 31, an imaging control unit 32, an optical system control unit 34, an LCD driver 35, a storage medium control unit 36, a flash memory control unit 37, and an SDRAM control unit 38. The controller 13 also includes an AE (Auto Exposure) processing unit 61, an AF (Auto Focus) processing unit 62, a sequence control unit 63, and a compression / decompression unit 64. The image processing unit 31, imaging control unit 32, optical system control unit 34, LCD driver 35, storage medium control unit 36, flash memory control unit 37, SDRAM control unit 38, AE processing unit 61, AF processing unit 62, sequence control unit 63, and compression / decompression unit 64 are connected to each other via a bus 39. 【0132】 The image processing unit 31 performs image processing based on the pixel signals generated by the solid-state imaging device 12. The image processing unit 31 includes a luminance / color signal generation unit 101, a luminance gamma unit 102, a luminance gain unit 103, a WB (White Balance) correction unit 104, a color gamma unit 105, a color difference conversion unit 106, and a color difference gain unit 107. 【0133】 The luminance / color signal generation unit 101 performs matrix calculations based on the pixel signals generated by the solid-state imaging device 12 to generate a luminance signal and a color signal. The luminance signal can, for example, indicate the luminance value for each pixel. The color signal can, for example, indicate the magnitude of the RGB components for each pixel. 【0134】 The luminance gamma unit 102 corrects the luminance of the luminance signal according to the display characteristics of the image. For example, the luminance gamma unit 102 can correct the luminance of the luminance signal according to the luminance characteristics of the LCD 15. The luminance gain unit 103 performs gain processing on the luminance signal. 【0135】 The WB correction unit 104 corrects the white balance of the color signal. The color gamma unit 105 corrects the color tone of the color signal according to the display characteristics of the image. For example, the color gamma unit 105 can correct the color tone of the color signal according to the color characteristics of the LCD 15. The color difference conversion unit 106 converts the RGB color signal into a color difference signal based on matrix calculations. The color difference gain unit 107 performs gain processing on the color difference signal. 【0136】The imaging control unit 32 controls the imaging of the solid-state imaging device 12. The imaging control unit 32 includes an exposure control unit 181, a white balance control unit 182, a gamma control unit 183, and a gain control unit 184. 【0137】 The exposure control unit 181 controls the exposure of the solid-state imaging device 12. At this time, the exposure control unit 181 can control the exposure time, exposure amount, shutter timing, etc. of the solid-state imaging device 12 based on the processing results of the AE processing unit 61, for example. The exposure control unit 181 can use the AE evaluation value as the processing result of the AE processing unit 61. 【0138】 The WB control unit 182 controls the gain amount for each RGB component of the WB correction unit 104 based on the input information input via the operation unit 19. The gamma control unit 183 controls the gamma characteristics of the luminance gamma unit 102 for the luminance signal and the gamma characteristics of the color gamma unit 105 for the color signal, respectively, based on the input information input via the operation unit 19. The gain control unit 184 controls the gain of the luminance gain unit 103 for the luminance signal and the gain of the color difference gain unit 107 for the color difference signal, respectively, based on the input information input via the operation unit 19. 【0139】 The optical system control unit 34 drives the optical system drive unit 14 based on the processing results of the AE processing unit 61 and the AF processing unit 62. The optical system control unit 34 includes an AF control unit 191, a zoom control unit 192, and an aperture control unit 193. The AF control unit 191 drives the AF motor 41 based on the processing results of the AF processing unit 62. The AF control unit 191 can use the AF evaluation value as the processing result of the AF processing unit 62. The zoom control unit 192 drives the zoom motor 42 based on the zoom operation of the operation unit 19. The aperture control unit 193 drives the aperture motor 43 based on the processing results of the AE processing unit 61. The aperture control unit 193 can use the AE evaluation value as the processing result of the AE processing unit 61. 【0140】 The LCD driver 35 drives the LCD 15. The LCD driver 35 converts the image data processed by the image processing unit 31 and the image data decompressed by the compression / decompression unit 64 into a video signal, and displays an image on the LCD 15 based on this video signal. 【0141】 The storage medium control unit 36 ​​controls the reading and writing of data to the storage medium 16. The flash memory control unit 37 controls the reading and writing of data to the flash memory 17. The SDRAM control unit 38 controls the reading and writing of data to the SDRAM 18. 【0142】 The AE processing unit 61 calculates an AE evaluation value for each predetermined region of the image data generated by the solid-state imaging device 12. The AF processing unit 62 calculates an AF evaluation value for each predetermined region of the image data generated by the solid-state imaging device 12. 【0143】 The sequence control unit 63 systematically controls the processing of the imaging device. At this time, the sequence control unit 63 can control the series of processes from when the image data generated by the solid-state imaging device 12 is processed, until it is displayed on the LCD 15. The sequence control unit 63 can also control the series of processes from when the image data generated by the solid-state imaging device 12 is processed, until it is compressed by the compression / decompression unit 64, and then stored on the storage medium 16. Furthermore, the sequence control unit 63 can perform interrupt processing based on the operation of the operation unit 19. 【0144】 The compression / decompression unit 64 compresses or decompresses the image data processed by the image processing unit 31 using a compression method such as JPEG (Joint Photographic Experts Group). 【0145】 The optical system drive unit 14 drives the optical system 11 based on control from the optical system control unit 34. The optical system drive unit 14 includes an AF motor 41, a zoom motor 42, and an aperture motor 43. The AF motor 41 moves the focus lens 21 in the optical axis direction based on control from the AF control unit 191. The zoom motor 42 moves the zoom lens 22 in the optical axis direction based on control from the zoom control unit 192. The aperture motor 43 adjusts the aperture diameter of the aperture 23 based on control from the aperture control unit 193. 【0146】 The LCD 15 displays captured images and various information to support the imaging operation. 【0147】The storage medium 16 stores images captured by the imaging device, etc. The storage medium 16 may be removable. The storage medium 16 may be, for example, a memory card or a USB (Universal Serial Bus) memory. 【0148】 The flash memory 17 stores various control programs executed by the controller 13, as well as parameters used to execute these control programs. 【0149】 The SDRAM 18 temporarily stores data generated by the processing of the controller 13. The SDRAM 18 may also include a buffer memory for storing image data for one frame. 【0150】 The operation unit 19 provides a user interface for operating the imaging device. The operation unit 19 may include, for example, buttons, dials, and switches provided on the imaging device. The operation unit 19 may also be configured as a touch panel together with the LCD 15. 【0151】 Depending on the camera's form factor, it may not have some of the above-mentioned functions, or conversely, it may have additional functions that are not disclosed. 【0152】 Figure 19 is a block diagram showing an example configuration of a solid-state imaging device according to the fourth embodiment. 【0153】 In the figure, the solid-state imaging device 12 includes a pixel array unit 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing unit 114, a horizontal scanning circuit 115, and a control circuit 116. 【0154】The pixel array section 111 comprises a plurality of pixels 120. The pixels 120 are arranged in a matrix along the row direction (also called the horizontal direction) and the column direction (also called the vertical direction). Each pixel 120 can form a source follower with the column readout circuit 113 when a signal is read out. Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 row by row when a signal is read out from each pixel 120. The vertical signal line 132 transmits the potential based on the current flowing when a signal is read out from the pixel 120 to the column signal processing unit 114 for each column. 【0155】 The vertical scanning circuit 112 scans the pixels 120 to be read out in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. 【0156】 The column readout circuit 113 can configure a source follower with each pixel 120 when reading a signal from each pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120. 【0157】 The column signal processing unit 114 processes the signals transmitted from each pixel 120 in the column direction. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted from each pixel 120 in the column direction. The column signal processing unit 114 can also perform analog-to-digital (AD) conversion processing based on the signals transmitted from each pixel 120 in the column direction and output an imaging signal Gout. 【0158】 The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel 120 and the reference signal. 【0159】The horizontal scanning circuit 115 scans the pixels 120 to be read out in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register. 【0160】 The control circuit 116 controls the vertical scanning circuit 112, the column reading circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column reading circuit 113, and the processing timing of the column signal processing unit 114. 【0161】 <5. Fifth Embodiment> In the first embodiment described above, a phase-locking circuit was applied to the imaging device. In this fifth embodiment, semiconductor chips, each provided with a pixel array section in which pixels are arranged in a matrix, are stacked. 【0162】 Figure 20 is a perspective view showing an example of stacking of pixel arrays according to the fifth embodiment. 【0163】 In the figure, the solid-state imaging device comprises semiconductor chips 921 and 922. Semiconductor chip 922 is stacked on semiconductor chip 921. 【0164】 A pixel array section 923 is formed on the semiconductor chip 922. Pixels 931 are arranged in a matrix in the row and column directions within the pixel array section 923. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922, enabling electrical connection between the semiconductor chips 921 and 922. 【0165】 Peripheral circuits 924 are formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array section 923 in the column direction. The oscillator circuit 928 can be provided with a phase-locked circuit according to any of the first to third embodiments described above. 【0166】The semiconductor chips 921 and 922 may be directly bonded. Hybrid bonding can be used for the direct bonding of the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu connections. The semiconductor substrate material used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP. 【0167】 Thus, in the fifth embodiment described above, the semiconductor chip 922 on which the pixel array 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed. 【0168】 <6. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots. 【0169】 Figure 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied. 【0170】 The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 21, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053. 【0171】The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle. 【0172】 The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc. 【0173】 The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing. 【0174】 The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light. 【0175】The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041. 【0176】 The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning. 【0177】 Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040. 【0178】 Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams. 【0179】The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 21, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display. 【0180】 Figure 22 shows an example of the installation position of the imaging unit 12031. 【0181】 In Figure 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105. 【0182】 The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes. 【0183】Figure 22 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained. 【0184】 At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection. 【0185】 For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed. 【0186】For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010. 【0187】 At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position. 【0188】The above describes an example of a vehicle control system to which the technology described herein can be applied. The technology described herein can be applied to the drive system control unit 12010, the body system control unit 12020, the external information detection unit 12030, the internal information detection unit 12040, the integrated control unit 12050, and the imaging unit 12031 among the configurations described above. Specifically, for example, the phase-synchronization circuit of the above embodiment can be applied to the drive system control unit 12010, the body system control unit 12020, the external information detection unit 12030, the internal information detection unit 12040, the integrated control unit 12050, and the imaging unit 12031. By applying the technology described herein to the vehicle control system 12000, the temporal resolution in digital processing can be improved. 【0189】 Furthermore, the phase-locking circuit of any of the first to third embodiments described above can be applied to imaging devices, as well as to electronic circuits used in communication devices, display devices, data processing devices, control devices, measuring devices, or printing devices. 【0190】 Furthermore, the embodiments described above are merely examples of how to realize the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology that bear the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the present technology. Also, the effects described herein are merely examples and are not limiting, and there may be other effects. 【0191】Furthermore, this technology can also be configured as follows: (1) A phase-synchronous circuit comprising: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal for the time-digital converter; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter. (2) The phase-synchronous circuit according to (1), wherein the offset correction unit comprises: a holding unit that holds the output of the time-digital converter as the offset; a second selector that switches between the offset and 0 and outputs the result; a first arithmetic unit that subtracts the output of the second selector from the output of the time-digital converter; and a third selector that switches between the output of the first arithmetic unit and 0 and outputs the result. (3) The phase-locked circuit according to (2), comprising: a digital control oscillator that generates the input signal; an accumulator that sets a count-up value for each period of the reference signal based on an FCW (Frequency Command Word); a counter that counts up for each period of the input signal; a second arithmetic unit that subtracts the output of the counter and the output of the third selector from the output of the accumulator; and a loop filter that band-limits the input to the digital control oscillator. (4) The phase-locked circuit according to claim 1, wherein the sample-and-hold circuit, the voltage-time converter and the time-digital converter constitute a time-domain ADC (Analog to Digital Converter). The phase-locked circuit according to (2) or (3). (5) The phase-locked circuit according to (4), wherein the time resolution of the time-domain ADC is higher than the time resolution of the time-digital converter. (6) The phase-locked circuit according to (4) or (5), comprising a frequency divider that divides the input signal generated by the digital control oscillator. (7) A phase-locking circuit according to any one of (2) to (6) above, comprising a digital time converter for delaying the reference signal.(8) The phase-locking circuit according to any one of (2) to (7), wherein the first selector inputs the time difference converted by the voltage-time converter to the time-digital converter when the subsampling mode is specified, and inputs the reference signal and the input signal to the time-digital converter when the normal mode is specified. (9) The normal mode is the phase-locking circuit according to (8), which is operated intermittently while the subsampling mode is in operation. (10) The phase-locking circuit according to (8) or (9), wherein the offset correction unit corrects the offset by selecting 0 with the third selector when switching between the normal mode and the subsampling mode. (11) The phase-locking circuit according to (8) or (9), wherein the second selector selects the offset, the first arithmetic unit subtracts the offset held in the holding unit from the output of the time-digital converter, and the offset correction unit corrects the offset by selecting the output of the first arithmetic unit with the third selector when switching between the normal mode and the subsampling mode. (12) A phase-locking circuit according to any one of (1) to (11) above for performing calibration of a phase-locking loop. (13) An imaging device comprising: an imaging unit provided with a plurality of pixels; and a phase-locking circuit that generates a clock signal for setting the operating timing of the imaging unit, wherein the phase-locking circuit comprises: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal to the time-digital converter; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter.(14) An electronic circuit comprising: a circuit section that operates based on a clock signal; and a phase-synchronous circuit that generates a clock signal for setting the operating timing of the circuit section, wherein the phase-synchronous circuit comprises: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time-digital converter between the input of the time difference converted by the voltage-time converter and the input of the reference signal and the input signal; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter. 【0192】 200 ADPLL 201 Accumulator 202, 217 Arithmetic Unit 203 Loop Filter 204 Digital Controlled Oscillator 206 Counter 207 Time Domain ADC 208 Digital Time Converter 209 Control Unit 211 Sample-and-Hold Circuit 212 Voltage-Time Converter 213 Operation Mode Selector 214 Time-Digital Converter 215 Flip-Flop 216 Operation Mode Selection Selector 218 Freeze Mode Selection Selector 219 Offset Correction Unit

Claims

1. A phase-locked circuit comprising: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal to the time-digital converter; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter.

2. The phase-synchronous circuit according to claim 1, wherein the offset correction unit comprises: a holding unit that holds the output of the time digital converter as the offset; a second selector that switches between the offset and 0 and outputs the result; a first arithmetic unit that subtracts the output of the second selector from the output of the time digital converter; and a third selector that switches between the output of the first arithmetic unit and 0 and outputs the result.

3. The phase-locked circuit according to claim 2, comprising: a digital control oscillator that generates the input signal; an accumulator that sets a count-up value for each period of the reference signal based on FCW (Frequency Command Word); a counter that counts up for each period of the input signal; a second arithmetic unit that subtracts the output of the counter and the output of the third selector from the output of the accumulator; and a loop filter that band-limits the input to the digital control oscillator.

4. The phase-locked circuit according to claim 1, wherein the sample-and-hold circuit, the voltage-time converter, and the time-digital converter constitute a time-domain ADC (Analog to Digital Converter).

5. The phase-locked circuit according to claim 4, wherein the time resolution of the time-domain ADC is higher than the time resolution of the time-digital converter.

6. The phase-locked circuit according to claim 4, further comprising a frequency divider for dividing the input signal generated by the digital control oscillator.

7. The phase-locking circuit according to claim 1, further comprising a digital time converter for delaying the reference signal.

8. The phase-locking circuit according to claim 2, wherein the first selector inputs the time difference converted by the voltage-time converter to the time-digital converter when the subsampling mode is specified, and inputs the reference signal and the input signal to the time-digital converter when the normal mode is specified.

9. The phase-locked circuit according to claim 8, wherein the normal mode is operated intermittently while operating in the subsampling mode.

10. The phase-locked circuit according to claim 8, wherein the offset correction unit corrects the offset by selecting 0 with the third selector when switching between the normal mode and the subsampling mode.

11. The phase-locked circuit according to claim 8, wherein the second selector selects the offset, the first arithmetic unit subtracts the offset held in the holding unit from the output of the time digital converter, and the offset correction unit corrects the offset by selecting the output of the first arithmetic unit with the third selector when switching between the normal mode and the subsampling mode.

12. The phase-locked circuit according to claim 1, which performs calibration of the phase-locked loop.

13. An imaging device comprising: an imaging unit provided with a plurality of pixels; a phase-locking circuit that generates a clock signal for setting the operating timing of the imaging unit, wherein the phase-locking circuit comprises: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time difference converted by the voltage-time converter to the input of the reference signal and the input signal to the time-digital converter; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter.

14. An electronic circuit comprising: a circuit section that operates based on a clock signal; and a phase-synchronous circuit that generates a clock signal to set the operating timing of the circuit section, wherein the phase-synchronous circuit comprises: a sample-and-hold circuit that subsamples an input signal based on a reference signal; a voltage-time converter that converts the voltage of the input signal subsampled by the sample-and-hold circuit into a time difference; a time-digital converter that detects the time difference converted by the voltage-time converter; a first selector that switches the input of the time-digital converter between the input of the time difference converted by the voltage-time converter and the input of the reference signal and the input signal; and an offset correction unit that corrects the offset based on the switching of the first selector based on the output of the time-digital converter.

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