An unmanned aerial vehicle data link terminal integrated with interference cancellation and a control method thereof

Abstract

The application belongs to the technical field of anti-interference of wireless communication equipment, and specifically discloses an interference cancellation integrated unmanned aerial vehicle data link terminal and a control method thereof. The application integrates the interference cancellation function on the basis of the U-band data link module, so as to improve the anti-interference capability in the signal transmission process, reduce the cost, and improve the product reliability. The interference cancellation function is realized by 4-receiving and 4-transmitting radio frequency single-chip integration, and the anti-interference link and the data link use the same radio frequency link, so that the weight, power consumption and size of the equipment are greatly reduced, the integration degree is improved, and the unmanned aerial vehicle demand is met. According to the signal strength of the double antennas and the state of the interface device, the corresponding interference cancellation processing is carried out. The signal after the interference processing is transmitted to the data link terminal in the form of a radio frequency signal, and the high-speed frequency hopping system is provided with the anti-blocking interference capability.

Description

Technical Field

[0001] This application belongs to the field of anti-interference technology for wireless communication equipment, and more specifically, relates to an integrated interference cancellation UAV data link terminal and its control method. Background Technology

[0002] Data links, acting as the neural network within UAV systems, construct a network architecture within the UAV system and between the UAV system and other systems, supporting interconnection between the UAV and the command and control center, playing a crucial role. The data link communication environment is a complex electromagnetic environment, susceptible to interference from various environmental factors, particularly electromagnetic interference from jammers in practice. Existing data link systems have significant shortcomings in dealing with jamming. Analysis reveals that malicious jamming methods targeting UAV data link communication systems can be mainly categorized into three types: tracking jamming, deceptive jamming, and jamming jamming. Jamming jammers transmit high-power, broadband noise signals to cover the target's communication frequency band. Since data link terminals typically use omnidirectional antennas for communication, these antennas cannot effectively distinguish between jamming and useful signals in space, resulting in the indiscriminate reception of high-intensity interference noise, thus drowning out useful signals. This can lead to data link communication interruption, causing the entire UAV system to lose control or connection. Therefore, as a vital information transmission system in unmanned combat systems, data link systems need to improve their resistance to strong jamming and interception.

[0003] The U-band data link complements and backs up other data links, used to transmit remote control and telemetry data for UAVs, ensuring reliable telemetry and remote control during flight. The U-band data link equipment consists of airborne and ground-based data link equipment. The external interference cancellation device uses three methods: radio frequency (RF), intermediate frequency (IF), and baseband. Its output needs to be connected to the data link processor via an external interface.

[0004] However, external architectures have significant drawbacks in terms of anti-interference performance. The physical connection (cables, interfaces) between external devices and data link equipment introduces additional signal attenuation, noise coupling, and impedance mismatch, leading to a decrease in the quality of useful signals and weakening the system's receiving sensitivity. Furthermore, clock synchronization errors and signal transmission delays between independent devices are difficult to control precisely. In scenarios where the cancellation algorithm heavily relies on the spatiotemporal consistency of the reference signal and the interference signal, synchronization deviations will directly increase the cancellation residue and degrade the suppression effect. Therefore, an integrated design of data link communication and interference cancellation devices is necessary. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide an integrated interference cancellation UAV data link terminal and its control method, aiming to solve the problems of signal attenuation, noise coupling, and impedance mismatch introduced by the physical connection between external devices and data link equipment, which lead to a decrease in the quality of useful signals and a reduction in the system's receiving sensitivity.

[0006] To achieve the above objectives, in a first aspect, this application provides a data link radio frequency front-end for integrated interference cancellation, comprising:

[0007] One main antenna interface for connecting the main antenna;

[0008] Two sampling antenna interfaces are provided for connecting sampling antennas respectively;

[0009] Power interface, used to connect an external power module;

[0010] Cancellation indicator interface, used to receive cancellation start signal sent by data link processor;

[0011] The PTT interface is used to receive PTT control commands issued by the data link processor.

[0012] The baseband data interface is used for bidirectional transmission and reception with the data link processor.

[0013] The receiving sampling / transmission generation module is used to synchronously receive, amplify, digitally controlled attenuate, bandpass filter and downconvert each U-band RF signal that enters through the antenna, and output the resulting digital intermediate frequency signal to the interference cancellation processor; it is also used to upconvert the baseband IQ signal that passes through the interference cancellation processor to U-band RF, filter and amplify it, and output it through the main antenna interface.

[0014] The interference cancellation processor is used to generate a cancellation indication pulse during the pause period after receiving the cancellation start signal from the data link processor, and to form a cancellation control state machine in combination with a local timer. It is also used to digitally down-convert the three digital intermediate frequency signals from the receive sampling / transmit generation module to obtain the baseband IQ signal, execute the digital cancellation algorithm to eliminate interference components, and obtain a clean baseband IQ signal, which is then sent to the data link processor. It is also used to receive the baseband IQ signal sent by the data link processor and directly pass it through to the receive sampling / transmit generation module.

[0015] Preferably, the receiving sampling / transmission generation module includes one transmission generation link, three radio frequency receiving links, a direct sampling ADC, a detection ADC, and a monitoring unit;

[0016] The transmission generation link consists of a DAC, a filter, and an amplifier. The baseband IQ signal, which is transparently transmitted by the interference cancellation processor, is directly output by the DAC to generate one U-band radio frequency signal. The output radio frequency signal is filtered by the filter and amplified by the amplifier before being output through the main antenna interface.

[0017] The radio frequency receiving link consists of a limiter, a bandpass filter, a detector circuit, and a receiving circuit. Each U-band radio frequency signal input through the antenna passes through the limiter, bandpass filter, and coupler in sequence, with one part entering the detector circuit and the other part entering the receiving circuit.

[0018] The direct sampling ADC is used to sample the signals output by each receiving circuit and output the digital intermediate frequency signal to the interference cancellation processor.

[0019] The detector ADC is used to sample the voltage value output by the detector circuit and output a digital detector signal to the monitoring unit.

[0020] The monitoring unit is used to detect whether there is interference signal in the digital detection signal and determine its strength. Based on the strength of the detection signal, it dynamically controls the digitally controlled attenuator of the receiving circuit to control the amplitude of the received signal to prevent oversaturation, and at the same time performs equipment health monitoring.

[0021] Preferably, the receive sampling / transmit generation module is implemented using a single 4-transmit 4-receive RF SOC chip, as detailed below:

[0022] Channel resource configuration: 3 RF receiving channels process the U-band RF signals of the main antenna and dual sampling antenna respectively, with 1 receiving channel reserved for redundancy; 4 transmitting channels support diversity transmission and MIMO extension;

[0023] Hardware integration architecture: The SOC chip integrates a mixer, a programmable digital filter, an automatic gain control unit, and an MCU processor to realize down-conversion, filtering, dynamic gain adjustment, and amplitude and phase correction of the received signal;

[0024] Synchronization and delay control: All three RF receiving channels are pre-set with two-stage filters, and the delay consistency between channels is ≤5ns; they share an external carrier for synchronization and a common reference clock for synchronization to eliminate phase drift between multiple channels.

[0025] Preferably, the receiving sampling / transmission generation module incorporates a self-correcting alignment algorithm for the timing of the three received signals to compensate for PCB trace delay deviations. The specific self-correcting alignment algorithm is as follows:

[0026] Triggering conditions include sleep wake-up, external MCU instruction, SOC cycle timing > 10 minutes after power-on, or interference cancellation processor temperature drift exceeding ±5℃. If the triggering conditions are met, calibration will be started.

[0027] Delay Deviation Quantization: The delay is calibrated to the debugging interface of the interference cancellation processor. The phase deviation between the signal edge and the system reference clock is measured by the time-to-analog converter in the SOC chip. The relative deviation value with other channels is calculated based on the shortest delay channel.

[0028] Dynamic compensation execution: Based on the relative deviation value, calculate the compensation level of the programmable delay line, configure the delay control register of each channel of the interference cancellation processor, and align the timing of the three received signals.

[0029] Preferably, when there is no interference, the main digital signal and the two auxiliary digital signals are added with equal weights after analog-to-digital conversion at the RF front end; when there is interference, the main digital signal and the two auxiliary digital signals are calculated with unequal weights after analog-to-digital conversion at the RF front end. The weights are determined by the direction, power, and received RF signal, and are either positive or negative.

[0030] To achieve the above objectives, in a second aspect, this application provides an integrated interference cancellation UAV data link terminal, including one main antenna, two sampling antennas, a data link RF front-end as described in the first aspect, a data link processor, and a power module;

[0031] The interference cancellation link and the data link share the same radio frequency receiving link;

[0032] The main antenna is connected to the receive sampling / transmit generation module of the data link RF front end via the main antenna interface, and is used to receive and transmit U-band RF signals;

[0033] The sampling antenna is connected to the receiving sampling / transmission generation module of the data link RF front end via the sampling antenna interface, and is used only to receive space U-band RF interference signals;

[0034] The data link RF front end is used for receiving, digitally processing, and transmitting three U-band RF signals.

[0035] The data link processor is used to send a cancellation start signal to the interference cancellation processor after the data link transmission service ends and during the reception service protection delay, so as to trigger the interference cancellation processor to start working; it is also used to control the carrier sensing or secondary sensing of the time slot, and the data link processor enters sleep mode when there is no carrier; it is also used to receive the clean baseband IQ signal output by the interference cancellation processor for protocol demodulation; it is also used to send the baseband IQ signal to be transmitted to the interference cancellation processor for transparent transmission to the receiving sampling / transmission generation module; it is also used to respond to the health status report of the monitoring unit and execute hard bypass or soft bypass control instructions to ensure fault degradation operation; it is also used to generate idle indication pulses through the PTT control instruction rest period to drive the state machine and realize seamless transition between transmission-cancellation-reception states;

[0036] The power module is used to power the data link RF front end and the data link processor.

[0037] Preferably, each product time-domain frame used by the UAV data link terminal includes two parts:

[0038] The first part consists of 11 micro-time slots. The first two micro-time slots are for synchronization buffering, and the last nine micro-time slots are for service activation operations. When a service needs to be activated, an activation message is sent.

[0039] The second part consists of 17 time slots, each of which is divided into 17 micro-time slots TS0-TS16. TS0 is the common SOP area, and the remaining 16 time slots are allocated to 16 nodes as the service activation operation time slots for the next receiving node.

[0040] Preferably, in the TS0 time slot, the first 7 micro-time slots are the SOP information transmission listening time. If there is no carrier during this listening time, it enters sleep mode. If there is a carrier, communication begins after carrier synchronization is completed. The 8th and 9th micro-time slots are the synchronization buffer, and the 10th to 17th micro-time slots are the service transmission area.

[0041] In each of the TS1-TS16 time slots, the first 7 micro-time slots listen for whether there is a carrier in that time slot. If there is a carrier, the service is received; if there is no carrier, the service continues to sleep. The 8th and 9th micro-time slots are for synchronization buffering, and the 10th to 17th micro-time slots are for service transmission.

[0042] Preferably, the TS0 time slot is used as a sensing time slot. The data link processor determines whether there is interference. If the sensed carrier is not the pre-defined carrier, it is considered that there is interference and cancellation processing is performed. Otherwise, no cancellation processing is performed.

[0043] Preferably, the time slot management method of the data link processor is as follows:

[0044] If there are no new service requests during the protection delay after the transmission service ends, a cancellation start signal is sent to the interference cancellation processor at the start of the synchronization buffer.

[0045] The idle indication pulse is generated during the PTT control command pause period to drive the three-state control state machine of "transmit → cancel → receive";

[0046] If a valid carrier within the TS0-TS16 time slot frame is detected within the listening window, service transmission is activated; otherwise, it enters sleep mode until the next listening window.

[0047] During service transmission, frequency switching is dynamically scheduled at 40,000 hops / second; when interference exceeds the limit, a soft bypass command is issued to switch to frequency hopping anti-interference mode.

[0048] Preferably, a temperature-compensated crystal oscillator is used as the clock reference, and a CY2305 is used for clock distribution to ensure that the synchronous clocks of the receiving baseband and the transmitting baseband are from the same source.

[0049] Preferably, the amplitude, phase, and time delay of the two sampling antenna channels are consistent, and an additional switching device is added between the main antenna and the antenna interface to control the reception and transmission of radio frequency signals.

[0050] To achieve the above objectives, in a third aspect, this application provides a control method for an integrated interference cancellation UAV data link terminal as described in the second aspect, comprising:

[0051] The main antenna receives U-band radio frequency signals, and two sampling antennas receive U-band radio frequency interference signals in space. The signals received by the three antennas enter the receive sampling / transmit generation module via the main antenna interface and the sampling antenna interface, respectively. In this module, each radio frequency signal undergoes low-noise amplification, digitally controlled attenuation, bandpass filtering, and initial down-conversion processing to convert it into a digital intermediate frequency (IF) signal, which is then output to the interference cancellation processor. The interference cancellation processor performs digital down-conversion on the three digital IF signals to obtain baseband IQ signals and executes a digital cancellation algorithm to eliminate interference components, ultimately outputting a clean baseband IQ signal to the data link processor. The data link processor performs communication protocol demodulation and service processing; or...

[0052] The data link processor sends the baseband IQ signal to be transmitted to the interference cancellation processor; the interference cancellation processor passes the signal through to the receive sampling / transmit generation module; in the receive sampling / transmit generation module, the baseband IQ signal is converted by DAC, up-converted to generate a U-band radio frequency signal, and then filtered and amplified; the amplified signal is output to the main antenna through the main antenna interface and transmitted.

[0053] It is understandable that the beneficial effects of the third aspect mentioned above can be found in the relevant descriptions in the second aspect above, and will not be repeated here.

[0054] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art:

[0055] (1) This application proposes a data link RF front-end for integrated interference cancellation, which integrates interference cancellation function on the basis of U-band data link module to improve anti-interference capability during signal transmission, reduce cost and improve product reliability; the cancellation function is realized by integrating 4 receive and 4 transmit RF single chip, and the anti-interference link and the data link use the same RF link, thereby greatly reducing the weight, power consumption and size of the device, improving integration, and improving the sensitivity of U-band data link, thereby meeting the needs of UAV.

[0056] (2) This application proposes an integrated UAV data link terminal for interference cancellation, which performs corresponding interference cancellation processing based on the signal strength of the dual antennas and the status of the interface device. The signal after interference processing is transmitted to the data link terminal in the form of radio frequency signal, providing the high-speed frequency hopping system with anti-blocking interference capability. Attached Figure Description

[0057] Figure 1 This is a schematic diagram of an integrated interference cancellation UAV data link terminal structure provided in an embodiment of this application.

[0058] Figure 2 This is a block diagram of the receiving sampling / transmission generation module provided in the embodiments of this application.

[0059] Figure 3 This is a timing diagram illustrating the collaborative operation of the data link and canceller provided in an embodiment of this application.

[0060] Figure 4 This is a schematic diagram of the anti-interference and data link combination method provided in the embodiments of this application.

[0061] Figure 5 This is a schematic diagram of the improved time-domain frame structure of the next-generation self-organizing network protocol provided in the embodiments of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0063] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.

[0064] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0065] In this application, the term "electrical connection" can refer to a direct circuit connection or a signal transmission via a communication protocol.

[0066] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0067] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0068] For ease of understanding, the English abbreviations and related technical terms used in the embodiments of this application will be explained and described below.

[0069] U-band refers to the Ultra High Frequency (UHF) band, with a frequency range of approximately 300 MHz to 3 GHz.

[0070] A U-band data link is a communication link that uses U-band (ultra-high frequency) radio frequencies to transmit data. It is mainly used for data transmission between UAVs and ground control stations, between UAVs, or between UAVs and other systems (such as satellites, relay stations, etc.).

[0071] The PTT interface stands for "Push-To-Talk" interface. It is an interface used to control the transmitter to turn on and off. Its main function is that when the user presses the PTT button, the device switches from receive mode to transmit mode, and releasing the button switches back to receive mode.

[0072] IQ signaling is an important signal processing method, widely used in signal modulation and demodulation. An IQ signal consists of two parts: an I (In-phase) signal and a Q (Quadrature) signal.

[0073] Transparent transmission means that the content and format of the signal remain unchanged during transmission, and the processing of the signal during transmission is transparent. In other words, the signal will not be parsed, modified, or re-encapsulated during transmission.

[0074] Direct output means that the signal is output directly after it is generated, without any additional processing or conversion.

[0075] The embodiments of this application are described below with reference to the accompanying drawings.

[0076] Firstly, such as Figure 1As shown, this application provides a data link RF front-end for integrated interference cancellation, including: one main antenna interface, two sampling antenna interfaces, a power interface, a cancellation indicator interface, a PTT interface, a baseband data interface, a receive sampling / transmit generation module, and an interference cancellation processor.

[0077] One main antenna interface for connecting the main antenna.

[0078] Two sampling antenna interfaces are provided for connecting sampling antennas respectively.

[0079] Power interface, used to connect an external power module.

[0080] The cancellation instruction interface is used to receive the cancellation start signal issued by the data link processor.

[0081] The PTT interface is used to receive PTT control commands issued by the data link processor.

[0082] The baseband data interface is used for bidirectional transmission and reception with the data link processor.

[0083] The receiving sampling / transmission generation module is used to synchronously receive, amplify, digitally controlled attenuate, bandpass filter, and perform initial downconversion processing on each U-band RF signal entering through the antenna, and output the resulting digital intermediate frequency signal to the interference cancellation processor; it is also used to upconvert the baseband IQ signal passed through the interference cancellation processor to the U-band RF, filter and amplify it, and output it through the main antenna interface.

[0084] The interference cancellation processor is used to generate a cancellation indication pulse during the pause period after receiving the cancellation start signal from the data link processor, and to form a cancellation control state machine in combination with a local timer. It is also used to digitally down-convert the three digital intermediate frequency signals from the receive sampling / transmit generation module to obtain the baseband IQ signal, execute the digital cancellation algorithm to eliminate interference components, and obtain a clean baseband IQ signal, which is then sent to the data link processor. It is also used to receive the baseband IQ signal sent by the data link processor and directly pass it through to the receive sampling / transmit generation module.

[0085] Preferably, such as Figure 2 As shown, the receiving sampling / transmission generation module includes one transmission generation link, three radio frequency receiving links, a direct sampling ADC (analog-to-digital converter), a detection ADC, and a monitoring unit.

[0086] The transmission generation link consists of a DAC (digital-to-analog converter), a filter, and an amplifier. The baseband IQ signal, which is passed through the interference cancellation processor, is directly output by the DAC to generate one U-band radio frequency signal. The output radio frequency signal is filtered by the filter and amplified by the amplifier before being output through the antenna interface.

[0087] The radio frequency receiving link consists of a limiter, a bandpass filter, a detector circuit, and a receiving circuit. Each U-band radio frequency signal input through the antenna passes through the limiter, bandpass filter, and coupler in sequence, with one part entering the detector circuit and the other part entering the receiving circuit.

[0088] The direct sampling ADC is used to sample the signals output by each receiving circuit and output the digital intermediate frequency signal to the interference cancellation processor.

[0089] The detector ADC is used to sample the voltage value output by the detector circuit and output a digital detector signal to the monitoring unit.

[0090] The monitoring unit is used to detect whether there is interference signal in the digital detection signal and determine its strength. Based on the strength of the detection signal, it dynamically controls the digitally controlled attenuator of the receiving circuit to control the amplitude of the received signal to prevent oversaturation, and at the same time performs equipment health monitoring.

[0091] Optionally, each detection circuit consists of a detector and an operational amplifier connected in series, used to detect the amplitude of the input signal and perform gain control by detecting the signal amplitude to realize the AGC (Automatic Gain Control) function.

[0092] Optionally, each receiving circuit consists of a digitally controlled attenuator, a filter, a digitally controlled attenuator, and a low-noise amplifier connected in series.

[0093] Preferably, the monitoring unit includes: a remote control module for monitoring the working status of each module of the interference cancellation device and outputting the monitoring results to the display and control module to realize the remote health monitoring function of the equipment; and a display and control module for receiving user settings and controlling the hard bypass, soft bypass and cancellation functions of the interference cancellation processing device.

[0094] This application proposes to replace the data link interference cancellation link by redesigning a high dynamic mixed-signal RF transceiver SOC (System-on-Chip) chip, such as... Figure 2The portion within the red dashed box is shown. It includes a mixer, PLL (phase-locked loop), AD / DA (analog-to-digital converter / digital-to-analog converter), and digital correction processing algorithms. The design with four transmit channels and four receive channels better suits the communication needs of specialized applications. It features high performance, high linearity, and high dynamic range. Internally, it integrates an AGC, a programmable FIR (finite impulse response filter), and an MCU processor (microcontroller), simplifying user-end development and supporting customized RF functions. External interfaces support 204B, LVDS (low voltage differential signaling), and CMOS, facilitating interconnection with peripherals of various performance and interface types. A self-calibrating alignment algorithm for I / O interface timing is also included, reducing the complexity of on-board routing design in larger systems.

[0095] Preferably, the receiving sampling / transmitting generation module is implemented using a single 4-transmit 4-receive RF SOC chip, as follows: (1) Channel resource configuration: 3 RF receiving channels process the U-band RF signals of the main antenna and dual sampling antenna respectively, and 1 receiving channel is reserved for redundancy; 4 transmitting channels support diversity transmission and MIMO extension; (2) Hardware integration architecture: The SOC chip integrates a mixer, programmable digital filter, automatic gain control unit and MCU processor to realize down-conversion, filtering, dynamic gain adjustment and digital signal amplitude and phase correction of the received signal; (3) Synchronization and delay control: all three RF receiving channels are pre-set with two-stage filters, and the delay consistency between channels is ≤5ns; the external carrier synchronization and the reference clock synchronization are shared to eliminate phase drift between multiple channels.

[0096] Preferably, the receiving sampling / transmission generation module incorporates a self-correcting alignment algorithm for the timing of the three received signals to compensate for PCB (printed circuit board) trace delay deviations.

[0097] The self-calibration alignment algorithm is as follows: (1) Triggering conditions include sleep wake-up, external MCU instruction, SOC cycle timing > 10 minutes after power-on or interference cancellation processor temperature drift exceeding ±5℃. If the triggering conditions are met, calibration is started; (2) Delay deviation quantization: calibrate the delay to the interference cancellation processor debugging interface, measure the phase deviation between the signal edge and the system reference clock through the time-to-analog converter in the SOC chip, and calculate the relative deviation value with other channels based on the shortest delay channel; (3) Dynamic compensation execution: calculate the compensation level of the programmable delay line based on the relative deviation value, configure the delay control register of each channel of the interference cancellation processor, and align the timing of the three received signals.

[0098] Preferably, when there is no interference, the main digital signal and the two auxiliary digital signals are added with equal weights after analog-to-digital conversion at the RF front end; when there is interference, the main digital signal and the two auxiliary digital signals are calculated with unequal weights after analog-to-digital conversion at the RF front end. The weights are determined by the direction, power, and received RF signal, and can be positive or negative.

[0099] In one illustrated embodiment, the main digital signal is The two auxiliary digital signals are respectively and Without interference, X = A + B + C; with interference, Weight and Same or different.

[0100] Secondly, such as Figure 1 As shown, this application provides an integrated interference cancellation UAV data link terminal, including one main antenna, two sampling antennas, a data link RF front-end as described in the first aspect, a data link processor, and a power module.

[0101] The interference cancellation link and the data link share the same radio frequency receiving link.

[0102] The main antenna is connected to the receive sampling / transmit generation module of the data link RF front end via the main antenna interface, and is used to receive and transmit U-band RF signals.

[0103] The sampling antenna is connected to the receive sampling / transmit generation module of the data link RF front end via the sampling antenna interface, and is used only to receive space U-band RF interference signals.

[0104] The data link RF front end is used for receiving, digitally processing, and transmitting three U-band RF signals.

[0105] The data link processor is used to send a cancellation start signal to the interference cancellation processor after the data link transmission service ends and during the reception service protection delay, so as to trigger the interference cancellation processor to start working; it is also used to control the carrier sensing or secondary sensing of the time slot, and the data link processor enters sleep mode when there is no carrier; it is also used to receive the clean baseband IQ signal output by the interference cancellation processor for protocol demodulation; it is also used to send the baseband IQ signal to be transmitted to the interference cancellation processor for transparent transmission to the receiving sampling / transmission generation module; it is also used to respond to the health status report of the monitoring unit and execute hard bypass or soft bypass control instructions to ensure fault degradation operation; it is also used to generate idle indication pulses through the PTT control instruction rest period to drive the state machine and realize seamless transition between transmission-cancellation-reception states.

[0106] The power module is used to power the data link RF front end and the data link processor.

[0107] Based on the above, this application provides a control method for an integrated interference cancellation UAV data link terminal, comprising:

[0108] (1) The main antenna receives U-band radio frequency signals, and the two sampling antennas receive U-band radio frequency interference signals in space. The signals received by the three antennas enter the receiving sampling / transmission generation module through the main antenna interface and the sampling antenna interface. In the receiving sampling / transmission generation module, each radio frequency signal is sequentially amplified by low noise, digitally controlled attenuation, bandpass filtering and first down-conversion processing, converted into digital intermediate frequency signals, and output to the interference cancellation processor. The interference cancellation processor performs digital down-conversion on the three digital intermediate frequency signals to obtain baseband IQ signals, and executes digital cancellation algorithm to eliminate interference components. Finally, it outputs pure baseband IQ signals to the data link processor. The data link processor performs communication protocol demodulation and service processing.

[0109] (2) The data link processor sends the baseband IQ signal to be transmitted to the interference cancellation processor → The interference cancellation processor transmits the signal to the receiving sampling / transmission generation module → In the receiving sampling / transmission generation module, the baseband IQ signal is converted by DAC and up-converted to generate a U-band radio frequency signal, which is then filtered and amplified by power → The amplified signal is output to the main antenna through the main antenna interface and transmitted.

[0110] It should be noted that, to achieve the anti-interference function of the U-band digital transceiver component, its anti-interference requirement is to suppress two U-band radio frequency interference signals. The number of sampling antennas needs to be the same as the number of interference signals; therefore, two sampling antennas are required to collect signals. The sampling antennas, together with the main antenna, collect both useful and interference signals. After signal acquisition and digital processing, the data link baseband IQ signal is obtained. Due to the path difference between the main antenna and the sampling antennas, the received radio frequency signals have different phases.

[0111] In the field of unmanned aerial vehicles (UAVs), the product's time-domain frame structure typically refers to the time-series structure of data transmission in a UAV communication system. It defines how data is organized and transmitted over time. This frame structure is part of the communication protocol and is used to ensure efficient and reliable data transmission between the UAV and ground control stations or other nodes.

[0112] Preferably, such as Figure 5As shown, each product time-domain frame used by the UAV data link terminal consists of two parts: the first part consists of 11 micro-time slots, the first 2 micro-time slots are for synchronization buffers, and the last 9 micro-time slots are for service activation operations, which are sent when there is a service need; the second part consists of 17 time slots, each time slot is divided into 17 micro-time slots TS0-TS16, TS0 is the common SOP area (common standard operating procedure area), and the remaining 16 time slots are allocated to 16 nodes respectively as the service activation operation time slots for the next receiving node.

[0113] In the absence of voice reservations, the other time slots are used for random data transmission. In the presence of voice reservations, the first voice call is reserved starting from TS1, the second voice call starts from the time slot following the reservation of the first voice call, the third voice call starts from the time slot following the reservation of the second voice call, and the remaining time slots are used for data transmission.

[0114] Preferably, in the TS0 time slot, the first 7 micro-time slots are the SOP information transmission listening time. If there is no carrier during this listening time, it enters sleep mode. If there is a carrier, communication begins after carrier synchronization is completed. The 8th and 9th micro-time slots are the synchronization buffer, and the 10th to 17th micro-time slots are the service transmission area. In each time slot of TS1-TS16, the first 7 micro-time slots are used to listen for whether there is a carrier in that time slot. If there is a carrier, the service is received. If there is no carrier, it continues to sleep. The 8th and 9th micro-time slots are the synchronization buffer, and the 10th to 17th micro-time slots are the service transmission area.

[0115] Preferably, the TS0 time slot is used as a sensing time slot. The data link processor determines whether there is interference. If the sensed carrier is not the pre-defined carrier, it is considered that there is interference and cancellation processing is performed. Otherwise, no cancellation processing is performed.

[0116] Preferably, the time slot management method of the data link processor is as follows: 1) During the protection delay after the transmission service ends (0.83ms before the listening window), if there is no new service request, a cancellation start signal is sent to the interference cancellation processor at the start of the synchronization buffer; 2) An idle indication pulse is generated using the PTT control instruction rest period to drive the "transmit → cancel → receive" three-state control state machine; 3) If a valid carrier is detected within the listening window, the service transmission is activated; otherwise, it enters sleep mode until the next time slot listening window.

[0117] Preferably, during service transmission, frequency switching is dynamically scheduled at 40,000 hops / second; when interference exceeds the limit (Received Signal Strength Indication RSSI > 30dBm), a soft bypass command is issued to switch to frequency hopping anti-interference mode.

[0118] Frequency hopping anti-interference mode is a communication technology that resists interference by rapidly changing the carrier frequency. Its working principle is as follows: (1) Frequency hopping sequence: A frequency hopping sequence is predefined, which determines the hopping order of the carrier frequency. (2) Fast hopping: During communication, the carrier frequency hops rapidly according to the frequency hopping sequence, usually completing a hop in milliseconds or less. (3) Synchronization: The receiver needs to use the same frequency hopping sequence as the transmitter and maintain synchronization in order to correctly demodulate the signal. (4) Spread spectrum: Frequency hopping technology achieves the spread spectrum effect by dispersing signal energy on multiple frequencies, thereby improving anti-interference capability.

[0119] Preferably, a temperature-compensated crystal oscillator is used as the clock reference, and a CY2305 is used for clock distribution to ensure that the synchronous clocks of the receiving baseband and the transmitting baseband are from the same source.

[0120] Preferably, the amplitude, phase, and time delay of the two sampling antenna channels are consistent, and an additional switching device is added between the main antenna and the antenna interface to control the reception and transmission of radio frequency signals.

[0121] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0122] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0123] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0124] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0125] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A data link radio frequency front-end for integrated interference cancellation, characterized in that, include: One main antenna interface for connecting the main antenna; Two sampling antenna interfaces are provided for connecting sampling antennas respectively; Power interface, used to connect an external power module; Cancellation indicator interface, used to receive cancellation start signal sent by data link processor; The PTT interface is used to receive PTT control commands issued by the data link processor. The baseband data interface is used for bidirectional transmission and reception with the data link processor. The receiving sampling / transmission generation module is used to synchronously receive, amplify, digitally controlled attenuate, bandpass filter and first down-convert each U-band radio frequency signal that enters through the antenna, and output the resulting digital intermediate frequency signal to the interference cancellation processor. It is also used to upconvert the baseband IQ signal that has been passed through the interference cancellation processor to the U-band radio frequency, and after filtering and amplification, output it through the main antenna interface; The interference cancellation processor is used to generate a cancellation indication pulse during the pause period after receiving the cancellation start signal from the data link processor, and combine it with the local timer to form a cancellation control state machine. It is also used to digitally downconvert the three digital intermediate frequency signals from the receiving sampling / transmission generation module to obtain baseband IQ signals, and after performing a digital cancellation algorithm to eliminate interference components, a clean baseband IQ signal is obtained and sent to the data link processor; it is also used to receive the baseband IQ signal sent by the data link processor and directly pass it through to the receiving sampling / transmission generation module.

2. The data link RF front-end as described in claim 1, characterized in that, The receiving sampling / transmission generation module includes one transmission generation link, three radio frequency receiving links, a direct sampling ADC, a detection ADC, and a monitoring unit; The transmission generation link consists of a DAC, a filter, and an amplifier. The baseband IQ signal, which is transparently transmitted by the interference cancellation processor, is directly output by the DAC to generate one U-band radio frequency signal. The output radio frequency signal is filtered by the filter and amplified by the amplifier before being output through the main antenna interface. The radio frequency receiving link consists of a limiter, a bandpass filter, a detector circuit, and a receiving circuit. Each U-band radio frequency signal input through the antenna passes through the limiter, bandpass filter, and coupler in sequence, with one part entering the detector circuit and the other part entering the receiving circuit. The direct sampling ADC is used to sample the signals output by each receiving circuit and output the digital intermediate frequency signal to the interference cancellation processor. The detector ADC is used to sample the voltage value output by the detector circuit and output a digital detector signal to the monitoring unit. The monitoring unit is used to detect whether there is interference signal in the digital detection signal and determine its strength. Based on the strength of the detection signal, it dynamically controls the digitally controlled attenuator of the receiving circuit to control the amplitude of the received signal to prevent oversaturation, and at the same time performs equipment health monitoring.

3. The data link RF front-end as described in claim 2, characterized in that, The receive sampling / transmit generation module is implemented using a single 4-transmit 4-receive RF SOC chip, as detailed below: Channel resource configuration: 3 RF receiving channels process the U-band RF signals of the main antenna and dual sampling antenna respectively, with 1 receiving channel reserved for redundancy; 4 transmitting channels support diversity transmission and MIMO extension; Hardware integration architecture: The SOC chip integrates a mixer, a programmable digital filter, an automatic gain control unit, and an MCU processor to realize down-conversion, filtering, dynamic gain adjustment, and amplitude and phase correction of the received signal; Synchronization and delay control: All three RF receiving channels are pre-set with two-stage filters, and the delay consistency between channels is ≤5ns; they share an external carrier for synchronization and a common reference clock for synchronization to eliminate phase drift between multiple channels.

4. The data link RF front-end as described in claim 3, characterized in that, The receiving sampling / transmission generation module incorporates a self-correcting alignment algorithm for the timing of the three received signals to compensate for PCB trace delay deviations. The specific self-correcting alignment algorithm is as follows: Triggering conditions include sleep wake-up, external MCU instruction, SOC cycle timing > 10 minutes after power-on, or interference cancellation processor temperature drift exceeding ±5℃. If the triggering conditions are met, calibration will be started. Delay Deviation Quantization: The delay is calibrated to the debugging interface of the interference cancellation processor. The phase deviation between the signal edge and the system reference clock is measured by the time-to-analog converter in the SOC chip. The relative deviation value with other channels is calculated based on the shortest delay channel. Dynamic compensation execution: Based on the relative deviation value, calculate the compensation level of the programmable delay line, configure the delay control register of each channel of the interference cancellation processor, and align the timing of the three received signals.

5. The data link RF front-end as described in claim 1, characterized in that, When there is no interference, the interference cancellation processor performs analog-to-digital conversion on the RF front end, and then adds the main digital signal and the two auxiliary digital signals with equal weights. When there is interference, the RF front end performs analog-to-digital conversion on the RF front end, and then calculates the main digital signal and the two auxiliary digital signals with unequal weights. The weights are determined by the direction, power, and received RF signal, and can be positive or negative.

6. A UAV data link end unit integrating interference cancellation, characterized in that, It includes one main antenna, two sampling antennas, a data link RF front-end as described in any one of claims 1 to 5, a data link processor, and a power module; The interference cancellation link and the data link share the same radio frequency receiving link; The main antenna is connected to the receive sampling / transmit generation module of the data link RF front end via the main antenna interface, and is used to receive and transmit U-band RF signals; The sampling antenna is connected to the receiving sampling / transmission generation module of the data link RF front end via the sampling antenna interface, and is used only to receive space U-band RF interference signals; The data link RF front end is used for receiving, digitally processing, and transmitting three U-band RF signals. The data link processor is used to send a cancellation start signal to the interference cancellation processor after the data link transmission service ends and during the reception service protection delay, so as to trigger the interference cancellation processor to start working; it is also used to control the carrier sensing or secondary sensing of the time slot, and the data link processor enters sleep mode when there is no carrier; it is also used to receive the clean baseband IQ signal output by the interference cancellation processor for protocol demodulation; it is also used to send the baseband IQ signal to be transmitted to the interference cancellation processor for transparent transmission to the receiving sampling / transmission generation module; it is also used to respond to the health status report of the monitoring unit and execute hard bypass or soft bypass control instructions to ensure fault degradation operation; it is also used to generate idle indication pulses through the PTT control instruction rest period to drive the state machine and realize seamless transition between transmission-cancellation-reception states; The power module is used to power the data link RF front end and the data link processor.

7. The UAV data link terminal as described in claim 6, characterized in that, Each product time-domain frame used by the UAV data link terminal includes two parts: The first part consists of 11 micro-time slots. The first two micro-time slots are for synchronization buffering, and the last nine micro-time slots are for service activation operations. When a service needs to be activated, an activation message is sent. The second part consists of 17 time slots, each of which is divided into 17 micro-time slots TS0-TS16. TS0 is the common SOP area, and the remaining 16 time slots are allocated to 16 nodes as the service activation operation time slots for the next receiving node.

8. The UAV data link terminal as described in claim 7, characterized in that, In the TS0 time slot, the first 7 micro-time slots are the SOP information transmission listening time. If there is no carrier during this listening time, it will enter sleep mode. If there is a carrier, communication will begin after carrier synchronization is completed. The 8th and 9th micro-time slots are the synchronization buffer, and the 10th to 17th micro-time slots are the service transmission area. In each of the TS1-TS16 time slots, the first 7 micro-time slots listen for whether there is a carrier in that time slot. If there is a carrier, the service is received; if there is no carrier, the service continues to sleep. The 8th and 9th micro-time slots are for synchronization buffering, and the 10th to 17th micro-time slots are for service transmission.

9. The UAV data link terminal as described in claim 8, characterized in that, The TS0 time slot is used as a sensing time slot. The data link processor determines whether there is interference. If the sensed carrier is not the pre-defined carrier, it is considered to be interfering and cancellation processing is performed. Otherwise, no cancellation processing is performed.

10. The UAV data link terminal as described in claim 8, characterized in that, The time slot management method of the data link processor is as follows: If there are no new service requests during the protection delay after the transmission service ends, a cancellation start signal is sent to the interference cancellation processor at the start of the synchronization buffer. The idle indicator pulse is generated during the PTT control command pause period to drive the "transmit → cancel → receive" three-state control state machine; If a valid carrier within the TS0-TS16 time slot frame is detected within the listening window, service transmission is activated; otherwise, it enters sleep mode until the next listening window. During service transmission, frequency switching is dynamically scheduled at 40,000 hops / second; when interference exceeds the limit, a soft bypass command is issued to switch to frequency hopping anti-interference mode.

11. The UAV data link terminal as described in claim 6, characterized in that, A temperature-compensated crystal oscillator is used as the clock reference, and a CY2305 is used for clock distribution to ensure that the synchronous clocks of the receiving baseband and the transmitting baseband are from the same source.

12. The UAV data link terminal as described in claim 6, characterized in that, The amplitude, phase, and time delay of the two sampling antenna channels are consistent. An additional switching device is added between the main antenna and the antenna interface to control the reception and transmission of radio frequency signals.

13. A control method for an integrated interference cancellation UAV data link terminal as described in any one of claims 6 to 12, characterized in that, include: The main antenna receives U-band radio frequency signals, and the two sampling antennas receive U-band radio frequency interference signals in space. The signals received by the three antennas enter the receive sampling / transmit generation module via the main antenna interface and the sampling antenna interface, respectively. In this module, each RF signal undergoes low-noise amplification, digitally controlled attenuation, bandpass filtering, and initial down-conversion processing to convert it into a digital intermediate frequency signal, which is then output to the interference cancellation processor. The cancellation processor performs digital down-conversion on the three digital intermediate frequency signals to obtain the baseband IQ signal, and executes a digital cancellation algorithm to eliminate interference components, finally outputting a clean baseband IQ signal to the data link processor. The data link processor performs communication protocol demodulation and business processing; or... The data link processor sends the baseband IQ signal to be transmitted to the interference cancellation processor; the interference cancellation processor passes the signal through to the receive sampling / transmit generation module; in the receive sampling / transmit generation module, the baseband IQ signal is converted by DAC, up-converted to generate a U-band radio frequency signal, and then filtered and amplified; the amplified signal is output to the main antenna through the main antenna interface and transmitted.

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