Data reading processing method, multi-level cache processor architecture, cache controller and device

Abstract

The application provides a data reading processing method, a multi-level cache processor architecture, a cache controller and equipment. The method is applied to the multi-level cache processor architecture. A transmission queue and a delivery queue are arranged in a first cache of the architecture. The transmission queue is used for storing return data corresponding to a first read request that is not hit in the first cache, and a return data packet is generated based on the return data and backfill requirements. The delivery queue is used for storing data requested by a second read request that is not hit in the first cache, and a return data packet is generated based on the requested data. The method comprises the following steps: in the case that the first cache receives return data corresponding to a target read request returned by a second cache, determining the request type of the target read request; in the case that it is determined that the target read request is a specific type of read request, storing target data requested by the target read request and the target read request into the delivery queue. The above method can improve the cache data reading efficiency and reduce the data reading delay.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data reading and processing method, a multi-level cache processor architecture, a cache controller, and a device. Background Technology

[0002] In a multi-level cache processor architecture, when a read / write request fails to find the required data in a certain level of cache, it needs to request the data from the next lower-level cache. This requires storing the read / write request in a transfer queue. When the required data returns from the next lower-level cache, it must wait for all requests preceding it in the transfer queue to complete before arbitrating the cache pipeline. Only after winning the pipeline can the data return operation for that read / write request be executed. This process leads to long data read latency and low data read efficiency. Summary of the Invention

[0003] Based on the above-mentioned technical problems, this application proposes a data reading and processing method, a multi-level cache processor architecture, a cache controller, and a device, which can improve cache data reading efficiency and reduce data reading latency.

[0004] The first aspect of this application provides a data reading and processing method applied to a multi-level cache processor architecture. In the first cache of the multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store the return data corresponding to a first read request that was not found in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by a second read request that was not found in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request.

[0005] The method includes:

[0006] When the first cache receives the return data corresponding to the target read request returned by the second cache, the first cache determines the request type of the target read request;

[0007] If it is determined that the target read request is a specific type of read request, the first cache obtains the target data requested by the target read request from the returned data, and stores the target data and the target read request in the delivery queue.

[0008] In some implementations, the method further includes:

[0009] If it is determined that the target read request is not the specific type of read request, the first cache stores the returned data and the target read request into the transmission queue.

[0010] In some implementations, the method further includes:

[0011] If the first cache determines that the target read request is not found in the first cache, it stores the target read request in the transmission queue;

[0012] The first cache stores the target data and the target read request into the delivery queue, including:

[0013] The first cache stores the target data in the transmission queue, and reads the target read request from the transmission queue and stores it in the transmission queue.

[0014] In some implementations, the specific type of read request includes a non-lookahead load instruction.

[0015] In some implementations, the method further includes:

[0016] If the first cache determines that the target read request is not found in the first cache, it sends a read request carrying a set identifier to the second cache; the read request is used to request the target data requested by the target read request, and the set identifier is used to indicate that the read request is the specific type of read request;

[0017] The first cache determines the request type of the target read request, including:

[0018] The first cache determines whether the target read request corresponding to the returned data carries the set identifier;

[0019] When the target read request carries the defined identifier, the first cache determines that the target read request is the specific type of read request;

[0020] Alternatively, if the target read request does not carry the set identifier, the first cache determines that the target read request is not the specific type of read request.

[0021] In some implementations, the method further includes:

[0022] If a first read request in the transmission queue and a second read request in the delivery queue simultaneously request the pipeline of the first cache, the first cache determines that the first read request or the second read request that completes its request submission preparation first wins the pipeline of the first cache.

[0023] In some implementations, the first cache uses a counter to count the number of times the pipeline wins the bid for the first cache;

[0024] The method further includes:

[0025] When the first read request in the transmission queue and the second read request in the delivery queue complete the request delivery preparation at the same time, the first cache determines whether the pipeline priority of the first cache is won by the competition between the delivery queue and the transmission queue, and determines whether the value of the counter has reached the set value.

[0026] If the pipeline that wins the first buffer in the delivery queue has a higher priority than the transmission queue, and the value of the counter has not reached the set value, the first buffer determines that the second read request in the transmission queue wins the pipeline of the first buffer;

[0027] or,

[0028] If the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and the value of the counter reaches the set value, the first cache is cleared and the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and it is determined that the first read request in the transmission queue wins the pipeline in the first cache.

[0029] or,

[0030] If the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and the value of the counter has not reached the set value, the first buffer determines that the first read request in the transmission queue wins the pipeline of the first buffer.

[0031] or,

[0032] If the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and the value of the counter reaches the set value, the first cache is cleared, the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and it is determined that the second read request in the transmission queue wins the pipeline in the first cache.

[0033] In some implementations, when the first read request in the transmission queue and the second read request in the delivery queue complete the request submission preparation at the same time, the first cache further determines whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request.

[0034] If it is determined whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request, the first cache determines that the first read request in the transmission queue wins the pipeline of the first cache, and deletes the second read request and the data corresponding to the second read request from the delivery queue.

[0035] A second aspect of this application provides a multi-level cache processor architecture. In the first cache of the multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store the return data corresponding to a first read request that was not found in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by a second read request that was not found in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request.

[0036] The multi-level cache processor architecture is configured to implement the data read processing method described above.

[0037] A third aspect of this application provides a cache controller applied to a multi-level cache processor architecture. In the first cache of the multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store return data corresponding to a first read request that was not found in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store data requested by a second read request that was not found in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request. The cache controller is configured to implement the above-described data reading processing method.

[0038] The fourth aspect of this application provides a computer device including the multi-level cache processor architecture described above, or including the cache controller described above.

[0039] The data reading processing method proposed in this application sets up a transmission queue and a delivery queue in the first cache of a multi-level cache processor architecture. The transmission queue is used to store the first read request that is missed in the first cache, and generates a return data packet corresponding to the first read request based on the returned data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by the second read request that is missed in the first cache, and generates a return data packet corresponding to the second read request based on the data requested by the second read request. Based on the above processor architecture, when the first cache receives the return data of the target read request returned by the second cache, and determines that the target read request is a specific type of read request, the first cache obtains the target data requested by the target read request from the returned data, and stores the target data and the target read request in the delivery queue. Based on the function of the delivery queue, the delivery queue only stores the target data requested by the target read request, and can directly use the target data requested by the target read request to generate the return data packet of the target read request. Therefore, the delivery queue can complete the delivery preparation work for the target read request faster than the transmission queue, thereby winning the pipeline of the first cache earlier than the transmission queue, and thus returning the target data requested by the target read request earlier. Compared to storing the target read request and its return data in a transmission queue and waiting for all requests preceding the target read request in the transmission queue to be processed before re-entering the pipeline, the above-mentioned processing provided in this application can improve the efficiency of the processor in reading data from the cache and reduce the latency of reading cached data. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application.

[0042] Figure 2 This is a schematic diagram of another multi-level cache processor architecture provided in an embodiment of this application.

[0043] Figure 3 This is a flowchart illustrating a data reading and processing method provided in an embodiment of this application. Detailed Implementation

[0044] The embodiments of this application are applicable to application scenarios where the processor reads data from the cache. By adopting the technical solutions of the embodiments of this application, the efficiency of the processor reading data from the cache can be improved and the data reading latency can be reduced.

[0045] In the hierarchical structure of a computer storage system, cache is a high-speed, small-capacity memory located between the central processing unit and main memory. It consists of static RAM chips, which have a relatively small capacity but are faster than main memory, approaching the speed of the CPU.

[0046] The working principle of caching is as follows: When the CPU needs to read data, it first searches for it in the CPU cache. If found, it reads the data immediately and sends it to the CPU for processing. If not found, it reads the data from the relatively slower main memory and sends it to the CPU for processing. Simultaneously, the data block containing this data is loaded into the cache. This allows subsequent reads of the entire data block to be performed from the cache, avoiding further access to main memory. This reading mechanism increases the CPU's cache hit rate, meaning that the data the CPU needs to read next is more likely to be in the CPU cache, with only a small amount of data needing to be read from main memory. This significantly saves the time the CPU spends directly reading from main memory and essentially eliminates waiting time when reading data.

[0047] The data in the cache is only a copy of a portion of the data in memory. Therefore, when the CPU searches for data in the cache, it may encounter situations where it cannot find the data (because some data has not been copied from memory to the cache). In this case, the CPU will still read the data from memory, thus slowing down the CPU's data read speed. However, the CPU will copy the read data into the cache for future use. Therefore, the more frequently data is accessed, the longer it remains in the cache. Furthermore, the most frequently accessed data changes over time, so the data in the cache needs to be frequently updated according to a specific algorithm to ensure that the data in the cache always represents the most frequently accessed data.

[0048] The technical solution of this application embodiment is applicable to a multi-level cache processor architecture, which includes multiple levels of cache, such as two-level cache, three-level cache, four-level cache, or any number of other cache levels.

[0049] In the multi-level cache described above, based on their distance from the processor core, the caches can be defined as Level 1 cache, Level 2 cache, Level 3 cache, and so on. The earlier the cache level, the closer it is to the processor core, and the faster the processor core can read data from it. Conversely, the later the cache level, the farther it is from the processor core, and the slower the processor core can read data from it. For example, the processor core can read data from the Level 1 cache faster than from the Level 2 cache, and from the Level 2 cache faster than from the Level 3 cache.

[0050] Generally, the earlier a cache is in the cache hierarchy, the more frequently the stored data is accessed by the processor core; conversely, the later a cache is in the cache hierarchy, the less frequently the stored data is accessed by the processor core. Furthermore, caches at earlier tiers typically have smaller storage spaces, while caches at later tiers generally have larger storage spaces.

[0051] Figure 1 This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application. In this multi-level cache processor architecture, three levels of cache are exemplarily shown, namely the first level cache L1, the second level cache L2, and the third level cache L3.

[0052] The first-level cache (L1) is further divided into instruction cache (L1I) and data cache (L1D). Instruction cache (L1I) is used to cache instructions, and data cache (L1D) is used to cache data.

[0053] The first-level cache L1 mentioned above, which includes instruction cache L1I and data cache L1D, shares the second-level cache L2.

[0054] See Figure 1 As shown, this multi-level cache processor architecture includes multiple processor cores. Each processor core is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. Multiple processor cores share a single Level 3 cache L3.

[0055] See also Figure 1 For multiple processor cores, different regions can be defined. Each processor core in each region is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. All processor cores in this region share a single Level 3 cache L3. Processor cores in multiple regions share the system main memory through an on-chip network.

[0056] In the processor architecture described above, when a LOAD instruction misses the required data in L1D, L1D sends a read request to L2 to read the data. If the data is still not found in L2, a read request is sent to L3 to read the data. If the data is still not found in L3, it needs to be read from main memory. During this process, if the required data is found in a certain level of cache, it is returned sequentially to the upper-level caches until it is returned to the processor. For example, if the data is read from L2, the cache line containing that data is returned to L1, where it is stored, and L1 then returns the cache line to the processor.

[0057] During processor operation, multiple data reads may occur consecutively within a short period. Therefore, the data reading process described above may happen continuously. For a certain level of cache, multiple read requests may be received in a short time. If multiple read requests happen to fail to find the data in the current cache, multiple read requests need to be sent to the next level of cache to obtain the corresponding data.

[0058] In the above process, in order to respond to each missed read request in an orderly manner, the missed read requests can be stored in a Transmission Queue (TQ). When the corresponding data is retrieved from the next level cache, the unfinished read requests in the Transmission Queue are then responded to.

[0059] For example, a transfer queue is set up in the second-level cache (L2). When a read request sent by L1D misses in L2, the read request is stored in the L2 transfer queue, and then a read request is sent to L3. When L3 returns the data, the read request in the transfer queue requests the pipeline in L2. When the pipeline is won, the data is fed back to L1D, completing the response processing for the read request.

[0060] In the above process, when the transmission queue stores read requests generated at different times, if L3 returns the data corresponding to a certain read request, all requests in the transmission queue that precede that read request need to be processed before it is the turn of that read request to request the L2 pipeline. This will result in a long data reading delay and low data reading efficiency.

[0061] To address the aforementioned technical problems, this application proposes a novel multi-level cache processor architecture and a data read processing method based on this architecture, which can improve the efficiency of the processor in reading data from the cache and shorten the data read latency.

[0062] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] This application first proposes a multi-level cache processor architecture, which is relative to... Figure 1 The improved architecture of the multi-level cache processor architecture shown is illustrated.

[0064] The multi-level caching architecture provided in this application includes multi-level caching, such as two-level caching, three-level caching, four-level caching, or any number of other caching levels.

[0065] As an example, see Figure 2 As shown, the multi-level cache processor architecture provided in this application embodiment includes three levels of cache, namely the first level cache L1, the second level cache L2, and the third level cache L3.

[0066] The first-level cache (L1) is further divided into instruction cache (L1I) and data cache (L1D). Instruction cache (L1I) is used to cache instructions, and data cache (L1D) is used to cache data.

[0067] The first-level cache L1 mentioned above, which includes instruction cache L1I and data cache L1D, shares the second-level cache L2.

[0068] See Figure 2 As shown, this multi-level cache processor architecture includes multiple processor cores. Each processor core is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. Multiple processor cores share a single Level 3 cache L3.

[0069] See also Figure 2 For multiple processor cores, different regions can be defined. Each processor core in each region is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. All processor cores in this region share a single Level 3 cache L3. Processor cores in multiple regions share the system main memory through an on-chip network.

[0070] In the first cache of the aforementioned multi-level cache processor architecture, both a transfer queue and a delivery queue are configured. This first cache can be any level cache in the aforementioned multi-level cache processor architecture, for example, for... Figure 2In the multi-level cache processor architecture shown, the first cache of this architecture can be the second-level cache L2. In other embodiments, the first cache of this multi-level cache processor architecture can also be the first-level cache L1 or the third-level cache L3. That is to say, in any cache of the multi-level cache processor architecture provided in this application embodiment, a pass queue and a transfer queue are set.

[0071] The transmission queue stores first read requests that missed in the first cache, as well as return data corresponding to the first read request returned by the second cache. The transmission queue generates a return data packet corresponding to the first read request based on the return data, data backfilling requirements, and formatting requirements. Specifically, when a first read request sent to the first cache misses, the first cache stores the first read request in the transmission queue and requests the requested data from the second cache. When the second cache returns the return data corresponding to the first read request, the first cache also stores the returned data in the transmission queue. When the data requested by a read request in the transmission queue is returned from the second cache, and all older requests preceding this read request have been processed, the transmission queue generates a return data packet based on the return data, data backfilling requirements, and formatting requirements of the read request. Simultaneously, it requests pipeline access from the first cache. Once pipeline access is secured, the first cache sends the return data packet corresponding to the first read request back to the requesting source, completing the response processing for the first read request.

[0072] The delivery queue is used to store second read requests that miss data in the first cache, as well as the data returned by the second cache corresponding to the second read request. It also generates a return data packet corresponding to the second read request based on the data requested by the second read request. Specifically, when a second read request sent to the first cache misses in the first cache, the second read request is stored in the delivery queue, and the second cache is requested for the data requested by the second read request. When the second cache returns the data corresponding to the second read request to the first cache, the first cache stores the second read request from the delivery queue to the delivery queue, and simultaneously retrieves the target data requested by the second read request from the return data sent by the second cache, and stores the target data directly in the delivery queue. Alternatively, when a second read request sent to the first cache misses in the first cache, the second read request is directly stored in the delivery queue; when the second cache returns the data corresponding to the second read request to the first cache, the target data requested by the second read request is retrieved from the return data sent by the second cache, and the target data is also stored in the delivery queue. When the target data requested by a read request in the delivery queue is returned from the second cache, and all older requests preceding this read request have been processed, the delivery queue generates a return data packet corresponding to the second read request based on the target data requested by the second read request. At the same time, it requests pipeline access to the first cache. Once the pipeline access is secured, the first cache sends the return data packet corresponding to the second read request back to the request source that sent the second read request, thus completing the response processing for the second read request.

[0073] In this embodiment, the second cache described above is the next level cache after the first cache. For example, when the first cache is... Figure 2 When the first level cache L1 is shown, the second cache is... Figure 2 The second-level cache (L2) shown in the diagram sends read requests to the first cache from a processor or processor core; when the first cache is... Figure 2 When the first level cache (L2) is shown, the second cache is... Figure 2 The third-level cache L3 shown in the diagram sends a read request to the first-level cache, which originates from the first-level cache L1.

[0074] In the multi-level cache processor architecture provided in this embodiment, a transmission queue and a delivery queue are set in the first cache. The transmission queue is used to store the first read request that is not hit in the first cache, and to generate a return data packet corresponding to the first read request based on the returned data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by the second read request that is not hit in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request.

[0075] The data returned by the second cache to the first cache in response to a read request typically includes the entire cache line containing the data requested by the read request. For example, the second cache might return the entire cache line containing the data requested by the read request to the first cache. Therefore, the size of the data returned by the first cache in response to a read request is usually larger than the data requested by the read request.

[0076] The transmission queue generates a return data packet corresponding to the first read request based on the returned data and the backfilling requirements associated with the first read request. Specifically, the transmission queue generates data packets for performing data backfilling and data return operations based on the returned data, according to data backfilling requirements, format requirements, etc., to meet the data return and data backfilling requirements during the cached data reading process. It is understandable that because the transmission queue needs to perform a data backfilling operation when returning data, the generated return data packet is larger, and the execution time of the data return operation is longer.

[0077] Typically, when a read request in the transmission queue returns, due to the bit width limitation of the first cache's upload port, the first cache needs two clock cycles to complete the return of data. For example, if the first cache's upload port has a bit width of 256 bits, but the data returned by the first cache is the data of an entire cacheline with a bit width of 512 bits, then it will take two clock cycles to complete the return of the entire cacheline.

[0078] Because the delivery queue only stores the data requested by the second read request and can generate the corresponding return data packet based on the data requested by the second read request without performing data backfilling or generating backfill data, the delivery queue can complete the submission preparation work corresponding to the request faster than the transmission queue. In other words, it can complete the return data packet generation operation corresponding to the read request faster. Furthermore, since the delivery queue only stores the data requested by the second read request, the return data packet it generates is smaller than the return data packet generated by the transmission queue. Compared to the read request data return in the transmission queue, the delivery queue only needs to occupy fewer ticks of the first buffer pipeline to complete the read request data return.

[0079] For example, assuming a second read request requests 64 bits of target data, the bit width of the target data requested by this second read request stored in the delivery queue is 64 bits, meaning the data to be returned is 64 bits wide. With the first cache's upload port having a bit width of 256 bits, the first cache pipeline only needs one cycle to return the 64-bit target data. Therefore, the delivery queue requires less storage space, and the second read request in the delivery queue, once it wins the pipeline in the first cache, is processed faster, occupying less of the first cache's pipeline. The delivery queue setup enables the first cache to complete read request data returns more quickly.

[0080] Based on the aforementioned multi-level cache processor architecture, another embodiment of this application provides a data read processing method applied to the aforementioned multi-level cache processor architecture. This method can be executed collaboratively by each level of cache in the aforementioned multi-level cache processor architecture, specifically by the cache controller of each level of cache. The cache controller for each level of cache can be the same cache controller, or each level of cache can be configured with a dedicated cache controller; this embodiment does not impose any limitations.

[0081] In this method, the return data corresponding to a specific type of read request can be quickly returned through a transfer queue, thereby improving the cache's response speed to specific type of read requests and enabling the processor to read the required data through specific type of read requests.

[0082] See Figure 3 As shown, the data reading and processing method provided in this application embodiment includes:

[0083] S101. When the first cache receives the return data of the corresponding target read request returned by the second cache, the first cache determines the request type of the target read request.

[0084] The aforementioned target read request refers to a read request for reading data from the first cache request and for reading data requested when the first cache misses.

[0085] In another embodiment, it is disclosed that when the first cache receives the aforementioned target read request and determines that the target read request has not been hit in the first cache, a read request is sent to the second cache to request the target data requested by the target read request from the second cache.

[0086] The second cache queries the target data requested by the target read request from the local cache. If the corresponding data is found, it returns the data to the first cache. If the corresponding data is not found, the second cache continues to request the corresponding data from the next lower level cache until the data is obtained, and then returns the data to the first cache.

[0087] For example, with Figure 2 Taking the second-level cache L2 as the first cache and the third-level cache L3 as the second cache as an example, when the second-level cache L2 receives a target read request sent by the first-level cache L1 to request the target data, it first queries the target data from the local cache data of the second-level cache L2.

[0088] If the target data is found in the local cache data of the second-level cache L2, the second-level cache L2 will send the cache line of the target data back to the first-level cache L1.

[0089] The data read by the LOAD instruction is typically less than 256 bits wide, while the data width in the L2 cache is 512 bits. Normally, when the LOAD instruction reads data from the L2 cache, it reads one cache line of data, i.e., 512 bits of data. Therefore, when the L2 cache finds the target data in its local cache, it sends the entire cache line containing that target data back to the L1 cache.

[0090] If the second-level cache L2 does not find the target data in its local cache, it means that the read request missed in the second-level cache L2. In this case, the second-level cache L2 sends a read request to the third-level cache L3 to request the read of the target data.

[0091] After receiving a read request from the second-level cache L2, the third-level cache L3 first queries the target data from the local cache. If the target data is found, it is returned to the second-level cache L2. If the target data is not found in the local cache, the third-level cache L3 reads the target data from main memory and returns it to the second-level cache L2.

[0092] When the first cache receives the return data corresponding to the target read request returned by the second cache, the first cache first determines the request type of the target read request, that is, determines whether the target read request is a specific type of read request.

[0093] Correspondingly, the aforementioned specific type of read request can be a read request corresponding to a non-look-ahead load instruction (read instruction). For example, when a load instruction issued by the processor misses in L1D, it will issue a read request to L2. This read request is a specific type of read request.

[0094] However, look-ahead read requests issued by store instructions (write instructions), such as when the processor issues look-ahead read requests before issuing certain store instructions (write instructions), do not belong to the specific type of read requests mentioned above.

[0095] In other words, in this embodiment, the processor's actual data reading request is a specific type of read request, while the processor's look-ahead read request for performing a write operation is not a specific type of read request.

[0096] In some embodiments, the first cache determines the type of a target read request by determining whether the target read request is a lookup read request issued by the processor before issuing a store instruction (write instruction). If the target read request is a lookup read request issued by the processor before issuing a store instruction (write instruction), it can be determined that the target read request is not a specific type of read request; if the target read request is not a lookup read request issued by the processor before issuing a store instruction (write instruction), or if it is determined that the target read request is a non-lookup load instruction, it can be determined that the target read request is a specific type of read request.

[0097] In another embodiment, when the first cache determines that the target read request has not been hit in the first cache, when sending a read request to the second cache for requesting the data requested by the target read request, a read request carrying a setting identifier is sent to the second cache, the setting identifier being used to indicate that the read request is the specific type of read request mentioned above.

[0098] In some embodiments, the aforementioned setting identifier can be any form of identifier, such as a symbol, keyword, etc.

[0099] Based on the above operations, when the first cache determines the request type of the target read request, it can do so by determining whether the target read request corresponding to the returned data carries the aforementioned set identifier.

[0100] If the target read request carries the aforementioned set identifier, the first cache can determine that the target read request is a specific type of read request as described above.

[0101] If the target read request does not carry the aforementioned set identifier, the first cache can determine that the target read request is not a specific type of read request.

[0102] S102. If it is determined that the target read request is the specific type of read request, the first cache obtains the target data requested by the target read request from the returned data, and stores the target data and the target read request in the transmission queue.

[0103] Specifically, through the processing of step S101, if the first cache determines that the target read request is the specific type of read request mentioned above, the first cache extracts the target data requested by the target read request from the returned data sent by the second cache (usually the data of a cache line), and stores the extracted target data and the target read request in the transmission queue in the first cache.

[0104] Once all older requests preceding the target read request in the delivery queue have been processed, the delivery queue generates a return data packet corresponding to the target read request based on the target data requested by the target read request. At the same time, it requests the pipeline of the first cache. When the pipeline is won, the first cache sends the return data packet corresponding to the target read request back to the request source that sent the target read request, thus completing the response processing for the target read request.

[0105] In processor architecture, the data width read by the load instruction is typically less than 256 bits. Therefore, the target data width stored in the transfer queue in the first cache does not exceed 256 bits. With a first cache upload port width of 256 bits, the return of the target data can be completed in one cycle of the first cache pipeline.

[0106] Data or read requests stored in the aforementioned transfer queue are arranged sequentially according to the order in which they were stored in the transfer queue, occupying the storage space of the transfer queue.

[0107] In some embodiments, when the target read request sent to the first cache misses in the first cache, the first cache stores the target read request in the delivery queue; when the second cache returns the return data corresponding to the target read request to the first cache, when the first cache determines that the target read request is a specific type of read request, the first cache obtains the target data requested by the target read request from the return data sent by the second cache, and stores the target data in the delivery queue as well.

[0108] Alternatively, in other embodiments, if the aforementioned target read request sent to the first cache misses in the first cache, the first cache stores the target read request in the transmission queue.

[0109] When the first cache receives the return data corresponding to the target read request from the second cache, if the first cache determines that the target read request is a specific type of read request, it reads the target read request from the transmission queue and stores it in the delivery queue, and obtains the target data requested by the target read request from the return data sent by the second cache, and stores the target data in the delivery queue as well.

[0110] In another embodiment, if the first cache determines that the target read request is not the specific type of read request, the first cache stores the received return data and the target read request to the transmission queue.

[0111] For example, if the target read request sent to the first cache misses in the first cache, the first cache stores the target read request in the transmission queue. When the first cache receives the return data corresponding to the target read request from the second cache, if the first cache determines that the target read request is not a specific type of read request, the first cache also stores the received return data in the transmission queue.

[0112] As described above, the data reading processing method proposed in this application sets up a transmission queue and a delivery queue in the first cache of a multi-level cache processor architecture. The transmission queue is used to store a first read request that is not hit in the first cache, and generates a return data packet corresponding to the first read request based on the returned data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by a second read request that is not hit in the first cache, and generates a return data packet corresponding to the second read request based on the data requested by the second read request. Based on the above processor architecture, when the first cache receives the return data corresponding to the target read request returned by the second cache, and determines that the target read request is a specific type of read request, the first cache obtains the target data requested by the target read request from the returned data, and stores the target data and the target read request in the delivery queue. Based on the functionality of the delivery queue, which stores only the target data requested by the target read request and can directly generate the return data packet for that target read request using that target data, the delivery queue can complete the preparation work for submitting the target read request faster than the transmission queue. This allows it to acquire the first buffer in the pipeline earlier than the transmission queue, and thus return the target data requested by the target read request earlier. Compared to storing the target read request and its return data in the transmission queue and waiting for all requests preceding it in the transmission queue to be processed before re-entering the pipeline, the processing method provided in this application improves the efficiency of the processor reading data from the cache and reduces the latency of cache data reads.

[0113] In some embodiments, pipelines that win the first buffer in the delivery queue have higher priority than pipelines in the transport queue. Therefore, when a first read request in the transport queue and a second read request in the delivery queue simultaneously request pipelines in the first buffer, the second read request in the delivery queue always wins the pipeline.

[0114] In another embodiment, when multiple second read requests are stored in the delivery queue, the second read requests in the delivery queue apply for the pipeline of the first cache in the order they enter the delivery queue. That is, the earlier a request enters the delivery queue, the earlier it applies for the pipeline of the first cache. The later a request enters the delivery queue, the later it can apply for the pipeline of the first cache only after all the requests that entered the delivery queue earlier have applied for the pipeline of the first cache.

[0115] Based on the above rules, once all requests in the delivery queue preceding the target read request have been allocated to the first cache pipeline, the target read request will begin to allocate to the first cache pipeline.

[0116] As described in the above embodiment, the data width read by the LOAD instruction is less than 256 bits, meaning the width of the return data packet corresponding to the aforementioned target read request is less than 256 bits. In the normal cache data reading process, when the first cache returns data to the request source, it returns the entire cache line. The width of a cache line is 512 bits. Since the upload port width of the first cache is limited to 256 bits, one cycle of the first cache pipeline can only return 256 bits of data. Therefore, two cycles of the first cache pipeline are required to complete the return of one cache line. However, for the aforementioned return data packet, since its width is less than 256 bits, when there is a vacancy in the first cache pipeline, the target read request can be inserted into the first cache pipeline. This allows the target read request in the delivery queue to win priority in the first cache pipeline, and the return data packet corresponding to the target read request can be returned in one cycle of the pipeline.

[0117] In other embodiments of the data reading processing method, when a first read request in the transmission queue and a second read request in the delivery queue simultaneously request the pipeline of the first buffer, the first buffer determines whether the first read request or the second read request that completes the request submission preparation first wins the pipeline of the first buffer.

[0118] Specifically, when a read request requests access to the first buffer pipeline, it begins submission preparation. Only after completing this preparation can it potentially win access to the first buffer pipeline. Therefore, when a first read request in the transmission queue and a second read request in the delivery queue simultaneously request access to the first buffer pipeline, both requests begin submission preparation simultaneously.

[0119] Because the delivery queue only stores the second read request and the data requested by it, and this data has a small bit width, typically smaller than the uplink port width, and because the delivery queue does not store backfill requirements or return requirements, a data backfill operation is not required when the second read request returns data. Therefore, no backfill preparation operation is needed, making it efficient and fast for preparing smaller data. In contrast, the transmission queue stores not only the first read request and its corresponding return data, but also backfill requirements and return requirements. Therefore, a data backfill operation is required when the first read request returns data, necessitating a backfill preparation operation from the transmission queue. Furthermore, the return data stored in the transmission queue is the data of an entire cacheline, with a larger data bit width, making it less efficient and slower for preparing larger data.

[0120] Therefore, when a first read request in the transmission queue and a second read request in the delivery queue simultaneously request the pipeline of the first cache, the second read request in the delivery queue will usually complete the request submission preparation first. At this time, the first cache will determine that the second read request that completes the request submission preparation first will win the pipeline of the first cache.

[0121] Based on the above processing mechanism, since the delivery queue only stores the second read request and the data it requests, the second read request in the delivery queue only needs to return the requested data and does not need to perform a data backfilling operation. Therefore, it does not need to perform a data backfilling preparation operation. Thus, when the second read request in the delivery queue and the first read request in the transmission queue simultaneously request the pipeline of the first buffer, the second read request in the delivery queue can always complete the request submission preparation first, and thus can win the pipeline of the first buffer first, thereby completing the data return operation faster and earlier, and improving data reading efficiency.

[0122] In another embodiment, the first buffer is further provided with a counter for counting the number of times the delivery queue or the transmission queue competes to win the pipeline of the first buffer, specifically for counting the number of times the delivery queue or the transmission queue continuously competes to win the pipeline of the first buffer.

[0123] In this embodiment, a priority can be set for the transmission queue and the delivery queue to win the first buffer pipeline. Furthermore, if a counter is used to count whether the transmission queue or the delivery queue has won the first buffer pipeline more than a set number of times, the priority setting for winning the first buffer pipeline for the transmission queue and the delivery queue is switched. This allows the transmission queue and the delivery queue to take turns winning the first buffer pipeline, preventing one of the transmission queues or the delivery queue from monopolizing the first buffer pipeline for an extended period and affecting the operation of the other queue.

[0124] In this embodiment, when a first read request in the transmission queue and a second read request in the delivery queue simultaneously request the pipeline of the first cache, the first cache determines that the first read request or the second read request that completes the request submission preparation first wins the pipeline of the first cache.

[0125] In the above process, if the first read request in the transmission queue and the second read request in the delivery queue complete the request submission preparation at the same time, the first cache determines whether the delivery queue competes with the transmission queue to win the pipeline priority of the first cache, and determines whether the value of the counter has reached the set value.

[0126] If the pipeline priority of the delivery queue winning the pipeline of the first cache is higher than that of the transmission queue, and the value of the counter has not reached the set value, that is, the number of times the delivery queue has won the pipeline of the first cache has not reached the set number, the first cache determines that the second read request in the delivery queue has won the pipeline of the first cache. That is, at this time, the second read request in the delivery queue can continue to be allowed to win the pipeline of the first cache.

[0127] If the pipeline priority of the delivery queue winning the first cache is higher than that of the transport queue, and the counter value reaches the set value (i.e., the number of times the delivery queue has won the first cache pipeline priority has reached the set number), then the first cache clears the counter and sets the priority of the transport queue winning the first cache pipeline priority to higher than that of the delivery queue. This essentially switches the priorities of the transport queue and the delivery queue winning the first cache pipeline priority. At this point, the first cache determines that the first read request in the transport queue has won the first cache pipeline. In subsequent processes, the counter is used to count the number of times the transport queue has won the first cache pipeline priority.

[0128] If the priority of the pipeline that the transmission queue wins over the first cache is higher than that of the transmission queue, and the value of the counter has not reached the set value, that is, the number of times the transmission queue has won the pipeline of the first cache has not reached the set number, then the first cache determines that the first read request in the transmission queue has won the pipeline of the first cache. In other words, the first read request in the transmission queue can continue to be allowed to win the pipeline of the first cache.

[0129] If the transmission queue wins the pipeline priority of the first cache with a higher priority than the delivery queue, and the counter value reaches the set value (i.e., the number of times the transmission queue has won the pipeline priority of the first cache has reached the set number), then the first cache clears the counter and sets the priority of the delivery queue winning the pipeline priority of the first cache to higher priority than the transmission queue. In other words, the priorities of the transmission queue and the delivery queue winning the pipeline priority of the first cache are switched. At this time, the first cache determines that the second read request in the delivery queue has won the pipeline priority of the first cache. In subsequent processes, the counter is used to count the number of times the transmission queue has won the pipeline priority of the first cache.

[0130] Based on the above scheme of this embodiment, the transmission queue and the delivery queue can take turns to win the pipeline of the first buffer, thereby avoiding any queue from occupying the pipeline of the first buffer for a long time and ensuring the normal operation of the first buffer globally.

[0131] In another embodiment, when the first read request in the transmission queue and the second read request in the delivery queue complete the request submission preparation at the same time, the first cache further determines whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request;

[0132] If it is determined whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request, the first cache determines that the first read request in the transmission queue wins the pipeline of the first cache, and deletes the second read request and the data corresponding to the second read request from the delivery queue.

[0133] Specifically, in this embodiment, when a read request misses in the first cache, it is stored in the transmission queue, and then the data requested by the read request is retrieved from the second cache. When the second cache returns the data corresponding to the read request, the returned data is stored in the transmission queue. Furthermore, if it is determined that the read request is a specific type of read request, both the read request and the data requested by the read request are stored in the delivery queue. Therefore, when a specific type of read request misses in the first cache, the read request is simultaneously stored in both the transmission queue and the delivery queue.

[0134] Based on the above processing mechanism, when the first read request in the transmission queue and the second read request in the delivery queue simultaneously request the pipeline of the first buffer, it is possible that the first read request in the transmission queue and the second read request in the delivery queue complete the request submission preparation at the same time, and the first read request and the second read request may be the same read request.

[0135] In this scenario, the first cache determines that the first read request in the transmission queue wins the pipeline of the first cache, meaning the transmission queue performs data return and data backfilling operations to ensure cache data consistency as much as possible. At this point, the first cache deletes the second read request and its corresponding data from the transmission queue. That is, while the transmission queue is performing data return and data backfilling operations for this read request, the read request and its requested data in the transmission queue no longer need to be returned; they can simply be deleted.

[0136] In another embodiment, it is disclosed that when a first read request in the transmission queue and a second read request in the delivery queue request the pipeline of the first buffer, the pipeline arbitration request carries the queue allocation item information.

[0137] Once the first read request in the transmission queue or the second read request in the delivery queue wins the pipeline for the first buffer, when the pipeline needs to read data, it matches the corresponding queue item based on the item information in the pipeline arbitration request, reads the corresponding data, and then performs a data return operation. This processing method does not require carrying actual data through the pipeline, thus reducing power consumption.

[0138] Another embodiment of this application provides a multi-level cache processor architecture. In the first cache of this multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store the return data corresponding to a first read request that is not hit in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by a second read request that is not hit in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request. The multi-level cache processor architecture is configured to implement the data reading processing method described in any of the above embodiments.

[0139] In some embodiments, the specific structure of the provided multi-level cache processor architecture is as follows: Figure 2 The structure shown.

[0140] Another embodiment of this application provides a cache controller applied to a multi-level cache processor architecture. In the first cache of the multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store return data corresponding to a first read request that was not found in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store data requested by a second read request that was not found in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request. The cache controller is configured to implement the data reading processing method described in any of the above embodiments.

[0141] The aforementioned cache controller can be a cache controller used to control data read and write operations in the first cache, in which case it can be a cache controller set in the first cache. Alternatively, the aforementioned cache controller can also be a cache controller used to control multi-level caches, in which case the cache controller can be set in any level of cache in the multi-level cache processor architecture, or set outside of any level of cache.

[0142] Another embodiment of this application provides a computer device that includes the multi-level cache processor architecture described above, or includes the cache controller described above.

[0143] The computer device can specifically be a personal computer, an industrial computer, a server, a smart terminal, a wearable device, etc.

[0144] Another embodiment of this application provides a data reading and processing apparatus, which can be applied to a multi-level cache processor architecture. In the first cache of the multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store the return data corresponding to a first read request that is not hit in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by a second read request that is not hit in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request.

[0145] The data reading and processing device can be applied to the aforementioned first cache, and the data reading and processing device includes:

[0146] The first processing unit is configured to determine the request type of the target read request when the first cache receives return data corresponding to the target read request returned by the second cache;

[0147] The second processing unit is configured to, when determining that the target read request is a specific type of read request, obtain the target data requested by the target read request from the returned data, and store the target data and the target read request into the transmission queue.

[0148] In some implementations, the second processing unit is further configured to:

[0149] If it is determined that the target read request is not the specific type of read request, the returned data and the target read request are stored in the transmission queue.

[0150] In some implementations, the second processing unit is further configured to:

[0151] If it is determined that the target read request is not found in the first cache, the target read request is stored in the transmission queue;

[0152] The second processing unit stores the target data and the target read request into the transmission queue, including:

[0153] The target data is stored in the transmission queue, and the target read request is read from the transmission queue and stored in the transmission queue.

[0154] In some implementations, the specific type of read request includes a non-lookahead load instruction.

[0155] In some implementations, the apparatus further includes:

[0156] A request sending unit is configured to send a read request carrying a set identifier to the second cache when the target read request is not found in the first cache; the read request is used to request the target data requested by the target read request, and the set identifier is used to indicate that the read request is a specific type of read request;

[0157] The first processing unit determines the request type of the target read request, including:

[0158] Determine whether the target read request corresponding to the returned data carries the set identifier;

[0159] If the target read request carries the set identifier, the target read request is determined to be the specific type of read request;

[0160] Alternatively, if the target read request does not carry the set identifier, it can be determined that the target read request is not the specific type of read request.

[0161] In some implementations, the apparatus further includes:

[0162] An arbitration processing unit is configured to determine, in the event that a first read request in the transmission queue and a second read request in the delivery queue simultaneously request the pipeline of the first cache, whether the first read request or the second read request that completes its request submission preparation first wins the pipeline of the first cache.

[0163] In some implementations, the apparatus further includes a counter for counting the number of times the pass queue or the transmission queue competes to win the pipeline of the first buffer;

[0164] The arbitration processing unit is also used for:

[0165] If the first read request in the transmission queue and the second read request in the delivery queue complete the request delivery preparation at the same time, it is determined that the delivery queue competes with the transmission queue to win the pipeline priority of the first buffer, and it is determined whether the value of the counter has reached the set value.

[0166] If the pipeline that wins the first buffer in the delivery queue has a higher priority than the transmission queue, and the value of the counter has not reached the set value, it is determined that the second read request in the transmission queue wins the pipeline in the first buffer.

[0167] or,

[0168] If the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and the value of the counter reaches the set value, then the counter is cleared and the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and it is determined that the first read request in the transmission queue wins the pipeline in the first buffer.

[0169] or,

[0170] If the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and the value of the counter has not reached the set value, it is determined that the first read request in the transmission queue wins the pipeline in the first buffer.

[0171] or,

[0172] If the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and the value of the counter reaches the set value, the counter is cleared and the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and it is determined that the second read request in the transmission queue wins the pipeline in the first buffer.

[0173] In some implementations, when the first read request in the transmission queue and the second read request in the delivery queue complete the request submission preparation at the same time, the arbitration processing unit further determines whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request.

[0174] If it is determined whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request, the first read request in the transmission queue wins the pipeline of the first cache, and the second read request and the data corresponding to the second read request are deleted from the delivery queue.

[0175] The data reading and processing apparatus provided in this embodiment belongs to the same concept as the data reading and processing method provided in the above embodiments of this application. It can execute the data reading and processing method provided in any of the above embodiments of this application and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in this embodiment can be found in the specific processing content of the data reading and processing method provided in the above embodiments of this application, and will not be repeated here.

[0176] The functions implemented by each of the above units can be implemented by the same or different processors, and this application embodiment does not limit this.

[0177] It should be understood that each unit in the above device can be implemented by a processor calling software. For example, the device includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of each unit in the device. The processor can be a general-purpose processor, such as a CPU or microprocessor, and the memory can be internal or external to the device. Alternatively, the units in the device can be implemented as hardware circuits. By designing the hardware circuits, some or all of the unit functions can be implemented. The hardware circuits can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, which implements some or all of the unit functions by designing the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented using a PLD, such as an FPGA, which can include a large number of logic gates. The connection relationships between the logic gates are configured through configuration files to implement some or all of the unit functions. All units in the above device can be implemented entirely by a processor calling software, entirely by hardware circuits, or partially by a processor calling software with the remaining parts implemented by hardware circuits.

[0178] In this application embodiment, a processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and execution capabilities, such as a CPU, microprocessor, GPU, or DSP. In another implementation, the processor can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, the processor may be a hardware circuit implemented as an ASIC or PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the processor loading instructions to implement the functions of some or all of the above units. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as an NPU, TPU, or DPU.

[0179] As can be seen, each unit in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0180] Furthermore, the units in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these units are integrated together and implemented in the form of a System-on-Chip (SoC). The SoC may include at least one processor for implementing any of the above methods or implementing the functions of the units in the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0181] In addition to the methods and devices described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps of the data reading and processing method described in any of the above embodiments of this specification.

[0182] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0183] Furthermore, embodiments of this application may also be storage media storing a computer program, which is executed by a processor using the data reading and processing method described in any of the above embodiments of this specification.

[0184] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0185] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0186] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0187] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0188] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0189] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0190] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0191] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0192] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0193] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0194] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data reading and processing method, characterized in that, Applied to a multi-level cache processor architecture, a transmission queue and a delivery queue are set in the first cache of the multi-level cache processor architecture. The transmission queue is used to store the return data corresponding to the first read request that was not hit in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by the second read request that was not found in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request; The method includes: When the first cache receives the return data corresponding to the target read request returned by the second cache, the first cache determines the request type of the target read request; If it is determined that the target read request is a specific type of read request, the first cache obtains the target data requested by the target read request from the returned data, and stores the target data and the target read request in the delivery queue.

2. The method according to claim 1, characterized in that, The method further includes: If it is determined that the target read request is not the specific type of read request, the first cache stores the returned data and the target read request into the transmission queue.

3. The method according to claim 1, characterized in that, The method further includes: If the first cache determines that the target read request is not found in the first cache, it stores the target read request in the transmission queue; The first cache stores the target data and the target read request into the delivery queue, including: The first cache stores the target data in the transmission queue, and reads the target read request from the transmission queue and stores it in the transmission queue.

4. The method according to any one of claims 1 to 3, characterized in that, The specific type of read request includes non-lookahead load instructions.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes: If the first cache determines that the target read request is not found in the first cache, it sends a read request carrying a set identifier to the second cache; the read request is used to request the target data requested by the target read request, and the set identifier is used to indicate that the read request is the specific type of read request; The first cache determines the request type of the target read request, including: The first cache determines whether the target read request corresponding to the returned data carries the set identifier; When the target read request carries the defined identifier, the first cache determines that the target read request is the specific type of read request; Alternatively, if the target read request does not carry the set identifier, the first cache determines that the target read request is not the specific type of read request.

6. The method according to any one of claims 1 to 3, characterized in that, The method further includes: If a first read request in the transmission queue and a second read request in the delivery queue simultaneously request the pipeline of the first cache, the first cache determines that the first read request or the second read request that completes its request submission preparation first wins the pipeline of the first cache.

7. The method according to claim 6, characterized in that, The first cache uses a counter to count the number of times the pipeline wins the bid for the first cache in the delivery queue or the transmission queue. The method further includes: When the first read request in the transmission queue and the second read request in the delivery queue complete the request delivery preparation at the same time, the first cache determines whether the pipeline priority of the first cache is won by the competition between the delivery queue and the transmission queue, and determines whether the value of the counter has reached the set value. If the pipeline that wins the first buffer in the delivery queue has a higher priority than the transmission queue, and the value of the counter has not reached the set value, the first buffer determines that the second read request in the transmission queue wins the pipeline of the first buffer; or, If the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and the value of the counter reaches the set value, the first cache is cleared and the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and it is determined that the first read request in the transmission queue wins the pipeline in the first cache. or, If the pipeline that wins the first buffer in the transmission queue has a higher priority than the transmission queue, and the value of the counter has not reached the set value, the first buffer determines that the first read request in the transmission queue wins the pipeline of the first buffer. or, If the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and the value of the counter reaches the set value, the first cache is cleared, the pipeline that wins the first cache in the transmission queue has a higher priority than the transmission queue, and it is determined that the second read request in the transmission queue wins the pipeline in the first cache.

8. The method according to claim 7, characterized in that, If the first read request in the transmission queue and the second read request in the delivery queue complete the request submission preparation at the same time, the first cache also determines whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request; If it is determined whether the first read request in the transmission queue and the second read request in the delivery queue are the same read request, the first cache determines that the first read request in the transmission queue wins the pipeline of the first cache, and deletes the second read request and the data corresponding to the second read request from the delivery queue.

9. A multi-level cache processor architecture, characterized in that, In the first cache of the multi-level cache processor architecture, a transmission queue and a delivery queue are provided. The transmission queue is used to store the return data corresponding to the first read request that was not hit in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by the second read request that was not found in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request; The multi-level cache processor architecture is configured to implement the data read processing method as described in any one of claims 1 to 8.

10. A cache controller, characterized in that, Applied to a multi-level cache processor architecture, a transmission queue and a delivery queue are set in the first cache of the multi-level cache processor architecture. The transmission queue is used to store the return data corresponding to the first read request that was not hit in the first cache, and to generate a return data packet corresponding to the first read request based on the return data and the backfill requirement corresponding to the first read request. The delivery queue is used to store the data requested by the second read request that was not hit in the first cache, and to generate a return data packet corresponding to the second read request based on the data requested by the second read request; the cache controller is configured to implement the data reading processing method as described in any one of claims 1 to 8.

11. A computer device, characterized in that, It includes the multi-level cache processor architecture as described in claim 9, or the cache controller as described in claim 10.

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