Memory processing method, electronic device, and related apparatus

Abstract

The application provides a memory processing method, an electronic device and related apparatuses, and relates to the technical field of terminals. The method is applied to an electronic device, the electronic device comprises a first storage space and a second storage space, and the second storage space stores a plurality of application data of a first application. In the method, in the case that the first application is switched from the background to the foreground, n times of first operations are performed, the first operation comprises: writing a data set into a cache block applied from the first storage space, wherein the data set comprises at least one piece of application data in the plurality of application data, the size of the data set is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3. In the first operation, the first size of the cache block in the i-th time is greater than or equal to the second size of the cache block in the (i-1)-th time, and i is 2-n. In this way, the bandwidth utilization can be improved based on the aggregated submission IO of at least one piece of data.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to a memory processing method, electronic device, and related apparatus. Background Technology

[0002] DMABUF is a shared memory buffer mechanism, and the DMABUF memory usage of a single application is typically 40MB to 250MB. When multiple applications are kept alive in the background, the overall system memory usage of DMABUF can become quite high.

[0003] To reduce DMABUF memory usage, one approach is to swap data from memory to UFS storage when the application is switched to the background. When the application returns to the foreground, the data from UFS is swapped back into memory. However, the large amounts of application data generated by applications are typically small; for example, 80% of application data is less than 1MB.

[0004] Therefore, data migration between UFS and memory can result in low bandwidth utilization. Summary of the Invention

[0005] This application provides a memory processing method, an electronic device, and related apparatus to improve bandwidth utilization during data migration between non-volatile storage media (such as UFS) and volatile storage media (such as memory).

[0006] In a first aspect, embodiments of this application provide a memory processing method applied to an electronic device. The electronic device includes a first storage space and a second storage space, wherein the second storage space stores multiple application data entries of a first application. For example, the first storage space may be a volatile memory, such as RAM, and the second storage space may be a non-volatile memory, such as UFS, or it may also be a storage medium such as eMMC or DRAM. This application does not limit the implementation of the second storage space.

[0007] The method of this application includes:

[0008] When the first application switches from the background to the foreground, the first operation is performed n times. The first operation includes: writing the dataset to a cache block requested from the first storage space, wherein the dataset includes at least one piece of application data from multiple pieces of application data in the second storage space, the size of the dataset is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3.

[0009] Wherein, the first size of the cache block in the i-th first operation is greater than or equal to the second size of the cache block in the (i-1)-th first operation, and the value of i is from 2 to n.

[0010] The first operation described here can also be understood as a file I / O operation. This allows for submitting file I / O for a dataset, that is, aggregating multiple application data together for file I / O. Compared to the implementation method of submitting file I / O for each piece of application data separately, the technical solution of this application can effectively improve bandwidth utilization. Furthermore, during the execution of multiple rounds of file I / O, the size of the cache block corresponding to the file I / O is not determined based on the size of the application data to be stored. Instead, the size of the cache block either increases successively or remains the same as the previous one. This ensures that the capacity of the cache block can store the application data contained in the dataset.

[0011] In one possible implementation, the first dimension is larger than the second dimension when the value of i is less than or equal to 3.

[0012] In the technical solution of this application, for example, the size of the cache block can be dynamically adjusted based on the bandwidth of file I / O. However, when the value of execution round i is less than or equal to 3, there is not enough bandwidth for comparison. Therefore, the size of the cache block can be fixed and enlarged so that the cache block based on the application can store the aggregated dataset.

[0013] In one possible implementation, when the value of i is greater than 3, the size of the cache block is determined based on the bandwidth.

[0014] In this way, when the value of execution round i is greater than 3, there is enough bandwidth to make comparisons and determine the actual bandwidth situation. Therefore, the size of the cache block can be determined based on the bandwidth. This allows for dynamic adjustment based on bandwidth conditions to determine whether the size of the cache block needs to be increased further, thus avoiding excessive data aggregation.

[0015] For example, the cache block size corresponding to the first operation in round i can be determined based on the bandwidth corresponding to the first operations in rounds x prior to round i. The rounds prior to round i are rounds 1 to i-1. For instance, x first operations can be randomly selected from rounds 1 to i-1, and the cache block size corresponding to the first operation in round i can be determined based on the bandwidth corresponding to these x first operations. Here, x can be an integer greater than or equal to 1, and the specific value of x can be chosen according to actual needs. Furthermore, the specific x rounds selected from rounds 1 to i-1 can also be set according to actual needs.

[0016] Furthermore, for example, it can be determined whether the first condition is met based on the bandwidth corresponding to the first operation in x rounds. The first condition can be a condition used to measure whether the bandwidth utilization of the current file I / O has reached the preset requirement (or can be understood as the preset utilization rate). The specific setting of the first condition can also be selected according to actual needs.

[0017] For example, if the first condition is not met, it means that the current file I / O bandwidth utilization has not yet reached the preset requirement. In this case, the size of the cache block can be increased based on the cache block size corresponding to the first operation in round (i-1) to enable the file I / O process to achieve higher bandwidth. If the first condition is met, it means that the current file I / O bandwidth utilization has reached the preset requirement. In this case, to avoid excessive data aggregation, the cache block size corresponding to the first operation in round (i-1) can be used, that is, the cache block size corresponding to the first operation in round (i) is equal to the cache block size corresponding to the first operation in round (i-1).

[0018] Here, we will introduce a specific implementation as an example. In one possible implementation, when the value of i is greater than 3, the first size is determined based on the first bandwidth, the second bandwidth, and the second size. The first bandwidth is the bandwidth corresponding to the (i-2)th first operation, and the second bandwidth is the bandwidth corresponding to the (i-3)th first operation.

[0019] In this implementation, the bandwidth change can be determined based on the bandwidth of two consecutive rounds. Then, based on the bandwidth change and the cache block size of the previous round (i-1 round) (i.e., the second size), the cache block size of the next round (i.e., the i-th round) (i.e., the first size) can be determined. This allows for dynamic determination of whether to increase the cache block size based on the current cache block size, so as to adjust the cache block size based on the actual bandwidth utilization on the one hand, and avoid excessive data aggregation on the other hand.

[0020] In one possible implementation, the first size is equal to the second size, provided that the first bandwidth and the second bandwidth satisfy a first quantitative relationship.

[0021] If the first bandwidth and the second bandwidth do not satisfy a first quantitative relationship, the first size is larger than the second size. The first quantitative relationship between the first bandwidth and the second bandwidth can be understood as the first condition described above.

[0022] In one possible implementation, the first quantitative relationship includes the ratio of the first bandwidth to the second bandwidth being less than a first preset threshold; and / or, the first quantitative relationship includes the difference between the first bandwidth and the second bandwidth being less than a second preset threshold.

[0023] In this implementation, the bandwidth change is determined based on the ratio or difference between two adjacent bandwidth measurements. Then, based on this bandwidth change, it's determined whether to increase the cache block size. Specifically, when the first and second bandwidths satisfy a first quantitative relationship, it means the bandwidth change is already small. In this case, increasing the cache block size provides a relatively small bandwidth gain and may even lead to over-aggregation. Therefore, when the first and second bandwidths satisfy the first quantitative relationship, the cache block size is not increased; that is, the first size equals the second size. Conversely, when the first and second bandwidths do not satisfy the first quantitative relationship, the bandwidth gain from increasing the cache block size increases rapidly. Therefore, in this case, increasing the cache block size can effectively improve bandwidth utilization.

[0024] In one possible implementation, when i is 1, the size of the cache block in the i-th first operation is a preset size. By presetting the size of the cache block in the first round, the initial size of the cache block can be reasonably set.

[0025] In one possible implementation, before performing the i-th first operation, the method further includes:

[0026] Perform a second operation, which includes: requesting a cache block from the first storage space based on the first size.

[0027] In one possible implementation, the second operation also includes: determining the dataset corresponding to the cache block.

[0028] The second operation can be understood as data preparation. It is understood that the technical solution of this application, when performing data aggregation for file I / O, does not cache data in a unit and wait for the amount of cached data in that unit to exceed a threshold before performing file I / O. Instead, after determining the size of the cache block, it directly selects at least one piece of application data from multiple pieces of application data that matches the size of the cache block to obtain a dataset, and then directly submits file I / O for this dataset. This implementation method does not need to wait for the amount of data to reach a threshold; instead, it can directly determine the matching dataset based on the size of the cache block and then directly submit the file I / O corresponding to that dataset. Therefore, this implementation method can improve the efficiency of data swapping from one storage space to another.

[0029] In one possible implementation, determining the dataset corresponding to the cache block includes:

[0030] Based on the first size, determine the dataset corresponding to the cache block.

[0031] In one possible implementation, the dataset corresponding to the cache block is determined based on the first size, including:

[0032] In the remaining application data in the second storage space, determine at least one combination of application data whose total size differs from the first size the smallest, to obtain the dataset corresponding to the cache block. The remaining application data refers to application data that has not yet been allocated to the dataset, or application data whose mapping relationship with the cache block has not been confirmed.

[0033] This allows us to determine which data to store in a cache block based on its size, thereby maximizing the utilization of the cache block.

[0034] In one possible implementation, the time period during which the first operation is performed (j-th time) is called the first time period, and the time period during which the second operation is performed before the (j+1)-th first operation is called the second time period. The first time period and the second time period overlap, and the value of j ranges from 1 to n-1. In another implementation, the first time period and the second time period overlap at least partially.

[0035] In one possible implementation, the first operation is executed based on the first thread, and the second operation is executed based on the second thread.

[0036] In other words, the data preparation and file I / O processing described in this application are executed asynchronously. This allows file I / O processing to be performed simultaneously while data preparation is being carried out, thereby improving CPU and bandwidth utilization.

[0037] In one possible implementation, when the first dimension is larger than the second dimension, the first dimension and the second dimension satisfy a second quantitative relationship.

[0038] In one possible implementation, the second quantitative relationship is: the first size is T times the second size, or the difference between the first size and the second size is a first value, where T is a value greater than or equal to 1. The first value can be a pre-set fixed value to indicate a constant growth based on the first value during cache block expansion.

[0039] In this implementation, by setting the first size and the second size to satisfy the second quantitative relationship, the size of the cache block can be enlarged based on specific rules so that the size of each cache block enlarged successively satisfies the relationship of equal ratio or equal arithmetic, which facilitates the maintenance and management of the cache block.

[0040] Secondly, embodiments of this application provide a memory processing method applied to an electronic device. The electronic device includes a first storage space and a second storage space. The first storage space stores multiple application data entries of a first application. For example, the first storage space can be memory, and the second storage space can be UFS, or the second storage space can also be a storage medium such as eMMC or DRAM. This application does not limit the implementation of the second storage space.

[0041] The method described in this application includes:

[0042] When the first application switches from the foreground to the background, the first operation is performed n times. The first operation includes: writing the dataset to a cache block requested from the second storage space, wherein the dataset includes at least one piece of application data from multiple pieces of application data, the size of the dataset is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3.

[0043] Wherein, the first size of the cache block in the i-th first operation is greater than or equal to the second size of the cache block in the (i-1)-th first operation, and the value of i is from 2 to n.

[0044] In one possible implementation, the first dimension is larger than the second dimension when the value of i is less than or equal to 3.

[0045] In one possible implementation, when the value of i is greater than 3, the size of the cache block is determined based on the bandwidth.

[0046] In one possible implementation, when the value of i is greater than 3, the first size is determined based on the first bandwidth, the second bandwidth, and the second size, where the first bandwidth is the bandwidth corresponding to the (i-2)th first operation and the second bandwidth is the bandwidth corresponding to the (i-3)th first operation.

[0047] In one possible implementation, the first size is equal to the second size, provided that the first bandwidth and the second bandwidth satisfy a first quantitative relationship.

[0048] If the first bandwidth and the second bandwidth do not satisfy the first quantitative relationship, the first size is larger than the second size.

[0049] In one possible implementation, the first quantitative relationship includes the ratio of the first bandwidth to the second bandwidth being less than a first preset threshold; and / or, the first quantitative relationship includes the difference between the first bandwidth and the second bandwidth being less than a second preset threshold.

[0050] In one possible implementation, when i is 1, the size of the cache block in the first operation of the i-th time is a preset size.

[0051] In one possible implementation, before performing the i-th first operation, the method further includes:

[0052] Perform a second operation, which includes: requesting a cache block from a second storage space based on a first size.

[0053] In one possible implementation, the second operation also includes: determining the dataset corresponding to the cache block.

[0054] In one possible implementation, determining the dataset corresponding to the cache block includes:

[0055] Based on the first size, determine the dataset corresponding to the cache block.

[0056] In one possible implementation, the dataset corresponding to the cache block is determined based on the first size, including:

[0057] Among the remaining application data in the first storage space, determine at least one combination of application data whose total size differs from the first size the smallest, to obtain the dataset corresponding to the cache block.

[0058] In one possible implementation, the time period during which the first operation is performed for the jth time is called the first time period, and the time period during which the second operation is performed before the (j+1)th time is called the second time period. The first time period and the second time period overlap, and the value of j is from 1 to n-1.

[0059] In one possible implementation, the first operation is executed based on the first thread, and the second operation is executed based on the second thread.

[0060] In one possible implementation, when the first dimension is larger than the second dimension, the first dimension and the second dimension satisfy a second quantitative relationship.

[0061] In one possible implementation, the second quantitative relationship is: the first size is T times the second size, or the difference between the first size and the second size is a first value, where T is a value greater than or equal to 1. The first value can be a pre-set fixed value to indicate a constant growth based on the first value during cache block expansion.

[0062] It is understandable that the current implementation is similar to the implementation described in the first aspect above. The difference lies in that the first aspect describes the scenario where the first application switches from the background to the foreground, and the application data stored in the second storage space (such as UFS) is switched to the first storage space (such as memory). The current second aspect describes the scenario where the first application switches from the background to the foreground, and the application data stored in the first storage space (such as memory) is switched to the second storage space (such as UFS). All related implementations are similar to those described above, differing only in the direction of data writing. Therefore, all related implementations can be understood by referring to the above embodiments.

[0063] Thirdly, this application provides a memory processing method applied to an electronic device, the electronic device including a first storage space and a second storage space, the second storage space storing multiple application data of a first application;

[0064] The method includes:

[0065] When the first application switches from the background to the foreground, the first operation is performed n times. The first operation includes: writing the dataset to a cache block requested from the first storage space, wherein the dataset includes at least one piece of application data from multiple pieces of application data in the second storage space, the size of the dataset is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3.

[0066] In addition, perform n second operations, the second operations including: requesting a cache block from the first storage space and determining the dataset corresponding to the cache block; wherein, the n first operations can correspond one-to-one with the n second operations, for example, the corresponding first operation can be performed after each second operation is performed;

[0067] The time period during which the first operation is performed (j-th time) is called the first time period, and the time period during which the second operation is performed (j+1-th time) is called the second time period. The first time period and the second time period overlap, and the value of j ranges from 1 to n-1. In one implementation, the first time period and the second time period overlap at least partially.

[0068] In one possible implementation, the first operation is executed based on the first thread, and the second operation is executed based on the second thread.

[0069] In one possible implementation, the first size of the cache block in the i-th first operation is greater than or equal to the second size of the cache block in the (i-1)-th first operation, where i takes the value 2 to n.

[0070] In one possible implementation, the first dimension is larger than the second dimension when the value of i is less than or equal to 3.

[0071] In one possible implementation, when the value of i is greater than 3, the size of the cache block is determined based on the bandwidth.

[0072] In one possible implementation, when the value of i is greater than 3, the first size is determined based on the first bandwidth, the second bandwidth, and the second size, where the first bandwidth is the bandwidth corresponding to the (i-2)th first operation and the second bandwidth is the bandwidth corresponding to the (i-3)th first operation.

[0073] In one possible implementation, the first size is equal to the second size, provided that the first bandwidth and the second bandwidth satisfy a first quantitative relationship.

[0074] If the first bandwidth and the second bandwidth do not satisfy the first quantitative relationship, the first size is larger than the second size.

[0075] In one possible implementation, the first quantitative relationship includes the ratio of the first bandwidth to the second bandwidth being less than a first preset threshold; and / or, the first quantitative relationship includes the difference between the first bandwidth and the second bandwidth being less than a second preset threshold.

[0076] In one possible implementation, when i is 1, the size of the cache block in the first operation of the i-th time is a preset size.

[0077] In one possible implementation, before performing the i-th first operation, the method further includes:

[0078] Perform a second operation, which includes: requesting a cache block from the first storage space based on the first size.

[0079] In one possible implementation, the second operation also includes: determining the dataset corresponding to the cache block.

[0080] In one possible implementation, determining the dataset corresponding to the cache block includes:

[0081] Based on the first size, determine the dataset corresponding to the cache block.

[0082] In one possible implementation, the dataset corresponding to the cache block is determined based on the first size, including:

[0083] In the remaining application data in the second storage space, determine at least one combination of application data with the smallest difference between the total size and the first size to obtain the dataset corresponding to the cache block. The remaining application data is the application data that has not yet been divided into the dataset.

[0084] In one possible implementation, when the first dimension is larger than the second dimension, the first dimension and the second dimension satisfy a second quantitative relationship.

[0085] In one possible implementation, the second quantitative relationship is: the first dimension is T times the second dimension, or the difference between the first dimension and the second dimension is the first value, where T is a value greater than or equal to 1.

[0086] In one possible implementation, the first storage space is volatile memory and the second storage space is non-volatile memory.

[0087] Fourthly, this application provides a memory processing method applied to an electronic device, the electronic device including a first storage space and a second storage space, the second storage space storing multiple application data of a first application;

[0088] The method includes:

[0089] Perform a second operation, which includes: requesting a cache block from the first storage space and determining the dataset corresponding to the cache block;

[0090] Perform a first operation, which includes writing a dataset to a cache block requested from a first storage space, wherein the dataset includes at least one piece of application data from multiple pieces of application data in a second storage space, and the size of the dataset is less than or equal to the size of the cache block.

[0091] In one possible implementation, the size of the cache block requested in the second operation is the same as the size of the cache block requested in the second operation of the previous round.

[0092] In one possible implementation, determining the dataset corresponding to the cache block includes:

[0093] The dataset corresponding to the cache block is determined based on the size of the cache block.

[0094] In one possible implementation, the dataset corresponding to the cache block is determined based on the size of the cache block, including:

[0095] In the remaining application data in the second storage space, determine at least one combination of application data with the smallest difference between the total size and the size of the cache block to obtain the dataset corresponding to the cache block. The remaining application data is the application data that has not yet been allocated to the dataset.

[0096] In one possible implementation, the size of the cache block requested in the second operation is determined based on bandwidth.

[0097] In one possible implementation, the size of the cache block requested in the second operation is determined based on the bandwidth corresponding to x rounds of second operations performed prior to this second operation, where the bandwidth corresponding to the second operation is also the bandwidth corresponding to the data set determined by the second operation. Here, x can be an integer greater than or equal to 1.

[0098] In one possible implementation, the size of the cache block requested in the second operation executed this time can be determined based on the size of the cache block in the previous round of the second operation, the first bandwidth and the second bandwidth, wherein the first bandwidth is the bandwidth corresponding to the third round of the second operation before the current second operation, and the second bandwidth is the bandwidth corresponding to the second round of the second operation before the current second operation.

[0099] In one possible implementation, if the first bandwidth and the second bandwidth satisfy a first quantitative relationship, the size of the cache block for the second operation executed in this round is equal to the size of the cache block corresponding to the second operation in the previous round.

[0100] If the first bandwidth and the second bandwidth do not satisfy the first quantitative relationship, the size of the cache block for the second operation executed in this round is larger than the size of the cache block corresponding to the second operation in the previous round.

[0101] In one possible implementation, the first quantitative relationship includes the ratio of the first bandwidth to the second bandwidth being less than a first preset threshold; and / or, the first quantitative relationship includes the difference between the first bandwidth and the second bandwidth being less than a second preset threshold.

[0102] In one possible implementation, if the second operation performed in this instance is the first round, the size of the cache block is a preset size.

[0103] In one possible implementation, the time period during which the first operation is performed is called the first time period, and the time period during which the second operation is performed in the next round is called the second time period, with at least partial overlap between the first time period and the second time period.

[0104] In one possible implementation, the first operation is executed based on the first thread, and the second operation is executed based on the second thread.

[0105] Fifthly, embodiments of this application provide an electronic device including a processor and a memory. The memory stores code instructions, and the processor executes the code instructions to perform the methods described in the first to fourth aspects. The memory can also be understood as the non-volatile memory described above.

[0106] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program or instructions that, when executed on a computer, cause the computer to perform the methods described in the first to fourth aspects.

[0107] In a seventh aspect, embodiments of this application provide a computer program product including a computer program, which, when run on a computer, causes the computer to perform the methods described in the first to fourth aspects.

[0108] Eighthly, this application provides a chip or chip system including at least one processor and a communication interface, wherein the communication interface and at least one processor are interconnected via a circuit, and the at least one processor is used to run computer programs or instructions to perform the methods described in the first to fourth aspects. The communication interface in the chip may be an input / output interface, pins, or circuits, etc.

[0109] In one possible implementation, the chip or chip system described above in this application further includes at least one memory storing instructions. The memory can be an internal storage unit of the chip, such as a register or cache, or it can be a storage unit of the chip itself (e.g., read-only memory, random access memory, etc.).

[0110] It should be understood that the second to eighth aspects of this application correspond to the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0111] Figure 1 A schematic diagram illustrating the implementation of shared memory provided in an embodiment of this application;

[0112] Figure 2 A schematic diagram illustrating memory usage provided in an embodiment of this application;

[0113] Figure 3 Schematic diagram of data migration implementation provided in the embodiments of this application Figure 1 ;

[0114] Figure 4 Schematic diagram of data migration implementation provided in the embodiments of this application Figure 2 ;

[0115] Figure 5 A schematic diagram illustrating the data exchange process provided in this application embodiment;

[0116] Figure 6 A flowchart illustrating the memory processing method provided in the embodiments of this application. Figure 1 ;

[0117] Figure 7 A schematic diagram illustrating the correspondence between IO size and bandwidth provided in an embodiment of this application;

[0118] Figure 8 A flowchart illustrating the memory processing method provided in the embodiments of this application. Figure 2 ;

[0119] Figure 9 A schematic diagram illustrating the correspondence between cache blocks and datasets provided in embodiments of this application;

[0120] Figure 10 This is a schematic diagram illustrating the implementation of determining the dataset provided in an embodiment of this application. Detailed Implementation

[0121] To facilitate understanding, the relevant terms and concepts involved in the embodiments of this application will be introduced below:

[0122] 1. Keep the application running in the background

[0123] Application background keep-alive refers to the strategy of keeping an application active when it is switched to the background (invisible to the user). This is usually to ensure that the application can continue to perform certain tasks in the background, such as push notifications, data synchronization, and location tracking.

[0124] 2. UFS

[0125] UFS (Universal Flash Storage) is a high-performance, non-volatile storage medium primarily used in mobile devices such as smartphones and tablets.

[0126] 3. I / O intensive tasks

[0127] Among them, IO-intensive tasks refer to tasks whose execution speed is mainly limited by the waiting time of input / output (I / O) operations.

[0128] 4. CPU-intensive tasks

[0129] CPU-intensive tasks are those whose execution speed is primarily limited by the CPU's computing power; these tasks typically require a large amount of computing resources.

[0130] 5. Memory

[0131] In the technical solution of this application, memory can be a separate device, such as memory in a PC device, where PC stands for Personal Computer. Alternatively, memory can be part of the processor, such as memory in a mobile phone.

[0132] 6. Electronic equipment

[0133] The electronic devices in this application embodiment can be referred to as user equipment (UE), terminal, etc. For example, electronic devices can be mobile phones, tablets, personal digital assistants (PDAs), handheld devices with wireless communication functions, computing devices, in-vehicle devices, vehicle-mounted devices, or wearable devices, virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, wireless terminals in industrial control, wireless terminals in smart homes, etc. The form of the electronic devices is not specifically limited in this application embodiment.

[0134] To better understand the technical solution of this application, the relevant technologies involved in this application are explained below.

[0135] DMABUF is a memory buffer sharing mechanism. DMABUF stands for Direct Memory Access Buffer Sharing Framework. Its core purpose is to efficiently share memory data between different hardware devices (such as GPUs, cameras, screens, etc.), avoid unnecessary data copying, and thus improve system performance and reduce latency.

[0136] DMABUF utilizes DMA (Direct Memory Access) technology, allowing hardware devices (such as GPUs, cameras, and screens) to directly read and write to memory buffers without CPU intervention in data transfer, reducing CPU overhead and enabling different hardware devices to access the same memory area through DMABUF. For example, video data captured by a camera can be directly transferred to the GPU for processing via DMABUF. Similarly, frames rendered by the GPU can be directly sent to the display controller (screen) for display via DMABUF. This reduces the overhead of data copying and memory management. The cache block allocated based on the DMABUF mechanism can be called a DMA buffer (DMA cache block), hereinafter referred to as a cache block.

[0137] The following is combined Figure 1 Further explanation of DMABUF Figure 1 This is a schematic diagram illustrating the implementation of shared memory provided in an embodiment of this application.

[0138] like Figure 1 As shown, for example, an application can request a buffer block from memory based on the DAMBUF mechanism, such as buffer block 101 shown in the figure. The application can also write data A into this buffer block 101. Different hardware devices, such as the GPU, camera, and screen shown in the figure, can access this buffer block 101 to enable different hardware devices to share memory data.

[0139] Figure 1 The example described uses a single application requesting one cache block. In actual implementation, a single application can request multiple cache blocks. Furthermore, multiple applications can exist within an electronic device, each requesting its own corresponding cache block. Similarly, the cache blocks requested by an application can be shared by multiple hardware devices.

[0140] A single application typically uses 40MB to 250MB of memory. Therefore, when multiple applications are kept running in the background, the overall system memory usage for DMABUF will be high, or it can be understood as the overall system memory usage based on the DMABUF mechanism. For example, in some cases, the overall system memory usage for DMABUF can reach as high as 2GB.

[0141] The following can be combined Figure 2 To understand further, Figure 2 This is a schematic diagram illustrating the memory usage implementation provided in an embodiment of this application.

[0142] It needs to be understood. Figure 2 The cache blocks shown are all cache blocks allocated based on the DMABUF mechanism, which will not be repeated below.

[0143] like Figure 2 As shown, for example, Application 1 requests cache blocks 201 and 202 from memory, writes data A of Application 1 to cache block 201, and writes data B of Application 1 to cache block 202. Application 2 requests cache blocks 203 and 204 from memory, writes data C of Application 2 to cache block 203, and writes data D of Application 2 to cache block 204. Application 3 requests cache blocks 205, 206, and 207 from memory, writes data E of Application 3 to cache block 205, and writes data F and G of Application 3 to cache block 206. Application 4 requests cache block 208 from memory and writes data H of Application 4 to cache block 208.

[0144] Based on the example described above, if application 1, application 2, application 3 and application 4 are all in a background keep-alive state, then the cache blocks requested by these applications will be continuously occupied, resulting in a high overall DMABUF usage.

[0145] To reduce DMABUF memory usage and improve memory efficiency and application keep-alive experience, this application proposes a technical solution that allows data stored in memory to be swapped to a storage medium when the application switches to the background. When the application switches back to the foreground, the data stored in the background is swapped back into memory. The storage medium can include, but is not limited to, UFS, eMMC (embedded MultiMediaCard), DRAM (Dynamic Random Access Memory), etc. The following description uses UFS as an example.

[0146] For example, it can be combined Figure 3 and Figure 4 To understand, Figure 3 Schematic diagram of data migration implementation provided in the embodiments of this application Figure 1 , Figure 4 Schematic diagram of data migration implementation provided in the embodiments of this application Figure 2 .

[0147] like Figure 3 As shown, in a scenario where the application (e.g., application 1) is in the foreground, the application requests cache blocks 301, 302, and 303 from memory. Cache block 301 stores application 1's data A, cache block 302 stores application 1's data B, and cache block 303 stores application 1's data C.

[0148] In scenarios where an application switches from the foreground to the background, for example, data A, B, and C stored in memory can be moved to the UFS storage medium. Correspondingly, cache blocks 101 and 102 in memory can be released to prevent application 1 from still occupying DMABUF cache blocks in memory while keeping it alive in the background. This allows for the mitigation of high overall DMABUF usage when multiple applications are kept alive in the background.

[0149] and reference Figure 4 In a scenario where the application (e.g., application 1) is in the background, data A, data B, and data C of application 1 are all swapped out and stored in UFS storage medium. For example, corresponding storage blocks are also allocated in UFS to store data A, data B, and data C. This application does not limit the implementation of the storage blocks for storing data A, data B, and data C; it can be one block or multiple blocks. The storage blocks are not shown in the figure. The specific implementation of the storage blocks can be set according to actual needs.

[0150] In scenarios where an application switches from the background to the foreground, data A, B, and C stored in UFS can be migrated to memory. For example, cache blocks 401, 402, and 403 can be allocated in memory, and data A can be written to cache block 401, data B to cache block 402, and data C to cache block 403. This swaps the application data stored in UFS into memory, allowing different hardware devices to directly read and write data based on DMABUF while the application is running in the foreground.

[0151] Based on the process described above, it's understandable that when an application switches from the background back to the foreground, data needs to be swapped from UFS into memory. Therefore, to ensure a smooth experience when switching to the foreground, the data swapping time should be as short as possible. The following section will combine... Figure 5One possible data exchange process will be described. Figure 5 This is a schematic diagram of the data exchange process provided in the embodiments of this application.

[0152] For a single application, multiple application data entries typically exist during its runtime. For example, in the example described above, application 1 has three application data entries: data A, data B, and data C. When the application switches to the background, these multiple application data entries are written to UFS storage. When the application switches to the foreground, these multiple application data entries stored in UFS storage need to be swapped into memory.

[0153] In one implementation, multiple pieces of application data can be processed sequentially. The implementation of writing data from UFS storage to memory typically involves two steps: data preparation and file I / O. Data preparation may include operations such as allocating buffer blocks and establishing mapping relationships (e.g., the mapping relationship between virtual addresses and physical addresses of data), while file I / O involves writing data into the allocated buffer blocks.

[0154] The following section uses three application data points, A, B, and C, from Application 1 as an example to illustrate the process of sequentially processing multiple application data points.

[0155] Reference Figure 5 During time period 1, data preparation can be performed on data A. This preparation may include allocating cache block 401 from memory, where the size of cache block 401 is the same as the size of data A; that is, the size of the cache block allocated corresponds to the size of data A. It may also include establishing a mapping relationship between cache block 401 and data A, so that data A can be written to cache block 401 later. Then, during time period 2, file I / O can be performed on data A, that is, writing data A from UFS to cache block 401. This completes the swapping of data A from UFS into memory.

[0156] Furthermore, during period 3, data preparation can be performed on data B. This preparation may include allocating cache block 402 from memory, where the size of cache block 402 is the same as the size of data B; that is, the size of the cache block allocated corresponds to the size of data B. It may also include establishing a mapping relationship between cache block 402 and data B, so that data B can be written to cache block 402 later. Then, during period 4, file I / O can be performed on data B, that is, writing data B from UFS to cache block 402. This completes the swapping of data B from UFS into memory.

[0157] Furthermore, during period 5, data preparation can be performed on data C. This preparation may include allocating cache block 403 from memory, where the size of cache block 403 is the same as the size of data C; that is, the size of the cache block allocated corresponds to the size of data C. It may also include establishing a mapping relationship between cache block 403 and data C, so that data C can be written to cache block 403 later. Then, during period 6, file I / O can be performed on data C, that is, writing data C from UFS to cache block 403. This completes the swapping of data C from UFS into memory.

[0158] Based on the process described above, it is possible to swap multiple pieces of application data from UFS into memory. In this implementation, data preparation and file I / O operations are performed for each piece of data. The processing of each piece of data is similar, and the process is repeated until all pieces of application data have been processed.

[0159] During the process of an application switching from the foreground to the background, multiple data entries of varying sizes are typically swapped in, such as 10 to 100 data entries. For example, the size of a single data entry can range from 10KB to 14MB. In actual implementation, the number of data entries and the size of each data entry can be determined according to the actual situation of the application, and this embodiment does not impose any restrictions on this.

[0160] However, among the numerous application data entries generated during application startup, a large portion of these entries are relatively small in size (or data volume; the data size mentioned in this article can be understood as data volume, where data size is also the data size). For example, 80% of the application data is less than 1MB. Therefore, sequentially performing data preparation and file I / O processing on multiple application data entries leads to low bandwidth utilization.

[0161] Based on the above Figure 5 Taking the scenario described above as an example, if data A is 20KB in size and time period 2 is 15ms long, then the actual bandwidth within time period 2 is 1.365MB / s. Assuming the electronic device can support a bandwidth of 500MB / s during the process of writing data from UFS to memory, the bandwidth utilization within time period 2 is very low. The same applies to transmitting data B in time period 4 and data C in time period 6; both suffer from low bandwidth utilization.

[0162] Furthermore, in the data swapping process described above, data preparation and file I / O are implemented sequentially. That is, data preparation and file I / O are performed for each piece of data in turn, and the data preparation for the next piece of data can only begin after the file I / O of one piece of data has been completed. File I / O is an I / O-intensive process, while data preparation is a CPU-intensive operation. This sequential implementation leads to relatively low CPU and bandwidth utilization.

[0163] For example, in the above Figure 5 In the data swapping example described, during periods 1, 3, and 5, the CPU is performing data preparation work, and the bandwidth is not utilized. Similarly, during periods 2, 4, and 5, file write / write operations are performed based on bandwidth, and the CPU is not utilized during these periods.

[0164] To address the aforementioned technical problems, this application proposes a memory processing method that can aggregate multiple application data entries for file I / O, where I / O aggregation can improve bandwidth utilization. However, excessive aggregation can amplify the data preparation time during processing, potentially causing file I / O to be delayed. Furthermore, excessive aggregation can impact the bandwidth of other I / O operations in the system. For instance, if the aggregated data size is too large within the same time period, excessive bandwidth consumption may affect the available bandwidth for other I / O tasks. Therefore, this application proposes a dynamic I / O aggregation method to perform I / O aggregation based on actual bandwidth utilization, avoiding over-aggregation.

[0165] Furthermore, the technical solution of this application can also separate the data preparation and file I / O processes to avoid serial processing, thereby improving the efficiency of bandwidth and CPU resource utilization.

[0166] Based on the above description, the memory processing method provided by this application will be described below with reference to specific embodiments. These embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0167] Figure 6 A flowchart illustrating the memory processing method provided in the embodiments of this application. Figure 1 , Figure 7 This is a schematic diagram illustrating the correspondence between IO size and bandwidth provided in an embodiment of this application. Figure 8 A flowchart illustrating the memory processing method provided in the embodiments of this application. Figure 2 , Figure 9 This is a schematic diagram illustrating the correspondence between cache blocks and datasets provided in an embodiment of this application. Figure 10 This is a schematic diagram illustrating the implementation of determining the dataset provided in an embodiment of this application.

[0168] Reference Figure 6 The memory processing method provided in this application embodiment may include:

[0169] S601. Request a cache block from memory. The size of the cache block is Mi, where i represents the execution round of data preparation.

[0170] As described above, the process of swapping application data from UFS into memory typically involves two steps: data preparation and file I / O. The implementation in this embodiment is similar, including data preparation and file I / O processing. The data preparation process specifically includes allocating cache blocks and establishing mapping relationships.

[0171] In the technical solution of this application, the data preparation process is executed in multiple rounds. In this embodiment, i represents the execution round of data preparation, where i is an integer greater than or equal to 1. It can be understood that the initial value of i is 1. After each round of data preparation is completed, the value of i is incremented by 1, and the next round of data preparation is carried out.

[0172] Each round of data preparation includes the operation of allocating a cache block from memory, whereby the allocated cache block is used to store the swapped-in application data. In this embodiment, Mi is used to represent the size of the cache block allocated during the i-th round of data preparation. For example, the size Mi of the cache block to be allocated in each round can be predetermined before each round of data preparation, and then a cache block of size Mi can be allocated from memory. For instance, the size Mi of the cache block can be determined based on bandwidth conditions.

[0173] In one implementation, the size of the cache block requested during data preparation can be determined based on bandwidth. For example, for the next round of data preparation to be executed (round i+1), the cache block size for round i+1 can be determined based on the bandwidth corresponding to the x rounds of data preparation executed before round i+1. The value of x can range from 1 to i, and the specific bandwidth corresponding to which rounds of data preparation before round i+1 are selected can also be set according to actual needs; this embodiment does not impose any restrictions on this. For example, the bandwidth corresponding to data preparation can be obtained after the file I / O corresponding to the data preparation is completed, for example, calculated based on the amount of file I / O data and the I / O duration. Alternatively, the bandwidth corresponding to this round of data preparation can be obtained through prediction after the completion of a round of data preparation; this embodiment also does not impose any restrictions on this.

[0174] Building upon this, the following section uses the example of determining the cache block size for the (i+1)th round of data preparation based on the bandwidth corresponding to the (i-2)th round of data preparation and the bandwidth corresponding to the (i-1)th round of data preparation. In this implementation, x is 2. It can be understood that the implementation is similar when x takes other values, which will not be elaborated upon further below.

[0175] For example, after the i-th round of data preparation is completed, the bandwidth change can be determined based on the bandwidth corresponding to the (i-2)-th and (i-1)-th rounds of data preparation. If the bandwidth change does not meet the preset conditions, the size of the cache block corresponding to the i-th round of data preparation can be increased to determine the size of the cache block corresponding to the (i+1)-th round of data preparation. Alternatively, if the bandwidth change meets the preset conditions, the size of the cache block corresponding to the i-th round of data preparation can be retained, i.e., no size increase can be performed, to determine the size of the cache block corresponding to the (i+1)-th round of data preparation, thus avoiding problems caused by excessive data aggregation.

[0176] In the implementation described above, the value of i can be from 1 to n, where n is the total number of execution rounds of data preparation, and n can be an integer greater than or equal to 1. For the case where i is equal to 1, i.e., the first round of data preparation, the size of the cache block requested in the first round can be preset, meaning the value of M1 can be preset. For example, the value of M1 can be 1MB or 2MB. The size of the cache block in the first round can be set according to actual needs, and this embodiment does not impose any restrictions on this. For the case where i is from 2 to n, the size of the cache block can be determined, for example, based on the size of the cache block in the (i-1)th round of data preparation.

[0177] It's understandable that after the first round of data preparation, the cache block size for the second round of data preparation needs to be determined. In the implementation described above, this is based on the bandwidth of the two consecutive rounds of data preparation already completed to determine whether to increase the cache block size. However, after the first round of data preparation, the bandwidth corresponding to the dataset from that round is temporarily unavailable because the file I / O for that round hasn't finished, making it impossible to determine bandwidth changes. Therefore, we could, for example, increase the size of the cache block corresponding to the first round of data preparation to obtain the size of the cache block for the second round. In other words, when determining the size of the cache block for the second round of data preparation, we don't consider bandwidth amplification; we directly increase the size.

[0178] Furthermore, after the second round of data preparation is complete, it is necessary to determine the cache block size corresponding to the third round of data preparation. In the implementation described above, it is necessary to determine whether to increase the cache block size based on the bandwidth corresponding to the two consecutive rounds of data preparation that have been completed before this round. However, after the third round of data preparation is complete, only the bandwidth corresponding to the first round of data preparation can be obtained (because the file I / O corresponding to the first round of data preparation has been completed), but the bandwidth corresponding to the second round of data preparation cannot be obtained (because the file I / O corresponding to the second round of data preparation has not been completed). At this time, it is impossible to determine the bandwidth change based on the bandwidth corresponding to the two rounds of file I / O. So, for example, we can set the cache block size corresponding to the second round of data preparation and then increase it to obtain the cache block size corresponding to the third round of data preparation. That is, when determining the cache block size corresponding to the third round of data preparation, we do not consider the bandwidth increase, but directly increase the size.

[0179] In other words, when the value of i is equal to 2 or equal to 3, the size of the cache block can be directly increased based on the current size of the cache block to determine the size of the cache block in the next round, without having to consider the bandwidth change.

[0180] When the value of i is greater than 3, the bandwidth corresponding to the data preparation of the previous two consecutive rounds can be obtained. Therefore, it is possible to determine whether the size of the cache block needs to be increased based on the bandwidth change.

[0181] S602. Determine the mapping relationship between dataset Xi and cache blocks.

[0182] In each round of data preparation, besides allocating cache blocks, there's also the operation of determining the mapping relationship between data and cache blocks—that is, determining which data to write to the cache blocks allocated in this round. Referring to the above description, in one implementation, a cache block of a corresponding size can be allocated based on the size of a single piece of application data. Subsequently, a mapping relationship is established between the application data and the cache block. However, when the size of a single piece of application data is small, the aforementioned problem of low bandwidth utilization will occur.

[0183] Therefore, in the technical solution of this application, the mapping relationship between the dataset and the cache block can be determined. A dataset can contain at least one piece of application data, which can enable multiple pieces of data to be aggregated together to perform file IO together, so as to avoid the problem of low data utilization caused by each piece of application data performing file IO separately.

[0184] For example, in each round of data processing, at least one piece of application data can be identified from the remaining application data in the UFS, thereby determining the dataset corresponding to this round of data processing. In this embodiment, Xi represents the dataset determined in the data preparation of the i-th round. The total size of at least one piece of application data is less than or equal to the size Mi of the cache block.

[0185] In one implementation, for example, from the remaining application data in the UFS, multiple application data entries with the smallest difference between their total size and the cache block size Mi can be selected to form a dataset Xi. There may be various combinations of these multiple application data entries with the smallest difference between their total size and the cache block size Mi; for example, they can be selected in a certain order or randomly. This embodiment does not limit this approach. This implementation method can maximize the utilization of the allocated cache blocks and avoid memory waste.

[0186] S603. Write the dataset Xi to the requested cache block.

[0187] After completing steps S601 and S602, one round of data preparation is complete. As described above, this round of data preparation establishes the mapping relationship between dataset Xi and the requested cache block. Then, file I / O for dataset Xi can be submitted to write dataset Xi into the requested cache block.

[0188] In the technical solution of this embodiment, data preparation and file I / O processing can be performed asynchronously, for example, as described in [reference needed]. Figure 8 In other words, after a round of data preparation is completed, on the one hand, file I / O will be submitted for the dataset Xi involved in this round of data preparation, and on the other hand, the next round of data preparation can be started simultaneously.

[0189] It is understandable that a file I / O operation is performed after each round of data preparation, which is the operation of writing the dataset into the allocated cache block as described in the current step. Therefore, it can be determined that the file I / O operation is also performed n times. That is, in the technical solution of this application, n file processing operations are performed, which can be referred to as the first operation. Similarly, in the technical solution of this application, n data preparation operations are also performed, which can be referred to as the second operation.

[0190] S604. Determine whether the data processing is complete. If yes, end the process; otherwise, execute S605.

[0191] Furthermore, after completing one round of data preparation, it is also possible to determine whether the swapping of application data in UFS has been completed, that is, to determine whether there is still unprocessed application data in UFS, where unprocessed application data is application data for which no mapping relationship has been established.

[0192] In one scenario, if it is determined that data processing is complete, the data preparation process can be terminated because there is no more application data that needs to be prepared.

[0193] In another scenario, if it is determined that data processing is incomplete, another round of data preparation and file I / O processing needs to be performed, as subsequent steps and the next round of data preparation will continue.

[0194] S605. Based on the bandwidth corresponding to the datasets of the two consecutive rounds preceding this round, determine the size of the cache block for the next round.

[0195] If data processing is incomplete, the next round of data preparation needs to be performed. Based on the above description, the size of the requested cache block can be determined in advance before each round of data preparation.

[0196] In one implementation, the size of the cache block for the next round (round i+1) can be determined based on the bandwidth corresponding to the datasets of the two consecutive rounds preceding the current round—that is, the bandwidth corresponding to the dataset of the round before that (round i-2) and the dataset of the previous round (round i-1). Rounds i-2 and i-1 are chosen because the bandwidth of the dataset can only be determined after file I / O is complete. At the start of data preparation for round i+1, the file I / O corresponding to data preparation for round i is usually still in progress, making it impossible to know the bandwidth corresponding to the dataset of round i. However, at the start of data preparation for round i+1, the file I / O corresponding to data preparation for rounds i-2 and i-1 has usually been completed, allowing the bandwidth corresponding to these two rounds of file I / O to be obtained. This enables data preparation for round i+1 to begin directly without waiting. Therefore, in order to ensure that multiple rounds of data preparation can be executed continuously, this embodiment compares the bandwidth corresponding to the dataset of round i-2 with the bandwidth corresponding to the dataset of round i-2 to determine the size of the cache block of round i+1.

[0197] For example, after the file I / O corresponding to the data preparation in round i-2 is completed, the bandwidth for file I / O of the dataset in round i-2 can be obtained, and after the file I / O corresponding to the data preparation in round i-1 is completed, the bandwidth for file I / O of the dataset in round i-1 can be obtained. Then, based on the bandwidth of these two rounds, it can be determined whether to increase the size of the cache block.

[0198] For the sake of illustrative purposes, the following description will be combined with... Figure 7 One possible correspondence between I / O size and bandwidth is introduced.

[0199] exist Figure 7 In the diagram, the horizontal axis represents the I / O size, which is the total size of the dataset determined during data preparation. The vertical axis represents bandwidth. For example, with a total dataset size of 10MB, the corresponding bandwidth is 2.6GB / s. The correspondence between the total dataset size and bandwidth for other datasets can be found in [reference needed]. Figure 7 This will be understood in more detail here.

[0200] After each round of data preparation is completed, file I / O can be submitted for the dataset determined in this round of data preparation. After the file I / O is completed, the bandwidth corresponding to this round of dataset can be determined.

[0201] Furthermore, the following section will describe the implementation process of determining the cache block size for the next round based on the bandwidth corresponding to the datasets from the previous two rounds. For ease of explanation, the bandwidth corresponding to the dataset from the (i-2)th round will be represented as IO. i-2 And represent the bandwidth corresponding to the dataset in the (i-1)th round as I / O. i-1 .

[0202] In one implementation, for example, I / O can be determined. i-1 and IO i-2 The ratio, that is Then I / O i-1 and IO i-2 The ratio is compared with a first preset threshold. The first preset threshold is used to determine whether the cache block size needs to be increased. For example, the first preset threshold can be a predefined fixed value, or it can be an empirical value, etc.

[0203] If the ratio is greater than or equal to the first preset threshold, it means that the bandwidth of the previous round has increased significantly compared to the bandwidth of the round before that. This indicates that the bandwidth gain brought about by the increase in the size of the cache block is still in a phase of rapid growth, and therefore it can be determined that the current bandwidth does not meet the preset conditions. Therefore, the size of the cache block in the current round (i.e., the i-th round) can be increased to obtain the size of the cache block in the next round.

[0204] For example, in each size expansion process, the current size can be multiplied by T to obtain the expanded size, where T is a value greater than or equal to 1. The value of T can be arbitrarily set according to actual needs. For example, the value of T can be a pre-selected fixed value, or the value of T can be a value that makes the sizes of the successively expanded cache blocks satisfy a specific data relationship. The specific data relationship introduced here can be, for example, geometric or arithmetic progression, or the specific data relationship can be set according to actual needs, as long as the value of T makes the size of the cache block in the later round greater than the size of the cache block in the previous round.

[0205] The following example uses a fixed value for T. For instance, if the cache block size in round i is 4MB and the value of T is fixed at 2, then the size can be increased from the 4MB cache block size in round i to obtain a cache block size of 8MB in round i+1.

[0206] Alternatively, during the size expansion process, a first value can be added to the current size to obtain the expanded size. The first value can be a pre-set fixed value, or it can be a value that makes the sizes of the sequentially enlarged cache blocks satisfy a specific data relationship. The specific data relationship is similar to that described above and will not be repeated here.

[0207] Alternatively, if the ratio is less than a first preset threshold, it means that the bandwidth increase in the previous round is relatively small compared to the round before that. This indicates that the bandwidth gain from increasing the cache block size is already quite small. In other words, if the cache block size continues to increase, although bandwidth can still be increased, the increase will be relatively small. As explained above, if the aggregated data size is too large, it will affect other I / O operations and result in excessively long data preparation times. Therefore, in this case, it can be determined that the current bandwidth meets the preset conditions. Therefore, the cache block size can be discontinued, and instead, the size corresponding to the cache block in the current round can be determined as the size corresponding to the cache block in the next round.

[0208] For example, if the cache block size in round i is 8MB, and if it is determined that the cache block size will not be expanded further based on the bandwidth of the dataset in round i and the bandwidth of the dataset in round i-1, then the cache block size in round i+1 can be determined to be 8MB.

[0209] Furthermore, in another implementation, for example, deterministic I / O can be used. i-1 and IO i-2 The difference, i.e., IO i-1 -IO i-2 Then I / O i-1 and IOi-2 The difference is compared with a second preset threshold. The second preset threshold is used to determine whether the cache block size needs to be increased. For example, the second preset threshold can be a predefined fixed value, or it can be an empirical value, etc.

[0210] If the difference is greater than or equal to the second preset threshold, it means that the bandwidth increase in the previous round is relatively large compared to the bandwidth in the round before that. This indicates that the bandwidth gain brought about by the increase in cache block size is still in a phase of rapid growth, and therefore it can be determined that the current bandwidth does not meet the preset conditions. Therefore, the size of the cache block in the current round can be increased to obtain the size of the cache block in the next round.

[0211] Alternatively, if the ratio is less than a first preset threshold, it means that the bandwidth increase in the previous round was relatively small compared to the bandwidth in the round before that. This indicates that the bandwidth gain from increasing the size of the cache block is already relatively small. Therefore, the size of the cache block can be further expanded, and instead, the size of the cache block in the current round can be determined as the size of the cache block in the next round.

[0212] In actual implementation, the specific implementation for determining the size of the cache block in the next round based on the bandwidth corresponding to the datasets of the two consecutive rounds preceding the current round can be selected according to actual needs. This embodiment does not impose any restrictions on this, as long as the bandwidth change is determined based on the bandwidth corresponding to the datasets of the two consecutive rounds preceding the current round, and then a decision is made on whether to continue increasing the size of the cache block based on the bandwidth change.

[0213] For example, you can refer to Figure 7 The correspondences introduced are illustrated with a specific example. Figure 7 In the diagram, the horizontal axis represents the I / O size, which is the total size of the dataset determined during data preparation. The vertical axis represents the bandwidth.

[0214] Reference Figure 7 The first point on the curve shown, for example, if the dataset corresponding to the (i-2)th round has a size of 1MB, then refer to... Figure 7 It can be determined that the corresponding bandwidth is 0.5 GB / s. For example, refer to... Figure 7 The second point on the curve shown, for example, if the dataset size corresponding to the (i-1)th round is 2MB, then refer to... Figure 7It can be determined that the corresponding bandwidth is 0.8 GB / s. Taking the ratio implementation as an example, the bandwidth ratio of these two rounds is 0.8 / 0.5 = 1.6. For example, the first preset threshold is set to 1.4. Since the bandwidth ratio is greater than the first preset threshold, the cache block can be expanded. For example, based on the size of the cache block in the i-th round (e.g., 2 MB), assuming the amplification factor T is fixed at 2, the expansion can be performed to obtain the size of the cache block in the next round (i+1 round) (i.e., 2 MB × 2 = 4 MB).

[0215] For example, refer to Figure 7 The 6th point on the curve shown, for example, if the dataset size for the (i-2)th round is 16MB, then refer to... Figure 7 It can be confirmed that the corresponding bandwidth is 3.2 GB / s. For example, refer to... Figure 7 The 7th point on the curve shown, for example, if the dataset size corresponding to the (i-1)th round is 32MB, then refer to... Figure 7 It can be determined that the corresponding bandwidth is 4GB / s. Taking the ratio implementation as an example, the bandwidth ratio between these two rounds is 4 / 3.2 = 1.17. For example, the first preset threshold is set to 1.4. Then it can be determined that the bandwidth ratio is less than the first preset threshold, so the expansion of the cache block can be stopped. That is, the size of the cache block in the i-th round (for example, 2MB) can be determined as the size of the cache block in the next round (i+1th round) (also 2MB).

[0216] After determining the size of the cache block in round i+1, the steps starting with S601 above can be continued based on the determined cache block size to perform the next round of data preparation and file I / O. This process is repeated multiple times until all the application's data in the UFS has been swapped in.

[0217] The above description focuses on the data preparation process. As can be understood from this description, data preparation and file I / O operations are one-to-one; that is, for every n rounds of data preparation, there will be a corresponding n rounds of file I / O. Furthermore, the implementation of the cache block size can be described as follows: the first size of the cache block in the i-th file I / O operation is greater than or equal to the second size of the cache block in the (i-1)-th file I / O operation.

[0218] When i is equal to 2 or 3 (i.e., when performing the second or third round of file I / O), there is no need to judge the bandwidth during the data preparation process. Instead, the cache block is directly expanded, so the first size is larger than the second size.

[0219] Furthermore, when the value of i is greater than 3, there are two possibilities for the first and second dimensions: the first dimension is greater than the second dimension, or the first dimension is equal to the second dimension.

[0220] For example, if the first condition is met, where the first size is equal to the second size, then no cache block expansion occurred during data preparation. If the first condition is not met, where the first size is greater than the second size, then cache block expansion occurred during data preparation.

[0221] The first condition includes: the first bandwidth and the second bandwidth satisfy a first quantitative relationship, where the first bandwidth is the bandwidth corresponding to the (i-2)th first operation, and the second bandwidth is the bandwidth corresponding to the (i-3)th first operation. That is, given that the first bandwidth corresponding to the (i-2)th first operation and the second bandwidth corresponding to the (i-3)th first operation satisfy the first quantitative relationship, the size of the cache block corresponding to the i-th first operation is larger than the size of the cache block corresponding to the (i-1)th first operation. In other words, in this case, the size of the cache block is enlarged during the data preparation process.

[0222] The first bandwidth can be represented as I / O, for example. i-2 The second bandwidth can be represented as I / O, for example. i-3 .

[0223] The first quantitative relationship may include the ratio of the first bandwidth to the second bandwidth being less than a first preset threshold; and / or the first quantitative relationship may include the difference between the first bandwidth and the second bandwidth being less than a second preset threshold.

[0224] The implementation of the second size is determined based on a first condition, which determines whether to expand the first size. This is similar to the implementation described above, which determines the size of the cache block in the next round based on the bandwidth corresponding to the datasets of the two consecutive rounds preceding the current round. The only difference is the number of rounds used in the description. The data preparation implementation described above focuses on determining the size of the cache block in the next round (round i+1), thus using the two rounds preceding the current round, since the current description is actually based on round i+1. However, the file I / O implementation described here describes the relationship between the cache block size in round i and round -1, therefore using rounds i-3 and i-2, since the current description is actually based on round i. The specific implementation can be understood by referring to the above description.

[0225] The process described above will be further explained in detail below with a specific example. Figure 8 and Figure 9The CCP demonstrated a five-round data processing procedure, followed by file I / O processing after each round. The following sections, with accompanying diagrams, provide a detailed explanation of each round of the data processing.

[0226] 1. First round of data processing

[0227] like Figure 8 As shown, in the first round of data processing, cache block 901 can be requested from memory, for example. Referring to the above embodiment, it can be understood that the size of the first-round cache block can be preset, meaning the starting size of the requested cache block can be pre-set. For example, if the starting size of the cache block is pre-set to 1MB, then the size of cache block 901 could be, for instance, 1MB. In actual implementation, the starting size of the cache block can be arbitrarily set according to actual needs; this embodiment does not impose any restrictions on this.

[0228] Next, it is necessary to determine the dataset corresponding to cache block 901. Figure 9 The diagram illustrates the dataset corresponding to each cache block, and each dataset can contain at least one piece of application data.

[0229] For example, it can be combined Figure 10 To understand the implementation of a given dataset, such as Figure 10 As shown in the figure. For example, there are currently 11 application data entries, namely data A to data K. The figure also shows the data size corresponding to each application data entry, which will not be elaborated here.

[0230] In this embodiment, for example, the combination of application data with the smallest difference between the total size and the size of cache block 901 can be selected from these 11 application data items to obtain the dataset corresponding to cache block 901. For instance, in the first round of data preparation, the size of cache block 901 is 1MB, so... Figure 10 Among the multiple application data points shown, select the data combination with the smallest difference between the sum of the data sizes and 1MB. For example, data A and data E can be defined as a dataset with a total size of 1MB.

[0231] Reference Figure 9 As shown, the dataset 1 corresponding to cache block 901 contains data A and data E. A mapping relationship between cache block 901 and dataset 1 can then be established. Next, file I / O for dataset 1 can be submitted to write dataset 1 into cache block 901, meaning data A and data E are aggregated and written to cache block 901. Compared to submitting separate file I / O for data A and data E, this implementation method can improve bandwidth utilization.

[0232] and reference Figure 8It is certain that in this embodiment, data preparation and file I / O are performed asynchronously. That is, after the first round of data preparation is completed, I / O processing of the dataset involved in the first round of data preparation will be submitted. Simultaneously with the I / O processing, the next round of data preparation will begin. Figure 8 The image shows the second round of data preparation performed in time period 2. (See image for details.) Figure 8 As shown, the time period corresponding to the first round of data preparation is Time Period 1, the time period corresponding to file I / O after the first round of data preparation is Time Period 6, and the time period corresponding to the second round of data preparation is Time Period 2. Time Period 6 and Time Period 2 overlap, indicating that file I / O and data preparation are executed asynchronously. (See also...) Figure 8 It can also be understood that the start time of period 6 is after the end time of period 1, which means that we need to wait for a round of data preparation to be completed before we can perform the file I / O corresponding to this round of data preparation.

[0233] After the first round of data processing is completed, it can be determined whether there is any remaining data. If so, the second round of data processing will continue.

[0234] As can be understood from the above embodiments, the technical solution of this application can determine whether to increase the size of the cache block to obtain the size of the cache block for the next round based on the bandwidth corresponding to the data processing of the two consecutive rounds preceding the current round (round i-2 and round i-1). However, after the first round of data processing is completed, only one round of data processing has been performed, and it is necessary to wait for the file I / O corresponding to the first round of data processing to be completed before the bandwidth corresponding to the first round of file I / O can be obtained. That is, the bandwidth of the first round of file I / O cannot be obtained at present, so it is impossible to determine the bandwidth change based on two rounds of data processing. Therefore, for the second round of data processing, the cache block size can be directly increased without determining the bandwidth change.

[0235] For example, the size of the enlarged cache block can be obtained by multiplying the current cache block size by T. This enlarged size is also the size determined for the next round of data preparation. For instance, if T is 2, then the cache block size for the second round of data processing will be 2MB.

[0236] 2. Second round of data processing

[0237] like Figure 8 As shown, in the second round of data processing, for example, a cache block 902 of size 2MB can be requested from memory.

[0238] Next, it is necessary to determine the dataset corresponding to cache block 902. For example, this can be done by combining... Figure 10 To understand the implementation of a given dataset, such as Figure 10 As shown. For example, there are currently 11 application data items, namely data A to data K. Referring to the above introduction, it can be determined that in the first round of data processing, data A and data E have been identified as data in the dataset corresponding to cache block 901, which means that the file I / O of these two data items has been committed. Therefore, these two data items will not participate in the subsequent data preparation work. Thus, in the second round of data processing, data will be selected from the remaining application data to determine the dataset.

[0239] In this embodiment, the remaining application data, along with data other than data A and data E, can be selected from these nine application data items. For example, the combination of application data with the smallest difference between its total size and the size of cache block 902 can be chosen to obtain the dataset corresponding to cache block 902. For instance, in the second round of data preparation, if the size of cache block 902 is 2MB, then... Figure 10 Among the multiple remaining application data points shown, select the data combination with the smallest difference between the sum of the data sizes and 2MB. For example, data G and data K can be defined as a dataset with a total size of 1.9MB.

[0240] Reference Figure 9 As shown, the dataset 2 corresponding to cache block 902 contains data G and data K. A mapping relationship between cache block 902 and dataset 2 can then be established. Next, file I / O for dataset 2 can be submitted to write dataset 2 into cache block 902, meaning that data G and data H are aggregated and written to cache block 902. Compared to implementing separate file I / O for data G and data K, this implementation method can improve bandwidth utilization.

[0241] and reference Figure 8 It is certain that in this embodiment, data preparation and file I / O are performed asynchronously. That is, after the second round of data preparation is completed, I / O processing of the dataset involved in the second round of data preparation will be submitted. Simultaneously with the I / O processing, the next round of data preparation will begin. Figure 8 The data preparation for the third round, as shown, was performed in time period 3. Figure 8 As shown, the time period corresponding to the second round of data preparation is time period 2, the time period corresponding to file I / O after the second round of data preparation is time period 7, and the time period corresponding to the third round of data preparation is time period 3. Time periods 7 and 3 overlap, indicating that file I / O and data preparation are executed asynchronously. (See also...) Figure 8 It can also be understood that the start time of period 7 is after the end time of period 2, which means that we need to wait for a round of data preparation to be completed before we can perform the file I / O corresponding to this round of data preparation.

[0242] After the second round of data processing is completed, it can be determined whether there is any remaining data. If so, the third round of data processing will continue.

[0243] As can be understood from the above embodiments, the technical solution of this application can determine whether to increase the size of the cache block to obtain the size of the cache block for the next round based on the bandwidth corresponding to the data processing of the two consecutive rounds preceding the current round (round i-2 and round i-1). However, after the second round of data processing is completed, only two rounds of data processing have been performed, and it is necessary to wait for the file I / O corresponding to the second round of data processing to be completed before the bandwidth corresponding to the file I / O of the second round can be obtained. That is, the bandwidth of the file I / O of the second round cannot be obtained at present, so it is impossible to determine the bandwidth change based on the two rounds of data processing. Therefore, for the third round of data processing, the cache block size can be directly increased without determining the bandwidth change.

[0244] For example, the size of the enlarged cache block can be obtained by multiplying the current cache block size by T, which is also the size determined for the next round of data preparation. For instance, if T is 2, then the cache block size for the third round of data processing would be 4MB.

[0245] 3. Third round of data processing

[0246] Reference Figure 8 For example, a 4MB cache block 903 can be requested from memory.

[0247] Next, it is necessary to determine the dataset corresponding to cache block 903. For example, this can be done by combining... Figure 10 To understand the implementation of a given dataset, such as Figure 10 As shown. For example, there are currently 11 application data entries, numbered from data A to data K. Similar to the above description, in the third round of data processing, data will be selected from the remaining application data excluding data A, data E, data G, and data K to determine the dataset. Among them, data A, data E, data G, and data K are data that have already been selected in previous rounds of data processing.

[0248] In this embodiment, for example, from the remaining application data excluding data A, data E, data G, and data K, the combination of application data with the smallest difference between the total size and the size of cache block 903 can be selected to obtain the dataset corresponding to cache block 903. For instance, in the third round of data preparation, the size of cache block 903 is 4MB, so... Figure 10Among the multiple remaining application data as shown, select the data combination with the smallest difference between the sum of the data sizes and 4MB. For example, data B, data D, and data H can be defined as a dataset with a total size of 4MB.

[0249] Reference Figure 9 As shown, the dataset 3 corresponding to cache block 903 contains data B, data D, and data H. A mapping relationship between cache block 903 and dataset 3 can then be established. Next, file I / O for dataset 3 can be submitted to write dataset 3 into cache block 903; that is, data B, data D, and data H are aggregated and written to cache block 903. Compared to implementing separate file I / O for data B, data D, and data H, this implementation method can improve bandwidth utilization.

[0250] and reference Figure 8 It is certain that in this embodiment, data preparation and file I / O are performed asynchronously. That is, after the third round of data preparation is completed, I / O processing of the dataset involved in the third round of data preparation will be submitted. Simultaneously with the I / O processing, the next round of data preparation will begin. Figure 8 The data preparation for the fourth round, performed in time period 4, is shown below. Figure 8 As shown, the time period corresponding to the third round of data preparation is time period 3, the time period corresponding to file I / O after the third round of data preparation is time period 8, and the time period corresponding to the fourth round of data preparation is time period 4. Time periods 8 and 4 overlap, indicating that file I / O and data preparation are executed asynchronously. (See also...) Figure 8 It is also understandable that the start time of time period 8 is after the end time of time period 3, which means that we need to wait for a round of data preparation to be completed before we can perform the file I / O corresponding to this round of data preparation.

[0251] After the third round of data processing is completed, it can be determined whether there is any remaining data. If so, the fourth round of data processing will continue.

[0252] As can be understood from the above embodiments, the technical solution of this application can determine whether to increase the size of the cache block to obtain the size of the cache block for the next round based on the bandwidth corresponding to the data processing of the two consecutive rounds preceding the current round (round i-2 and round i-1). For example, based on the file I / O processing corresponding to the first round of data processing (i.e., file I / O for dataset 1), the corresponding bandwidth IO1 can be determined, and based on the file I / O processing corresponding to the second round of data processing (i.e., file I / O for dataset 2), the corresponding bandwidth IO2 can be determined. For instance, if the ratio of IO2 to IO1 is greater than a preset threshold, then it can be determined that the size of the cache block needs to be further increased.

[0253] For example, the size of the enlarged cache block can be obtained by multiplying the current cache block size by T. For instance, if T is 2, then the cache block size corresponding to the 4th round of data processing would be 8MB.

[0254] 4. Fourth round of data processing

[0255] like Figure 8 As shown, in the fourth round of data processing, for example, a cache block 904 of size 8MB can be requested from memory.

[0256] Next, it is necessary to determine the dataset corresponding to cache block 904. For example, this can be done by combining... Figure 10 To understand the implementation of a given dataset, such as Figure 10 As shown. For example, there are currently 11 application data entries, numbered from A to K. Similar to the above description, in the fourth round of data processing, data will be selected from the remaining application data excluding A, E, G, K, B, D, and H to determine the dataset. Data A, E, G, K, B, D, and H are data that have already been selected in previous rounds of data processing.

[0257] In this embodiment, for example, from the remaining application data excluding data A, data E, data G, data K, data B, data D, and data H, the combination of application data with the smallest difference between the total size and the size of cache block 904 can be selected to obtain the dataset corresponding to cache block 904. For instance, in the fourth round of data preparation, if the size of cache block 904 is 8MB, then... Figure 10 Among the multiple remaining application data points shown, select the data combination with the smallest difference between the sum of the data sizes and 8MB. For example, data F and data I can be defined as a dataset with a total size of 8MB.

[0258] Reference Figure 9 As shown, the dataset 4 corresponding to cache block 904 contains data F and data I. A mapping relationship between cache block 904 and dataset 4 can then be established. Next, file I / O for dataset 4 can be submitted to write dataset 4 into cache block 904, meaning that data F and data I are aggregated and written to cache block 904. Compared to implementing separate file I / O for data F and data I, this implementation method can improve bandwidth utilization.

[0259] and reference Figure 8It is certain that in this embodiment, data preparation and file I / O are performed asynchronously. That is, after the fourth round of data preparation is completed, I / O processing of the dataset involved in the fourth round of data preparation will be submitted. Simultaneously with the I / O processing, the next round of data preparation will begin. Figure 8 The image shows the fifth round of data preparation performed during time period 5. (As shown...) Figure 8 As shown, the time period corresponding to the fourth round of data preparation is time period 4, the time period corresponding to file I / O after the fourth round of data preparation is time period 9, and the time period corresponding to the fifth round of data preparation is time period 5. Time periods 9 and 5 overlap, indicating that file I / O and data preparation are executed asynchronously. (See also...) Figure 8 It is also understandable that the start time of period 9 is after the end time of period 4, which means that we need to wait for a round of data preparation to be completed before we can perform the file I / O corresponding to this round of data preparation.

[0260] After the fourth round of data processing is completed, it can be determined whether there is any remaining data. If so, the fifth round of data processing will continue.

[0261] As can be understood from the above embodiments, the technical solution of this application can determine whether to increase the size of the cache block to obtain the size of the cache block for the next round based on the bandwidth corresponding to the data processing of the two consecutive rounds preceding the current round (round i-2 and round i-1). For example, based on the file I / O processing corresponding to the second round of data processing (i.e., file I / O for dataset 2), the corresponding bandwidth IO2 can be determined, and based on the file I / O processing corresponding to the third round of data processing (i.e., file I / O for dataset 3), the corresponding bandwidth IO3 can be determined. For instance, if the ratio of IO3 to IO2 is less than a preset threshold, then it can be determined that there is no need to increase the size of the cache block.

[0262] For example, the size of the cache block in the fourth round of data processing can be determined as the size of the cache block in the fifth round of data processing. Then the cache block size corresponding to the fifth round of data processing would be equal to 8MB.

[0263] 5. Fifth round of data processing

[0264] like Figure 8 As shown, in the fifth round of data processing, for example, a cache block 905 of size 8MB can be requested from memory.

[0265] Next, it is necessary to determine the dataset corresponding to cache block 905. For example, this can be done by combining... Figure 10 To understand the implementation of a given dataset, such as Figure 10As shown. For example, there are currently 11 application data entries, numbered from A to K. Similar to the above description, in the fourth round of data processing, data will be selected from the remaining application data excluding A, E, G, K, B, D, H, F, and I to determine the dataset. Data A, E, G, K, B, D, H, F, and I are data that have already been selected in previous rounds of data processing.

[0266] In this embodiment, for example, from the remaining application data excluding data A, data E, data G, data K, data B, data D, data H, data F, and data I, the combination of application data with the smallest difference between the total size and the size of cache block 905 can be selected to obtain the dataset corresponding to cache block 905. For example, in the 5th round of data preparation, the size of cache block 905 is 8MB, then... Figure 10 Among the multiple remaining application data points shown, select the data combination with the smallest difference between the sum of the data sizes and 8MB. For example, data C and data J can be defined as a dataset with a total size of 7.1MB.

[0267] Reference Figure 9 As shown, the dataset 5 corresponding to cache block 905 contains data C and data J. A mapping relationship between cache block 905 and dataset 5 can then be established. Next, file I / O for dataset 5 can be submitted to write dataset 5 into cache block 905, meaning that data C and data J are aggregated and written to cache block 905. Compared to implementing separate file I / O for data C and data J, this implementation method can improve bandwidth utilization.

[0268] After the fifth round of data processing is completed, it can be determined whether there is any remaining data. If there is no remaining data, the current process can be terminated, meaning there is no need to execute the next round of data processing.

[0269] and reference Figure 8 It is certain that in this embodiment, data preparation and file I / O are performed asynchronously. That is, after the fifth round of data preparation is completed, the I / O processing of the dataset involved in the fifth round of data preparation will be submitted; in this example, there is no next round of data processing. Figure 8 As shown, the time period corresponding to the 5th round of data preparation is time period 5, and the time period corresponding to the file I / O after the 5th round of data preparation is time period 10. The start time of time period 10 is after the end time of time period 5, which means that we need to wait for the completion of one round of data preparation before we can perform the file I / O corresponding to this round of data preparation.

[0270] Furthermore, it should be noted that in the data preparation stage, the technical solution of this application selects the data combination whose sum of data sizes differs from the size of the cache block by choosing the combination with the smallest difference between the sum of the data sizes and the size of the cache block. However, it is understandable that in actual implementation, there may be multiple combinations of data whose sum of data sizes differs from the size of the cache block.

[0271] For example, considering an 8MB cache block, among multiple application data entries, suppose there are four data entries with sizes of 3MB, 5MB, 2MB, and 6MB respectively. Then, the difference between the size of the 3MB and 5MB data combination and the size of the 8MB cache block is 0, and the difference between the size of the 2MB and 6MB data combination and the size of the 8MB cache block is also 0. This means that the 3MB and 5MB data combination can be identified as the dataset corresponding to this cache block, and the 2MB and 6MB data combination can also be identified as the dataset corresponding to this cache block.

[0272] If there are multiple data combinations whose sum of data sizes has the smallest difference from the size of the cache block, for example, one of the data combinations described here can be selected as the dataset corresponding to the cache block.

[0273] In summary, the technical solution of this application can aggregate multiple application data items together for file I / O during multi-round data processing by expanding the size of the cache block. Compared to the implementation method of submitting file I / O separately for each application data item, the technical solution of this application can effectively improve bandwidth utilization. Furthermore, the technical solution of this application does not continuously increase the size of the cache block during the expansion process. Instead, it determines whether to continue expanding the cache block size based on the actual bandwidth of the file I / O corresponding to the dataset. If the bandwidth already meets the preset conditions, the cache block is not expanded further, and the current cache block size is retained. This avoids excessive data aggregation and ensures a reasonable time ratio between data preparation and file I / O based on aggregated I / O.

[0274] Furthermore, in the technical solution of this application, when performing data aggregation for file I / O, the data is not cached in a unit first, and then file I / O is performed only after the amount of cached data in that unit exceeds a threshold. It is understandable that this implementation, which waits for the amount of cached data to reach a threshold before submitting file I / O, requires waiting for the cumulative amount of multiple data entries to reach a specific threshold. Therefore, the time spent waiting for the data to reach the preset threshold will result in latency.

[0275] For example, after writing data 1 to the cache unit, the cached data volume is below the threshold; after writing data 2 to the cache unit, the cached data volume is also below the threshold; after writing data 3 to the cache unit, the cached data volume reaches the threshold. Then, these three data entries are submitted together for file I / O. It can be understood that this implementation waits for three data entries to be written to the cache unit before performing subsequent file I / O, and this waiting period causes latency in the data writing process.

[0276] The technical solution of this application involves, after determining the size of the cache block, directly selecting at least one piece of application data from multiple pieces of application data that matches the size of the cache block to obtain a dataset, and then directly submitting file I / O for this dataset. This implementation method does not require waiting for the data volume to reach a threshold; instead, it can directly determine the matching dataset based on the size of the cache block and then directly submit the file I / O corresponding to that dataset. Therefore, this implementation method can improve the efficiency of data swapping from one storage space to another.

[0277] Furthermore, the technical solution of this application also proposes asynchronous execution of file I / O and data preparation, which allows file I / O and data preparation to be executed in parallel. For example, after submitting file I / O for one data preparation, the next data preparation can be executed synchronously, which can further improve the efficiency of data swapping from one storage space to another.

[0278] For example, before adopting the technical solution of this application, the IO size was mainly concentrated between 500K and 14MB, the IO bandwidth was about 1.2GB / s, and the bandwidth utilization rate was 20% to 50%. After adopting the technical solution of this application, the IO size was mainly concentrated between 32 and 64MB, the IO bandwidth was about 3.5GB / s, and the bandwidth utilization rate was 80% to 95%. It can be seen that the technical solution of this application can significantly improve the bandwidth utilization rate.

[0279] It's also important to understand that, besides the low bandwidth utilization issue when writing data from UFS to memory during an application switch from the background to the foreground, the process of writing data from memory to UFS during the application switch from the foreground to the background also suffers from low bandwidth utilization. The above describes solutions for improving bandwidth utilization during the process of writing data from UFS to memory. In fact, the same techniques can be used to improve bandwidth utilization when writing data from memory to UFS. The specific implementation in this scenario is similar to that described above; the only difference is the direction of data writing. That is, the application data was originally stored in memory, and now it needs to be swapped out of memory to UFS.

[0280] Furthermore, as can be understood from the above description, the data preparation and file I / O processing described in this application are executed asynchronously. In one implementation, for example, data preparation operations can be performed based on a first thread, and file I / O operations can be performed based on a second thread. This achieves asynchronous execution of data preparation and file I / O, thereby improving CPU and bandwidth utilization.

[0281] It should also be noted that the above embodiments describe the implementation of determining the cache block size, that is, the size of the cache block in the i-th round of data preparation can be determined based on the size of the cache block in the (i-1)-th round of data preparation. However, it is understood that the current cache block allocation is for storing application data. Although the size of application data is usually relatively small, it is possible to aggregate multiple data submissions to store multiple application data in the cache block allocated in the i-th round. However, in some special cases, if the size of multiple remaining application data items in UFS is larger than the size of the cache block in the i-th round of data preparation, then there will be no data available to be stored in that cache block in this round.

[0282] To avoid this situation, after determining the size of the cache block in the i-th round of data preparation based on the size of the cache block in the (i-1)-th round of data preparation, it can be determined whether there are any application data records in the remaining UFS with a size smaller than the currently determined cache block size. If so, the i-th round of data preparation is performed using the currently determined cache block size to request a cache block, as this ensures that there is data that can be written to the cache block.

[0283] However, if no application data with a size smaller than the currently determined cache block size exists, it means that the remaining data in UFS cannot be written to a cache block of that size. In this case, the size of the cache block in the i-th round of data preparation can be adjusted. For example, the currently determined cache block size can be increased by a factor of T to obtain the size of the cache block in the i-th round of data preparation. Subsequent cache block requests in the i-th round can then be based on this size. Alternatively, the application data with the smallest size can be determined from the remaining application data, and its size can be set as the size of the cache block in the i-th round of data preparation. This ensures that at least one piece of data can be written to this cache block.

[0284] After determining the size of the cache block in the i-th round of data preparation based on the size of the cache block in the (i-1)-th round of data preparation, the specific strategy for adjusting the size of the cache block in the i-th round of data preparation can be determined according to actual needs, as long as it ensures that at least one piece of application data can be written to the cache block requested in the i-th round. It is also important to understand that determining the size of the cache block is done before requesting the cache block; therefore, the implementation of adjusting the size of the cache block described above will be completed before the cache block request operation included in the i-th round of data preparation.

[0285] Based on the above description, the memory processing method provided in this application will be further explained below. The memory processing method provided in this application can be applied to electronic devices, wherein the electronic device has a first storage space and a second storage space. The first storage space can be volatile memory, for example, RAM. The second storage space can be non-volatile memory, for example, UFS, and multiple application data entries of a first application can be stored in the second storage space.

[0286] The technical solution of this application may include the following steps:

[0287] When the first application switches from the background to the foreground, the first operation is performed n times. The first operation includes: writing the dataset to a cache block requested from the first storage space, wherein the dataset includes at least one piece of application data from multiple pieces of application data in the second storage space, the size of the dataset is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3.

[0288] The first operation is the file I / O operation described above. For details on the specific implementation of the electronic device performing the first operation n times, please refer to the file I / O processing described in the above embodiments for understanding, which will not be repeated here.

[0289] Furthermore, in the technical solution of this application, the first size of the cache block in the first operation of the i-th iteration is greater than or equal to the second size of the cache block in the (i-1)-th iteration, where i takes the value of 2 to n. That is, the size of the cache block involved in the n first operations is either increased sequentially or remains the same as the previous round. The determination of the cache block size in multi-round processing can be understood with reference to the description of the above embodiments, and will not be repeated here.

[0290] In summary, the technical solution of this application can aggregate at least one piece of data into a dataset to submit file I / O, thereby improving bandwidth utilization.

[0291] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0292] This application provides an electronic device, which includes a processor and a memory; the memory stores computer execution instructions; the processor executes the computer execution instructions stored in the memory, causing the electronic device to perform the above-described method.

[0293] This application provides a chip. The chip includes a processor, which is used to call a computer program in memory to execute the technical solutions in the above embodiments. Its implementation principle and technical effects are similar to those in the related embodiments described above, and will not be repeated here.

[0294] This application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, it implements the methods described above. The methods described in the above embodiments can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted over the computer-readable medium. The computer-readable medium can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium accessible by a computer.

[0295] In one possible implementation, a computer-readable medium may include random access memory (RAM), read-only memory (ROM), compact discread-only memory (CD-ROM) or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other medium intended to carry or store required program code in the form of instructions or data structures, and accessible by a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. As used herein, disks and optical discs include optical discs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0296] This application provides a computer program product, which includes a computer program that, when run, causes the computer to perform the above-described method.

[0297] It should be noted that the modules or components described in the above embodiments can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), etc. Furthermore, when a module is implemented through processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processors capable of calling program code, such as a controller. Additionally, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0298] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0299] The term "multiple" in this document refers to two or more. The term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the preceding and following related objects; in formulas, " / " indicates a "division" relationship. Additionally, it should be understood that in the description of this application, words such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0300] It is understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application.

[0301] It is understood that, in the embodiments of this application, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

Claims

1. A memory processing method, characterized in that, The method is applied to an electronic device, which includes a first storage space and a second storage space, wherein the second storage space stores multiple application data of a first application; The method includes: When the first application switches from the background to the foreground, the first operation is performed n times. The first operation includes: writing the dataset into a cache block requested from the first storage space, wherein the dataset includes at least one piece of application data from multiple pieces of application data in the second storage space, the size of the dataset is less than or equal to the size of the cache block, and n is an integer greater than or equal to 3. Wherein, the first size of the cache block in the i-th first operation is greater than or equal to the second size of the cache block in the (i-1)-th first operation, and the value of i is 2 to n; Before performing the i-th first operation, the method further includes: Perform a second operation, the second operation including: requesting the cache block from the first storage space based on the first size, and determining the dataset corresponding to the cache block; The process of determining the dataset corresponding to the cache block includes: identifying, from the remaining application data in the second storage space, a combination of at least one application data whose total size differs from the first size the smallest, to obtain the dataset corresponding to the cache block, wherein the remaining application data is application data that has not yet been assigned to the dataset.

2. The method according to claim 1, characterized in that, When the value of i is less than or equal to 3, the first dimension is greater than the second dimension.

3. The method according to claim 1 or 2, characterized in that, When the value of i is greater than 3, the size of the cache block is determined based on the bandwidth.

4. The method according to claim 3, characterized in that, When the value of i is greater than 3, the first size is determined based on the first bandwidth, the second bandwidth, and the second size. The first bandwidth is the bandwidth corresponding to the (i-2)th first operation, and the second bandwidth is the bandwidth corresponding to the (i-3)th first operation.

5. The method according to claim 4, characterized in that, When the first bandwidth and the second bandwidth satisfy a first quantitative relationship, the first size is equal to the second size; If the first bandwidth and the second bandwidth do not satisfy a first quantitative relationship, the first size is larger than the second size.

6. The method according to claim 5, characterized in that, The first quantitative relationship includes the ratio of the first bandwidth to the second bandwidth being less than a first preset threshold; and / or, the first quantitative relationship includes the difference between the first bandwidth and the second bandwidth being less than a second preset threshold.

7. The method according to any one of claims 1, 2, 4-6, characterized in that, When i is 1, the size of the cache block in the i-th first operation is a preset size.

8. The method according to any one of claims 1, 2, 4-6, characterized in that, The time period during which the first operation is performed for the jth time is the first time period, and the time period during which the second operation is performed before the (j+1)th first operation is the second time period. The first time period and the second time period overlap, and the value of j is 1 to n-1.

9. The method according to claim 8, characterized in that, The first operation is executed based on the first thread, and the second operation is executed based on the second thread.

10. The method according to any one of claims 1, 2, 4-6, and 9, characterized in that, When the first dimension is larger than the second dimension, the first dimension and the second dimension satisfy a second quantitative relationship.

11. The method according to claim 10, characterized in that, The second quantitative relationship is: the first dimension is T times the second dimension, or the difference between the first dimension and the second dimension is a first value, where T is a value greater than or equal to 1.

12. The method according to claim 1, characterized in that, The first storage space is a volatile memory, and the second storage space is a non-volatile memory.

13. An electronic device, characterized in that, The electronic device includes: one or more processors and memory; The memory is coupled to the one or more processors, the memory being used to store computer program code, the computer program code including computer instructions, the one or more processors invoking the computer instructions to cause the electronic device to perform the method as described in any one of claims 1-12.

14. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the one or more processors being used to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions that, when executed on an electronic device, cause the electronic device to perform the method as described in any one of claims 1-12.

16. A computer program product, characterized in that, The computer program product includes computer program code that, when run on an electronic device, causes the electronic device to perform the method as described in any one of claims 1-12.

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