Multi-phase clock-based cross-clock domain synchronization circuit and method

Abstract

The application relates to the technical field of integrated circuits, and discloses a multi-phase clock-based cross-clock domain synchronization circuit and method, wherein the circuit comprises a selector, an asynchronous clock synchronization module and a digital signal processor; wherein serial data to be transmitted and a low-frequency clock are input into the selector, the selector is used for outputting corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock; the asynchronous clock synchronization module is used for outputting corresponding alignment data to the digital signal processor according to the input RX parallel data, the clock of the digital signal processor and the low-frequency clock; the asynchronous clock synchronization module is used for performing phase alignment on the RX parallel data and the clock of the digital signal processor; and the digital signal processor is used for performing data processing on the alignment data. The application can realize stable transmission of low-delay cross-clock domain data.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a cross-clock domain synchronization circuit and method based on multi-phase clocks. Background Technology

[0002] In a data transmission system, serial data and a clock are sent from the transmitter (TX) to the receiver (RX). Driven by the input clock, the RX converts the serial data into parallel data and sends the parallel data to the digital signal processing unit (DSP). However, since the DSP's clock and the RX's input clock are asynchronous, with the same frequency but an uncertain phase relationship, the data and the DSP's clock must be aligned to enable correct sampling by the DSP, thus achieving cross-clock domain data transmission.

[0003] Currently, the traditional method uses an asynchronous first-in-first-out (FIFO) memory to achieve cross-clock domain data transfer. During the application, data is written to the FIFO driven by the first clock cycle, and the write pointer (wptr, pointing to the address where the data was written) is incremented. Driven by the second clock cycle, data is read from the FIFO, and the read pointer (rptr, pointing to the address where the data was read) is incremented. By monitoring the relationship between wptr and rptr, it is ensured that the FIFO is neither full nor empty. Therefore, the data written to the FIFO remains unchanged until it is read by the second clock cycle, thus achieving stable sampling of data across clock domains.

[0004] As can be seen from the working principle of FIFO, data needs to be sampled once by the first clock when written to the FIFO, and once by the second clock when read from the FIFO. Since the cross-clock domain data transmission occurs on parallel data, using FIFO will introduce a significant delay. Taking 1to8RX serial-to-parallel conversion as an example, the period of parallel data is 8ui (unit time), so using FIFO technology will introduce at least 16ui of delay, which cannot meet the application requirements of high-speed data transmission systems such as Die to Die.

[0005] Therefore, there is an urgent need for a cross-clock domain data transmission scheme with lower latency. Summary of the Invention

[0006] This invention provides a cross-clock domain synchronization circuit and method based on multi-phase clocks to solve the problem that existing data transmission schemes have long delay times and cannot meet the requirements of high-speed data transmission.

[0007] To achieve the above objectives, the present invention provides a cross-clock domain synchronization circuit based on a multi-phase clock, comprising a selector, an asynchronous clock synchronization module, and a digital signal processor; wherein,

[0008] The serial data to be transmitted and the low-frequency clock are input into the selector, and the selector is used to output the corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock.

[0009] The asynchronous clock synchronization module is used to output corresponding alignment data to the digital signal processor based on the input RX parallel data, the clock of the digital signal processor, and the low-frequency clock.

[0010] The asynchronous clock synchronization module is used to phase-align the RX parallel data with the clock of the digital signal processor.

[0011] The digital signal processor is used to process the alignment data.

[0012] Alternatively, an optional technical solution is that the low-frequency clock is obtained based on the clock transmitted by TX; wherein the clock transmitted by TX is divided to obtain a low-frequency clock with the corresponding number of phases, and the low-frequency clock is input into the selector.

[0013] In addition, an optional technical solution is that the asynchronous clock synchronization module includes: a first flip-flop array, a second flip-flop array, a third flip-flop array, a delay array, a first selector array, a second selector, and logic gates;

[0014] The delay array is connected to the second trigger array;

[0015] The first trigger array and the second trigger array are respectively connected to the input terminals of the first selector array;

[0016] The output of the first selector array is connected to the logic gate;

[0017] The output of the logic gate is connected to the second selector;

[0018] The second selector is connected to the third trigger array, and the alignment data is output through the third trigger array.

[0019] Alternatively, the low-frequency clock can be input to the first trigger array, the second selector, and processed by the delay array before being input to the second trigger array.

[0020] The clock of the digital signal processor is input to the first flip-flop array and the second flip-flop array respectively;

[0021] The RX parallel data is input to the third trigger array.

[0022] In addition, an optional technical solution is that the output signal of the logic gate is a one-hot code generated based on the output signal of the first selector array; wherein the one-hot code is respectively input to the second selector and input to the first selector array after processing.

[0023] Alternatively, the clock of the digital signal processor and the low-frequency clock may have the same frequency.

[0024] Alternatively, an optional technical solution is to obtain a selection signal by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1>When the value is 1, the nth bit of the low-frequency clock is used to sample and align the parallel data of the RX; n is the number of bits of the low-frequency clock.

[0025] On the other hand, the present invention also provides a cross-clock domain synchronization method based on a multi-phase clock, which utilizes the aforementioned cross-clock domain synchronization circuit of a multi-phase clock to synchronously transmit serial data to be transmitted; wherein, the method includes:

[0026] The serial data to be transmitted and the low-frequency clock are input into the selector, and the low-frequency clock is input into the asynchronous clock synchronization module;

[0027] The selector acquires the RX parallel data corresponding to the serial data and sends it to the asynchronous clock synchronization module.

[0028] The asynchronous clock synchronization module performs phase alignment between the RX parallel data and the clock of the digital signal processor, obtains the aligned data, and sends it to the digital signal processor.

[0029] The alignment data is processed by the digital signal processor.

[0030] Alternatively, an optional technical solution is to obtain a selection signal by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1>When the value is 1, the nth bit of the low-frequency clock is used to sample and align the parallel data of the RX; n is the number of bits of the low-frequency clock.

[0031] In addition, an optional technical solution includes: delaying the nth low-frequency clock bit to obtain the corresponding delayed clock signal;

[0032] The delayed clock signal is sampled using the clock of the digital signal processor to ensure that the selection signal sel <n-1>=1;

[0033] The delay time is greater than the clock jitter of the digital signal processor.

[0034] The multi-phase clock-based cross-clock domain synchronization circuit and method provided by the present invention can phase-align RX parallel data with the clock of the digital signal processor based on the asynchronous clock synchronization module, obtain the aligned data and send it to the digital signal processor, effectively reducing the delay time, and is applicable to various types of serial-to-parallel conversion circuits.

[0035] To achieve the foregoing and related objectives, one or more aspects of the invention include the features which will be described in detail below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the cross-clock domain synchronization circuit based on a multi-phase clock according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the circuit structure of the asynchronous clock synchronization module according to an embodiment of the present invention;

[0038] Figure 3 This is a timing diagram of a cross-clock domain synchronization circuit based on a multi-phase clock according to an embodiment of the present invention;

[0039] Figure 4 This is a flowchart of a cross-clock domain synchronization method based on a multi-phase clock, according to an embodiment of the present invention.

[0040] Figure reference numerals: First flip-flop array 1, Second flip-flop array 2, Third flip-flop array 3, Delay array 4, Second selector 5, First selector array 6, Logic gate 7.

[0041] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone.

[0043] In the embodiments of this application, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different.

[0044] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being better or more advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0045] In view of the problem that the existing technology has long delay and cannot meet the requirements of high-speed data transmission, the present invention provides a cross-clock domain synchronization circuit and method based on multi-phase clock, which does not require writing data into a FIFO and then reading it out, and can effectively reduce the data transmission delay. It can be applied to various types of serial-to-parallel conversion circuits.

[0046] The technical solution of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Specifically, Figure 1 A schematic circuit structure of a cross-clock domain synchronization circuit based on a multi-phase clock according to an embodiment of the present invention is shown.

[0048] like Figure 1 As shown, the cross-clock domain synchronization circuit based on multi-phase clock in this embodiment of the invention includes a selector, an asynchronous clock synchronization module, and a digital signal processor. The serial data to be transmitted and the low-frequency clock are both input into the selector, so that the selector outputs corresponding RX parallel data according to the serial data and the low-frequency clock. Since the low-frequency clock and the clock of the digital signal processor are asynchronous, they have the same frequency but an uncertain phase relationship. Therefore, to ensure that the data can be correctly sampled by the digital signal processor, the RX parallel data and the clock of the digital signal processor need to be aligned.

[0049] Therefore, in this invention, the obtained RX parallel data and low-frequency clock are input into an asynchronous clock synchronization module. The asynchronous clock synchronization module outputs corresponding aligned data to the digital signal processor based on the input RX parallel data, the clock of the digital signal processor, and the low-frequency clock. In this process, the asynchronous clock synchronization module performs phase alignment between the RX parallel data and the clock of the digital signal processor, enabling the digital signal processor to perform correct sampling and realize relevant data processing on the aligned data.

[0050] The low-frequency clock can be obtained based on the clock sent by TX. The clock sent by TX is divided by 8 to obtain the low-frequency clock with the corresponding number of phases, and the low-frequency clock is input into the selector (1:8).

[0051] Specifically, such as Figure 1 As shown, data represents the serial data to be transmitted sent by TX, and clock represents the clock sent by TX. The clock sent by TX is divided by frequency, for example, by 8 to obtain an 8-phase low-frequency clock ck8t<7:0>. Driven by the low-frequency clock ck8t<7:0>, the serial data data is converted into 8-channel low-speed parallel data d8t<7:0> (i.e., RX parallel data). The parallel data d8t<7:0> is further aligned with the clock ck_dig of the digital signal processor (DSP) after passing through the asynchronous clock alignment module, resulting in aligned data d8t_dig<7:0>, which is then sent to the DSP.

[0052] Figure 2 A schematic circuit structure of an asynchronous clock synchronization module according to an embodiment of the present invention is shown. Figure 3 A synchronization timing diagram of a cross-clock domain synchronization circuit based on a multiphase clock is shown according to an embodiment of the present invention.

[0053] As 1 to Figure 3 As shown in the figure, the asynchronous clock synchronization module of this embodiment further includes: a first flip-flop array 1 (x8 indicates 8 first flip-flops), a second flip-flop array 2 (x8 indicates 8 second flip-flops), a third flip-flop array 3 (x8 indicates 8 third flip-flops), a delay array 4 (x8 indicates 8 delays), a first selector array 6 (x8 indicates 8 two-to-one first selectors), a second selector 5, and a logic gate 7 (x8 indicates 8 logic gates); wherein, the delay array 4 is connected to the second flip-flop array 2; the first flip-flop array 1 and the second flip-flop array 2 are respectively connected to the input terminals of the first selector array 6; the output terminal of the first selector array 6 is connected to the logic gates; the output terminal of the logic gate 7 is connected to the second selector 5; the second selector 5 is connected to the third flip-flop array 3, and finally the processed aligned data is output through the third flip-flop array 3.

[0054] The low-frequency clock ck8t<7:0> is input to the first flip-flop array 1, the second selector 5, and the second flip-flop array 2 after being delayed by the delay array 4; the digital signal processor clock ck_dig is input to the first flip-flop array 1 and the second flip-flop array 2, and the RX parallel data d8t<7:0> is input to the third flip-flop array 3.

[0055] Furthermore, the output signal of the logic gate is a one-hot code generated based on the output signal of the first selector array; wherein the one-hot code is input to the second selector and then input to the first selector array after processing.

[0056] Specifically, the selection signal sel<7:0> is obtained by sampling the parallel data ck8t<7:0> of RX through the clock ck_dig of the digital signal processor, where sel <7> ck8t sampled by ck_dig <7> Get, sel <6> ck8t sampled by ck_dig <0> Therefore, we can extrapolate from this. Since ck8t<7:0> is an 8-phase clock, the phase difference between two adjacent phases is 1ui (unit of time). Therefore, sel<7:0> will have 4 consecutive 0s and 4 consecutive 1s, and there is only one transition edge from 0 to 1.

[0057] Among them, with Figure 3 For example, in the specific case shown, sel <6> =0 and sel <5> Since the value is 1, it can be determined that the rising edge of ck_dig occurs at ck8t. <6> The falling edge and ck8t <5> Between the falling edges. To ensure the data can be correctly sampled by ck_dig, first use ck8t. <6> The data is sampled on the rising and falling edges, where the RX parallel data d8t<7:0> was originally with ck8t. <7> Alignment with the rising edge, using ck8t here. <6> The data is sampled on the rising edge, and the resulting aligned data d8t_dig<7:0> will be matched with ck8t. <6> The rising edge is aligned, and in this case, the rising edge of the digital signal processor's clock ck_dig is located in the middle of the aligned data. The timing is also the largest at this time, so the phase relationship between the data and ck_dig can be determined. At this time, the aligned data is sent to the DSP. When ck_dig samples the data, there is sufficient margin in the setup time and hold time, thereby realizing the propagation of data across clock domains.

[0058] It should be noted that the above sel <6> and sel <5> The specific examples given are for ease of explanation only; in actual application, sel <n>=0, sel <n-1>If the value is 1, then ck8t is used. <n>The data is sampled to align it, where n is a positive integer (in the example attached, n ranges from 0 to 7).

[0059] As a specific example, d8t<7:0> represents 8 parallel data segments with a width of 8ui, ck8t<7:0> represents 8 clock cycles with a period of 8ui, with an interval of 1ui between each two adjacent clock cycles, and ck_dig represents a clock cycle with a period of 8ui transmitted from the DSP. ck_dig and ck8t<7:0> are asynchronous clocks, with the same frequency but an uncertain phase relationship.

[0060] Furthermore, `sel_onehot<7:0>` represents a one-hot code, meaning that only one bit is 1 at a time, while the remaining 7 bits are 0. `sel_onehot<7:0>` represents 8 signals, each controlling a 2-to-1 MUX (i.e., the first selector array). `ck_dig` samples `ck8t<7:0>` through the first flip-flop array 1, and the sampling result is connected to terminal 0 of the 2-to-1 MUX (the MUX outputs this port signal when the control signal is 0). `ck8t<7:0>` passes through a delay array, i.e., the delay module, to obtain `ck8t_delay<7:0>`. `ck_dig` samples `ck8t_delay<7:0>` through the second flip-flop array, and the sampling result is connected to terminal 1 of the 2-to-1 MUX (the MUX outputs this port signal when the control signal is 1).

[0061] Furthermore, without loss of generality, it is assumed that initially sel_onehot<7:0> are all 0. Therefore, the signal at the 0 end of the first selector array MUX output, i.e., sel<7:0> is the sampling result of ck_dig on ck8t<7:0>. Assume that the asynchronous clock phase relationship at this time is... Figure 3 As shown, at this time, ck_dig samples ck8t<7:6> and ck8t<1:0> as 0, and ck8t<5:2> as 1. Therefore, sel<7:6> and sel<1:0> are 0, and sel<5:2> is 1. That is, sel<7:0> is 8'b00111100, and sel<6:0,7> is 8'b01111000. Therefore, after passing through a logic gate that inverts one end, i.e., an AND gate, only sel_onehot is obtained. <6> It is 1, while sel_onehot <7> Both sel_onehot<5:0> and sel_onehot<7:0> are 0. At this time, sel_onehot<7:0> is 8'b01000000, and sel_onehot<0,7:1> is 8'b00100000. Therefore, the fifth 2-to-1 MUX outputs a 1 signal, while the other seven 2-to-1 MUXs still output 0 signals, thus achieving metastability handling.

[0062] The signal sel<6:0,7> = 8'b01111000 is defined by concatenation: the high 7 bits are the original signal's <6:0> (i.e., bits 6 to 0), and the lowest bit (bit 0) is the original signal's bit 7. Combining this with the assignment 8'b01111000, we can see that the concatenated bits 7 to 1 correspond to the original <6:0> with a value of 0111100, and the concatenated bit 0 corresponds to the original bit 7 with a value of 0.

[0063] In addition, sel_onehot<7:0> also serves as a control signal for an 8-to-1 MUX (second selector). The value of a bit in sel_onehot<7:0> being 1 determines which port the MUX outputs the signal to. <6> The value is 1, therefore the output of the 8-to-1 MUX is ck8t. <6> , i.e. ck8t <6> The third flip-flop array dff is driven to sample the parallel data input d8t<7:0> to obtain d8t_dig<7:0>, so that the data is aligned with the ck_dig clock, thus completing the data synchronization across clock domains.

[0064] In the cross-clock domain synchronization circuit based on multi-phase clocks in this embodiment of the invention, a selection signal is obtained by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1>When the value is 1, the digital signal processor's clock is used to sample and align the nth bit of the low-frequency clock. This can also be understood as sampling and aligning the parallel data of RX using the nth bit of the low-frequency clock; n is the number of bits in the low-frequency clock.

[0065] Furthermore, to ensure the accuracy and reliability of data transmission, the metastability caused by clock jitter also needs to be considered, according to the appendix to this application. Figure 3 As shown in the timing diagram, when ck_dig is sampled at ck8t <5> At the falling edge, the jitter of ck_dig will cause jitter at the sampling time, thus affecting the sampled sel. <5> It will jitter between 0 and 1, and the clock of the selected aligned data will be in ck8t. <6> and ck8t <5> The jitter between data points reduces the timing margin of the data and may even cause data errors.

[0066] Therefore, to avoid metastability issues, in a specific embodiment of the present invention, when sel <6> sel is 0 <5> When it is 1, the original sel <5> It is ck8t sampled by ck_dig <5> The result is changed to ck_dig sampling ck8t_delay <5> Get sel <5> ck8t_delay <5> By ck8t <5> This is achieved through a delay, and the delay time must be greater than the jitter time. At this point, even if ck_dig jitters due to the jitter, sel <5> It remains at 1, therefore the selected clock will not jitter. When the phase change of ck_dig causes sel <5> When it becomes 0, the selected clock will become ck8t. <5> ,sel <5> ck8t will be resampled by ck_dig <5> Get, and sel <4> The ck8t_delay will be sampled by ck_dig. <4> Thus, the jitter of ck_dig will still not have metastability issues.

[0067] It should be noted that, depending on the application scenario and requirements, some modules or devices in the circuit can be replaced without changing the working principle of the multi-phase clock cross-clock domain synchronization circuit of this invention. For example, the above-mentioned flip-flops can be selected as rising edge sampling or falling edge sampling DFF, or high level conduction latch or low level conduction latch; the delay array can be implemented by inverters, buffers, transmission gates, delay lines, etc., and the selector can adopt various structures such as transmission gates and tri-state gates.

[0068] Furthermore, the logic for generating sel_onehot<7:0> through signals sel<7:0> and sel<6:0,7> is not limited to the "AND gate" (logic gate) shown in the accompanying drawings. Logic that satisfies the following truth table Table 1 is within the scope of protection claimed in this invention.

[0069] Table 1

[0070]

[0071] Furthermore, in the specific embodiment of the cross-clock domain synchronization circuit based on multi-phase clocks according to the present invention, when sel <n>=0 and sel <n-1>When the value is 1, select ck8t. <n>Regarding synchronized data, it should be noted that technical solutions that employ other variations but essentially still identify jumps in sampling results between two adjacent sampling points or separated by one or more sampling points are also within the scope of protection of this invention, such as sel. <n>=1 and sel <n-1>=0; or sel <n>=0 and sel <n-1>=1; or sel<n+1> =0 and sel <n-1>=1, or sel<n+1> =1 and sel <n-1>The value is 0. Based on actual circuit requirements, CK8T can be selected. <n>In addition, other phase clocks can also be selected.

[0072] Furthermore, the circuit structure of this invention is not only applicable to serial-to-parallel circuits with values ​​from 1 to 8, but also applicable to all serial-to-parallel circuits with values ​​from 1 to N (positive integers).

[0073] Corresponding to the above-mentioned cross-clock domain synchronization circuit based on multi-phase clocks, the present invention also provides a cross-clock domain synchronization method based on multi-phase clocks, which uses the above-mentioned cross-clock domain synchronization circuit based on multi-phase clocks to synchronously transmit serial data to be transmitted.

[0074] Specifically, the cross-clock domain synchronization method based on multi-phase clocks according to embodiments of the present invention includes at least the following steps:

[0075] S100: Input the serial data to be transmitted and the low-frequency clock into the selector, and input the low-frequency clock into the asynchronous clock synchronization module;

[0076] S200: Obtains the RX parallel data corresponding to the serial data through the selector and sends it to the asynchronous clock synchronization module;

[0077] S300: Based on the asynchronous clock synchronization module, the parallel data of RX is phase-aligned with the clock of the digital signal processor, the aligned data is obtained and sent to the digital signal processor;

[0078] S400: Data processing of alignment data via a digital signal processor.

[0079] The selection signal is obtained by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1>When the value is 1, the parallel data of RX is sampled and aligned using the nth bit of the low-frequency clock; n is the number of bits of the low-frequency clock.

[0080] Furthermore, the cross-clock domain synchronization method based on multiphase clocks may also include: delaying the nth low-frequency clock bit to obtain the corresponding delayed clock signal; sampling the delayed clock signal using the clock of a digital signal processor to ensure the selection signal sel <n-1>The value is 1; and the delay time is greater than the jitter of the digital signal processor's clock to ensure the reliability of sampling.

[0081] Specifically, such as Figure 4 As shown in the flowchart, the signal ck8t is first determined. <n>Whether it is selected as synchronous data; otherwise, jitter is ignored and ck8t is sampled directly through ck_dig. <n-1>The selection signal sel is obtained <n-1>If so, then sample ck8t_delay using ck_dig. <n-1>The selection signal sel is obtained <n-1>Then determine whether the signal satisfies sel <n>=0 and sel <n-1>=1, if so, select ck8t <n>As synchronization data, it is transmitted in alignment with the ck_dig signal, and this step is repeated cyclically to complete the synchronous transmission of all data.

[0082] It should be noted that the embodiments of the cross-clock domain synchronization method based on multi-phase clocks can be referred to the specific description in the embodiments of the cross-clock domain synchronization circuit based on multi-phase clocks, and will not be repeated here.

[0083] According to the multi-phase clock-based cross-clock domain synchronization circuit provided by the present invention, the serial data and clock sent by the transmitter are processed by a selector and frequency divider, and then input into an asynchronous clock synchronization module. The asynchronous clock synchronization module performs phase alignment of the processed parallel data with the clock of the digital signal processor, and sends the obtained aligned data to the digital signal processor for synchronous sampling processing. Not only is the circuit structure simple, but it can also effectively reduce the delay time and is applicable to various types of serial-to-parallel conversion circuits.

[0084] The cross-clock domain synchronization circuit and method based on a multi-phase clock according to the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various modifications can be made to the cross-clock domain synchronization circuit and method based on a multi-phase clock according to the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A cross-clock domain synchronization circuit based on a multi-phase clock, characterized in that, It includes a selector, an asynchronous clock synchronization module, and a digital signal processor; among which, The serial data to be transmitted and the low-frequency clock are input into the selector, and the selector is used to output the corresponding RX parallel data to the asynchronous clock synchronization module according to the serial data and the low-frequency clock. The asynchronous clock synchronization module is used to output corresponding alignment data to the digital signal processor based on the input RX parallel data, the clock of the digital signal processor, and the low-frequency clock. The asynchronous clock synchronization module is used to phase-align the RX parallel data with the clock of the digital signal processor. The digital signal processor is used to process the alignment data; The asynchronous clock synchronization module includes: a first flip-flop array, a second flip-flop array, a third flip-flop array, a delay array, a first selector array, a second selector, and logic gates; The delay array is connected to the second trigger array; The first trigger array and the second trigger array are respectively connected to the input terminals of the first selector array; The output of the first selector array is connected to the logic gate; The output of the logic gate is connected to the second selector; The second selector is connected to the third trigger array, and the alignment data is output through the third trigger array.

2. The cross-clock domain synchronization circuit based on multi-phase clocks as described in claim 1, characterized in that, The low-frequency clock is obtained based on the clock transmitted by TX; wherein, The clock transmitted by TX is divided to obtain a low-frequency clock with the corresponding number of phases, and the low-frequency clock is input into the selector.

3. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 1, characterized in that, The low-frequency clock is input to the first trigger array, the second selector, and after being processed by the delay array, it is input to the second trigger array. The clock of the digital signal processor is input to the first flip-flop array and the second flip-flop array respectively; The RX parallel data is input to the third trigger array.

4. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 1, characterized in that, The output signal of the logic gate is a one-hot code generated based on the output signal of the first selector array; wherein the one-hot code is input to the second selector and, after processing, input to the first selector array.

5. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 1, characterized in that, The clock of the digital signal processor has the same frequency as the low-frequency clock.

6. The cross-clock domain synchronization circuit based on a multi-phase clock as described in claim 1, characterized in that, A selection signal is obtained by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1> When the value is 1, the nth bit of the low-frequency clock is used to sample and align the RX parallel data; n is the number of bits in the low-frequency clock. < / n> 7. A cross-clock domain synchronization method based on a multi-phase clock, characterized in that, The serial data to be transmitted is synchronously transmitted using a cross-clock domain synchronization circuit of a multiphase clock as described in any one of claims 1 to 6; wherein the method includes: The serial data to be transmitted and the low-frequency clock are input into the selector, and the low-frequency clock is input into the asynchronous clock synchronization module; The selector acquires the RX parallel data corresponding to the serial data and sends it to the asynchronous clock synchronization module. The asynchronous clock synchronization module performs phase alignment between the RX parallel data and the clock of the digital signal processor, obtains the aligned data, and sends it to the digital signal processor. The alignment data is processed by the digital signal processor. The asynchronous clock synchronization module includes: a first flip-flop array, a second flip-flop array, a third flip-flop array, a delay array, a first selector array, a second selector, and logic gates. The delay array is connected to the second trigger array; The first trigger array and the second trigger array are respectively connected to the input terminals of the first selector array; The output of the first selector array is connected to the logic gate; The output of the logic gate is connected to the second selector; The second selector is connected to the third trigger array, and the alignment data is output through the third trigger array.

8. The cross-clock domain synchronization method based on multi-phase clocks as described in claim 7, characterized in that, A selection signal is obtained by sampling the low-frequency clock using the clock of the digital signal processor; wherein, when the selection signal sel <n>The value is 0, so the selection signal sel is selected. <n-1> When the value is 1, the nth bit of the low-frequency clock is used to sample and align the RX parallel data; n is the number of bits in the low-frequency clock.< / n-1> < / n> 9. The cross-clock domain synchronization method based on multi-phase clocks as described in claim 8, characterized in that, Also includes: Delay the nth low-frequency clock bit to obtain the corresponding delayed clock signal; The delayed clock signal is sampled using the clock of the digital signal processor to ensure that the selection signal sel <n-1> =1;< / n-1> The delay time is greater than the clock jitter of the digital signal processor.

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